Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The present disclosure relates to semiconductor structures and methods of manufacturing semiconductor structures. A semiconductor structure includes a first die, a second die, and an inter-die via (IDV). The first die includes an interconnect structure and a CMOS device electrically connected to the interconnect structure. The second die includes a memory element including a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, from a top-down perspective, a perimeter region of the ferroelectric layer is exposed by the second electrode and surrounds the second electrode. The IDV electrically connects the interconnect structure of the first die to the memory element of the second die.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor structures and methods for manufacturing semiconductor structures. Background Technology

[0002] The heat resistance of CMOS devices limits the choice of materials for the ferroelectric memory formed on them. Furthermore, CMOS devices suffer from low reliability due to their low stress tolerance to deformation of ferroelectric memory in operation. Summary of the Invention

[0003] This disclosure relates in a first aspect to a semiconductor structure, comprising: a first die including an interconnect structure and a CMOS device electrically connected to the interconnect structure; a second die including a memory element, the memory element including a first electrode, a ferroelectric layer on the first electrode and a second electrode on the ferroelectric layer, wherein, in a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode; and an inter-die via (IDV) electrically connecting the interconnect structure of the first die to the memory element of the second die.

[0004] A second aspect of this disclosure relates to a semiconductor structure comprising: a semiconductor die including a dielectric structure having a cavity exposed from an upper surface of the semiconductor die and an interconnect structure located below the cavity; and a semiconductor device stacked on the semiconductor die, the semiconductor device including a first conductive layer, a ferroelectric layer on the first conductive layer, and a second conductive layer on the ferroelectric layer, wherein, in a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second conductive layer, and the ferroelectric layer is located directly above the cavity of the semiconductor die.

[0005] A third aspect of this disclosure relates to a method of manufacturing a semiconductor structure, comprising: providing a first wafer including a CMOS device; providing a second wafer including a ferroelectric memory, wherein the ferroelectric memory includes a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, in a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode; forming a recess in the first wafer, the recess being exposed from an upper surface of the first wafer; and bonding the second wafer to the upper surface of the first wafer to form a cavity defined by the ferroelectric memory and the recess of the first wafer. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1A This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0008] Figure 1B This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figure 1C This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0010] Figure 1D This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0011] Figure 1E This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0012] Figure 1F This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 1G This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0014] Figure 2 This is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0015] Figure 3A This is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0016] Figure 3B This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0017] Figure 4 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figure 5A This is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0019] Figure 5B This is a top view of a semiconductor structure according to some embodiments of the present disclosure.

[0020] Figure 6A , Figure 6B , Figure 6C and Figure 6DThis is a top view of various semiconductor structures according to some embodiments of the present disclosure.

[0021] Figures 7A to 7H This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0022] Figures 8A to 8F This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "upper," etc.) to describe the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device during use or operation, other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0025] While the numerical ranges and parameters set forth in this disclosure are approximate, the values ​​set forth in the specific embodiments are reported as precisely as possible. However, any numerical value inherently contains some error, which is necessarily due to deviations typically found in the results of corresponding test measurements. Furthermore, as used herein, the terms “about,” “substantially,” or “basically” generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, when considered by those skilled in the art, the terms “about,” “substantially,” or “basically” mean within an acceptable standard error of the average. Except in operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages disclosed herein, such as amounts of material, durations, temperatures, operating conditions, ratios of quantities, etc., should be understood to be modified in all cases by the terms “about,” “substantially,” or “basically.” Therefore, unless otherwise indicated, the numerical parameters set forth in this disclosure and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted based at least on the number of significant figures reported and by applying common rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. Unless otherwise stated, all ranges disclosed herein include endpoints.

[0026] The embodiments of this disclosure discuss semiconductor structures comprising wafers that are individually fabricated and then bonded together, with electrical connections between them via inter-die vias (IDVs). Therefore, the processing temperature of a ferroelectric memory on one wafer can be unaffected by or limited by the processing temperature of a CMOS device on another wafer. This allows for more flexible selection of ferroelectric materials, thereby enabling relatively satisfactory performance of the ferroelectric memory depending on the specific application.

[0027] Figure 1A This is a cross-sectional view of a semiconductor structure 1A according to some embodiments of the present disclosure.

[0028] refer to Figure 1A In some embodiments, the semiconductor structure 1A includes dies 10 and 20, IDVs 30A and 30B, vias 30C and 30D, an insulating support layer 40, and conductive layers 50A and 50B.

[0029] Die 10 may include a semiconductor substrate 110. Semiconductor substrate 110 may include silicon, germanium, silicon-germanium or other suitable semiconductor materials. Semiconductor substrate 110 may be a bulk substrate or a semiconductor-on-insulator (SOI) substrate.

[0030] In some embodiments, die 10 includes one or more CMOS devices (e.g., CMOS devices 120 and 120A). In some embodiments, CMOS devices 120 and 120A are formed on or within semiconductor substrate 110. Semiconductor substrate 110 may also include one or more isolation structures (not shown) that define active regions for forming CMOS devices 120 and 120A.

[0031] In some embodiments, die 10 further includes a dielectric structure 130 and an interconnect structure 140 located within the dielectric structure 130. In some embodiments, the dielectric structure 130 and the interconnect structure 140 are disposed or formed on a semiconductor substrate 110. In some embodiments, the interconnect structure 140 is electrically connected to CMOS devices 120 and 120A. In some embodiments, the interconnect structure 140 includes one or more conductive layers (e.g., conductive layers 141, 141a, 142, 143, and 143a) and one or more conductive vias (e.g., conductive vias 146, 147, 148, and 148a) electrically connected to the conductive layers. In some embodiments, the bottommost conductive via 148 of the interconnect structure 140 is electrically connected to the CMOS device 120. In some embodiments, the bottommost conductive via 148a of the interconnect structure 140 is electrically connected to the CMOS device 120A. In some embodiments, CMOS devices 120 and 120A are configured to perform different functions depending on the specific application.

[0032] The dielectric structure 130 may be an interlayer dielectric (ILD) layer or include an interlayer dielectric (ILD) layer. The dielectric structure 130 may include, but is not limited to, SiN. X SiO X The conductive layers and conductive vias in the interconnect structure 140 may include various conductive materials, such as copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), alloys thereof, or combinations thereof, but this disclosure is not limited thereto.

[0033] In some embodiments, die 10 has a cavity 10C. In some embodiments, cavity 10C is located below die 20. In some embodiments, dielectric structure 130 of die 10 has cavity 10C. In some embodiments, cavity 10C is an enclosed space defined by dielectric structure 130. In some embodiments, cavity 10C is filled with air or an inert gas, such as nitrogen or argon.

[0034] In some embodiments, the cavity 10C is exposed by the upper surface 101 of the die 10. In some embodiments, the cavity 10C is exposed by the upper surface (e.g., upper surface 101) of the dielectric structure 130. In some embodiments, the cavity 10C has a depth T1 equal to or greater than about 0.1 μm. In some embodiments, the depth T1 of the cavity 10C is about 0.1 μm to about 100 μm, about 0.1 μm to about 50 μm, about 0.1 μm to about 20 μm, about 0.1 μm to about 10 μm, about 0.1 μm to about 5 μm, or about 0.1 μm to about 1 μm. In some embodiments, the cavity 10C has a width W1 equal to or greater than about 5 μm. In some embodiments, the width W1 of the cavity 10C is about 5 μm to about 100 μm.

[0035] In some embodiments, the interconnect structure 140 is spaced apart from the cavity 10C. In some embodiments, the interconnect structure 140 is covered by the dielectric structure 130. In some embodiments, the conductive layer and conductive vias are not exposed to the cavity 10C.

[0036] In some embodiments, the cavity 10C has a bottom surface 10C2, a top surface 10C1, and a plurality of side surfaces 10C3. In some embodiments, the side surfaces 10C3 of the cavity 10C are substantially planar or flat surfaces. In some embodiments, the side surfaces 10C3 of the cavity 10C are substantially perpendicular to the bottom surface 10C2 of the cavity 10C. In some embodiments, the side surfaces 10C3 of the cavity 10C are substantially straight sidewalls. In some embodiments, the bottom surface 10C2 of the cavity 10C is substantially planar or flat surfaces.

[0037] Die 20 may include one or more semiconductor devices 220. In some embodiments, die 20 includes a ferroelectric layer 223. In some embodiments, semiconductor device 220 includes electrodes 221 and 225 and the ferroelectric layer 223. In some embodiments, the ferroelectric layer 223 is located between electrodes 221 and 225. In some embodiments, the width 225W of electrode 225 is smaller than the width 223W of ferroelectric layer 223. In some embodiments, the width 223W of ferroelectric layer 223 is smaller than the width 221W of electrode 221. In some embodiments, a peripheral region of ferroelectric layer 223 is exposed by and surrounds electrode 225. In some embodiments, the edge of ferroelectric layer 223 is recessed (i.e., separated from) the edge of electrode 221 by about 0.1 μm to about 10 μm. In some embodiments, the edge of electrode 225 is recessed (i.e., separated from) the edge of ferroelectric layer 223 by about 0.1 μm to about 10 μm. In some embodiments, semiconductor device 220 is a memory element or includes a memory element. In some embodiments, the semiconductor device 220, which includes electrodes 221 and 225 and a ferroelectric layer 223, is a ferroelectric memory.

[0038] In some embodiments, electrodes 221 and 225 may comprise any suitable conductive material. In some embodiments, electrodes 221 and 225 may comprise Pt, Cu, W, Co, Al, Ta, TaN, TiN, alloys thereof, or combinations thereof. In some embodiments, the material of the ferroelectric layer 223 may be any suitable ferroelectric material or may include any suitable ferroelectric material. In some embodiments, the ferroelectric layer 223 may comprise hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO2), etc. X ), hafnium zirconium oxide (HfZrO) X Aluminum oxide (Al2O3), titanium dioxide (TiO2), lanthanum oxide (LaO2) X ), Barium SrTiO X BST), or lead zirconium titanium oxide (PbZrTiO) X (e.g., PZT), where the value of x is greater than 0 and less than 1. In some embodiments, the thickness of the ferroelectric layer 223 is equal to or greater than about 0.1 μm. In some embodiments, the thickness of the ferroelectric layer 223 is about 0.1 μm to about 10 μm, about 0.1 μm to about 5 μm, about 0.1 μm to about 1 μm, or about 0.1 μm to about 0.5 μm.

[0039] In some embodiments, the processing temperature of the semiconductor device 220 of die 20 is higher than the processing temperature of the CMOS device 120 of die 10. In some embodiments, the processing temperature of the ferroelectric layer 223 is higher than the processing temperature of the CMOS device 120 of die 10. In some embodiments, the processing temperature of the ferroelectric layer 223 is about 100°C or higher than the processing temperature of the CMOS device 120 of die 10. In some embodiments, the processing temperature of the ferroelectric layer 223 is higher than about 500°C, about 600°C, or about 700°C. For example, in some cases where the ferroelectric layer 223 of the semiconductor die 20 is PZT, after the initial deposition of the ferroelectric layer 223, the ferroelectric layer 223 is dried and prepared for calcination. The calcination process occurs at temperatures above 600°C, and in some cases even above 1000°C, thereby raising the PZT compound to high temperatures without melting in the absence of oxygen to remove impurities or volatile substances, thereby providing high-quality PZT material. These temperatures are high enough to be detrimental to the CMOS device 120, for example, by altering the threshold voltage due to unacceptable diffusion of dopants from the channel region and / or source / drain region of the transistor, or by other problems caused by such high temperatures. Therefore, in some embodiments, a ferroelectric layer 223 is formed on the semiconductor die 20 and a calcination process is performed on the semiconductor die 20 prior to wafer bonding. Then, only after calcination, the die 20 is bonded to the die 10 using IDVs 30A, 30B, thereby providing high-quality PZT ferroelectric material integrated with the CMOS device. Thus, high-temperature PZT ferroelectric material that can be processed at 600°C or higher is compatible with CMOS devices with a thermal budget of less than 425°C.

[0040] Die 20 may further include a dielectric structure 230 (also referred to as a "passivation layer"), and one or more semiconductor devices 220 may be formed in the dielectric structure 230. In some embodiments, the hardness of the dielectric structure 230 of die 20 is less than the hardness of the dielectric structure 130 of die 10. In some embodiments, the dielectric structure 230 has a thickness T2 of about 0.5 μm to about 100 μm. The dielectric structure 230 may be silicon oxide, silicon oxynitride, silicon nitride, or any combination thereof, or may include silicon oxide, silicon oxynitride, silicon nitride, or any combination thereof.

[0041] In some embodiments, the semiconductor device 220 is located above the cavity 10C of the die 10. In some embodiments, the cavity 10C is located below the semiconductor device 220. In some embodiments, the cavity 10C is located directly below the semiconductor device 220. In some embodiments, the ferroelectric layer 223 of the semiconductor device 220 is located above the cavity 10C of the die 10. In some embodiments, the cavity 10C is located below the ferroelectric layer 223. In some embodiments, the cavity 10C is located directly below the ferroelectric layer 223. In some embodiments, the projection of the semiconductor device 220 is completely within the projection of the cavity 10C. In some embodiments, the projection of the ferroelectric layer 223 is completely within the projection of the cavity 10C. In some embodiments, the edge of the semiconductor device 220 (or electrode 221) is recessed (or separated from) the edge of the cavity 10C by a distance D1 equal to or greater than about 1 μm. In some embodiments, the edge of the semiconductor device 220 (or electrode 221) is recessed (or separated from) the edge of the cavity 10C by a distance D1, which is from about 1 μm to about 10 μm, from about 1 μm to about 5 μm, from about 1 μm to about 3 μm, or from about 1 μm to about 2 μm. In some embodiments, the distance D2 may be the same as or different from the distance D3.

[0042] The cavity 10C offers benefits because, during data storage operations, applying a potential over the ferroelectric layer 223 can generate stresses that deform the ferroelectric material. Therefore, without the cavity, these stresses would attempt to “bend” or “bow” the ferroelectric layer 223, while the solid material surrounding the ferroelectric layer would resist such bending or bowing, thus creating harmful stresses within the ferroelectric layer. By including the cavity 10C, the ferroelectric layer can now freely distort its shape in response to the stresses generated by the applied potential (e.g., it can freely “bend” or “bow”—see example...). Figure 1G Therefore, in some embodiments, the ferroelectric layer 223 is disposed directly above the cavity, and the ferroelectric layer 223 has a bend or bow, which is transmitted to the upper surface 10C1 of the cavity, thereby the bent upper surface of the cavity demonstrates that the stress that would otherwise be applied to the ferroelectric layer 223 is relieved.

[0043] Still referencing Figure 1AIDVs 30A and 30B can electrically connect die 10 to die 20. In some embodiments, IDV 30A electrically connects semiconductor device 220 (or memory element) to CMOS device 120 of die 10. In some embodiments, IDV 30A electrically connects electrode 221 of semiconductor device 220 to CMOS device 120. CMOS device 120 can be configured to control semiconductor device 220 (or memory element). In some embodiments, IDV 30A extends through die 10 and die 20 to electrically connect CMOS device 120 to electrode 221 of semiconductor device 220. In some embodiments, IDV 30A extends through dielectric structure 130 and dielectric structure 230 to electrically connect CMOS device 120 to electrode 221 of semiconductor device 220. In some embodiments, IDV 30A extends along one side of cavity 10C. In some embodiments, IDV 30A extends below (i.e., beyond) the bottom surface 10C2 of cavity 10C. In some embodiments, the IDV 30A is separated from the edge of the cavity 10C by a distance D2 equal to or greater than about 0.5 μm. In some embodiments, the distance D2 between the IDV 30A and the edge of the cavity 10C is from about 0.5 μm to about 10 μm, from about 0.5 μm to about 5 μm, from about 0.5 μm to about 3 μm, or from about 0.5 μm to about 1 μm.

[0044] In some embodiments, IDV 30B electrically connects semiconductor device 220 to conductive layer 141a of interconnect structure 140. In some embodiments, IDV 30B penetrates die 10 and die 20 to electrically connect semiconductor device 220 to conductive layer 141a of interconnect structure 140. In some embodiments, IDV 30B penetrates dielectric structure 130 and dielectric structure 230 to electrically connect semiconductor device 220 to conductive layer 141a of interconnect structure 140. In some embodiments, IDV 30B extends along one side of cavity 10C. In some embodiments, IDV 30B extends below (i.e., beyond) the bottom surface 10C2 of cavity 10C. In some embodiments, IDV 30B is separated from the edge of cavity 10C by a distance D3 equal to or greater than about 0.5 μm. In some embodiments, the IDV30B is separated from the edge of the cavity 10C by a distance D3, which is from about 0.5 μm to about 10 μm, from about 0.5 μm to about 5 μm, from about 0.5 μm to about 3 μm, or from about 0.5 μm to about 1 μm.

[0045] In some embodiments, IDV 30A is electrically connected to electrode 221 via conductive layer 50A and via 30C. In some embodiments, IDV 30A penetrates dielectric structure 230. In some embodiments, IDV 30B is electrically connected to electrode 225 via conductive layer 50B and via 30D. In some embodiments, IDV 30B penetrates dielectric structure 230.

[0046] In some embodiments, IDV 30A has a height H1 equal to or greater than about 1 μm. In some embodiments, IDV 30A has a height H1 ranging from about 1 μm to about 100 μm, from about 1 μm to about 80 μm, from about 1 μm to about 50 μm, or from about 1 μm to about 20 μm. In some embodiments, IDV 30B has a height H2 equal to or greater than about 1 μm. In some embodiments, IDV 30B has a height H2 ranging from about 1 μm to about 100 μm, from about 1 μm to about 80 μm, from about 1 μm to about 50 μm, or from about 1 μm to about 20 μm. In some embodiments, the height H1 of IDV 30A may be the same as or different from the height H2 of IDV 30B.

[0047] In some embodiments, conductive layers 50A and 50B are disposed on or formed on the dielectric structure 230 of the die 20. Conductive layers 50A and 50B may include Cu, W, Co, Al, Ta, TaN, TiN, alloys thereof, or combinations thereof.

[0048] An insulating support layer 40 may be disposed or formed between the ferroelectric layer 223 and the cavity 10C. In some embodiments, the insulating support layer 40 is disposed or formed between the semiconductor device 220 and the cavity 10C. In some embodiments, a portion of the bottom surface 402 of the insulating support layer 40 is exposed to the cavity 10C. In some embodiments, the cavity 10C is an enclosed space defined by the dielectric structure 130 and the insulating support layer 40. In some embodiments, IDVs 30A and 30B penetrate the die 10 and the insulating support layer 40 to be electrically connected to the semiconductor device 220. In some embodiments, the insulating support layer 40 has a thickness from about 3 μm to about 10 μm, from about 4 μm to about 8 μm, or from about 5 μm to about 6 μm. In some embodiments, the insulating support layer 40 may include any suitable insulating material. In some embodiments, the insulating support layer 40 includes silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon (e.g., undoped polycrystalline silicon), or combinations thereof.

[0049] Figure 1B This is a cross-sectional view of a semiconductor structure 1B according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 1B is similar to... Figure 1A The semiconductor structure 1A in the diagram is shown below, and the differences between the two are as follows. Descriptions of similar components are omitted.

[0050] In some embodiments, the interconnect structure 140 includes one or more conductive layers (e.g., conductive layers 141, 142, 142a, 143, 144, and 144a) and one or more conductive vias (e.g., conductive vias 146, 147, 148, 149, and 149a) electrically connected to the conductive layers. In some embodiments, the bottom conductive via 149 of the interconnect structure 140 is electrically connected to the CMOS device 120. In some embodiments, the bottom conductive via 149a of the interconnect structure 140 is electrically connected to the CMOS device 120A. In some embodiments, IDV 30B electrically connects the semiconductor device 220 to the conductive layer 142a of the interconnect structure 140.

[0051] In some embodiments, IDV 30A extends along one side of cavity 10C and stops before reaching the height of bottom surface 10C2 of cavity 10C. In some embodiments, the height of bottom surface of IDV 30A is higher than the height of bottom surface 10C2 of cavity 10C. IDV 30A is electrically connected to CMOS device 120 through conductive layers 141, 142, 143 and 144 and conductive vias 146, 147, 148 and 149.

[0052] Figure 1C This is a cross-sectional view of a semiconductor structure 1C according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 1C is similar to... Figure 1A The semiconductor structure 1A in the diagram is shown below, and the differences between the two are as follows. Descriptions of similar components are omitted.

[0053] In some embodiments, IDV 30A electrically connects electrode 225 of semiconductor device 220 to CMOS device 120. In some embodiments, via 30C electrically connects electrode 225 to IDV 30A. In some embodiments, IDV 30B electrically connects electrode 221 of semiconductor device 220 to conductive layer 141a of interconnect structure 140. In some embodiments, via 30D electrically connects electrode 221 to IDV 30B.

[0054] Figure 1D This is a cross-sectional view of a semiconductor structure 1D according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 1D is similar to... Figure 1A The semiconductor structure 1A in the diagram is shown below, and the differences between the two are as follows. Descriptions of similar components are omitted.

[0055] In some embodiments, IDV 30A electrically connects electrode 225 of semiconductor device 220 to CMOS device 120. In some embodiments, via 30C electrically connects electrode 225 to IDV 30A. In some embodiments, IDV 30B electrically connects electrode 221 of semiconductor device 220 to conductive layer 142a of interconnect structure 140. In some embodiments, via 30D electrically connects electrode 221 to IDV 30B.

[0056] Figure 1E This is a cross-sectional view of a semiconductor structure 1E according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 1E is similar to... Figure 1A The semiconductor structure 1A in the diagram is shown below, and the differences between the two are as follows. Descriptions of similar components are omitted.

[0057] In some embodiments, the interconnect structure 140 includes one or more conductive layers (e.g., conductive layers 141, 142, 142a, 143, 144, 144a, and 145) and one or more conductive vias (e.g., conductive vias 146, 147, 148, 149, and 149a) electrically connected to the conductive layers. In some embodiments, the lowermost conductive via 149 of the interconnect structure 140 is electrically connected to the CMOS device 120. In some embodiments, the lowermost conductive via 149a of the interconnect structure 140 is electrically connected to the CMOS device 120A. In some embodiments, IDV 30B electrically connects the semiconductor device 220 to the conductive layer 142a of the interconnect structure 140.

[0058] In some embodiments, interconnect structure 140 is exposed to cavity 10C. In some embodiments, interconnect structure 140 is exposed from dielectric structure 130. In some embodiments, conductive layer 145 is exposed to cavity 10C. In some embodiments, cavity 10C is filled with an inert gas, such as nitrogen or argon.

[0059] Figure 1F This is a cross-sectional view of a semiconductor structure 1F according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 1F is similar to... Figure 1A The semiconductor structure 1A in the diagram is shown below, and the differences between the two are as follows. Descriptions of similar components are omitted.

[0060] In some embodiments, the side surface 10C3 of the cavity 10C is a curved surface. In some embodiments, the bottom surface 10C2 of the cavity 10C is a curved surface. In some embodiments, the side surface 10C3 and the bottom surface 10C2 form a bending angle.

[0061] Figure 2 This is a top view of a semiconductor structure 2 according to some embodiments of the present disclosure. In some embodiments, Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and / or Figure 1G The semiconductor structure 2 can be shown along... Figure 2 A cross-sectional view of section 2-2' in the diagram.

[0062] In some embodiments, the die 10 of the semiconductor structure 2 includes a plurality of cavities 10C. In some embodiments, the die 20 of the semiconductor structure 2 includes a plurality of semiconductor devices 220. In some embodiments, the semiconductor structure 2 includes a plurality of semiconductor devices 220 located on a plurality of corresponding cavities 10C. In some embodiments, two adjacent cavities 10C are separated from each other by a distance D4 equal to or greater than about 1 μm. In some embodiments, the distance D4 between two adjacent cavities 10C is about 1 μm to about 100 μm, about 1 μm to about 50 μm, about 1 μm to about 10 μm, or about 1 μm to about 5 μm.

[0063] In some embodiments, from a top view, the semiconductor device 220 is entirely within the projection of the corresponding cavity 10C. In some embodiments, from a top view, the area of ​​the ferroelectric layer 223 is smaller than the area of ​​the corresponding cavity 10C. In some embodiments, from a top view, the area of ​​the semiconductor device 220 is smaller than the area of ​​the corresponding cavity 10C.

[0064] In some embodiments, IDV 30A of one of the cavities 10C is disposed adjacent to IDV 30B of an adjacent cavity 10C. In some embodiments, conductive layers 50A and 50B extend along direction DR2, semiconductor devices 220 (or cavities 10C) are arranged along direction DR1, and the angle formed by direction DR1 and direction DR2 is greater than 0 and less than about 90°. In some embodiments, multiple structures, each including a semiconductor device 220 and conductive layers 50A and 50B connected to the semiconductor device 220, are arranged in an alternating manner. In some embodiments, multiple structures, each including a semiconductor device 220 and IDV 30A and 30B connected to the semiconductor device 220, are arranged in an alternating manner.

[0065] According to some embodiments of this disclosure, wafers 10 and 20 are fabricated separately and then bonded together, with electrical connections achieved via IDV, instead of fabricating the semiconductor device 220 (or ferroelectric memory) directly on die 10. Therefore, the processing temperature of the semiconductor device 220 (or ferroelectric memory) on wafer 20 is not affected or limited by the processing temperature of the CMOS device on die 10. Consequently, the material of the ferroelectric layer 223 can be selected with greater flexibility, thereby enabling the semiconductor device 220 to achieve relatively satisfactory performance for the specific application.

[0066] Furthermore, according to some embodiments of this disclosure, by utilizing the design of a cavity 10C directly beneath the semiconductor device 220 (or ferroelectric memory), the cavity 10C can provide sufficient buffer space for the deformation of the semiconductor device 220 during operation. Therefore, the structure and / or components of the die 10 are not affected or damaged, thereby improving the reliability of the semiconductor structure.

[0067] Figure 3A This is a top view of a semiconductor structure 3 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 3 is similar to... Figure 2 Semiconductor structure 2 in the diagram, the differences between the two are as follows. Descriptions of similar components are omitted.

[0068] In some embodiments, IDV 30A of one of the cavities 10C is disposed adjacent to IDV 30B of an adjacent cavity 10C. In some embodiments, conductive layers 50A and 50B extend along direction DR1, and semiconductor devices 220 (or cavities 10C) are arranged along direction DR1. In some embodiments, conductive layers 50A and 50B are arranged in an alternating manner. In some embodiments, IDV 30A and IDV 30B are arranged in an alternating manner.

[0069] Figure 3B This is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. In some embodiments, FIG3 may show the semiconductor structure 3 along... Figure 3A The cross-sectional view of section line 3-3' in the figure.

[0070] In some embodiments, the die 10 of the semiconductor structure 3 includes a plurality of cavities 10C. In some embodiments, the die 20 of the semiconductor structure 3 includes a plurality of semiconductor devices 220. In some embodiments, the semiconductor structure 3 includes a plurality of semiconductor devices 220 on a plurality of corresponding cavities 10C. In some embodiments, two adjacent cavities 10C are separated from each other by a distance D4 equal to or greater than about 1 μm. In some embodiments, the distance D4 between two adjacent cavities 10C is about 1 μm to about 100 μm, about 1 μm to about 50 μm, about 1 μm to about 10 μm, or about 1 μm to about 5 μm.

[0071] Figure 4 This is a cross-sectional view of a semiconductor structure 4 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 4 is similar to... Figure 3A Semiconductor structure 3 in the diagram, the differences between the two are as follows. Descriptions of similar components are omitted.

[0072] In some embodiments, the conductive layer 141 of the interconnect structure 140 is located between adjacent cavities 10C. In some embodiments, each of the bottom surfaces of the IDV 30A is located between adjacent cavities 10C.

[0073] Figure 5A This is a top view of a semiconductor structure 5A according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 5A is similar to... Figure 2 Semiconductor structure 2 in the diagram, the differences between the two are as follows. Descriptions of similar components are omitted.

[0074] In some embodiments, conductive layers 50A and 50B are substantially aligned in direction DR1. In some embodiments, IDV 30A and 30B are substantially aligned in direction DR1.

[0075] Figure 5B This is a top view of a semiconductor structure 5B according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 5B is similar to... Figure 2 Semiconductor structure 2 in the diagram, the differences between the two are as follows. Descriptions of similar components are omitted.

[0076] In some embodiments, conductive layers 50A and 50B extend in direction DR1. In some embodiments, semiconductor devices 220 are arranged in an alternating manner in direction DR1. In some embodiments, cavities 10C are arranged in an alternating manner in direction DR1.

[0077] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a top view of various semiconductor structures according to some embodiments of the present disclosure. In some embodiments, Figure 6A , Figure 6B , Figure 6C and Figure 6D Each of the above illustrates an arrangement that includes a semiconductor device 220, a corresponding cavity 10C, conductive layers 50A and 50B, and IDVs 30A and 30B.

[0078] refer to Figure 6A In some embodiments, the semiconductor device 220 has a circular shape, and the cavity 10C has a square shape. In some embodiments, the extending direction of the conductive layer 50A forms an angle of less than about 180° with the extending direction of the conductive layer 50B.

[0079] refer to Figure 6B In some embodiments, both the semiconductor device 220 and the cavity 10C have a circular shape.

[0080] refer to Figure 6CIn some embodiments, both the semiconductor device 220 and the cavity 10C have a square shape.

[0081] refer to Figure 6D In some embodiments, conductive layers 50A and 50B are arranged in an alternating manner.

[0082] Figures 7A to 7H This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0083] refer to Figure 7A A sacrificial layer 720 can be formed on the carrier 710, an insulating support layer 40 can be formed on the sacrificial layer 720, and one or more semiconductor devices 220 (or ferroelectric memories) can be formed on the insulating support layer 40.

[0084] In some embodiments, the carrier 710 may be a silicon substrate or include a silicon substrate. In some embodiments, the sacrificial layer 720 may include an oxide, such as silicon dioxide. In some embodiments, the sacrificial layer 720 may be formed by deposition. In some embodiments, the insulating support layer 40 may include polysilicon (e.g., undoped polysilicon).

[0085] In some embodiments, each semiconductor device 220 is formed by forming an electrode 221 on an insulating support layer 40, forming a ferroelectric layer 223 on the electrode 221, and forming an electrode 225 on the ferroelectric layer 223. An electrode material may be formed on the insulating support layer 40 (e.g., by deposition), and then the electrode material may be patterned to form the electrode 221. A ferroelectric material may be formed on the electrode 221 (e.g., by deposition), and then the ferroelectric material may be patterned to form each ferroelectric layer 223 on the corresponding electrode 221. An electrode material may be formed on the ferroelectric layer 223 (e.g., by deposition), and then the electrode material may be patterned to form each electrode 225 on the corresponding ferroelectric layer 223. Thus, the semiconductor device 220 is formed on the insulating support layer 40.

[0086] refer to Figure 7BThe carrier 710 can be removed by grinding to expose the sacrificial layer 720. In some embodiments, a dielectric structure 230 is formed on the semiconductor device 220. The dielectric structure 230 may include an oxide, such as silicon dioxide. The dielectric structure 230 may be formed by deposition. In some embodiments, the carrier 730 is bonded to the dielectric structure 230. In some embodiments, the carrier 710 is removed by grinding after the carrier 730 has been bonded to the dielectric structure 230, which serves as a support for the grinding operation. In some embodiments, the grinding operation may remove a portion of the sacrificial layer 720. Thus, a wafer is formed that includes a die 20 and includes the dielectric structure 230 and the semiconductor device 220 formed in the dielectric structure 230.

[0087] refer to Figure 7C The sacrificial layer 720 can be removed by etching to expose the insulating support layer 40. In some embodiments, the sacrificial layer 720 is removed by a wet etching operation. In some embodiments, the sacrificial layer 720 is completely removed by a wet etching operation. When the wet etching operation has high etch selectivity between the sacrificial layer 720 and the insulating support layer 40, the sacrificial layer 720 can be completely removed without damaging the insulating support layer 40, so the insulating support layer 40 can be provided with a satisfactory predetermined thickness.

[0088] refer to Figure 7D A wafer 10 may be provided, which includes one or more CMOS devices 120 and 120A, a dielectric structure 130 and an interconnect structure 140, and one or more recesses 10R may be formed in the wafer 10. In some embodiments, the recesses 10R are exposed from the upper surface 101 of the wafer 10.

[0089] In some embodiments, the recess 10R can be formed by etching. In some embodiments, a patterned mask layer 740 having one or more openings can be disposed or formed on the upper surface 101 of the dielectric structure 130 of the wafer 10, and an etching operation can be performed on the dielectric structure 130 according to the patterned mask layer 740 to form the recess 10R directly below the openings of the patterned mask layer 740. In some embodiments, the etching operation can be an isotropic etching operation (e.g., dry etching), so that the formed recess 10R has relatively straight sidewalls. In some other embodiments, the etching operation can be an anisotropic etching operation (e.g., wet etching), and the formed recess 10R can then have curved sidewalls (see reference). Figure 1F The curved side surface 10C3 of the cavity 10C shown.

[0090] refer to Figure 7EWafer 20 may be bonded to the upper surface 101 of wafer 10 to form one or more cavities 10C defined by semiconductor device 220 (or ferroelectric memory) and recesses 10R of wafer 10. In some embodiments, insulating support layer 40 is bonded to the upper surface 101 of wafer 10. In some embodiments, after wafer 200 is bonded to the upper surface 101 of wafer 10, each cavity is defined by insulating support layer 40 and each recess 10R of wafer 10.

[0091] refer to Figure 7F The carrier 730 can be removed. In some embodiments, the carrier 730 can be removed from the dielectric structure 230 by grinding or heating.

[0092] refer to Figure 7G Inter-via openings 30A and 30B can be formed penetrating wafers 10 and 20, vias 30C and 30D can be formed within the dielectric structure 230, and conductive layers 50A and 50B can be formed on the dielectric structure 230. In some embodiments, a plurality of inter-via openings penetrating wafers 10 and 20 are formed, for example, by etching, and conductive material is formed in the inter-via openings, for example, by sputtering. In some embodiments, a CMP operation can be performed to remove excess conductive material located outside the inter-via openings. In some embodiments, conductive material is formed on the dielectric structure 230, for example, by sputtering, and the conductive material contacts IDVs 30A and 30B and vias 30C and 30D. In some embodiments, the conductive material is then patterned to form conductive layers 50A and 50B.

[0093] refer to Figure 7H A dielectric structure 94 (also referred to as a "passivation layer") can be formed on the dielectric structure 230. Via openings can be formed that penetrate the dielectric structure 94 and wafers 10 and 20 to stop at the conductive layer 143b of the interconnect structure 140. In some embodiments, conductive material is formed in the via openings to form an IDV 90, and a conductive layer 92 is formed on the dielectric structure 94 and electrically connected to the IDV 90. In some embodiments, the IDV 90 and the conductive layer 92 can be used to electrically connect CMOS devices 120 and / or 120A to external circuitry. The external circuitry can be configured to control CMOS devices 120 and / or 120A. Thus, forming... Figure 7H Semiconductor structure 7 is shown in the figure.

[0094] Figures 8A to 8F This is a cross-sectional view of an intermediate stage of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0095] refer to Figure 8AAn insulating support layer 40A may be formed on the carrier 710, and one or more semiconductor devices 220 (or ferroelectric memories) may be formed on the insulating support layer 40A. In some embodiments, the carrier 710 may be a silicon substrate or include a silicon substrate. In some embodiments, the insulating support layer 40A may include an oxide, such as silicon dioxide.

[0096] refer to Figure 8B The carrier 710 can be partially removed by grinding, and the remaining carrier 710' has a reduced thickness.

[0097] refer to Figure 8C The carrier 710' can be removed by chemical mechanical polishing (CMP) to expose the formed insulating support layer 40. In some embodiments, the carrier 710' is completely removed by CMP. In some embodiments, the CMP operation can remove a portion of the insulating support layer 40A to form an insulating support layer 40 with a reduced thickness.

[0098] refer to Figure 8D It can perform similar actions Figures 7D-7E The operations shown are for bonding wafer 10 to wafer 20 and can form one or more cavities 10C.

[0099] refer to Figure 8E It can perform similar actions Figures 7F-7G The operations shown are to remove the carrier 730 and form IDV 30A and 30B, vias 30C and 30D, and conductive layers 50A and 50B.

[0100] refer to Figure 8F It can perform similar actions Figure 7H The operations shown are used to form IDV 90, conductive layer 92, and dielectric structure 94. This forms... Figure 8F The semiconductor structure shown is 8.

[0101] According to one embodiment, a semiconductor structure includes a first die, a second die, and an inter-die via (IDV). The first die includes an interconnect structure and a CMOS device electrically connected to the interconnect structure. The second die includes a memory element comprising a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, from a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode. The IDV electrically connects the interconnect structure of the first die to the memory element of the second die.

[0102] According to one embodiment, a semiconductor structure includes a semiconductor wafer and a semiconductor device. The semiconductor wafer includes a dielectric structure having a cavity exposed from the upper surface of the semiconductor die and an interconnect structure located below the cavity. The semiconductor device is stacked on the semiconductor die and includes a first conductive layer, a ferroelectric layer on the first conductive layer, and a second conductive layer on the ferroelectric layer, wherein, from a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second conductive layer, and the ferroelectric layer is located above the cavity of the semiconductor wafer.

[0103] According to one embodiment, a method of manufacturing a semiconductor structure includes: providing a first wafer including a CMOS device; providing a second wafer including a ferroelectric memory, wherein the ferroelectric memory includes a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, from a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode; forming a recess in the first wafer, the recess being exposed from an upper surface of the first wafer; and bonding the second wafer to the upper surface of the first wafer to form a cavity defined by the ferroelectric memory and the recess of the first wafer.

[0104] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0105] Example 1. A semiconductor structure comprising:

[0106] The first die includes an interconnect structure and a CMOS device electrically connected to the interconnect structure;

[0107] A second die includes a memory element comprising a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, from a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode; and

[0108] Inter-die vias (IDVs) electrically connect the interconnect structure of the first die to the memory element of the second die.

[0109] Example 2. The semiconductor structure according to Example 1, wherein the first die has a cavity located above the interconnect structure, exposed by the upper surface of the first die, and located directly below the ferroelectric layer.

[0110] Example 3. The semiconductor structure according to Example 2, wherein the ferroelectric layer has curvature, and the curvature is at least partially transmitted to the upper surface of the cavity closest to the ferroelectric layer.

[0111] Example 4. The semiconductor structure according to Example 2, wherein the projection of the ferroelectric layer is completely within the projection of the cavity when viewed from a top angle.

[0112] Example 5. The semiconductor structure according to Example 2 further includes: an insulating support layer located between the ferroelectric layer and the cavity, wherein the IDV penetrates the first die and the insulating support layer to be electrically connected to the second die.

[0113] Example 6. The semiconductor structure according to Example 1, wherein the first die includes a plurality of cavities exposed from the upper surface of the first die, the second die has a plurality of memory elements including the memory elements, and a ferroelectric layer of each of the plurality of memory elements is located directly above each of the plurality of cavities.

[0114] Example 7. The semiconductor structure according to Example 1, wherein the IDV extends through the first die and the second die to electrically connect the CMOS device to the first electrode or the second electrode of the memory element.

[0115] Example 8. A semiconductor structure comprising:

[0116] A semiconductor die includes a dielectric structure having a cavity exposed from a top surface of the semiconductor die and an interconnect structure located below the cavity; and

[0117] A semiconductor device, stacked on a semiconductor die, includes a first conductive layer, a ferroelectric layer on the first conductive layer, and a second conductive layer on the ferroelectric layer, wherein, from a top view, the peripheral region of the ferroelectric layer is exposed by and surrounds the second conductive layer, and the ferroelectric layer is located directly above the cavity of the semiconductor die.

[0118] Example 9. The semiconductor structure according to Example 8, wherein the cavity is filled with air or an inert gas.

[0119] Example 10. The semiconductor structure according to Example 8 further includes: an insulating support layer located between the ferroelectric layer and the cavity, wherein the cavity is an enclosed space defined by the dielectric structure and the insulating support layer.

[0120] Example 11. The semiconductor structure according to Example 10, wherein a portion of the bottom surface of the insulating support layer defines a curved upper surface of the cavity.

[0121] Example 12. The semiconductor structure according to Example 10 further includes: an inter-die via (IDV) that penetrates the semiconductor die and the insulating support layer to electrically connect the interconnect structure of the semiconductor die to the semiconductor device.

[0122] Example 13. The semiconductor structure according to Example 12, wherein the IDV extends along one side of the cavity and is spaced apart from that side of the cavity.

[0123] Example 14. The semiconductor structure according to Example 8 further includes: a plurality of semiconductor devices, the plurality of semiconductor devices including the semiconductor devices stacked on the semiconductor die, the dielectric structure having a plurality of cavities, and a ferroelectric layer of each of the plurality of semiconductor devices being located directly above each of the plurality of cavities.

[0124] Example 15. The semiconductor structure according to Example 8, wherein the semiconductor device is located entirely within the projection of the cavity when viewed from a top view.

[0125] Example 16. A method for manufacturing a semiconductor structure, comprising:

[0126] Provide a first wafer including CMOS devices;

[0127] A second wafer including a ferroelectric memory is provided, wherein the ferroelectric memory includes a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, from a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode;

[0128] A recess is formed in the first wafer, the recess being exposed from the upper surface of the first wafer; and

[0129] The second wafer is bonded to the upper surface of the first wafer to form a cavity defined by the ferroelectric memory and the recess of the first wafer.

[0130] Example 17. The method according to Example 16 further includes:

[0131] The ferroelectric memory is formed on an insulating support layer before the second wafer is bonded to the upper surface of the first wafer, wherein, after the second wafer is bonded to the upper surface of the first wafer, the cavity is defined by the insulating support layer and a recess in the first wafer.

[0132] Example 18. The method according to Example 17 further includes:

[0133] A sacrificial layer is formed on the carrier;

[0134] The insulating support layer is formed on the sacrificial layer, wherein the ferroelectric memory is formed on the insulating support layer after the insulating support layer is formed on the sacrificial layer;

[0135] The carrier is removed by grinding to expose the sacrificial layer; and

[0136] The sacrificial layer is removed by etching to expose the insulating support layer.

[0137] Example 19. The method according to Example 18 further includes:

[0138] The insulating support layer is bonded to the upper surface of the first wafer.

[0139] Example 20. The method according to Example 17 further includes:

[0140] The insulating support layer is formed on the carrier, wherein the ferroelectric memory is formed on the insulating support layer after the insulating support layer is formed on the carrier;

[0141] The carrier is partially removed by grinding; and

[0142] The carrier is removed by chemical mechanical polishing to expose the insulating support layer.

Claims

1. A semiconductor structure, comprising: The first die includes an interconnect structure and a CMOS device electrically connected to the interconnect structure; A second die includes a memory element comprising a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, from a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode; and Inter-die vias (IDVs) electrically connect the interconnect structure of the first die to the memory element of the second die. The first die has a cavity located above the interconnect structure, exposed by the upper surface of the first die, and located directly below the ferroelectric layer.

2. The semiconductor structure according to claim 1, wherein, The ferroelectric layer has curvature, and the curvature is at least partially transmitted to the upper surface of the cavity closest to the ferroelectric layer.

3. The semiconductor structure according to claim 1, wherein, The projection of the ferroelectric layer is completely within the projection of the cavity when viewed from above.

4. The semiconductor structure according to claim 1, further comprising: An insulating support layer is located between the ferroelectric layer and the cavity, wherein the IDV penetrates the first die and the insulating support layer to be electrically connected to the second die.

5. The semiconductor structure according to claim 1, wherein, The first die includes a plurality of cavities exposed from the upper surface of the first die, and the second die has a plurality of memory elements including the memory elements, and the ferroelectric layer of each of the plurality of memory elements is located directly above each of the plurality of cavities.

6. The semiconductor structure according to claim 1, wherein, The IDV passes through the first die and the second die to electrically connect the CMOS device to the first electrode or the second electrode of the memory element.

7. A semiconductor structure comprising: A semiconductor die includes a dielectric structure having a cavity exposed from a top surface of the semiconductor die and an interconnect structure located below the cavity; as well as A semiconductor device, stacked on a semiconductor die, includes a first conductive layer, a ferroelectric layer on the first conductive layer, and a second conductive layer on the ferroelectric layer, wherein, from a top view, the peripheral region of the ferroelectric layer is exposed by and surrounds the second conductive layer, and the ferroelectric layer is located directly above the cavity of the semiconductor die.

8. The semiconductor structure according to claim 7, wherein, The cavity is filled with air or inert gas.

9. The semiconductor structure according to claim 7, further comprising: An insulating support layer is located between the ferroelectric layer and the cavity, wherein the cavity is a closed space defined by the dielectric structure and the insulating support layer.

10. The semiconductor structure according to claim 9, wherein, A portion of the bottom surface of the insulating support layer defines the curved upper surface of the cavity.

11. The semiconductor structure according to claim 9, further comprising: Inter-die vias (IDVs) penetrate the semiconductor die and the insulating support layer to electrically connect the interconnect structure of the semiconductor die to the semiconductor device.

12. The semiconductor structure according to claim 11, wherein, The IDV extends along one side of the cavity and is spaced apart from that side of the cavity.

13. The semiconductor structure according to claim 7, further comprising: A plurality of semiconductor devices, the plurality of semiconductor devices including semiconductor devices stacked on the semiconductor die, the dielectric structure having a plurality of cavities, and a ferroelectric layer of each of the plurality of semiconductor devices being located directly above each of the plurality of cavities.

14. The semiconductor structure according to claim 7, wherein, The semiconductor device is located entirely within the projection of the cavity when viewed from above.

15. A method for manufacturing a semiconductor structure, comprising: Provide a first wafer including CMOS devices; A second wafer including a ferroelectric memory is provided, wherein the ferroelectric memory includes a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein, from a top view, a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode; A recess is formed in the first wafer, the recess being exposed from the upper surface of the first wafer; and The second wafer is bonded to the upper surface of the first wafer to form a cavity defined by the ferroelectric memory and the recess of the first wafer.

16. The method of claim 15, further comprising: The ferroelectric memory is formed on an insulating support layer before the second wafer is bonded to the upper surface of the first wafer, wherein, after the second wafer is bonded to the upper surface of the first wafer, the cavity is defined by the insulating support layer and a recess in the first wafer.

17. The method of claim 16, further comprising: A sacrificial layer is formed on the carrier; The insulating support layer is formed on the sacrificial layer, wherein the ferroelectric memory is formed on the insulating support layer after the insulating support layer is formed on the sacrificial layer; The carrier is removed by grinding to expose the sacrificial layer; and The sacrificial layer is removed by etching to expose the insulating support layer.

18. The method of claim 17, further comprising: The insulating support layer is bonded to the upper surface of the first wafer.

19. The method of claim 16, further comprising: The insulating support layer is formed on the carrier, wherein the ferroelectric memory is formed on the insulating support layer after the insulating support layer is formed on the carrier; The carrier is partially removed by grinding; and The carrier is removed by chemical mechanical polishing to expose the insulating support layer.

Images