Electrostatic discharge circuit, display substrate, and display device

Abstract

An electrostatic discharge circuit includes a first voltage line, a second voltage line, and a plurality of transistors. The first voltage line provides a first voltage signal that is greater than a second voltage signal provided by the second voltage line. The plurality of transistors are connected in series between the first voltage line and the second voltage line. At least one transistor of the plurality of transistors is an oxide thin film transistor that includes a top gate and a bottom gate, the bottom gate being electrically connected to a third voltage line. The first voltage signal provided by the first voltage line is greater than a third voltage signal provided by the third voltage line.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an electrostatic discharge circuit, a display substrate, and a display device. Background Technology

[0002] Electrostatic discharge (ESD) is a common phenomenon during the manufacturing and transportation of display panels. When ESD occurs, a large current is generated in a very short time, which can easily cause electrostatic damage, such as dielectric breakdown and short circuits in transistors. Therefore, ESD circuits need to be incorporated into display panels. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides an electrostatic discharge circuit, a display substrate, and a display device.

[0005] In one embodiment, this disclosure provides an electrostatic discharge circuit, including: a first voltage line, a second voltage line, and a plurality of transistors. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line. The plurality of transistors are connected in series between the first voltage line and the second voltage line. At least one of the plurality of transistors is an oxide thin-film transistor, which includes a top gate and a bottom gate, and the bottom gate of the oxide thin-film transistor is electrically connected to a third voltage line. The first voltage signal provided by the first voltage line is greater than the third voltage signal provided by the third voltage line.

[0006] In some exemplary embodiments, the third voltage signal provided by the third voltage line is less than the second voltage signal provided by the second voltage line.

[0007] In some exemplary embodiments, all transistors in the electrostatic discharge circuit are oxide thin-film transistors, and are N-type transistors.

[0008] In some exemplary embodiments, the electrostatic discharge circuit includes four oxide thin-film transistors (OTCs) connected in series, wherein the first terminal of the first OTC CTC is electrically connected to the first voltage line, the second terminal and top gate of the i-th OTC CTC are electrically connected to the first terminal of the (i+1)-th OTC CTC, and the second terminal of the fourth OTC CTC is electrically connected to the second voltage line, where i is a positive integer greater than or equal to 1 and less than 4. The bottom gates of all four OTC CTCs are electrically connected to the third voltage line; the top gate and second terminal of the second OTC CTC and the first terminal of the third OTC CTC are all electrically connected to a signal input terminal.

[0009] In some exemplary embodiments, the electrostatic discharge circuit includes two oxide thin-film transistors connected in series. The first terminal of one oxide thin-film transistor is electrically connected to the first voltage line, the top gate and the second terminal of the oxide thin-film transistor are electrically connected to the first terminal and the signal input terminal of the other oxide thin-film transistor, and the second terminal of the other oxide thin-film transistor is electrically connected to the second voltage line; the bottom gates of both oxide thin-film transistors are electrically connected to the third voltage line.

[0010] On the other hand, embodiments of this disclosure provide a display substrate, including: a substrate and at least one signal line and at least one electrostatic discharge circuit disposed on the substrate. The substrate includes a display area and a peripheral area located on at least one side of the display area. The at least one signal line and at least one electrostatic discharge circuit are located in the peripheral area. Each electrostatic discharge circuit is connected between a first voltage line and a second voltage line and is electrically connected to a signal line, configured to provide an electrostatic discharge path for the signal line. The electrostatic discharge circuit includes at least one oxide thin-film transistor. The oxide thin-film transistor includes an active layer, a bottom gate, and a top gate, the bottom gate being located on the side of the active layer closer to the substrate, the top gate being located on the side of the active layer farther from the substrate, and the bottom gate being electrically connected to a third voltage line. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line and greater than a third voltage signal provided by the third voltage line.

[0011] In some exemplary embodiments, the orthographic projection of the top gate of the oxide thin-film transistor onto the substrate is located within the orthographic projection range of the bottom gate onto the substrate.

[0012] In some exemplary embodiments, the bottom gates of the plurality of oxide thin-film transistors of the at least one electrostatic discharge circuit are integral structures.

[0013] In some exemplary embodiments, the first voltage line, the second voltage line, and the third voltage line are located on the side of the top gate of the oxide thin-film transistor away from the substrate.

[0014] In some exemplary embodiments, the display area is characterized by having multiple data lines; the display substrate includes multiple signal lines and multiple electrostatic discharge circuits, the multiple signal lines including multiple data leads; the multiple data leads are electrically connected to the multiple data lines respectively. The multiple electrostatic discharge circuits include multiple first electrostatic discharge circuits; at least one data lead is electrically connected to at least one first electrostatic discharge circuit; the at least one first electrostatic discharge circuit is adjacent to the connected data lead in a first direction, the first electrostatic discharge circuit includes multiple oxide thin-film transistors, the multiple oxide thin-film transistors of the first electrostatic discharge circuit are arranged along a second direction, and the first direction intersects the second direction.

[0015] In some exemplary embodiments, the plurality of data leads include a plurality of sets of data leads, at least one set of data leads including two adjacent data leads disposed in different layers, wherein the orthographic projections of the two data leads on the substrate do not overlap.

[0016] In some exemplary embodiments, the first electrostatic discharge circuit electrically connected to each of the two data leads in the at least one set of data leads is located between the two data leads, adjacent in the second direction, and electrically connected to the same first voltage line.

[0017] In some exemplary embodiments, the first electrostatic discharge circuits electrically connected to each of the two data leads in the at least one set of data leads are symmetrically arranged about the first voltage line.

[0018] In some exemplary embodiments, one of the at least one set of data leads is in the same layer as the bottom gate of the oxide thin film transistor of the connected first electrostatic discharge circuit, and the other data lead is located on the side of the bottom gate of the oxide thin film transistor closer to the substrate.

[0019] In some exemplary embodiments, the display substrate includes multiple signal lines and multiple electrostatic discharge circuits. The multiple signal lines include multiple drive leads, and the multiple electrostatic discharge circuits include multiple second electrostatic discharge circuits. At least one drive lead is electrically connected to at least two second electrostatic discharge circuits. An array of at least two second electrostatic discharge circuits electrically connected to one drive lead is arranged.

[0020] In some exemplary embodiments, at least two second electrostatic discharge circuits electrically connected to a drive lead are symmetrically arranged about the drive lead.

[0021] In some exemplary embodiments, the display substrate includes multiple signal lines and multiple electrostatic discharge circuits. The multiple signal lines include multiple drive signal lines. The multiple electrostatic discharge circuits include multiple third electrostatic discharge circuits. At least one drive signal line is electrically connected to at least one third electrostatic discharge circuit. The third electrostatic discharge circuit includes four oxide thin-film transistors connected in series, and the four oxide thin-film transistors are arranged in an array.

[0022] In some exemplary embodiments, the display substrate further includes: at least one auxiliary resistor trace located in the peripheral region; at least one signal line including: a first trace and a second trace, the first trace being electrically connected to the at least one electrostatic discharge circuit, the second trace being located on the side of the first trace closer to the display region, and the first trace and the second trace being electrically connected through the auxiliary resistor trace.

[0023] In some exemplary embodiments, the orthogonal projection of the at least one auxiliary resistor trace onto the substrate is a serpentine trace.

[0024] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0025] On the other hand, embodiments of this disclosure provide a display substrate, including: a substrate, at least one signal line, and at least one electrostatic discharge (ESD) circuit. The substrate includes a display area and a peripheral area located on at least one side of the display area. The at least one signal line and at least one ESD circuit are located in the peripheral area. Each ESD circuit includes a plurality of transistors connected in series between a first voltage line and a second voltage line. At least one of the plurality of transistors is an oxide thin-film transistor (OST). The OST includes a top gate and a bottom gate, and the bottom gate of the OST is electrically connected to a third voltage line. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line and greater than a third voltage signal provided by the third voltage line. A signal line is electrically connected to at least one ESD circuit, and the signal line is configured to release static electricity through the at least one ESD circuit; the plurality of transistors within the at least one ESD circuit electrically connected to the signal line are arranged in an array, or the plurality of ESD circuits electrically connected to the signal line are arranged in an array.

[0026] In some exemplary embodiments, the display substrate includes multiple signal lines and multiple electrostatic discharge circuits. The multiple signal lines include multiple data leads. The display area is provided with multiple data lines. The multiple data leads are electrically connected to the multiple data lines respectively. The multiple electrostatic discharge circuits include multiple first electrostatic discharge circuits, and at least one data lead is electrically connected to at least one first electrostatic discharge circuit. The first electrostatic discharge circuit includes multiple oxide thin-film transistors, and the multiple oxide thin-film transistors are arranged in an array on one side of the connected data leads.

[0027] In some exemplary embodiments, the plurality of signal lines further include a plurality of drive leads, and the plurality of electrostatic discharge circuits further include a plurality of second electrostatic discharge circuits; the plurality of second electrostatic discharge circuits are located on the side of the plurality of first electrostatic discharge circuits away from the display area. At least one drive lead is electrically connected to at least two second electrostatic discharge circuits, and the at least two second electrostatic discharge circuits electrically connected by one drive lead are arranged in an array. At least one second electrostatic discharge circuit includes a plurality of oxide thin-film transistors, and the plurality of oxide thin-film transistors are arranged in an array on one side of the connected drive lead.

[0028] In some exemplary embodiments, the display substrate further includes: at least one auxiliary resistor trace located in the peripheral region; at least one signal line including: a first trace and a second trace, the first trace being electrically connected to the at least one electrostatic discharge circuit, the second trace being located on the side of the first trace closer to the display region, and the first trace and the second trace being electrically connected through the auxiliary resistor trace.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0031] Figure 1A and Figure 1B This is a schematic diagram of the working principle of an oxide thin-film transistor.

[0032] Figure 2 This is a schematic diagram of the working principle of an oxide thin-film transistor according to at least one embodiment of the present disclosure;

[0033] Figure 3 This is a circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0034] Figure 4 This is another circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0035] Figure 5 This is a plan view of a display substrate according to at least one embodiment of the present disclosure;

[0036] Figure 6 A circuit diagram of a first electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0037] Figure 7 This is a partial top view of the first border region according to at least one embodiment of the present disclosure;

[0038] Figure 8 for Figure 7 A partial cross-sectional view along the Q-Q' direction;

[0039] Figure 9A for Figure 7 A planar schematic diagram of the first border region after the formation of the first conductive layer;

[0040] Figure 9B for Figure 7A planar schematic diagram of the first border region after the formation of the second conductive layer;

[0041] Figure 9C for Figure 7 A planar schematic diagram of the first border region after the semiconductor layer has been formed.

[0042] Figure 9D for Figure 7 A planar schematic diagram of the first border region after the formation of the third conductive layer;

[0043] Figure 9E for Figure 7 A plan view of the first border region after the fourth insulating layer is formed;

[0044] Figure 10A This is another partial top view of the first border region of at least one embodiment of the present disclosure;

[0045] Figure 10B for Figure 10A A planar schematic diagram of the first border region after the formation of the second conductive layer;

[0046] Figure 10C for Figure 10A A plan view of the first border region after the fourth insulating layer is formed;

[0047] Figure 11 A circuit diagram of a second electrostatic discharge circuit electrically connected to the drive lead wires according to at least one embodiment of this disclosure;

[0048] Figure 12A This is another partial top view of the first border region of at least one embodiment of the present disclosure;

[0049] Figure 12B for Figure 12A A planar schematic diagram of the first border region after the formation of the second conductive layer;

[0050] Figure 12C for Figure 12A A planar schematic diagram of the first border region after the semiconductor layer has been formed.

[0051] Figure 12D for Figure 12A A planar schematic diagram of the first border region after the formation of the third conductive layer;

[0052] Figure 12E for Figure 12A A plan view of the first border region after the fourth insulating layer is formed;

[0053] Figure 13 Another circuit diagram of a second electrostatic discharge circuit electrically connected to the drive lead wires, which is at least one embodiment of this disclosure;

[0054] Figure 14A This is another partial top view of the first border region of at least one embodiment of the present disclosure;

[0055] Figure 14B for Figure 14A A planar schematic diagram of the first border region after the formation of the second conductive layer;

[0056] Figure 14C for Figure 14A A planar schematic diagram of the first border region after the semiconductor layer has been formed;

[0057] Figure 14D for Figure 14A A planar schematic diagram of the first border region after the formation of the third conductive layer;

[0058] Figure 14E for Figure 14A A plan view of the first border region after the fourth insulating layer is formed;

[0059] Figure 15 A circuit diagram of a third electrostatic discharge circuit electrically connected to the drive signal line for at least one embodiment of this disclosure;

[0060] Figure 16A This is a partial top view of the third border region of at least one embodiment of the present disclosure;

[0061] Figure 16B for Figure 16A A planar schematic diagram of the third border region after the formation of the second conductive layer;

[0062] Figure 16C for Figure 16A A planar schematic diagram of the third border region after the semiconductor layer has been formed.

[0063] Figure 16D for Figure 16A A planar schematic diagram of the third border region after the formation of the third conductive layer;

[0064] Figure 16E for Figure 16A A plan view of the third border region after the fourth insulating layer is formed;

[0065] Figure 17 This is another partial top view of the first border region of at least one embodiment of the present disclosure;

[0066] Figure 18 for Figure 17 A schematic diagram of the auxiliary resistor routing in the circuit;

[0067] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0068] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0069] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0070] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0071] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0072] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0073] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0074] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0075] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0076] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0077] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0078] In this disclosure, "approximately" and "roughly" refer to situations where the limits are not strictly defined, allowing for errors in the process and measurement. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%. In this disclosure, "symmetric" refers to situations where the limits are not strictly defined, allowing for approximately symmetry within the range of errors in the process and measurement.

[0079] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0080] In this disclosure, a serpentine routing refers to a type of zigzag curve. For example, one end of the routing extends a certain distance in one direction, then bends and meanders to extend a certain distance in the opposite direction, then bends and meanders again to extend in the same direction, and so on, repeating this bend and meandering several times to form a serpentine routing.

[0081] In some implementations, oxide thin-film transistors (OTTFTs) are gradually becoming the main material for next-generation display devices due to their fast response speed and high switching current ratio. However, OTFTs are N-type transistors, operating in the accumulation region, making it difficult to achieve a positive threshold voltage (Vth), which has delayed the widespread application of OTFTs.

[0082] Figure 1A and Figure 1B This is a schematic diagram illustrating the working principle of an oxide thin-film transistor. In some examples, such as... Figure 1A and Figure 1B As shown, an oxide thin-film transistor may include an active layer 100, a gate 103, a source 101, and a drain 102. A first gate insulator (GI) layer 104 is disposed between the active layer 100 and the gate 103. The active layer 100 may be made of a metal oxide material, such as indium gallium zinc oxide (IGZO).

[0083] like Figure 1A As shown, when the threshold voltage Vth of the oxide thin-film transistor is greater than 0, since IGZO itself is an N-type semiconductor, the oxide thin-film transistor operates in the carrier accumulation region when it is turned on, and the carriers participating in current formation are electrons. When the gate-source voltage difference Vgs of the oxide transistor is 0, the gate-source voltage difference Vgs is less than the threshold voltage Vth, and the oxide thin-film transistor is in the off state. The carrier concentration at the interface between the gate insulating layer 104 and the active layer 100 (e.g., IGZO) is insufficient to form a current.

[0084] like Figure 1B As shown, when the threshold voltage Vth of the oxide thin film transistor is less than 0, and when the gate-source voltage difference Vgs = 0, the gate-source voltage difference Vgs is greater than the threshold voltage Vth, the oxide thin film transistor is in the turn-on state, and the carrier concentration at the interface between the gate insulating layer 104 and the active layer 100 (e.g., IGZO) can form a current.

[0085] Therefore, when both the threshold voltage Vth and the gate-source voltage difference Vgs of an oxide thin-film transistor (OTTFT) are less than 0V, the gate-source voltage difference Vgs may be greater than the threshold voltage Vth, causing the OTFT to remain in the on state. In some implementations, OTFTs are used in the electrostatic discharge (ESD) circuit of the display substrate. Due to the aforementioned problems with OTFTs, the stability of the ESD circuit can be easily affected, leading to defects in the display product.

[0086] This embodiment provides an electrostatic discharge circuit, a display substrate, and a display device, which helps to improve the performance of oxide thin-film transistors in the electrostatic discharge circuit, enhance the stability of the electrostatic discharge circuit, and thus improve the antistatic capability of the display substrate.

[0087] This embodiment provides an electrostatic discharge circuit, including: a first voltage line, a second voltage line, and a plurality of transistors. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line. The plurality of transistors are connected in series between the first and second voltage lines. At least one of the transistors is an oxide thin-film transistor (OTFT), which includes a top gate and a bottom gate. The bottom gate of the OTFT is electrically connected to a third voltage line. The first voltage signal provided by the first voltage line is greater than the third voltage signal provided by the third voltage line.

[0088] In this example, a series-connected transistor refers to a transistor whose first terminal is electrically connected to the second terminal of an adjacent transistor, or a transistor whose second terminal is electrically connected to the first terminal of an adjacent transistor.

[0089] The electrostatic discharge circuit provided in this embodiment uses an oxide thin-film transistor, and the bottom gate of the oxide thin-film transistor is electrically connected to the third voltage line. This can shift the threshold voltage of the oxide thin-film transistor to a positive value, so that the oxide transistor can be successfully turned off when the gate-source voltage difference is 0V, thereby enhancing the stability of the electrostatic discharge circuit.

[0090] In some examples, the magnitude of the third voltage signal can be determined based on the degree of offset of the threshold voltage of the oxide thin-film transistor. For example, the second voltage signal provided by the second voltage line can be different from the third voltage signal provided by the third voltage line. For example, the third voltage signal can be less than 0V. For example, the third voltage signal provided by the third voltage line can be less than the second voltage signal provided by the second voltage line. This example, by setting the third voltage signal to be less than the second voltage signal and the first voltage signal, makes the forward bias effect of the threshold voltage of the oxide thin-film transistor more pronounced.

[0091] Figure 2This is a schematic diagram illustrating the working principle of an oxide thin-film transistor according to at least one embodiment of the present disclosure. In some examples, such as... Figure 2 As shown, the oxide thin-film transistor of this example may include: an active layer 100, a top gate 103a, a bottom gate 103b, a source 101, and a drain 102. A first gate insulating layer 104 is disposed between the active layer 100 and the top gate 103a, and a second gate insulating layer 106 is disposed between the active layer 100 and the bottom gate 103b. The active layer 100 may be made of a metal oxide material, such as IGZO.

[0092] In some examples, such as Figure 2 As shown, when the threshold voltage Vth of the oxide thin-film transistor is less than 0 and the gate-source voltage difference Vgs is 0, the oxide thin-film transistor is in the on state, and the carrier concentration at the interface between the first gate insulating layer 104 and the active layer 100 can form a current. When the bottom gate 103b of the oxide thin-film transistor is connected to the third voltage line, the induced holes generated at the interface between the second gate insulating layer 106 and the active layer 100 can recombine with the electrons on the surface of the active layer 100. Since the active layer 100 is very thin, electrons at the interface between the first gate insulating layer 104 and the active layer 100 can diffuse to the interface between the second gate insulating layer 106 and the active layer 100, thereby reducing the number of electrons at the interface between the first gate insulating layer 104 and the active layer 100 to a level insufficient to form a current. In this way, by electrically connecting the bottom gate 103b to the third voltage line, the threshold voltage Vth can be made greater than 0, that is, the threshold voltage Vth is forward biased, so that when the gate-source voltage difference Vgs is 0, the oxide thin-film transistor can be in the off state. This example demonstrates how to successfully turn off an oxide thin-film transistor (OTTFT) when the gate-source voltage difference is zero by adjusting the threshold voltage of the OTFT to be forward biased.

[0093] Figure 3 This is a circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, such as... Figure 3As shown, the electrostatic discharge circuit may include four transistors connected in series, such as transistors TS1 to TS4. All four transistors may be N-type transistors and oxide thin-film transistors. Transistors TS1 to TS4 may each have a top gate and a bottom gate. The first terminal of the first transistor is electrically connected to the first voltage line PL1; the second terminal and top gate of the i-th transistor are electrically connected to the first terminal of the (i+1)-th transistor; and the second terminal of the fourth transistor is electrically connected to the second voltage line PL2, where i is a positive integer greater than or equal to 1 and less than 4. In other words, the top gate and second terminal of transistor TS1 are electrically connected to the first terminal of transistor TS2, and the first terminal of transistor TS1 is electrically connected to the first voltage line PL1; the top gate and second terminal of transistor TS2 are electrically connected to the first terminal of transistor TS3; the top gate and first terminal of transistor TS3 are electrically connected to the second terminal of transistor TS4; and the second terminal of the top gate of transistor TS4 is electrically connected to the second voltage line PL2. The signal input terminal XL is electrically connected to the top gate and second terminal of transistor TS2 and the first terminal of transistor TS3. The bottom gates of transistors TS1 to TS4 are all electrically connected to the third voltage line PL3.

[0094] In some examples, the first voltage line PL1 can continuously provide a first voltage signal VGH, for example, the first voltage signal VGH can be a constant high potential signal; the second voltage line PL2 can continuously provide a second voltage signal VGL1, for example, the second voltage signal VGL1 can be a constant low potential signal; and the third voltage line PL3 can continuously provide a third voltage signal VGL2, for example, the third voltage signal VGL2 can be a constant low potential signal. The first voltage signal VGH can be greater than the second voltage signal VGL1 and greater than the third voltage signal VGL2. The second voltage signal VGL1 can be greater than the third voltage signal VGL2. By electrically connecting the bottom gates of multiple oxide thin-film transistors to the third voltage line and providing a third voltage signal lower than the first voltage signal, the threshold voltage Vth of the oxide thin-film transistor can be forward biased, so that the oxide thin-film transistor can be in the off state when the gate-source voltage difference Vgs of the oxide thin-film transistor is 0. In this example, by adjusting the forward bias of the threshold voltage of the oxide thin-film transistor, the oxide thin-film transistor can be successfully turned off when the gate-source voltage difference is 0.

[0095] In some examples, when a momentary high voltage (e.g., 100V) occurs in the signal input terminal XL due to the accumulation of positive charge, transistors TS2 and TS1 can be turned on to release the positive charge through the first voltage line PL1; when a momentary low voltage (e.g., -100V) occurs in the signal input terminal XL due to the accumulation of negative charge, transistors ST3 and ST4 can be turned on to release the negative charge through the second voltage line PL2.

[0096] Figure 4This is another circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, such as... Figure 4 As shown, the electrostatic discharge circuit may include two transistors, TS5 and TS6, connected in series. Both transistors TS5 and TS6 may be N-type transistors and are oxide thin-film transistors. The top gate and second terminal of transistor TS5 are electrically connected to the first terminal of transistor TS6. The first terminal of transistor TS5 is electrically connected to a first voltage line, and the top gate and second terminal of transistor TS6 are electrically connected to a second voltage line PL2. The bottom gates of both transistors TS5 and TS6 are electrically connected to a third voltage line PL3. The signal input terminal XL is electrically connected to the top gate and second terminal of transistor TS5 and the first terminal of transistor TS6.

[0097] In this example, the first terminals of transistors TS5 and TS6 are both connected to their top gates, forming an equivalent diode connection. When a momentary high voltage occurs at the signal input terminal XL due to the accumulation of positive charge, transistor TS5 is effectively turned on, releasing the positive charge through the first voltage line PL1; conversely, when a momentary low voltage occurs at the signal input terminal XL due to the accumulation of negative charge, transistor TS6 is effectively turned on, releasing the negative charge through the second voltage line PL2.

[0098] In other examples, the electrostatic discharge (ESD) protection circuit may include a P-type transistor and an N-type transistor, where the N-type transistor is an oxide thin-film transistor. The top gate and drain of the N-type transistor are electrically connected and to a second voltage line; the gate and drain of the P-type transistor are electrically connected and to a first voltage line. The bottom gate of the N-type transistor may be electrically connected to a third voltage line. The signal input terminal may be electrically connected to the source of both the N-type and P-type transistors. When positive charge accumulates at the signal input terminal, causing the source potential of the P-type transistor to be higher than the first voltage signal VGH provided by the first voltage line, the P-type transistor can conduct to perform ESD discharge; when negative charge accumulates at the signal input terminal, causing the source potential of the N-type transistor to be lower than the second voltage signal VGL1 provided by the second voltage line, the N-type transistor can conduct to perform ESD discharge. However, this embodiment does not limit the number of oxide thin-film transistors in the ESD discharge circuit.

[0099] This embodiment also provides a display substrate, including: a substrate and at least one signal line and at least one electrostatic discharge circuit disposed on the substrate. The substrate includes a display area and a peripheral area located on at least one side of the display area. The at least one signal line and at least one electrostatic discharge circuit are located in the peripheral area. Each electrostatic discharge circuit is connected between a first voltage line and a second voltage line and is electrically connected to a signal line, configured to provide an electrostatic discharge path for the signal line. The electrostatic discharge circuit includes at least one oxide thin-film transistor. The oxide thin-film transistor includes an active layer, a bottom gate, and a top gate, the bottom gate being located on the side of the active layer closer to the substrate, the top gate being located on the side of the active layer farther from the substrate, and the bottom gate being electrically connected to a third voltage line. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line and greater than a third voltage signal provided by the third voltage line. For example, the second voltage signal provided by the second voltage line may be greater than the third voltage signal provided by the third voltage line.

[0100] The display substrate provided in this example, by electrically connecting the bottom gate of the oxide thin-film transistor in the electrostatic discharge circuit to the third voltage line, can shift the threshold voltage of the oxide thin-film transistor to a positive value, enabling the oxide transistor to be successfully turned off when the gate-source voltage difference is 0V. This improves the performance of the oxide thin-film transistor in the electrostatic discharge circuit, enhances the stability of the electrostatic discharge circuit, and thus improves the anti-static capability of the display substrate.

[0101] In some exemplary embodiments, the orthographic projection of the top gate of the oxide thin-film transistor onto the substrate can be located within the orthographic projection range of the bottom gate onto the substrate. In other words, the orthographic projection of the bottom gate of the oxide thin-film transistor onto the substrate can cover the orthographic projection of the top gate onto the substrate. This example, by setting the orthographic projection of the bottom gate of the oxide thin-film transistor onto the substrate to cover the orthographic projection of the top gate onto the substrate, can achieve light shielding of the channel region of the active layer of the oxide thin-film transistor, thereby ensuring the performance of the oxide thin-film transistor.

[0102] In some exemplary embodiments, the bottom gates of multiple oxide thin-film transistors in at least one electrostatic discharge circuit can be a single, integrated structure. This example, by integrating the bottom gates of multiple oxide thin-film transistors into a single structure, facilitates electrical connection to a third voltage line, reduces the number of vias between the transistors and the third voltage line, and improves the uniformity of the third voltage signal transmitted through the bottom gate.

[0103] In some exemplary embodiments, the display substrate may include multiple signal lines and multiple electrostatic discharge (ESD) circuits. For example, the multiple signal lines may include multiple data leads, and the multiple ESD circuits may include multiple first ESD circuits, with at least one data lead electrically connected to at least one first ESD circuit. Alternatively, the multiple signal lines may include multiple drive leads, and the multiple ESD circuits may include multiple second ESD circuits, with at least one drive lead electrically connected to at least two second ESD circuits. Another example is that the multiple signal lines may include multiple drive signal lines, and the multiple ESD circuits may include multiple third ESD circuits, with at least one drive signal line electrically connected to at least one third ESD circuit. This example improves the ESD immunity of the display substrate by providing corresponding ESD circuits for each of the multiple signal lines.

[0104] In some examples, the display substrate can be a liquid crystal display (LCD) substrate, an organic light-emitting diode (OLED) substrate, a plasma display panel (PDP), or an electrophoretic display panel (EPD). OLEDs are active-matrix light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, flexible display devices that use OLEDs as light-emitting devices and are controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0105] The following examples illustrate the solution of this embodiment. In these examples, an OLED display substrate is used as an example.

[0106] Figure 5 This is a plan view of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as... Figure 5As shown, the display substrate may include: a display area AA and a peripheral area BB located around the display area AA. The peripheral area BB may include: a first border area B1 and a second border area B2 located on opposite sides of the display area AA along the second direction Y, and a third border area B3 and a fourth border area B4 located on opposite sides of the display area AA along the first direction X. For example, the first border area B1 may be the bottom border of the display substrate, the second border area B2 may be the top border of the display substrate, the third border area B3 may be the left border of the display substrate, and the fourth border area B4 may be the right border of the display substrate. The two ends of the first border area B1 are connected to the third border area B3 and the fourth border area B4, and the two ends of the second border area B2 are also connected to the third border area B3 and the fourth border area B4.

[0107] In some examples, such as Figure 5 As shown, the display area AA can be a flat area comprising multiple sub-pixels PX that make up a pixel array, and these sub-pixels PX are configured to display moving or still images. The display area AA can be referred to as the effective area. In some examples, the display substrate can be a flexible substrate, and thus the display substrate can be deformable, such as rolled up, bent, folded, or rolled up.

[0108] In some examples, such as Figure 5 As shown, the display area AA may include at least multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a first direction X, and the multiple data lines DL may extend along a second direction Y. The orthogonal projections of the multiple gate lines GL and the multiple data lines DL on the substrate intersect to form multiple sub-pixel regions, each sub-pixel region containing one sub-pixel PX. The multiple data lines DL are electrically connected to the multiple sub-pixels PX, and the multiple data lines DL can be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL are electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL can be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals, or may include both scan signals and light emission control signals.

[0109] In some examples, such as Figure 5 As shown, the first direction X can be the extension direction of the grid line GL in the display area AA (row direction), and the second direction Y can be the extension direction of the data line DL in the display area AA (column direction). The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y can be perpendicular to each other.

[0110] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0111] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0112] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In other examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors.

[0113] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate—an LTPS+Oxide (LTPO) display substrate—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0114] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0115] In some examples, such as Figure 5 As shown, the first bezel area B1 of the display substrate may include: a fan-out routing area B11, a bending area B12, a first circuit area B13, and a signal access area B14, arranged sequentially along a direction away from the display area AA. The fan-out routing area B11 can be connected to the display area AA and may include at least: multiple data leads 111, multiple drive leads 112, a first power line, and a second power line. The first power line may be configured to connect to a high-potential power line of the display area AA, and the second power line may be configured to connect to a low-potential power line. The multiple data leads 111 may be electrically connected to multiple data lines DL of the display area AA, for example, they may be electrically connected one-to-one. The multiple data leads 111 may extend to the bending area B12 in a fan-out routing manner. The multiple drive leads 112 may extend to the third bezel area B3 and the fourth bezel area B4 and be electrically connected to the drive signal lines 113 in the third bezel area B3 and the fourth bezel area B4. Figure 5 The following example illustrates two drive signal lines 113 within the third border region B3 and two drive signal lines 113 within the fourth border region B4. This embodiment does not limit the number of drive signal lines. Multiple data leads 111 can extend to the first circuit region B13 through the bending region B12, and multiple drive leads 112 can extend to the first circuit region B13 through the bending region B12.

[0116] In some examples, such as Figure 5 As shown, the bending area B12 is connected between the fan-out routing area B11 and the first circuit area B13. The bending area B12 may include a composite insulating layer with grooves. The grooves may be configured to bend the first circuit area B13 and the signal access area B14 to the back of the display area AA.

[0117] In some examples, such as Figure 5 As shown, the first circuit region B13 may include at least a plurality of first electrostatic discharge circuits 21. The plurality of first electrostatic discharge circuits 21 may be electrically connected to a plurality of data leads 111; for example, each data lead 111 may be electrically connected to one first electrostatic discharge circuit 21. The first electrostatic discharge circuits 21 may be configured to eliminate static electricity on the data leads 111 to prevent electrostatic damage to the display substrate. In this example, by placing the first electrostatic discharge circuits 21 in the first circuit region B13, it is advantageous to reduce the size of the fan-out trace area B11 along the second direction Y, thereby facilitating a narrow bezel design for the display substrate. However, this embodiment is not limited to this. In other examples, a plurality of first electrostatic discharge circuits 21 may be placed in the fan-out trace area B11.

[0118] In some examples, such as Figure 5 As shown, the first circuit area B13 may further include multiple driver chip areas (e.g., four driver chip areas 11a, 11b, 11c, and 11d). The driver chip areas are located on the side of the first electrostatic discharge circuit 21 away from the bending area B12. The four driver chip areas may be arranged sequentially along the first direction X. Each driver chip area may be equipped with a driver chip (IC, Integrated Circuit), which can be electrically connected to the data line DL of the display area AA via data lead 111. The driver chip can be configured to generate the driving signal required to drive the sub-pixels and provide the driving signal to the data line DL of the display area AA. For example, the driving signal may be a data signal that drives the brightness of the sub-pixels.

[0119] In some examples, such as Figure 5 As shown, the signal access area B14 is connected to the first circuit area B13 and may include multiple bonding pin areas (e.g., four bonding pin areas 12a, 12b, 12c, and 12d), which may be arranged sequentially along a first direction X. Each bonding pin area may include multiple bonding pins. The multiple bonding pins may be configured to be bonded to at least one corresponding circuit board (e.g., a flexible printed circuit board (FPC)). The multiple bonding pins in a bonding pin area may be correspondingly connected to a driver chip in a driver chip area; for example, pins in the driver chip area may be electrically connected to bonding pins in the corresponding bonding pin area via pin connection lines.

[0120] In some examples, such as Figure 5As shown, the first circuit region B13 may further include multiple second electrostatic discharge circuits 22. Multiple second electrostatic discharge circuits 22 may be disposed on opposite sides of each driver chip region along the first direction X. The multiple second electrostatic discharge circuits 22 may be electrically connected to multiple drive leads 112, which may extend to the signal access region B14 and be electrically connected to the bonding pins of the signal access region B14 to be configured to receive drive signals (e.g., including start signals, clock signals, etc.). For example, one drive lead 112 may be electrically connected to multiple second electrostatic discharge circuits 22. In some examples, the multiple drive leads may include: a start signal lead for transmitting a start signal, and a clock signal lead for transmitting a clock signal.

[0121] In some examples, such as Figure 5 As shown, the output terminal of at least one drive lead 112 connected to multiple second electrostatic discharge circuits 22 can be electrically connected to the auxiliary resistor trace 25. By setting the auxiliary resistor trace 25, the voltage of the drive lead 112 can be stabilized.

[0122] In some examples, such as Figure 5 As shown, a first cutting area B5 may be provided on the side of the signal access area B14 away from the display area AA. The first cutting area B5 may contain multiple test pin groups 13 and multiple fourth electrostatic discharge circuits 24. The fourth electrostatic discharge circuits 24 may be located on the side of the test pin groups 13 closest to the display area AA. Each test pin group 13 may include multiple test pins arranged along a first direction X. The test pins may be configured to transmit signals during the lamp-lighting test phase. The test pins may be electrically connected to the bonding pins within the signal access area B14 via test transmission traces, which may also be electrically connected to the fourth electrostatic discharge circuits 24. The fourth electrostatic discharge circuits 24 may be configured to eliminate static electricity from the test transmission traces.

[0123] In some examples, during the fabrication of the display substrate, a display motherboard can be prepared first, and then the motherboard can be cut to divide it into multiple display substrates. Each display substrate can be used to form a single display device. Several inspections are required during the fabrication of the display substrate, one important of which is Cell Test (CT) Light-on, also known as ET Light-on inspection. ET Light-on inspection is performed before the display substrate is bonded to the circuit board. A detection signal is input to the display substrate, causing its sub-pixels to display color. A defect detection device then checks one or more sub-pixels to determine if they are in good condition, thus confirming the presence of defects in the display substrate. In this example, the first cutting area B5 will be removed during the cutting process after ET inspection.

[0124] In some examples, such as Figure 5As shown, the third border region B3 and the fourth border region B4 may each include a second circuit region, a power line region, a crack dam region, and a second cutting region sequentially arranged along the direction of the display region AA. The second circuit region may be connected to the display region AA and may include at least a gate driving circuit 30, which may be electrically connected to multiple gate lines GL in the display region AA. The power line region may be connected to the second circuit region and may include at least a low-level power line, which may extend in a direction parallel to the edge of the display region and be connected to the cathode of the display region AA. The crack dam region may be connected to the power line region and may include at least multiple cracks formed on the composite insulating layer. The second cutting region may be connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, which may be configured such that after all film layers of the display substrate are prepared, the cutting settings can be cut along the cutting grooves respectively.

[0125] In some examples, the first border area B1 to the fourth border area B4 can be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam can extend along a direction parallel to the edge of the display area to form a ring structure around the display area AA. The edge of the display area is the edge of the display area AA on the side closer to the first border area B1 to the fourth border area B4.

[0126] In some examples, such as Figure 5 As shown, the third frame region B3 and the fourth frame region B4 are further provided with a plurality of third electrostatic discharge circuits 23. At least one drive signal line 113 can be connected to at least one third electrostatic discharge circuit 23. For example, one drive signal line 113 can be electrically connected to two third electrostatic discharge circuits 23. The third electrostatic discharge circuit 23 connected to one drive signal line 113 in the third frame region B3 can be located in the region of the third frame region B3 adjacent to the first frame region B1, and in the region of the third frame region B3 adjacent to the second frame region B2. The drive signal line 113 can extend to the first frame region B1 and be electrically connected to the drive lead 112 in the first frame region B1. For example, the plurality of drive signal lines 113 in the third frame region B3 and the fourth frame region B4 can include at least one start signal line and a plurality of clock signal lines. The third electrostatic discharge circuit 23 can be configured to eliminate static electricity on the electrically connected drive signal lines 113 to prevent electrostatic damage to the display substrate.

[0127] Figure 6 This is a circuit diagram of a first electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, such as... Figure 6As shown, the first electrostatic discharge circuit may include four series-connected oxide thin-film transistors: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. All four transistors, from T1 to T4, are N-type transistors. The first terminal of the first transistor T1 is electrically connected to a first voltage line PL1, its top gate and second terminal are electrically connected to the first terminal of the second transistor T2, and its bottom gate is electrically connected to a third voltage line PL3. The top gate and second terminal of the second transistor T2 are electrically connected to the first terminal of the third transistor T3, and its bottom gate is electrically connected to the third voltage line PL3. The top gate and second terminal of the third transistor T3 are electrically connected to the first terminal of the fourth transistor T4, and its bottom gate is electrically connected to the third voltage line PL3. The top gate and second terminal of the fourth transistor T4 are electrically connected to a second voltage line PL2. The top gate and second terminal of the second transistor T2 and the first terminal of the third transistor T3 are electrically connected to a data lead 111.

[0128] Figure 7 This is a partial top view of the first border region of at least one embodiment of the present disclosure. Figure 7 A schematic diagram of a first electrostatic discharge circuit electrically connected by a data lead 111a is shown. Figure 8 for Figure 7 A partial cross-sectional view along the Q-Q' direction.

[0129] In some examples, such as Figure 8 As shown, in a direction perpendicular to the display substrate, the peripheral region of the display substrate may include at least: a substrate 500, and a first conductive layer 511, a first insulating layer 501, a second conductive layer 512, a second insulating layer 502, a semiconductor layer 510, a third insulating layer 503, a third conductive layer 513, a fourth insulating layer 504, and a fourth conductive layer 514 sequentially disposed on the substrate 500. The second conductive layer 512 may also be referred to as a first gate metal layer, and the third conductive layer 513 may also be referred to as a second gate metal layer. The second insulating layer 502 and the third insulating layer 503 may also be referred to as gate insulating layers. For example, the first insulating layer 501 to the fourth insulating layer 504 may all be inorganic insulating layers. However, this embodiment is not limited to this.

[0130] In some examples, the pixel circuitry of the display area of ​​the display substrate may consist only of oxide thin-film transistors. The film structure of the pixel circuitry in the display area may be similar to that of the circuitry in the surrounding area. A planarization layer, a light-emitting structure layer, and an encapsulation structure layer may be sequentially disposed on the side of the fourth conductive layer of the display area away from the substrate. The light-emitting structure layer may, for example, include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer may include the anode of a light-emitting element, and the anode may be disposed on the planarization layer. The pixel definition layer may be disposed on the anode layer and the planarization layer, and the pixel definition layer has pixel openings that expose at least a portion of the anode surface. The organic light-emitting layer is at least partially disposed within the pixel openings and is connected to the anode. The cathode is disposed on the organic light-emitting layer and is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the drive of the anode and cathode. The encapsulation structure layer may, for example, include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer. However, this embodiment is not limited thereto. In other examples, the pixel circuitry of the display area may include oxide thin-film transistors and low-temperature polycrystalline silicon thin-film transistors.

[0131] In some examples, the organic light-emitting layer may include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode. In some examples, the hole injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the hole blocking layers may be a common layer connected together. However, this embodiment is not limited in this respect.

[0132] Figure 9A for Figure 7 A planar schematic diagram of the first border region after the formation of the first conductive layer. Figure 9B for Figure 7 A planar schematic diagram of the first border region after the formation of the second conductive layer. Figure 9C for Figure 7 A planar schematic diagram of the first border region after the semiconductor layer is formed. Figure 9D for Figure 7 A planar schematic diagram of the first border region after the formation of the third conductive layer. Figure 9E for Figure 7 A planar schematic diagram of the first border region after the fourth insulating layer is formed.

[0133] In some examples, such as Figure 9AAs shown, the first conductive layer in the first border region may include a data lead 111a. The data lead 111a may extend at least along the second direction Y. Figure 9B As shown, the second conductive layer in the first frame region may include the bottom gates of multiple oxide thin-film transistors of the first electrostatic discharge circuit, such as the bottom gate T12 of the first transistor, the bottom gate T22 of the second transistor, the bottom gate T32 of the third transistor, and the bottom gate T42 of the fourth transistor. The bottom gates T12, T22, T32, and T42 of the first transistor may be an integral structure and arranged sequentially along the second direction Y, adjacent to the data lead 111a in the first direction X. The orthographic projection of the bottom gates of the multiple oxide thin-film transistors of the first electrostatic discharge circuit onto the substrate does not overlap with the orthographic projection of the data lead 111a onto the substrate.

[0134] In some examples, such as Figure 9C As shown, the semiconductor layer in the first border region may include: active layers of multiple oxide thin-film transistors of the first electrostatic discharge circuit, such as active layers T10 of the first transistor, T20 of the second transistor, T30 of the third transistor, and T40 of the fourth transistor. The active layers T10, T20, T30, and T40 of the first transistor may be a single structure and arranged sequentially along the second direction Y. For example, the single structure may be a strip-shaped structure extending along the second direction Y. The active layer T10 of the first transistor overlaps with the orthographic projection of the bottom gate T12 onto the substrate. The active layer T20 of the second transistor at least partially overlaps with the orthographic projection of the bottom gate T22 onto the substrate; for example, the orthographic projection of the active layer T20 of the second transistor onto the substrate may be located within the orthographic projection range of the bottom gate T22 onto the substrate. The orthographic projections of the active layer T30 of the third transistor and the bottom gate T32 onto the substrate at least partially overlap. For example, the orthographic projection of the active layer T30 of the third transistor onto the substrate may be located within the orthographic projection range of the bottom gate T32 onto the substrate. The orthographic projections of the active layer T40 of the fourth transistor onto the substrate and the orthographic projections of the bottom gate T42 onto the substrate may at least partially overlap.

[0135] In some examples, such as Figure 9DAs shown, the third conductive layer in the first border region may include the top gates of multiple oxide thin-film transistors of the first electrostatic discharge circuit, such as the top gate T11 of the first transistor T1, the top gate T21 of the second transistor T2, the top gate T31 of the third transistor T3, and the top gate T41 of the fourth transistor T4. The orthographic projections of the top gates T11, T21, T31, and T41 onto the substrate may all be rectangles of the same size. The top gates T11, T21, T31, and T41 may be arranged sequentially along the second direction Y. The orthographic projection of the top gate T11 of the first transistor T1 onto the substrate can fall within the orthographic projection range of the bottom gate T12 onto the substrate; the orthographic projection of the top gate T21 of the second transistor T2 onto the substrate can fall within the orthographic projection range of the bottom gate T22 onto the substrate; the orthographic projection of the top gate T31 of the third transistor T3 onto the substrate can fall within the orthographic projection range of the bottom gate T32 onto the substrate; and the orthographic projection of the top gate T41 of the fourth transistor T4 onto the substrate can fall within the orthographic projection range of the bottom gate T42 onto the substrate. In this example, the bottom gate of the oxide thin-film transistor can shield the overlapping area of ​​the active layer and the top gate, thus providing light shielding for the channel region and helping to ensure the performance of the oxide thin-film transistor.

[0136] In some examples, such as Figure 9E As shown, the fourth insulating layer in the first frame region may have multiple vias, for example, it may include first vias V1 to tenth vias V10. The fourth and third insulating layers in the first vias V1 to fifth vias V5 may be removed, exposing at least a portion of the surface of the semiconductor layer. The fourth insulating layer in the sixth vias V6 to ninth vias V9 may be removed, exposing at least a portion of the surface of the third conductive layer. The fourth, third, second, and first insulating layers in the tenth via V10 may be removed, exposing at least a portion of the surface of the first conductive layer.

[0137] In some examples, such as Figure 7As shown, the fourth conductive layer in the first frame region may include: a first voltage line PL1, a second voltage line (e.g., the second voltage line PL2a), and multiple connection electrodes (e.g., first connection electrode 401 to third connection electrode 403). The first voltage line PL1 can be electrically connected to one end of the active layer T10 of the first transistor T1 through a first via V1. The first connection electrode 401 can be electrically connected to the top gate T41 of the first transistor T1 through a sixth via V6, and can also be electrically connected to the connection end of the active layer T10 of the first transistor T1 and the active layer T20 of the second transistor T2 through a second via V2. The second connection electrode 402 can be electrically connected to the top gate T21 of the second transistor T2 through a seventh via V7, and can also be electrically connected to the connection end of the active layer T20 of the second transistor T2 and the active layer T30 of the third transistor T3 through a third via V3, and can also be electrically connected to the data lead 111a through a tenth via V10. The third connection electrode 403 can be electrically connected to the top gate T31 of the third transistor T3 through the eighth via V8, and can also be electrically connected to the connection terminal of the active layer T30 of the third transistor T3 and the active layer T40 of the fourth transistor T4 through the fourth via V4. The second voltage line PL2a can be electrically connected to the top gate T41 of the fourth transistor T4 through the ninth via V9, and can also be electrically connected to one end of the fourth active layer T40 through the fifth via V5.

[0138] Figure 10A This is another partial top view of the first border region of at least one embodiment of the present disclosure. Figure 10A The diagram illustrates six data leads and six first electrostatic discharge circuits that are electrically connected to each of the six data leads. Figure 10B for Figure 10A A planar schematic diagram of the first border region after the formation of the second conductive layer. Figure 10C for Figure 10A A planar schematic diagram of the first border region after the fourth insulating layer is formed.

[0139] In some examples, such as Figures 10A to 10CAs shown, the multiple data leads 111 in the first border region may include multiple sets of data leads. These multiple sets of data leads may be arranged sequentially along a first direction X. At least one set of data leads may include two adjacent data leads 111a and 111b disposed on different layers. For example, data lead 111a may be located in the first conductive layer, and data lead 111b may be located in the second conductive layer, i.e., it is in the same layer as the bottom gate of the oxide thin-film transistor of the first electrostatic discharge circuit. The orthogonal projections of data leads 111a and 111b within a set onto the substrate may not overlap. Data leads 111a and 111b may extend at least along a second direction Y. The first electrostatic discharge circuit 21a electrically connected to data lead 111a and the first electrostatic discharge circuit 21b electrically connected to data lead 111b within a set may be located between data leads 111a and 111b and arranged along the second direction Y. The first electrostatic discharge circuit 21a electrically connected to data lead 111a can be located on the side of the first electrostatic discharge circuit 21b electrically connected to data lead 111b that is away from the display area. No first electrostatic discharge circuit is provided between adjacent groups of data leads. In other words, a first electrostatic discharge circuit 21a electrically connected to a data lead 111a and a first electrostatic discharge circuit 21b electrically connected to a data lead 111b can be provided between a data lead 111a and an adjacent data lead 111b along the first direction X. No first electrostatic discharge circuit is provided between a data lead 111a and an adjacent data lead 111b along the other side of the first direction X; they can be directly adjacent.

[0140] In some examples, such as Figures 10A to 10C As shown, the fourth insulating layer in the first frame region may also be provided with multiple eleventh vias V11 and multiple twelfth vias V12. The integrated structure formed by the bottom gates of the four oxide thin-film transistors of the first electrostatic discharge circuit 21a can be electrically connected to a third voltage line PL3a through two vertically arranged eleventh vias V11. The integrated structure formed by the bottom gates of the four oxide thin-film transistors of the first electrostatic discharge circuit 21b can be electrically connected to another third voltage line PL3b through two vertically arranged twelfth vias V12. The film layer structures of the first electrostatic discharge circuit 21a and the second electrostatic discharge circuit 21b can be referred to... Figures 7 to 9E As shown, it will not be elaborated further here.

[0141] In some examples, such as Figure 10AAs shown, the first voltage line PL1, the second voltage lines PL2a and PL2b, and the third voltage lines PL3a and PL3b can be located in the fourth conductive layer. The first voltage lines PL1, PL2a and PL2b, and PL3a and PL3b can extend at least along the first direction X. The first electrostatic discharge circuits 21a and 21b are electrically connected to the same first voltage line PL1. The second voltage line PL2a connected to the first electrostatic discharge circuit 21a can be located on the side of the first voltage line PL1 away from the display area, and the third voltage line PL3a connected to the first electrostatic discharge circuit 21a can be located on the side of the second voltage line PL2a away from the first voltage line PL1. The second voltage line PL2b connected to the first electrostatic discharge circuit 21b can be located on the side of the first voltage line PL1 closer to the display area, and the third voltage line PL3b connected to the first electrostatic discharge circuit 21b can be located on the side of the second voltage line PL2b closer to the display area. The first electrostatic discharge circuit 21a, which is electrically connected to the data lead 111a within a group, and the first electrostatic discharge circuit 21b, which is electrically connected to the data lead 111b, can be symmetrically arranged about the first voltage line PL1.

[0142] The arrangement and layout of the first electrostatic discharge circuit in this example is beneficial for saving space and enabling a narrow bezel design for the display substrate. Arranging multiple data leads at intervals on different conductive layers can help reduce the spacing between adjacent data leads and reduce signal interference between them. However, this embodiment is not limited to this. In other examples, multiple data leads can be arranged on the same layer, for example, all located on the first conductive layer or the second conductive layer.

[0143] Figure 11 This is a circuit diagram of a second electrostatic discharge circuit electrically connected to the drive lead wires according to at least one embodiment of this disclosure. In some examples, such as... Figure 11As shown, a drive lead 112 can be electrically connected to two second electrostatic discharge circuits 22a and 22b. Second electrostatic discharge circuit 22a may include a fifth transistor T5A and a sixth transistor T6A, and second electrostatic discharge circuit 22b may include a fifth transistor T5B and a sixth transistor T6B. The first terminal of the fifth transistor T5A is electrically connected to the first voltage line PL1, the top gate and second terminal of the fifth transistor T5A are electrically connected to the first terminal of the sixth transistor T6A, and the top gate and second terminal of the sixth transistor T6A are electrically connected to the second voltage line PL2. The first terminal of the fifth transistor T5B is electrically connected to the first voltage line PL1, the top gate and second terminal of the fifth transistor T5B are electrically connected to the first terminal of the sixth transistor T6B, and the top gate and second terminal of the sixth transistor T6B are electrically connected to the second voltage line PL2. The drive lead 112 is electrically connected to the top gate and second terminal of the fifth transistor T5A, the first terminal of the sixth transistor T6A, the top gate and second terminal of the fifth transistor T5B, and the first terminal of the sixth transistor T6B. The bottom gates of the fifth transistors T5A and T5B, and the bottom gates of the sixth transistors T6A and T6B, are all electrically connected to the third voltage line PL3.

[0144] Figure 12A This is another partial top view of the first border region of at least one embodiment of the present disclosure. Figure 12A The diagram illustrates two second electrostatic discharge circuits electrically connected to a drive lead. Figure 12B for Figure 12A A planar schematic diagram of the first border region after the formation of the second conductive layer.

[0145] Figure 12C for Figure 12A A planar schematic diagram of the first border region after the semiconductor layer is formed. Figure 12D for Figure 12A A planar schematic diagram of the first border region after the formation of the third conductive layer. Figure 12E for Figure 12A A planar schematic diagram of the first border region after the fourth insulating layer is formed.

[0146] In some examples, such as Figure 12A As shown, the two second electrostatic discharge circuits 22a and 22b electrically connected to the drive signal line 112 can be arranged along the first direction X and can be symmetrically arranged about the drive signal line 112.

[0147] In some examples, such as Figure 12BAs shown, the second conductive layer in the first frame region may include: the bottom gate of the oxide thin-film transistor of the second electrostatic discharge circuit (e.g., including: the bottom gate T52A of the fifth transistor and the bottom gate T62A of the sixth transistor of the second electrostatic discharge circuit 22a, and the bottom gate T52B of the fifth transistor and the bottom gate T62B of the sixth transistor of the second electrostatic discharge circuit 22b), and a first connection line 551. The bottom gates T52A and T62A of the fifth transistor of the second electrostatic discharge circuit 22a, the bottom gates T52B and T62B of the fifth transistor of the second electrostatic discharge circuit 22b, and the first connection line 551 may be an integral structure. The first connection line 551 may extend at least along the first direction X and be electrically connected to the third voltage line located in the fourth conductive layer. The bottom gates T52A and T62A of the fifth transistor in the second electrostatic discharge circuit 22a can be symmetrically arranged about the first connection line 551, and the bottom gates T52B of the fifth transistor and T62B of the sixth transistor in the second electrostatic discharge circuit 22b can be symmetrically arranged about the first connection line 551.

[0148] In some examples, such as Figure 12C As shown, the semiconductor layer in the first frame region may include: the active layer of the oxide thin-film transistor of the second electrostatic discharge circuit (e.g., including the active layer T50A of the fifth transistor and the active layer T60A of the sixth transistor of the second electrostatic discharge circuit 22a, and the active layer T50B of the fifth transistor and the active layer T60B of the sixth transistor of the second electrostatic discharge circuit 22b), and a plurality of oxide interconnects (e.g., including the first oxide interconnect 601 to the fourth oxide interconnect 604). The active layers T50A and T60A of the fifth transistor of the second electrostatic discharge circuit 22a may be symmetrically arranged with respect to the first connection line 551, and the active layers T50B and T60B of the fifth transistor of the second electrostatic discharge circuit 22b may be symmetrically arranged with respect to the first connection line 551. Taking the active layer T50A of the fifth transistor in the second electrostatic discharge circuit 22a as an example, the active layer T50A can be approximately rectangular and has a strip-shaped groove. This strip-shaped groove extends, for example, along the first direction X. The orthographic projection of this strip-shaped groove onto the substrate can overlap with the orthographic projection of the bottom gate T52A onto the substrate, for example, it can be located within the orthographic projection range of the bottom gate T52A onto the substrate. In this example, by providing a strip-shaped groove in the active layer, the width of the active layer can be reduced (for example, the length of the active layer along the second direction Y can be less than 50 micrometers), avoiding the situation where the width of the active layer is too large, which would cause burning and affect the performance of the transistor.

[0149] In some examples, such as Figure 12CAs shown, the first oxide interconnect 601 can be located on the side of the active layer T50A of the fifth transistor away from the active layer T60A of the sixth transistor, and the second oxide interconnect 602 can be located on the side of the active layer T60A of the sixth transistor away from the active layer T60A of the fifth transistor. The third oxide interconnect 603 can be located on the side of the active layer T50B of the fifth transistor away from the active layer T60B of the sixth transistor, and the second oxide interconnect 604 can be located on the side of the active layer T60B of the sixth transistor away from the active layer T60B of the fifth transistor. The orthographic projection of the first oxide interconnect 601 to the fourth oxide interconnect 604 onto the substrate can all be serpentine traces. By setting the oxide interconnects to a serpentine trace configuration, it is beneficial to increase the resistance of the oxide interconnects.

[0150] In some examples, such as Figure 12D As shown, the third conductive layer in the first frame region may further include: the top gate of the oxide thin-film transistor of the second electrostatic discharge circuit (e.g., including: the top gate T51A of the fifth transistor and the top gate T61A of the sixth transistor of the second electrostatic discharge circuit 22a, and the top gate T51B of the fifth transistor and the top gate T61B of the sixth transistor of the second electrostatic discharge circuit 22b), the second connecting line 552, and the third connecting line 553. The top gate T51A of the fifth transistor of the second electrostatic discharge circuit 22a and the top gate T51B of the fifth transistor of the second electrostatic discharge circuit 22b can be an integral structure. The orthogonal projection of this integral structure onto the substrate can be approximately "mountain" shaped, thereby preventing the second electrostatic discharge circuit from being burned due to excessive current concentration. The top gate T61A of the sixth transistor of the second electrostatic discharge circuit 22a and the top gate T61B of the sixth transistor of the second electrostatic discharge circuit 22b can also be an integral structure. The integrated structure of the top gate T51A of the fifth transistor in the second electrostatic discharge circuit 22a and the top gate T51B of the fifth transistor in the second electrostatic discharge circuit 22b, together with the integrated structure of the top gate T61A of the sixth transistor in the second electrostatic discharge circuit 22a and the top gate T61B of the sixth transistor in the second electrostatic discharge circuit 22b, can be symmetrically arranged about the first connection line 551. In this example, the top gates T51A, T51B, T61A, and T61B can adopt a dual-gate structure, which is beneficial for improving the stability of the oxide thin-film transistor.

[0151] In some examples, such as Figure 12DAs shown, the second connecting line 552 and the third connecting line 553 can extend at least along the first direction X. The second connecting line 552 can be located on the side of the second electrostatic discharge circuits 22a and 22b closer to the display area, and the third connecting line 553 can be located on the side of the second electrostatic discharge circuits 22a and 22b away from the display area. The second connecting line 552 can be electrically connected to the second voltage line located on the fourth conductive layer, and the third connecting line 553 can be electrically connected to the third voltage line located on the fourth conductive layer.

[0152] In some examples, such as Figure 12E As shown, the fourth insulating layer in the first frame region may also be provided with multiple vias, such as vias V21 to V44. The fourth and third insulating layers within vias V21 to V36 may be removed, exposing at least a portion of the surface of the semiconductor layer. The fourth insulating layer within vias V37 to V44 may be removed, exposing at least a portion of the surface of the third conductive layer.

[0153] In some examples, such as Figures 12A to 12EAs shown, the fourth conductive layer in the first frame region may include: a drive lead 112 and multiple connection electrodes (e.g., eleventh connection electrode 411 to eighteenth connection electrode 418). The eleventh connection electrode 411 can be electrically connected to one end of the active layer T60A of the sixth transistor T6A through multiple twenty-first vias V21, and can also be electrically connected to the first oxide connection block 601 through at least one twenty-third via V23, and can also be electrically connected to the second connection line 552 through multiple forty-first vias V41. The twelfth connection electrode 412 can be electrically connected to the top gate T61A of the sixth transistor T6A through a thirty-seventh via V37, and can also be electrically connected to the first oxide connection block 601 through a twenty-fourth via V24. The thirteenth connection electrode 413 can be electrically connected to one end of the active layer T60B of the sixth transistor T6B through multiple twenty-sixth vias V26, and can also be electrically connected to the third oxide connection block 603 through at least one twenty-eighth via V28, and can also be electrically connected to the second connection line 552 through multiple forty-second vias V42. The fourteenth connecting electrode 414 can be electrically connected to the top gate T61B of the sixth transistor T6B through the thirty-eighth via V38, and can also be electrically connected to the third oxide connecting block 603 through the twenty-seventh via V27. The fifteenth connecting electrode 415 can be electrically connected to one end of the active layer T50A of the fifth transistor T5A through multiple vertically arranged twenty-ninth vias V29, and can also be electrically connected to the third connecting line 553 through multiple forty-third vias V43. The sixteenth connecting electrode 416 can be electrically connected to the second oxide connecting block 602 through the thirty-first via V31, and can also be electrically connected to the top gate T51A of the fifth transistor T5A through the thirty-ninth via V39. The seventeenth connecting electrode 417 can be electrically connected to one end of the active layer T50B of the fifth transistor T5B through multiple vertically arranged thirty-fourth vias V34, and can also be electrically connected to the third connecting line 553 through multiple forty-fourth vias V44. The eighteenth connecting electrode 418 can be electrically connected to the fourth oxide connecting block 604 through the thirty-sixth via V36, and can also be electrically connected to the top gate T51B of the fifth transistor T5B through the fortieth via V40.

[0154] In some examples, such as Figures 12A to 12EAs shown, the drive lead 112 can be electrically connected to the other end of the active layer T60A of the sixth transistor T6A through multiple vertically arranged 22nd vias V22, and can also be electrically connected to the other end of the active layer T60B of the sixth transistor T6B through multiple vertically arranged 25th vias V25, and can also be electrically connected to the other end of the active layer T50A of the fifth transistor T5A through multiple vertically arranged 30th vias V30, and can also be electrically connected to the other end of the active layer T50B of the fifth transistor T5B through multiple vertically arranged 33rd vias V33, and can also be electrically connected to the first oxide connecting block 601 through the 32nd via V32, and can also be electrically connected to the third oxide connecting block 603 through the 35th via V35.

[0155] In this example, "vertical arrangement" refers to the arrangement along the second direction Y, and "horizontal arrangement" refers to the arrangement along the first direction X.

[0156] In this example, the fifth transistor T5A is electrically connected to the drive lead 112 via the first oxide connector 601, the fifth transistor T5B is electrically connected to the drive lead 112 via the third oxide connector 603, the sixth transistor T6A is electrically connected to the second voltage line PL2 via the second oxide connector 602, and the sixth transistor T6B is electrically connected to the second voltage line PL2 via the fourth oxide connector 604. By using oxide connectors, the resistance of the connection path can be increased, thereby protecting the components in the second electrostatic discharge circuit and preventing electrostatic discharge from occurring in the second electrostatic discharge circuit.

[0157] Figure 13 This is another circuit diagram of a second electrostatic discharge circuit electrically connected to the drive lead wires, representing at least one embodiment of this disclosure. In some examples, such as... Figure 13As shown, a drive lead 112 can be electrically connected to six second electrostatic discharge circuits 22c, 22d, 22e, 22f, 22g, and 22h. The second electrostatic discharge circuit 22c may include a fifth transistor T5C and a sixth transistor T6C. The top gate and second terminal of the fifth transistor T5C are electrically connected to the first terminal of the sixth transistor T6C and the drive lead 112. The first terminal of the fifth transistor T5C is electrically connected to the first voltage line PL1, and the top gate and second terminal of the sixth transistor T6C are electrically connected to the second voltage line PL2. The bottom gates of the fifth transistor T5C and the sixth transistor T6C are electrically connected to the third voltage line PL3. The second electrostatic discharge circuit 22d may include a fifth transistor T5D and a sixth transistor T6D; the second electrostatic discharge circuit 22e may include a fifth transistor T5E and a sixth transistor T6E; the second electrostatic discharge circuit 22f may include a fifth transistor T5F and a sixth transistor T6F; the second electrostatic discharge circuit 22g may include a fifth transistor T5G and a sixth transistor T6G; and the second electrostatic discharge circuit 22h may include a fifth transistor T5H and a sixth transistor T6H. The circuit structures of the second electrostatic discharge circuits 22d, 22e, 22f, 22g, and 22h are the same as those of the second electrostatic discharge circuit 22c, and therefore will not be described in detail here.

[0158] Figure 14A This is another partial top view of the first border region of at least one embodiment of the present disclosure. Figure 14A The diagram illustrates six second electrostatic discharge circuits electrically connected to a drive signal line. Figure 14B for Figure 14A A planar schematic diagram of the first border region after the formation of the second conductive layer.

[0159] Figure 14C for Figure 14A A planar schematic diagram of the first border region after the semiconductor layer is formed. Figure 14D for Figure 14A A planar schematic diagram of the first border region after the formation of the third conductive layer. Figure 14E for Figure 14A A planar schematic diagram of the first border region after the fourth insulating layer is formed.

[0160] In some examples, such as Figure 14AAs shown, the six second electrostatic discharge circuits electrically connected to the drive signal line 112 can be arranged in an array, for example, a 3×2 array. Second electrostatic discharge circuits 22c, 22e, and 22g can be arranged in a column along the second direction Y; second electrostatic discharge circuits 22d, 22f, and 22h can be arranged in a column along the second direction Y; second electrostatic discharge circuits 22c and 22d can be arranged in a row along the first direction X; second electrostatic discharge circuits 22e and 22f can be arranged in a row along the first direction X; and second electrostatic discharge circuits 22g and 22h can be arranged in a row along the first direction X. Second electrostatic discharge circuits 22c and 22d can be symmetrically arranged about the drive signal line 112; second electrostatic discharge circuits 22e and 22f can be symmetrically arranged about the drive signal line 112; and second electrostatic discharge circuits 22g and 22h can be symmetrically arranged about the drive signal line 112. The second electrostatic discharge circuits 22c and 22e can be arranged symmetrically about the fifth connection line 555, and the second electrostatic discharge circuits 22d and 22f can also be arranged symmetrically about the fifth connection line 555. The arrangement of the second electrostatic discharge circuits in this example can help save space.

[0161] In some examples, such as Figure 14BAs shown, the second conductive layer in the first frame region may include: the bottom gate of the oxide thin film transistor of the second electrostatic discharge circuit (e.g., including: the bottom gate T52C of the fifth transistor T5C and the bottom gate T62C of the sixth transistor T6C of the second electrostatic discharge circuit 22c; the bottom gate T52D of the fifth transistor T5D and the bottom gate T62D of the sixth transistor T6D of the second electrostatic discharge circuit 22d; the bottom gate T52E of the fifth transistor T5E and the bottom gate T62E of the sixth transistor T6E of the second electrostatic discharge circuit 22e; the bottom gate T52F of the fifth transistor T5F and the bottom gate T62F of the sixth transistor T6F of the second electrostatic discharge circuit 22f; the bottom gate T52G of the fifth transistor T5G and the bottom gate T62G of the sixth transistor T6G of the second electrostatic discharge circuit 22g; and the bottom gate T52H of the fifth transistor T5H and the bottom gate T62H of the sixth transistor T6H of the second electrostatic discharge circuit 22h). In this circuit, the bottom gates T52C of the fifth transistor T5C and T62C of the sixth transistor T6C in the second electrostatic discharge circuit 22c, the bottom gates T52D of the fifth transistor T5D and T62D of the sixth transistor T6D in the second electrostatic discharge circuit 22d, can be an integral structure; the bottom gates T52E of the fifth transistor T5E and T62E of the sixth transistor T6E in the second electrostatic discharge circuit 22e, the bottom gates T52F of the fifth transistor T5F and T62F of the sixth transistor T6F in the second electrostatic discharge circuit 22f, the bottom gates T52G of the fifth transistor T5G and T62G of the sixth transistor T6G in the second electrostatic discharge circuit 22g, and the bottom gates T52H of the fifth transistor T5H and T62H of the sixth transistor T6H in the second electrostatic discharge circuit 22h can be an integral structure. For example, the integral structure of the bottom gate of the oxide thin-film transistor in the second electrostatic discharge circuit can be electrically connected to the third voltage line located on the fourth conductive layer.

[0162] In some examples, such as Figure 14CAs shown, the semiconductor layer of the first frame region may include: the active layer of transistors of a plurality of second electrostatic discharge circuits, and a plurality of oxide interconnects (e.g., including the fifth oxide interconnect 605 to the fifteenth oxide interconnect 615). The active layers T50C of the fifth transistor T5C and T60C of the sixth transistor T6C in the second electrostatic discharge circuit 22c can be integrated into one structure; the active layers T50D of the fifth transistor T5D and T60D of the sixth transistor T6D in the second electrostatic discharge circuit 22d can be integrated into one structure; the active layers T50E of the fifth transistor T5E and T60E of the sixth transistor T6E in the second electrostatic discharge circuit 22e can be integrated into one structure; the active layers T50F of the fifth transistor T5F and T60F of the sixth transistor T6F in the second electrostatic discharge circuit 22f can be integrated into one structure; the active layers T50G of the fifth transistor T5G and T60G of the sixth transistor T6G in the second electrostatic discharge circuit 22g can be integrated into one structure; the active layers T50H of the fifth transistor T5H and T60H of the sixth transistor T6H in the second electrostatic discharge circuit 22h can be integrated into one structure. The fifth oxide connector 605 and the seventh oxide connector 607 can be symmetrically arranged with respect to the drive signal line; the sixth oxide connector 606 and the eighth oxide connector 608 can be symmetrically arranged with respect to the drive signal line; the ninth oxide connector 609 and the eleventh oxide connector 611 can be symmetrically arranged with respect to the drive signal line; the tenth oxide connector 610 and the twelfth oxide connector 612 can be symmetrically arranged with respect to the drive signal line; the fourteenth oxide connector 614 and the sixteenth oxide connector 616 can be symmetrically arranged with respect to the drive signal line; and the thirteenth oxide connector 613 and the fifteenth oxide connector 615 can be symmetrically arranged with respect to the drive signal line. In this example, oxide connectors are used in the electrical connection paths between the transistor and the drive leads and voltage lines. This increases the resistance of the connection paths, thereby protecting the components within the second electrostatic discharge circuit and preventing electrostatic discharge from occurring in the second electrostatic discharge circuit.

[0163] In some examples, such as Figure 14DAs shown, the third conductive layer in the first frame region may include: top gates of multiple second electrostatic discharge circuits and multiple connecting lines (e.g., fourth connecting line 554 to seventh connecting line 557). The top gate T61C of the sixth transistor T6C of the second electrostatic discharge circuit 22c and the top gate T61D of the sixth transistor T6D of the second electrostatic discharge circuit 22d can be an integral structure. The top gate T51C of the fifth transistor T5C of the second electrostatic discharge circuit 22c and the top gate T51D of the fifth transistor T5D of the second electrostatic discharge circuit 22d can also be an integral structure. The top gate T51E of the fifth transistor T5E of the second electrostatic discharge circuit 22e and the top gate T51F of the fifth transistor T5F of the second electrostatic discharge circuit 22f can also be an integral structure. The top gate T51G of the fifth transistor T5G in the second electrostatic discharge circuit 22g and the top gate T51H of the fifth transistor T5H in the second electrostatic discharge circuit 22h can be an integral structure; the top gate T61H of the sixth transistor T6H in the second electrostatic discharge circuit 22h and the top gate T61H of the sixth transistor T6H in the second electrostatic discharge circuit 22h can be an integral structure.

[0164] In some examples, such as Figure 14D As shown, the fourth connecting line 554 to the seventh connecting line 557 can all extend along the first direction X and be arranged sequentially along the second direction Y. The fourth connecting line 554 can be located on the side of the second electrostatic discharge circuit 22c away from the second electrostatic discharge circuit 22e, and is configured to be electrically connected to the second voltage line. The fifth connecting line 555 can be located between the second electrostatic discharge circuits 22c and 22e, and is configured to be electrically connected to the first voltage line. The sixth connecting line 556 can be located between the second electrostatic discharge circuits 22e and 22g, and is configured to be electrically connected to the second voltage line. The seventh connecting line 557 can be located on the side of the second electrostatic discharge circuit 22g away from the second electrostatic discharge circuit 22e, and is configured to be electrically connected to the first voltage line.

[0165] In some examples, such as Figure 14E As shown, the fourth insulating layer in the first frame region may also be provided with multiple vias, such as vias V51 to V81. The fourth and third insulating layers within vias V1 to V71 may be removed, exposing at least a portion of the surface of the semiconductor layer; the fourth insulating layer within vias V72 to V81 may be removed, exposing at least a portion of the surface of the third conductive layer.

[0166] In some examples, such as Figure 14AAs shown, the fourth conductive layer in the first frame region may include: a drive lead 112 and multiple connecting electrodes (e.g., the twenty-first connecting electrode 421 to the thirtieth connecting electrode 430). This example uses the second electrostatic discharge circuits 22c, 22e, and 22g as examples for illustration. The film layer connection relationships of the second electrostatic discharge circuits 22d, 22f, and 22h can be referred to the film layer connection relationships of the second electrostatic discharge circuits 22c, 22e, and 22g, and therefore will not be repeated here.

[0167] In some examples, such as Figures 14A to 14E As shown, the drive lead 112 can be electrically connected to the active layer T60C of the sixth transistor T6C and the active layer T50C of the fifth transistor T5C through multiple horizontally arranged 52 vias V52, and can also be electrically connected to the fifth oxide connection block 605 through the 56th via V56, thus achieving electrical connection with the second electrostatic discharge circuit 22c; it can also be connected to the active layer T50E of the fifth transistor T5E and the active layer T50C of the sixth transistor T6E through multiple horizontally arranged 59 vias V59. The connection terminal of layer T60E is electrically connected, and it can also be electrically connected to the ninth oxide connection block 609 through the sixty-second via V62, thus achieving electrical connection with the second electrostatic discharge circuit 22e; it can also be electrically connected to the connection terminals of the active layer T50G of the fifth transistor T5G and the active layer T60G of the sixth transistor T6G through multiple horizontally arranged sixty-six vias V66, and it can also be electrically connected to the thirteenth oxide connection block 613 through the seventieth via V70, thus achieving electrical connection with the second electrostatic discharge circuit 22g. The drive lead 112 can also be electrically connected to the second electrostatic discharge circuits 22d, 22f, and 22h.

[0168] In some examples, such as Figures 14A to 14EAs shown, the twenty-first connecting electrode 421 can be electrically connected to the fourth connecting line 554 through a plurality of vertically arranged seventy-second vias V72, and can also be electrically connected to the sixth oxide connecting block 606 through a fifty-fourth via V54, and can also be electrically connected to one end of the active layer T60C of the sixth transistor T6C through a plurality of horizontally arranged fifty-first vias V51. The fourth connecting line 554 can be electrically connected to the first voltage line PL1. The twenty-second connecting electrode 422 can be electrically connected to the sixth oxide connecting block 606 through a fifty-fifth via V55, and can also be electrically connected to the top gate T61C of the sixth transistor T6C through a plurality of vertically arranged seventy-third vias V73. The twenty-third connecting electrode 423 can be electrically connected to the fifth oxide connecting block 605 through a fifty-seventh via V57, and can also be electrically connected to the top gate T51C of the fifth transistor T5C through a plurality of vertically arranged seventy-fourth vias V74. The 24th connecting electrode 424 can be electrically connected to one end of the active layer T50C of the fifth transistor T5C through a plurality of horizontally arranged 53 vias V53, and can also be electrically connected to the fifth connecting line 555 through a plurality of vertically arranged 75 vias V75, and can also be electrically connected to one end of the active layer T50E of the fifth transistor T5E through a plurality of horizontally arranged 58 vias V58. The 25th connecting electrode 425 can be electrically connected to the ninth oxide connecting block 609 through a 61 via V61, and can also be electrically connected to the top gate T51E of the fifth transistor T5E through a 76 via V76. The 26th connecting electrode 426 can be electrically connected to the tenth oxide connecting block 610 through a 63 via V63, and can also be electrically connected to the top gate T61E of the sixth transistor T6E through a 77 via V77. The twenty-seventh connecting electrode 427 can be electrically connected to one end of the active layer T60E of the sixth transistor T6E through a plurality of horizontally arranged sixtieth vias V60, and can also be electrically connected to the tenth oxide connecting block 610 through a sixty-fourth via V64, and can also be electrically connected to the sixth connecting line 556 through a plurality of vertically arranged seventy-eighth vias V78, and can also be electrically connected to the fourteenth oxide connecting block 614 through a sixty-eighth via V68, and can also be electrically connected to one end of the active layer T60G of the sixth transistor T6G through a plurality of horizontally arranged sixty-fifth vias V65. The twenty-eighth connecting electrode 428 can be electrically connected to the fourteenth oxide connecting block 614 through a sixty-ninth via V69, and can also be electrically connected to the top gate T61G of the sixth transistor T6G through a seventy-ninth via V79. The twenty-ninth connecting electrode 429 can be electrically connected to the thirteenth oxide connecting block 613 through a seventy-first via V71, and can also be electrically connected to the top gate T51G of the fifth transistor T5G through an eightieth via V80.The thirtieth connecting electrode 430 can be electrically connected to one end of the active layer T50G of the fifth transistor T5G through multiple horizontally arranged sixty-seventh vias V67, and can also be electrically connected to the seventh connecting line 557 through multiple vertically arranged eighty-first vias V81.

[0169] The arrangement and connection of the second electrostatic discharge circuit in this example not only helps to reduce space occupation, but also helps to release static electricity from the drive leads.

[0170] Figure 15 This is a circuit diagram of a third electrostatic discharge circuit electrically connected to the drive signal lines, according to at least one embodiment of this disclosure. In some examples, such as... Figure 15 As shown, a drive signal line 113 can be electrically connected to at least one third electrostatic discharge circuit. The third electrostatic discharge circuit may include four oxide thin-film transistors, such as a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The first terminal of the seventh transistor T7 is electrically connected to a first voltage line PL1, and its top gate and second terminal are electrically connected to the first terminal of the eighth transistor T8; the top gate and second terminal of the eighth transistor T8 are electrically connected to the first terminal of the ninth transistor T9; the top gate and second terminal of the ninth transistor T9 are electrically connected to the first terminal of the tenth transistor T10; and the top gate and second terminal of the tenth transistor T10 are electrically connected to a second voltage line PL2. The drive signal line 113 can be electrically connected to the top gate and second terminal of the eighth transistor T8 and the first terminal of the ninth transistor T9. The bottom gates of all tenth transistors T7 to T10 are electrically connected to the third voltage line PL3.

[0171] Figure 16A This is a partial top view of the third border region of at least one embodiment of the present disclosure. Figure 16A The diagram illustrates a third electrostatic discharge circuit electrically connected to a drive signal line. Figure 16B for Figure 16A A planar schematic diagram of the third border region after the formation of the second conductive layer. Figure 16C for Figure 16A A planar schematic diagram of the third border region after the semiconductor layer is formed. Figure 16D for Figure 16A A planar schematic diagram of the third border region after the formation of the third conductive layer. Figure 16E for Figure 16A A planar schematic diagram of the third border region after the formation of the fourth insulating layer.

[0172] In some examples, such as Figure 16AAs shown, the four oxide thin-film transistors in the third electrostatic discharge circuit can be arranged in an array. For example, the seventh transistor T7 and the eighth transistor T8 can be arranged in a column along the second direction Y, the ninth transistor T9 and the tenth transistor T10 can be arranged in a column along the second direction Y, the seventh transistor T7 and the tenth transistor T10 can be arranged in a row along the first direction X, and the eighth transistor T8 and the ninth transistor T9 can be arranged in a row along the first direction X.

[0173] In some examples, such as Figure 16B As shown, the second conductive layer in the third frame region may include: the bottom gate of the oxide thin-film transistor of the third electrostatic discharge circuit (e.g., including the bottom gate T72 of the seventh transistor, the bottom gate T82 of the eighth transistor, the bottom gate T92 of the ninth transistor, and the bottom gate T102 of the tenth transistor), and the eighth connection line 558. The bottom gate T72 of the seventh transistor, the bottom gate T82 of the eighth transistor, the bottom gate T92 of the ninth transistor, the bottom gate T102 of the tenth transistor, and the eighth connection line 558 may be an integral structure. The eighth connection line 558 may be electrically connected to the third voltage line located in the fourth conductive layer.

[0174] In some examples, such as Figure 16C As shown, the semiconductor layer in the third frame region may include: the active layer of the oxide thin-film transistor of the third electrostatic discharge circuit (e.g., including: the active layer T70 of the seventh transistor, the active layer T80 of the eighth transistor, the active layer T90 of the ninth transistor, and the active layer T100 of the tenth transistor of the third electrostatic discharge circuit). The active layer T70 of the seventh transistor and the active layer T80 of the eighth transistor may be a single structure, for example, a strip structure extending along the second direction Y. The active layer T90 of the ninth transistor and the active layer T100 of the tenth transistor may be a single structure, for example, a strip structure extending along the second direction Y.

[0175] In some examples, such as Figure 16D As shown, the third conductive layer in the third border region may include the top gate of the oxide thin-film transistor of the third electrostatic discharge circuit (e.g., the top gate T71 of the seventh transistor, the top gate T81 of the eighth transistor, the top gate T91 of the ninth transistor, and the top gate T101 of the tenth transistor). The orthogonal projection of the top gate T71 of the seventh transistor and the top gate T81 of the eighth transistor onto the substrate may be a U-shape with the opening tilted to the left; the orthogonal projection of the top gate T91 of the ninth transistor and the top gate T101 of the tenth transistor onto the substrate may be a U-shape with the opening tilted to the right. The orthogonal projection of the top gate of the oxide thin-film transistor onto the substrate may be located within the orthogonal projection range of the bottom gate onto the substrate. In this example, the seventh, eighth, ninth, and tenth transistors may all be dual-gate structures, which can improve circuit stability.

[0176] In some examples, such as Figure 16E As shown, the fourth insulating layer in the third frame region may include multiple vias, such as vias V91 to V100. The fourth and third insulating layers within vias V91 to V96 may be removed, exposing at least a portion of the surface of the semiconductor layer. The fourth insulating layer within vias V97 to V100 may be removed, exposing at least a portion of the surface of the third conductive layer.

[0177] In some examples, such as Figures 16A to 16E As shown, the fourth conductive layer in the third frame region may include at least a plurality of connection electrodes (e.g., connection electrodes 431 to 435, respectively). Connection electrode 431 can be electrically connected to one end of the active layer T70 of the seventh transistor via via 91, and can also be electrically connected to the first voltage line, for example, as an integral structure with the first voltage line. Connection electrode 432 can be electrically connected to the connection ends of the active layers T70 and T80 of the seventh and eighth transistors via via 92, and can also be electrically connected to the top gate T71 of the seventh transistor via via 97. Connection electrode 433 can be electrically connected to one end of the active layer T80 of the eighth transistor via via 93, can also be electrically connected to one end of the active layer T90 of the ninth transistor via via 94, and can also be electrically connected to the top gate T81 of the eighth transistor via via 98. The thirty-third connecting electrode 433 can be electrically connected to the drive signal line, for example, it can be an integral structure with the drive signal line. The thirty-fourth connecting electrode 434 can be electrically connected to the connection terminals of the active layer T90 of the ninth transistor and the active layer T100 of the tenth transistor through the ninety-fifth via V95, and can also be electrically connected to the top gate T91 of the ninth transistor through the ninety-ninth via V99. The thirty-fifth connecting electrode 435 can be electrically connected to one end of the active layer T100 of the tenth transistor through the ninety-sixth via V96, and can also be electrically connected to the top gate T101 of the tenth transistor through the hundredth via V100. The thirty-fifth connecting electrode 435 can be electrically connected to the second voltage line, for example, it can be an integral structure with the second voltage line. The orthographic projection of the thirty-second connecting electrode 432, the thirty-third connecting electrode 433, the thirty-fourth connecting electrode 434, and the thirty-fifth connecting electrode 435 onto the substrate can be approximately L-shaped.

[0178] In some examples, the structure of the third electrostatic discharge circuit in the fourth border area can be similar to that of the third electrostatic discharge circuit in the third border area, so it will not be described again here.

[0179] The arrangement of the third electrostatic discharge circuit in this example is space-saving and facilitates the routing of drive signal lines.

[0180] Figure 17 This is another partial top view of the first border region of at least one embodiment of the present disclosure. Figure 18 for Figure 17 A schematic diagram of the auxiliary resistor routing. In some examples, such as... Figure 17 As shown, a drive lead 112 may include a first trace 112a and a second trace 112b. The first trace 112a may be electrically connected to multiple second electrostatic discharge circuits (e.g., including second electrostatic discharge circuits 22a and 22b). The second trace 112b and the first trace 112a may be electrically connected to an auxiliary resistor trace 25. For example, one end of the first trace 112a of the drive lead 112 may extend to a signal access area and be electrically connected to a bonding pin of the signal access area. The other end of the first trace 112a may be electrically connected to one end of the auxiliary resistor trace 25 through multiple vias formed in the fourth insulating layer. One end of the second trace 112b may be electrically connected to the other end of the auxiliary resistor trace 25 through multiple vias formed in the fourth insulating layer. The other end of the second trace 112b may extend to a third or fourth border area and be electrically connected to a drive signal line in the third or fourth border area.

[0181] In some examples, taking the drive lead 112 as the start signal lead for transmitting the start signal, by electrically connecting the start signal lead to the auxiliary resistor trace 25, the current of the start signal can be reduced, thus regulating the voltage of the start signal lead. However, this embodiment is not limited to this. In other examples, the clock signal lead, data lead, and drive signal line can each be electrically connected to their respective auxiliary resistor traces to achieve voltage regulation.

[0182] In some examples, such as Figure 18 As shown, the orthogonal projection of the auxiliary resistor trace 25 onto the substrate can be a serpentine trace. By setting the auxiliary resistor trace 25 as a serpentine trace, the resistance value can be increased by increasing the length of the auxiliary resistor trace, so that the resistance of the auxiliary resistor trace can play a role in reducing the current of the drive lead, and the space occupied can be reduced. However, this embodiment is not limited to this. In other examples, the auxiliary resistor trace can adopt a strip structure with a larger width to meet the resistance requirements for reducing the current of the drive lead.

[0183] In some examples, such as Figure 18 As shown, the auxiliary resistor trace 25 may include a convex bend 251 and a concave bend 252. The convex bend 251 and the concave bend 252 may be chamfered to alleviate stress concentration in the semiconductor layer where the auxiliary resistor trace is located.

[0184] In some examples, such as Figure 5 As shown, the circuit and film structure of the fourth electrostatic discharge circuit 24 can be similar to those of the aforementioned second electrostatic discharge circuit 22. For example, the film structure of the fourth electrostatic discharge circuit 24 can be similar to... Figure 14A As shown. However, this embodiment is not limited in this respect.

[0185] In other examples, multiple data leads in the surrounding area can be arranged on the same layer, for example, all located on the second conductive layer, and the surrounding area may not have a first conductive layer. The bottom gates of the first, second, and third electrostatic discharge circuits can be located on the first gate metal layer, and the top gates can be located on the second gate metal layer. However, this embodiment is not limited to this.

[0186] This embodiment also provides a display substrate, including: a substrate, at least one signal line, and at least one electrostatic discharge (ESD) circuit. The substrate includes a display area and a peripheral area located on at least one side of the display area. The at least one signal line and at least one ESD circuit are located in the peripheral area. Each ESD circuit includes a plurality of transistors connected in series between a first voltage line and a second voltage line. At least one of the plurality of transistors is an oxide thin-film transistor (OST). The OST includes a top gate and a bottom gate, and the bottom gate of the OST is electrically connected to a third voltage line. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line and is greater than a third voltage signal provided by the third voltage line. A signal line is electrically connected to at least one ESD circuit, and the signal line is configured to release static electricity through the at least one ESD circuit; the plurality of transistors in the at least one ESD circuit electrically connected to the signal line are arranged in an array, or the plurality of ESD circuits electrically connected to the signal line are arranged in an array.

[0187] The display substrate provided in this example, by electrically connecting the bottom gate of the oxide thin-film transistor (OTFT) in the electrostatic discharge (ESD) circuit to a third voltage line, can shift the threshold voltage of the OTFT to a positive value. This allows the OTFT to successfully turn off when the gate-source voltage difference is 0V, thereby improving the performance of the OTFT in the ESD circuit, enhancing the stability of the ESD circuit, and thus improving the ESD resistance of the display substrate. Furthermore, the ESD circuit in this example uses an array arrangement; the multiple transistor arrays within the ESD circuit help save space and facilitate a narrow bezel design.

[0188] In some exemplary embodiments, the display substrate includes multiple signal lines and multiple electrostatic discharge circuits. The multiple signal lines include multiple data leads. The display area is provided with multiple data lines. The multiple data leads are electrically connected to the multiple data lines respectively. The multiple electrostatic discharge circuits include multiple first electrostatic discharge circuits, and at least one data lead is electrically connected to at least one first electrostatic discharge circuit. The first electrostatic discharge circuit includes multiple oxide thin-film transistors, and the multiple oxide thin-film transistors are arranged in an array on one side of the connected data leads.

[0189] In some exemplary embodiments, the plurality of signal lines further include a plurality of drive leads, and the plurality of electrostatic discharge circuits further include a plurality of second electrostatic discharge circuits; the plurality of second electrostatic discharge circuits are located on the side of the plurality of first electrostatic discharge circuits away from the display area. At least one drive lead is electrically connected to at least two second electrostatic discharge circuits, and the at least two second electrostatic discharge circuits electrically connected by one drive lead are arranged in an array. At least one second electrostatic discharge circuit includes a plurality of oxide thin-film transistors, and the plurality of oxide thin-film transistors are arranged in an array on one side of the connected drive lead.

[0190] In some exemplary embodiments, the display substrate further includes: at least one auxiliary resistor trace located in the peripheral region; at least one signal line including: a first trace and a second trace, the first trace being electrically connected to the at least one electrostatic discharge circuit, the second trace being located on the side of the first trace closer to the display region, and the first trace and the second trace being electrically connected through the auxiliary resistor trace.

[0191] The structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0192] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, such as... Figure 19 As shown, this embodiment provides a display device 91, including the display substrate 910 of the aforementioned embodiment. In some examples, the display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0193] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this application.

Claims

1. An electrostatic discharge circuit, characterized in that, include: A first voltage line and a second voltage line, wherein the first voltage line provides a first voltage signal that is greater than the second voltage line provides a second voltage signal; Multiple transistors are connected in series between a first voltage line and a second voltage line; at least one of the multiple transistors is an oxide thin-film transistor, the oxide thin-film transistor includes an active layer, a top gate and a bottom gate, the bottom gate of the oxide thin-film transistor is electrically connected to a third voltage line; a first voltage signal provided by the first voltage line is greater than a third voltage signal provided by the third voltage line; a first gate insulating layer is disposed between the active layer and the top gate, and a second gate insulating layer is disposed between the active layer and the bottom gate, the active layer being made of a metal oxide material; All transistors in the electrostatic discharge circuit are oxide thin-film transistors, and are N-type transistors; The electrostatic discharge circuit includes four oxide thin-film transistors connected in series. The bottom gates of the four oxide thin-film transistors are all electrically connected to the third voltage line. The top gate and second electrode of the second oxide thin-film transistor and the first electrode of the third oxide thin-film transistor are all electrically connected to the signal input terminal. Alternatively, the electrostatic discharge circuit includes two oxide thin-film transistors connected in series, wherein the top gate and second terminal of one oxide thin-film transistor are electrically connected to the first terminal and signal input terminal of the other oxide thin-film transistor, and the bottom gates of both oxide thin-film transistors are electrically connected to the third voltage line.

2. The circuit according to claim 1, characterized in that, The third voltage signal provided by the third voltage line is less than the second voltage signal provided by the second voltage line.

3. The circuit according to claim 1, characterized in that, The electrostatic discharge circuit includes four oxide thin-film transistors connected in series, wherein the first terminal of the first oxide thin-film transistor is electrically connected to the first voltage line, the second terminal and top gate of the i-th oxide thin-film transistor are electrically connected to the first terminal of the (i+1)-th oxide thin-film transistor, and the second terminal of the fourth oxide thin-film transistor is electrically connected to the second voltage line, where i is a positive integer greater than or equal to 1 and less than 4.

4. The circuit according to claim 1, characterized in that, The electrostatic discharge circuit includes two oxide thin-film transistors connected in series. The first electrode of one oxide thin-film transistor is electrically connected to the first voltage line, and the second electrode of the other oxide thin-film transistor is electrically connected to the second voltage line.

5. A display substrate, characterized in that, include: The substrate includes a display area and a peripheral area located on at least one side of the display area; At least one signal line and at least one electrostatic discharge circuit are located in the surrounding area; Each electrostatic discharge circuit is connected between the first voltage line and the second voltage line and is electrically connected to a signal line, and is configured to provide an electrostatic discharge path to the signal line; The electrostatic discharge circuit includes at least one oxide thin-film transistor; the oxide thin-film transistor includes an active layer, a bottom gate, and a top gate, the bottom gate being located on the side of the active layer closer to the substrate, the top gate being located on the side of the active layer away from the substrate, and the bottom gate being electrically connected to a third voltage line; a first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line, and is also greater than a third voltage signal provided by the third voltage line; a first gate insulating layer is disposed between the active layer and the top gate, and a second gate insulating layer is disposed between the active layer and the bottom gate; the active layer is made of a metal oxide material. All transistors in the electrostatic discharge circuit are oxide thin-film transistors, and are N-type transistors; The electrostatic discharge circuit includes four oxide thin-film transistors connected in series. The bottom gates of the four oxide thin-film transistors are all electrically connected to the third voltage line. The top gate and second electrode of the second oxide thin-film transistor and the first electrode of the third oxide thin-film transistor are all electrically connected to the signal input terminal. Alternatively, the electrostatic discharge circuit includes two oxide thin-film transistors connected in series, wherein the top gate and second terminal of one oxide thin-film transistor are electrically connected to the first terminal and signal input terminal of the other oxide thin-film transistor, and the bottom gates of both oxide thin-film transistors are electrically connected to the third voltage line.

6. The display substrate according to claim 5, characterized in that, The orthographic projection of the top gate of the oxide thin-film transistor onto the substrate is located within the orthographic projection range of the bottom gate onto the substrate.

7. The display substrate according to claim 5, characterized in that, The bottom gates of the plurality of oxide thin-film transistors in the at least one electrostatic discharge circuit are integral structures.

8. The display substrate according to claim 5, characterized in that, The first voltage line, the second voltage line, and the third voltage line are located on the side of the top gate of the oxide thin-film transistor away from the substrate.

9. The display substrate according to any one of claims 5 to 8, characterized in that, The display area is provided with multiple data lines; the display substrate includes multiple signal lines and multiple electrostatic discharge circuits; The multiple signal lines include: multiple data leads; the multiple data leads are electrically connected to the multiple data lines respectively; The plurality of electrostatic discharge circuits include: a plurality of first electrostatic discharge circuits; at least one data lead is electrically connected to at least one first electrostatic discharge circuit; the at least one first electrostatic discharge circuit and the connected data lead are adjacent in a first direction, the first electrostatic discharge circuit includes a plurality of oxide thin film transistors, the plurality of oxide thin film transistors of the first electrostatic discharge circuit are arranged along a second direction, and the first direction and the second direction intersect.

10. The display substrate according to claim 9, characterized in that, The multiple data leads include multiple sets of data leads, and at least one set of data leads includes two adjacent data leads disposed in different layers, wherein the orthographic projections of the two data leads on the substrate do not overlap.

11. The display substrate according to claim 10, characterized in that, The first electrostatic discharge circuit electrically connected to each of the two data leads in the at least one set of data leads is located between the two data leads, adjacent in the second direction, and electrically connected to the same first voltage line.

12. The display substrate according to claim 11, characterized in that, The first electrostatic discharge circuits electrically connected to each of the two data leads in the at least one set of data leads are symmetrically arranged about the first voltage line.

13. The display substrate according to claim 10, characterized in that, One of the at least one set of data leads is in the same layer as the bottom gate of the oxide thin-film transistor of the first electrostatic discharge circuit, and the other data lead is located on the side of the bottom gate of the oxide thin-film transistor closer to the substrate.

14. The display substrate according to any one of claims 5 to 8, characterized in that, The display substrate includes multiple signal lines and multiple electrostatic discharge circuits. The multiple signal lines include multiple drive leads. The multiple electrostatic discharge circuits include multiple second electrostatic discharge circuits. At least one drive lead is electrically connected to at least two second electrostatic discharge circuits. An array of at least two second electrostatic discharge circuits electrically connected to one drive lead is arranged.

15. The display substrate according to claim 14, characterized in that, At least two second electrostatic discharge circuits electrically connected to a drive lead are symmetrically arranged about the drive lead.

16. The display substrate according to any one of claims 5 to 8, characterized in that, The display substrate includes multiple signal lines and multiple electrostatic discharge circuits. The multiple signal lines include multiple drive signal lines. The multiple electrostatic discharge circuits include multiple third electrostatic discharge circuits. At least one drive signal line is electrically connected to at least one third electrostatic discharge circuit. The third electrostatic discharge circuit includes four oxide thin-film transistors connected in series, and the four oxide thin-film transistors are arranged in an array.

17. The display substrate according to claim 5, characterized in that, The display substrate further includes: at least one auxiliary resistor trace located in the peripheral area; at least one signal line including: a first trace and a second trace, the first trace being electrically connected to the at least one electrostatic discharge circuit, the second trace being located on the side of the first trace closer to the display area, and the first trace and the second trace being electrically connected through the auxiliary resistor trace.

18. The display substrate according to claim 17, characterized in that, The at least one auxiliary resistor trace is projected onto the substrate in a serpentine pattern.

19. A display device, characterized in that, Includes the display substrate as described in any one of claims 5 to 18.

20. A display substrate, characterized in that, include: The substrate includes a display area and a peripheral area located on at least one side of the display area; At least one signal line and at least one electrostatic discharge circuit are located in the surrounding area; Each electrostatic discharge circuit includes a plurality of transistors connected in series between a first voltage line and a second voltage line. At least one of the plurality of transistors is an oxide thin-film transistor (OST). The OST includes an active layer, a top gate, and a bottom gate. The bottom gate of the OST is electrically connected to a third voltage line. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line and a third voltage signal provided by the third voltage line. A first gate insulating layer is disposed between the active layer and the top gate, and a second gate insulating layer is disposed between the active layer and the bottom gate. The active layer is made of a metal oxide material. A signal line is electrically connected to at least one electrostatic discharge circuit, the signal line being configured to release static electricity through the at least one electrostatic discharge circuit; or, the signal line is electrically connected to an array of multiple transistors within the at least one electrostatic discharge circuit; All transistors in the electrostatic discharge circuit are oxide thin-film transistors, and are N-type transistors; The electrostatic discharge circuit includes four oxide thin-film transistors connected in series. The bottom gates of the four oxide thin-film transistors are all electrically connected to the third voltage line. The top gate and second electrode of the second oxide thin-film transistor and the first electrode of the third oxide thin-film transistor are all electrically connected to the signal input terminal. Alternatively, the electrostatic discharge circuit includes two oxide thin-film transistors connected in series, wherein the top gate and second terminal of one oxide thin-film transistor are electrically connected to the first terminal and signal input terminal of the other oxide thin-film transistor, and the bottom gates of both oxide thin-film transistors are electrically connected to the third voltage line.

21. The display substrate according to claim 20, characterized in that, The display substrate includes multiple signal lines and multiple electrostatic discharge circuits. The multiple signal lines include multiple data leads. The display area is provided with multiple data lines. The multiple data leads are electrically connected to the multiple data lines respectively. The multiple electrostatic discharge circuits include multiple first electrostatic discharge circuits. At least one data lead is electrically connected to at least one first electrostatic discharge circuit. The first electrostatic discharge circuit includes multiple oxide thin-film transistors, which are arranged in an array on one side of the connected data leads.

22. The display substrate according to claim 21, characterized in that, The multiple signal lines also include multiple drive leads, and the multiple electrostatic discharge circuits also include multiple second electrostatic discharge circuits; the multiple second electrostatic discharge circuits are located on the side of the multiple first electrostatic discharge circuits away from the display area; At least one drive lead is electrically connected to at least two second electrostatic discharge circuits, and the at least two second electrostatic discharge circuits connected by the drive lead are arranged in an array. At least one second electrostatic discharge circuit includes a plurality of oxide thin film transistors, which are arranged in an array on one side of the connected drive lead.

23. The display substrate according to any one of claims 20 to 22, characterized in that, The display substrate further includes: at least one auxiliary resistor trace located in the peripheral area; at least one signal line including: a first trace and a second trace, the first trace being electrically connected to the at least one electrostatic discharge circuit, the second trace being located on the side of the first trace closer to the display area, and the first trace and the second trace being electrically connected through the auxiliary resistor trace.

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