A trench gate IGBT

Abstract

The present application relates to a trench gate IGBT. The trench gate IGBT at least comprises a first type of trench and a P-type doped deep junction region. A second type of trench is additionally provided between the first type of trench and the P-type doped deep junction region. The second type of trench is used to slow down or isolate the charging of the first type of trench by the P-type doped deep junction region. The present application realizes a significant reduction in power consumption while improving the controllability of the IGBT device with a small increase in the delay time when the IGBT is turned on. Since the IGBT device is generally a high-power device, it is very important to significantly reduce the power consumption of the IGBT while ensuring that the increase in delay time is within an acceptable range. The improvement in the controllability of the IGBT device brought about by the present application can also avoid the mis-opening of the IGBT device, and at the same time avoid the problem of switching oscillation of the IGBT in some cases.

Description

Technical Field

[0001] This invention relates to IGBTs, and more particularly to a trench gate IGBT. Background Technology

[0002] In the field of power semiconductor devices, trench gate structures are now commonly used in insulated gate bipolar transistors (IGBTs). The trench gate structure eliminates the JFET region, avoiding current congestion and resulting in a lower on-state voltage drop. However, due to the higher channel density, it increases the inter-electrode coupling capacitance (especially Miller capacitance), reducing the device's switching speed and increasing switching losses. Simultaneously, high channel density increases the saturation current, resulting in a smaller short-circuit safe operating area.

[0003] Because a large number of non-equilibrium carriers need to be injected into the collector side when an IGBT is turned on to generate a conductivity modulation effect, thereby reducing the on-state voltage drop. On the one hand, turning on an IGBT requires charging the gate, and the charging speed determines the IGBT's turn-on speed, which in turn depends on the IGBT's parasitic capacitance, including C. ge and C gc On the other hand, the introduced non-equilibrium carriers will produce a significant current tailing effect when the device is turned off, which makes the IGBT turn-off speed slower and increases the turn-off loss.

[0004] Furthermore, to optimize the relationship between turn-off loss and on-state voltage drop in trench-gate IGBTs and improve the carrier injection enhancement effect, an IGBT with a P-type doped deep junction region, namely the Injection Enhanced IGBT (IEGT), was developed. The introduction of the P-type doped deep junction region can adjust the carrier distribution in the N-type breakdown region, thereby achieving a better trade-off between dynamic and static performance.

[0005] In the turn-on phase of a traditional injection-enhanced IGBT, a large number of holes injected into the bottom P-type collector region accumulate in the P-type doped deep junction region and the bottom of the trench. This causes the potential of the P-type doped deep junction region to change too rapidly, resulting in an additional displacement current charging the gate, which in turn leads to V... ge With rapid increases, the gate voltage and gate resistance connected to the gate cannot effectively control dI. c / dt. And excessively large dI c / dt will further lead to excessively large dV ce / dt, therefore the switching controllability of this IGBT device is poor. Furthermore, the Miller capacitance C of a traditional injection-enhanced IGBT... gc The large size of the Miller plateau during the switching process leads to a long duration of switching losses. Therefore, there is an urgent need for a new trench gate IGBT device to address the issues of high switching controllability and high switching losses in traditional injection-enhanced IGBTs.

[0006] Chinese patent CN111370475A discloses a trench gate IGBT and its device, improving upon existing trench gate IGBTs. The improved trench gate IGBT includes an emitter, a p-well region, a gate, a gate oxide layer, a drift region, and a back collector. The gate is located within the trench, and the gate is isolated from the emitter, p-well region, and drift region by the gate oxide layer. The trench is disposed inside a substrate, and the boundary between the trench and the drift region has multiple recesses. During the switching process of the trench gate IGBT, the multiple recessed gate oxide layers at the interface between the trench and the drift region can trap and accumulate electron charge, thereby improving the conduction capability and solving the technical problem of excessive switching power consumption in existing trench gate IGBTs, thus achieving the beneficial effect of reducing the switching power consumption of trench gate IGBTs. However, the patent has a drawback: the way it completely wraps the trench with the gate oxide layer can reduce the dynamic power consumption of the IGBT, reduce the gate capacitance and increase the switching speed to a certain extent. However, the increase in switching speed causes the IGBT to stay in the Miller plateau for a long time, which in turn leads to a significant increase in power consumption during the IGBT's turn-on phase and at the same time reduces the controllability of the IGBT's switching.

[0007] Furthermore, on the one hand, there are differences in understanding among those skilled in the art; on the other hand, the applicant studied a large number of documents and patents when making this invention, but due to space limitations, not all details and contents were listed in detail. However, this does not mean that the present invention does not possess the features of these prior art. On the contrary, the present invention already possesses all the features of the prior art, and the applicant reserves the right to add relevant prior art to the background art. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a trench-gate IGBT, the structure of which includes at least a first type of trench and a P-type doped deep junction region. A second type of trench is further disposed between the first type of trench and the P-type doped deep junction region, the second type of trench serving to mitigate or isolate the charging of the first type of trench by the P-type doped deep junction region. This invention has minimal impact on the cost of IGBT device fabrication, maintaining the same process, but the structural design change significantly improves its turn-on performance, reduces power consumption by more than 30%, and greatly reduces heat generation, enabling the improved IGBT device to operate for extended periods.

[0009] According to a preferred embodiment, the emitter conductor connected to the second type of trench has zero potential compared to the control potential connected to the first type of trench. The second type of trench serves as an isolation layer to prevent additional charging of the first type of trench by the P-type doped deep junction region.

[0010] According to a preferred embodiment, the first type of trench comprises a first type of conductive polycrystalline silicon encapsulated by an insulating dielectric layer. The second type of trench comprises a second type of conductive polycrystalline silicon encapsulated by the insulating dielectric layer, or the second type of trench is formed by the insulating dielectric layer.

[0011] According to a preferred embodiment, the second type of trench, in direct contact with the P-type doped deep junction region, isolates the hole flow from the P-type doped deep junction region to the first type of trench during the IGBT turn-on phase. This invention introduces the second type of trench to provide additional isolation for the charging current of the P-type doped deep junction region, preventing it from flowing to the first type of trench, thereby reducing the additional charging process during the IGBT device turn-on phase.

[0012] According to a preferred embodiment, the emitter conductors between the first type of trench and the second type of trench can be spaced apart in the trench extension direction. The emitter conductors between the first type of trench and the second type of trench can be spaced apart in a discontinuous manner with slotted intervals in the trench extension direction to reduce conduction voltage drop loss. By changing from full coverage of the emitter conductors to open holes, this invention reduces the damage caused by conduction voltage drop. The second type of trenches in this invention also result in a narrower trench spacing, ensuring a flow path during the opening process and reducing conduction voltage drop loss. The use of spaced openings and reduced trench spacing can reduce V... cesat (On-state voltage drop) loss, or even virtually no loss, while avoiding additional charging of the first type trench by the P-type doped deep junction region.

[0013] According to a preferred embodiment, the structure further includes a first P-type base region, a second P-type base region, and an N-type source region. The first P-type base region, the second P-type base region, and the N-type source region are covered by the emitter conductor and connected to the E potential via a wire; the second type of trench is covered by the emitter conductor and connected to the E potential via a wire. The first P-type base region and the second P-type base region between the first type of trench and the second type of trench are extremely narrow, and the emitter conductor is spaced across the upper surface of these extremely narrow first P-type base regions and the second P-type base region, and connected to the E potential via a wire, thus almost without sacrificing V. cesat (Conduction voltage drop)

[0014] According to a preferred embodiment, the first type of trench and the second type of trench are disposed separately from each other, with the first P-type base region and the second P-type base region separated in between. The first type of trench of the present invention is in direct contact with the first P-type base region and the second P-type base region on both its left and right sides, and an emitter conductor is covered on the upper surface of the first P-type base region and the second P-type base region, and connected to the E potential via a wire. Therefore, the Miller capacitance C of the IGBT device designed in this invention... gc Smaller, shorter Miller plateau duration during switching process (e.g.) Figure 7As shown in the figure, the switching loss is low.

[0015] According to a preferred embodiment, the structure further includes a P-type collector region, an N-type buffer region, and an N-type breakdown voltage region. The P-type collector region, the N-type buffer region, and the N-type breakdown voltage region are arranged in sequence such that the N-type breakdown voltage region contacts the first type of trench, the second type of trench, the P-type doped deep junction region, and the first P-type base region.

[0016] According to a preferred embodiment, the P-type doped deep junction region, the first P-type base region, and the second P-type base region are arranged to cover the N-type breakdown voltage region and not to contact the P-type collector region and the N-type buffer region in order to guide hole flow.

[0017] According to a preferred embodiment, the P-type collector region is covered with a collector conductor; the first type of trench is covered with a gate conductor and connected to the G potential via a wire. Attached Figure Description

[0018] Figure 1 This is a two-dimensional cross-section of a trench gate IGBT structure according to a preferred embodiment of the present invention;

[0019] Figure 2 This is a three-dimensional axial cross-sectional view of a trench gate IGBT structure according to a preferred embodiment of the present invention;

[0020] Figure 3 This is a two-dimensional cross-sectional schematic diagram of a conventional injection-enhanced trench gate IGBT structure provided by the present invention;

[0021] Figure 4 This is a schematic diagram of a three-dimensional axial section of a conventional injection-enhanced trench gate IGBT structure provided by the present invention.

[0022] Figure 5 This is a two-dimensional cross-sectional schematic diagram of a trench gate IGBT structure according to another preferred embodiment of the present invention;

[0023] Figure 6 This is a three-dimensional axial cross-sectional view of a trench gate IGBT structure according to another preferred embodiment of the present invention;

[0024] Figure 7 The conventional injection-enhanced trench gate IGBT structure of the preferred embodiment provided by this invention differs from the IGBT structure designed in this invention in terms of V during the device turn-on phase. ge Waveform diagram;

[0025] Figure 8The conventional injection-enhanced trench gate IGBT structure of the preferred embodiment provided by this invention and the IGBT structure designed in this invention differ in I0 during the device turn-on phase. c Waveform diagram;

[0026] Figure 9 The conventional injection-enhanced trench gate IGBT structure according to a preferred embodiment of the present invention and the IGBT structure designed in the present invention have different dI values ​​during the device turn-on phase. c / dt waveform;

[0027] Figure 10 The conventional injection-enhanced trench gate IGBT structure of the preferred embodiment provided by this invention differs from the IGBT structure designed in this invention in terms of V during the device turn-on phase. ce Waveform diagram;

[0028] Figure 11 The preferred embodiment of the present invention provides a conventional injection-enhanced trench gate IGBT structure, and the IGBT structure designed in this invention has different dV values ​​during the device turn-on phase. ce / dt waveform;

[0029] Figure 12 These are power waveform diagrams of a conventional injection-enhanced trench gate IGBT structure and an IGBT structure designed in this invention during the device turn-on phase, representing a preferred embodiment of the present invention.

[0030] List of reference numerals

[0031] 1: Collector conductor; 2: Emitter conductor; 3: Gate conductor; 10: P-type collector region; 20: N-type buffer zone; 30: N-type breakdown voltage region; 40: Type I trench; 41: Type I conductive polysilicon; 42: Insulating dielectric layer; 43: Type II trench; 44: Type II conductive polysilicon; 50: P-type doped deep junction region; 51: First P-type base region; 52: N-type source region; 53: Second P-type base region. Detailed Implementation

[0032] The following is a detailed description with reference to the accompanying drawings.

[0033] I c When the gate (G) and emitter (E) are short-circuited, a certain V is applied. ce In this case, the leakage current between the collector C and emitter E of the IGBT.

[0034] V ge : Under a certain I c The turn-on voltage of the IGBT.

[0035] V ce (V cesat): Apply a certain V between the gate G and the emitter ge Or a certain I c Under these conditions, the saturation voltage drop between the collector C and emitter E of the IGBT.

[0036] dI c / dt:I c Curve showing how it changes over time.

[0037] dV ce / dt:V ce Curve showing how it changes over time.

[0038] Example 1

[0039] The present invention aims to propose a trench gate IGBT structure to improve the switching controllability of IGBTs and reduce switching losses.

[0040] like Figure 3 The image shows a two-dimensional cross-sectional schematic diagram of a conventional injection-enhanced trench gate IGBT structure in the prior art. Figure 4 The figure shown is a three-dimensional axial cross-sectional view of a conventional injection-enhanced trench gate IGBT structure in the prior art.

[0041] Reference Figure 3 and Figure 4 This describes a conventional injection-enhanced trench gate IGBT. This conventional injection-enhanced trench gate IGBT includes two first-type trenches 40 and two P-type doped deep junction regions 50. The two first-type trenches 40 are located within an N-type breakdown region 30 near their top surface, and their top surfaces are provided with gate conductors 3. The two P-type doped deep junction regions 50 are located outside one of the two first-type trenches 40. Figure 3 It is used to regulate the carrier distribution in the N-type withstand voltage region 30.

[0042] according to Figure 3 Within the opposing regions of the two first-type trenches 40, an N-type source region 52, a second P-type base region 53, and a first P-type base region 51 are provided. Specifically, an N-type source region 52 is provided in the corresponding region of each of the two first-type trenches 40 facing the second P-type base region 53, thus forming two N-type source regions 52 between the two first-type trenches 40 and the lateral sides of the second P-type base region 53. The second P-type base region 53 completely separates the two N-type source regions 52 in the extending direction of the first-type trenches 40. The second P-type base region 53 is a highly concentrated P-type doped region and is connected to the first P-type base region 51 to keep the first P-type base region 51 at a low potential under the action of the emitter conductor 2, thereby avoiding latch-up effects.

[0043] according to Figure 3Emitter conductors 2 are provided on the upper surfaces of the second P-type base region 53 and the two N-type source regions 52. The internal space formed by the insulating dielectric layer 42 of the first type trench 40 is filled with a first type conductive polysilicon 41 for providing gate voltage to the IGBT, wherein the first type conductive polysilicon 41 has a gate conductor 3 on the top.

[0044] according to Figure 3 The bottom of the N-type withstand voltage region 30 is provided with an N-type buffer zone 20 and a P-type collector region 10 in sequence. The bottom surface of the P-type collector region 10 is provided with the collector conductor 1 of the trench gate IGBT.

[0045] like Figure 4 As shown, in a conventional injection-enhanced trench gate IGBT structure, the P-type doped deep junction region 50 is directly adjacent to the first type trench 40 with an insulating dielectric layer 42. During the turn-on phase of a conventional injection-enhanced trench gate IGBT, a large number of holes injected from the bottom P-type collector region 10 flow to the first P-type base region 51. However, some holes still accumulate at the bottom of the P-type doped deep junction region 50 and the first type trench 40, making the potential of the P-type doped deep junction region 50 higher than that of the first type trench 40. This generates an additional displacement current charging the gate, resulting in a higher gate voltage V0. ge The current increases rapidly. However, since the displacement current charging is unpredictable and varies with operating conditions, and the gate voltage remains constant while the gate resistance adjustment must address the unpredictable displacement current charging, dI cannot be effectively controlled under all circumstances. c / dt. And due to excessively large dI c / dt will be accompanied by an excessively large dV ce The / dt parameter results in poor switching controllability of traditional IGBT devices. Furthermore, the Miller capacitance C of traditional injection-enhanced IGBTs... gc The larger the value, the longer the Miller plateau duration during the switching process, resulting in greater switching losses.

[0046] The charging process in the prior art is as follows: During the IGBT device's turn-on process, the collector C potential provides a high voltage relative to the emitter E potential, allowing holes originating from it to flow from the collector C towards the P-type collector region 10, the N-type buffer region 20, and the N-type breakdown voltage region 30; that is, holes flow from bottom to top. When the gate G potential is greater than the IGBT threshold voltage (turn-on voltage), a conductive channel is formed at the interface where the first P-type base region 51 contacts the first type of trench 40. At this time, if the potential between the collector C potential and the emitter E potential is greater than zero, an electron channel is formed from the emitter E potential from the N-type source region 52, the first P-type base region 51 to the N-type breakdown voltage region 30. Holes flow from bottom to top to the second P-type base region 53. However, during the IGBT device's turn-on phase, not all holes in the collector C potential flow towards the first P-type base region 51. Because the P-type doped deep junction region 50 has a relatively large junction depth, some holes flow towards the P-type doped deep junction region 50, and these holes also flow along the bottom interface between the P-type doped deep junction region 50 and the first type trench 40 to the first P-type base region 51 and the second P-type base region 53. During this stage, the P-type doped deep junction region 50 provides additional charging to the first type trench 40.

[0047] The aforementioned conductive channels appear at the two interfaces between the first P-type base region 51 and the insulating dielectric layer 42 of the first type trench 40. The first P-type base region 51 itself is a low-concentration P-type doped region. When the gate potential (G) is greater than the IGBT threshold voltage, under the influence of a positive gate voltage, the first type of conductive polysilicon 41 within the first type trench 40 will generate an electric field pointing from the gate to the first P-type base region 51, but no current will be generated. This electric field repels holes and attracts electrons, causing electrons in the N-type source region 52 to be attracted to the two interfaces between the first P-type base region 51 and the insulating dielectric layer 42 of the first type trench 40. When the positive gate voltage reaches a certain value, these electrons form an inversion layer at the interface between the first P-type base region 51 and the insulating dielectric layer 42 of the first type trench 40. The accumulation of the inversion layer at this interface leads to the formation of a conductive channel, i.e., an electron conductive channel. Preferably, the N-type source region 52 is the region that emits electrons and is an N-type doped region. The formation of the conductive channel enables the N-type source region 52 and the N-type breakdown voltage region 30 to conduct, allowing electrons from the N-type source region 52 to flow to the N-type breakdown voltage region 30, thus enabling the emitter 2 and the collector 1 to conduct.

[0048] When a potential is applied to the gate, the potential of the first type of trench 40 gradually approaches the applied potential, thereby generating a conductive channel. Displacement current charging intensifies the formation of the conductive channel, increasing the formation time and dI. c The current change between the emitter and collector ( / dt) deviates from the expected design value.

[0049] In existing IGBT structures, the gate voltage is kept at a fixed value. For the first P-type base region 51 and the second P-type base region 53, during the IGBT device turn-on phase, if there are no external influencing factors, the gate charging rate will typically gradually slow down. However, if... Figure 3 and Figure 4 As shown, in the prior art, the P-type doped deep junction region 50 additionally charges the first type trench 40, resulting in a sharp increase in the gate charging rate. For example... Figure 7 The solid line segment shows an inflection point during the rising phase, indicating a sudden acceleration in the charging rate. This leads to false turn-on issues in existing conventional injection-enhanced trench gate IGBT structures. The reason is that the additional charging of the P-type doped deep junction region 50 to the first-type trench 40 results in a high gate change rate, causing false turn-on. During the IGBT device's turn-on phase, excessively rapid or / or slow changes in voltage and / or current are detrimental to IGBT switching control. Furthermore, the Miller capacitance C in existing conventional injection-enhanced trench gate IGBT structures... gc The larger the value, the longer the Miller plateau duration during the switching process, resulting in greater switching losses.

[0050] Therefore, there is an urgent need for a new trench gate IGBT device to solve the switching controllability problem and reduce switching losses of traditional injection-enhanced IGBTs.

[0051] This invention provides a trench gate IGBT structure. For example... Figure 1 The image shown is a two-dimensional cross-sectional schematic diagram of a trench-gate IGBT structure according to the present invention. Figure 2 The figure shown is a three-dimensional axial cross-sectional view of a grooved grid IGBT structure according to the present invention.

[0052] In such Figure 1 and Figure 2 The trench gate IGBT of the present invention shown includes two first-type trenches 40 and two P-type doped deep junction regions 50. The two first-type trenches 40 are located within the N-type breakdown region 30 near the top surface, and their top surfaces are provided with gate conductors 3. The two P-type doped deep junction regions 50 are respectively located outside one of the two first-type trenches 40. Figure 1 It is used to regulate the carrier distribution in the N-type withstand voltage region 30.

[0053] In the region where one of the two first-type trenches 40 faces the corresponding P-type doped deep junction region 50, a second-type trench 43 is also provided adjacent to the P-type doped deep junction region 50. This second-type trench 43 is spaced from the first-type trenches 40 in the following manner: a spacer portion consisting of a second P-type base region 53 and a first P-type base region 51 is additionally provided in the region between the second-type trench 43 and the corresponding first-type trench 40. The spacer portion extends longitudinally along the trench between the first-type trench 40 and the second-type trench 43. Conductive contact portions are provided at intervals along the longitudinal extension direction of the spacer portion. The conductive contact portion of the second P-type base region 53 near the spacer portion maintains the same potential as the emitter conductor 2. The first P-type base region 51, vertically away from the conductive contact portion, is connected to the N-type breakdown voltage region 30. The first P-type base region 51 is used to isolate carrier losses in the N-type breakdown voltage region 30. The spacer portion is used to ensure the withstand voltage of the N-type withstand voltage region 30 and to prevent the N-type withstand voltage region 30 from directly contacting the conductor and conducting electricity. Preferably, the width of the spacer portion formed by the second P-type base region 53 and the first P-type base region 51 is greater than zero and less than the distance between the two first-type trenches 40, and preferably equal to the width of the second P-type base region 53 between the two first-type trenches 40. When the width of the spacer portion is equal to the width of the second P-type base region 53 between the two first-type trenches 40, the same process can be used to process and etch the structure, thereby reducing processing costs.

[0054] During the turn-on phase of the trench-gate IGBT, the second type of trench 43 slows down or isolates the additional charging of the first type of trench 40 by the P-type doped deep junction region 50. When the collector conductor 1 is supplied with a high voltage, the second type of trench 43, which is adjacent to the P-type doped deep junction region 50 and spaced apart from the first type of trench 40, slows down or isolates the additional charging of the first type of trench 40 by the P-type doped deep junction region 50 located outside the trench-gate IGBT, whose potential is higher than that of the first type of trench 40 due to the accumulation of some holes. This reduces the conductor voltage drop V between the collector conductor 1 and the emitter conductor 2. ce The peak rate of change is reduced to improve the switching controllability of trench gate IGBTs.

[0055] A second P-type base region 53 and a first P-type base region 51 are sequentially arranged from top to bottom between the first type trench 40 and the second type trench 43. The top surface of the second P-type base region 53 is provided with an emitter conductor 2. The second P-type base region 53 and the first P-type base region 51 constitute a spacer. By reducing the physical distance between the first type trench 40 and the second type trench 43, the flow path during the turn-on phase of the trench gate IGBT is ensured, resulting in greater accumulation of charge carriers near the top, thereby reducing the conductor voltage drop V between the collector conductor 1 and the emitter conductor 2. ceThis reduces losses and avoids additional charging of the first type trench 40 by the P-type doped deep junction region 50. Within the opposing regions of the two first type trenches 40, an N-type source region 52, a second P-type base region 53, and a first P-type base region 51 are provided. An N-type source region 52 is provided in the corresponding region of each of the two first type trenches 40 facing the second P-type base region 53, thus forming two N-type source regions 52 between the lateral sides of the second P-type base region 53 and the two first type trenches 40. An emitter conductor 2 is provided on the upper surface of the second P-type base region 53 and the two N-type source regions 52. The internal space formed by the insulating dielectric layer 42 of the first type trench 40 is filled with first type conductive polysilicon 41, and its top surface is provided with a gate conductor 3. The internal space formed by the insulating dielectric layer 42 of the second type trench 43 is filled with second type conductive polysilicon 44, and its top surface is provided with an emitter conductor 2. An N-type buffer zone 20 and a P-type collector region 10 are sequentially provided at the bottom of the N-type withstand voltage region 30. The bottom surface of the P-type collector region 10 is provided with the collector conductor 1 of the trench gate type IGBT.

[0056] like Figure 1 and Figure 2 As shown, the trench gate IGBT (structure) may include a first type trench 40 and a P-type doped deep junction region 50. A second type trench 43 is additionally provided between the first type trench 40 and the P-type doped deep junction region 50. The second type trench 43 is used to slow down or isolate the charging of the first type trench 40 by the P-type doped deep junction region 50. Compared with the control potential connected to the first type trench 40, the emitter conductor 2 connected to the second type trench has zero potential.

[0057] According to a preferred embodiment, the first type of trench 40 and the second type of trench 43 are separated from each other, and the first P-type base region 51 and the second P-type base region 53 are spaced very narrowly apart. The vertical bottom of the first type of trench 40 and the second type of trench 43 is an arc surface. Preferably, the trench gate IGBT of the present invention has a set of P-type doped deep junction regions 50, second type of trench 43 and first type of trench 40 arranged sequentially from the outside to the inside, wherein another set of P-type doped deep junction regions 50, second type of trench 43 and first type of trench 40 is symmetrically arranged with respect to the axial surface of the trench gate IGBT and the previous set of P-type doped deep junction regions 50, second type of trench 43 and first type of trench 40, so as to form a trench gate IGBT with P-type doped deep junction regions 50, second type of trench 43, first type of trench 40, first type of trench 40, second type of trench 43 and P-type doped deep junction regions 50 arranged sequentially. The emitter conductor 2 is spaced across the upper surfaces of the extremely narrow first P-type base region 51 and the second P-type base region 53 and connected to the E potential via a wire. It should be noted that the doping concentrations of the first and second P-type base regions can be freely set according to requirements, without affecting the implementation of the invention, and are not a key design feature of the invention.

[0058] According to a preferred embodiment, the first type of trench 40 includes a first type of conductive polysilicon 41 wrapped by an insulating dielectric layer 42. The second type of trench 43 includes a second type of conductive polysilicon 44 wrapped by an insulating dielectric layer 42. The P-type doped deep junction region 50, the first P-type base region 51, and the second P-type base region 53 are all disposed vertically above the N-type withstand voltage region 30. Preferably, the N-type buffer zone 20 is disposed vertically below the N-type withstand voltage region 30. The P-type collector region 10 is disposed below the N-type buffer zone 20. It should be noted that during the turn-on phase of the IGBT structure, the potential of the P-type doped deep junction region 50 during charging is slightly higher than the potential of the first type of conductive polysilicon 41. The second type of trench 43 serves as an isolation layer to prevent additional charging of the first type of trench 40 by the P-type doped deep junction region 50. The insulating dielectric layer 42 can be an insulating oxide layer.

[0059] According to a preferred embodiment, the lower surface of the P-type collector region 10 is covered with a collector conductor 1. The upper surface of the first type trench 40 is covered with a gate conductor 3 and connected to the G potential via a wire. The upper surfaces of the first P-type base region 51, the second P-type base region 53, and the N-type source region 52 are covered with emitter conductors 2 and connected to the E potential via wires; the upper surface of the second type trench 43 is covered with emitter conductors 2 and connected to the E potential via a wire.

[0060] According to a preferred embodiment, the second type of trench 43 is adjacent to the P-type doped deep junction region 50. The present invention introduces the second type of trench 43 to provide additional isolation for the charging current of the P-type doped deep junction region 50, preventing it from flowing into the first type of trench 40, thereby reducing the additional gate charging process during the IGBT device's turn-on phase.

[0061] This invention isolates the first type of trench 40 and the P-type doped deep junction region 50 through the second type of trench 43, which can prevent the displacement current charging process of the P-type doped deep junction region 50 on the first type of trench 40 during the IGBT device turn-on process, thus ensuring V ge The rate of change slows down, allowing dI in the initial phase to... c / dt and dV ce The peak value of / dt decreases (e.g.) Figure 9 and Figure 11As shown), the switching controllability is superior. For a power semiconductor device, long-term operational reliability is a critical characteristic, and the factor affecting reliability is the device's power loss. The trench gate IGBT of the present invention reduces the power consumption during the IGBT turn-on phase by more than 30% by addressing the displacement current charging of the first type trench 40 by the P-type doped deep junction region 50, thereby improving the switching reliability and controllability of the IGBT. Furthermore, since the first P-type base region 51 and the second P-type base region 53 between the first type trench 40 and the second type trench 43 are extremely narrow, and the emitter conductor 2 is spaced across the upper surface of the extremely narrow first P-type base region 51 and the second P-type base region 53 and connected to the E potential through a wire, V is almost not sacrificed. cesat (Conduction voltage drop)

[0062] The first type of trench 40 of this invention is in direct contact with the first P-type base region 51 and the second P-type base region 53 on both its left and right sides. Furthermore, the upper surfaces of the first P-type base region 51 and the second P-type base region 53 are covered with emitter conductors 2, which are connected to the E potential via wires. Therefore, the Miller capacitance C of the IGBT device designed in this invention... gc Smaller, shorter Miller plateau duration during switching process (e.g.) Figure 7 As shown in the figure, the switching loss is low.

[0063] It should be noted that in this invention, the collector conductor 1 is the bus voltage. The emitter conductor 2 is grounded. The gate conductor 3 is the control voltage, which is higher than the potential of the first type of conductive polycrystalline silicon 41.

[0064] This invention delays the time it takes for the voltage to reach the Miller plateau by 0.0625 μs by isolating the charging current. This doubles the voltage arrival time compared to existing technologies. Furthermore, the voltage rise curve of this invention does not exhibit an inflection point, while existing technologies show a clear inflection point in the charging current, resulting in an additional charging effect.

[0065] According to a preferred embodiment, the emitter conductors 2 between the first type of trench 40 and the second type of trench 43 can be spaced apart in the trench extension direction. The emitter conductors 2 between the first type of trench 40 and the second type of trench 43 are spaced apart, not continuous. Preferably, the emitter conductors 2 between the first type of trench 40 and the second type of trench 43 can be spaced apart in the trench extension direction with a slot interval of 0.2 μm to 0.4 μm. Preferably, the slot interval can be designed according to different process requirements, preferably below 0.5 μm. Slotting is used to avoid current loss. For example, in the IGBT on-state, if there is no slotting, some charge carriers will be lost from the emitter conductors 2 between the first type of trench 40 and the second type of trench 43. If there is spaced slotting, the lost charge carriers can be reduced to a better level. It is described as a "better level" rather than the "optimal level" because it is difficult to simultaneously achieve the optimal level of both the isolation effect and the reduction of charge carrier loss from spaced slotting. Preferably, the vacancy rate caused by the spacing of the emitter conductors 2 between the first type of trench 40 and the second type of trench 43 ranges from 10% to 30%, preferably 20%. Preferably, the larger the spacing between the emitter conductors 2, the higher the C... ge The smaller the capacitance. For example, when the empty percentage caused by the gap reaches 20%, C ge The capacitance reduction reaches 5% or even higher, and the gate charging delay is reduced by 5%, resulting in a significant improvement in the switching characteristics of the IGBT. Specifically, the spacing of the emitter conductor 2 between the first type of trench 40 and the second type of trench 43 in this invention represents a balanced choice between isolation and reduction of carrier loss. It simultaneously achieves the effects of isolating and preventing carrier loss from the N-type withstand layer 30, and the design of the emitter conductor 2 spacing also reduces C. ge The capacitor is used to reduce the charging delay of the first type of trench 40, thereby significantly improving the switching characteristics of the IGBT.

[0066] The second type of trenches in this invention also results in a narrower trench spacing, ensuring a flow path during the opening process and reducing conduction voltage drop loss. The use of spaced openings and reduced trench spacing can reduce V... cesat (On-state voltage drop) loss, or even virtually no loss, while avoiding additional charging of the first type trench 40 by the P-type doped deep junction region 50.

[0067] like Figure 7 As shown, it illustrates the gate voltage V during the device turn-on phase of the existing conventional injection-enhanced trench gate IGBT structure and the IGBT structure designed in this invention. ge Waveform diagram. Figure 7 The horizontal axis represents time, and the vertical axis represents V. geThe starting interval (first interval) of the horizontal axis is 10 μs, and the subsequent intervals are 0.125 μs. It can be clearly seen that the traditional injection-enhanced trench gate IGBT structure exhibits a significant inflection point phenomenon during the voltage waveform rise, and the Miller plateau duration of the IGBT structure designed in this invention is shortened.

[0068] The Miller plateau corresponding to the Miller capacitance corresponds to the voltage drop time of the IGBT device during the turn-on phase. When the current rise time is similar, a shorter voltage drop time results in lower power consumption during the IGBT device's turn-on phase, conforming to the formula W = ∫(V×I)dt, where W is power consumption, V is voltage, I is current, and t is time. If the voltage drop exhibits a tailing effect during the IGBT device's turn-off phase, failing to continue decreasing, it will lead to excessive power consumption.

[0069] like Figure 8 As shown, it illustrates the Ig ratio of existing conventional injection-enhanced trench gate IGBT structures to the IGBT structure designed in this invention during the device turn-on phase. c Waveform diagram. Figure 8 The horizontal axis represents time, and the vertical axis represents I. c The starting grid (first grid) of the x-axis is 10 μs, and the subsequent intervals are 0.125 μs. Figure 8 The current waveform of the IGBT device during the turn-on phase is displayed.

[0070] like Figure 9 As shown, it illustrates the difference in dI between existing conventional injection-enhanced trench gate IGBT structures and the IGBT structure designed in this invention during the device turn-on phase. c / dt waveform diagram. Figure 9 The horizontal axis represents time, and the vertical axis represents dI. c / dt. The starting cell (first cell) of the x-axis is 10μs, and the subsequent intervals are 0.125μs. Figure 9 The rate of change of current over time is obtained by differentiating the current waveform of the IGBT device during the turn-on phase. This is the current slope. The IGBT structure designed in this invention significantly reduces the peak value of the current slope, which is beneficial to the controllability of the IGBT device.

[0071] like Figure 10 As shown, it illustrates the voltage drop V between the collector conductor 1 and the emitter conductor 2 during dynamic operation in the device turn-on phase of a conventional injection-enhanced trench gate IGBT structure and the IGBT structure designed in this invention. ce Waveform diagram. Figure 10 The horizontal axis represents time, and the vertical axis represents V. ce The starting grid (first grid) of the x-axis is 10 μs, and the subsequent intervals are 0.125 μs. Figure 10This represents the variation of the voltage difference between the collector voltage and the emitter voltage of an IGBT device during the turn-on phase.

[0072] like Figure 11 As shown, it illustrates the dV values ​​of existing conventional injection-enhanced trench gate IGBT structures and the IGBT structure designed in this invention during the device turn-on phase. ce / dt waveform diagram. Figure 11 The horizontal axis represents time, and the vertical axis represents dV. ce / dt. The starting cell (first cell) of the x-axis is 10μs, and the subsequent intervals are 0.125μs. Figure 11 The slope of the voltage difference change is obtained by differentiating the voltage difference between the collector and emitter voltages during the turn-on phase of an IGBT device. The maximum absolute value of the voltage difference change slope in a traditional injection-enhanced trench gate IGBT structure is around 25000 V / μs. However, the maximum absolute value of the voltage difference change slope in the improved IGBT structure of this invention is less than 15000 V / μs, broadening the application range of this IGBT structure and improving the switching controllability of the IGBT device.

[0073] This invention has minimal impact on the cost of IGBT device manufacturing, maintaining the same process, but the structural design changes significantly improve its turn-on performance, reducing power consumption by over 30% and greatly reducing heat generation. The improved IGBT device can operate for extended periods. This invention achieves a substantial reduction in power consumption while improving the switching controllability of the IGBT device by adding only a slight delay during the IGBT turn-on phase. Since IGBT devices are generally high-power devices, significantly reducing power consumption while keeping the increase in delay within an acceptable range is a crucial technical approach. The improved switching controllability of the IGBT device brought about by this invention also prevents accidental turn-on of the IGBT device and avoids switching oscillations in certain situations.

[0074] Example 2

[0075] This embodiment is a further improvement on embodiment 1, and repeated content will not be described again.

[0076] like Figure 5 The diagram shown is a two-dimensional cross-sectional view of another trench-gate IGBT structure according to the present invention. Figure 6 The figure shown is a three-dimensional axial cross-sectional view of another grooved grid IGBT structure according to the present invention.

[0077] According to a preferred embodiment, the trench-gate IGBT structure may include a first type of trench 40 and a P-type doped deep junction region 50. A second type of trench 43 is additionally provided between the first type of trench 40 and the P-type doped deep junction region 50. The second type of trench 43 is used to slow down or isolate the charging of the first type of trench 40 by the P-type doped deep junction region 50. The second type of trench 43 is composed of an insulating dielectric layer 42. The insulating dielectric layer 42 can be an insulating oxide layer. Another trench-gate IGBT structure designed in this invention eliminates the second type of conductive polysilicon 44 in the second type of trench 43, further increasing the insulation effect, and using a single material to construct the second type of trench 43 can save material costs and reduce manufacturing difficulty.

[0078] This invention provides a trench gate IGBT (Insulated Gate Bipolar Translator) device. A first type of trench 40 has a gate conductor 3 covering its upper surface and is connected to the G potential via a wire; a second type of trench 43 has an emitter conductor 2 covering its upper surface and is connected to the E potential via a wire. By isolating the first type of trench 40 and the P-type doped deep junction region 50 through the second type of trench 43, the displacement current charging process of the P-type doped deep junction region 50 on the first type of trench 40 during the turn-on process can be avoided, enhancing the switching controllability of the device. Furthermore, this device has a smaller Miller capacitance and lower switching losses.

[0079] Throughout the text, the features indicated by "preferred" are only optional and should not be construed as mandatory. Therefore, the applicant reserves the right to abandon or delete the relevant preferred features at any time.

[0080] It should be noted that the specific embodiments described above are exemplary. Those skilled in the art can devise various solutions inspired by the disclosure of this invention, and these solutions all fall within the scope of this invention and its protection. Those skilled in the art should understand that this specification and its accompanying drawings are illustrative and not intended to limit the scope of the claims. The scope of protection of this invention is defined by the claims and their equivalents. This specification contains multiple inventive concepts; terms such as "preferredly," "according to a preferred embodiment," or "optionally" indicate that the corresponding paragraph discloses an independent concept. The applicant reserves the right to file divisional applications based on each inventive concept.

Claims

1. A trench gate IGBT, characterized by, The IGBT includes at least a first type of trench (40) and a P-type doped deep junction region (50), wherein, A second type of trench (43) is also provided between the first type of trench (40) and the P-type doped deep junction region (50). The P-type doped deep junction region (50), the second type of trench (43) and the first type of trench (40) are arranged in sequence from the outside to the inside. The second type of trench (43) isolates the first type of trench (40) and the P-type doped deep junction region (50) to provide additional isolation for the charging current of the P-type doped deep junction region (50) so that it does not flow to the first type of trench (40). The second type of trench (43) is in direct contact with the P-type doped deep junction region (50) to isolate the hole flow of the P-type doped deep junction region (50) to the first type of trench (40) during the IGBT turn-on phase, so as to slow down or isolate the charging of the P-type doped deep junction region (50) to the first type of trench (40). In the region between the second type of trench (43) and the corresponding first type of trench (40), an additional spacer consisting of a second P-type base region (53) and a first P-type base region (51) is provided. The spacer extends longitudinally along the trench between the first type of trench (40) and the second type of trench (43). The spacer is provided with conductive contact portions at intervals in its longitudinal extension direction. The conductive contact portion of the second P-type base region (53) near the spacer maintains the same potential as the emitter conductor (2). The emitter conductors (2) between the first type of trench (40) and the second type of trench (43) are spaced apart at least in the extension direction of the trench, wherein the emitter conductors (2) between the first type of trench (40) and the second type of trench (43) are spaced apart in a discontinuous manner with slotted intervals at least in the extension direction of the trench to reduce the on-state voltage drop loss; the range of the vacancy rate caused by the spaced distribution of the emitter conductors (2) between the first type of trench (40) and the second type of trench (43) is 10% to 30%.

2. The trench-gate IGBT according to claim 1, characterized by, Compared to the control potential connected to the first type of trench (40), the emitter conductor (2) connected to the second type of trench (43) has zero potential.

3. The trench-gate IGBT according to claim 1, characterized by, The first type of trench (40) comprises a first type of conductive polycrystalline silicon (41) enclosed by an insulating dielectric layer (42), wherein, The second type of trench (43) comprises a second type of conductive polysilicon (44) enclosed by the insulating dielectric layer (42), or The second type of trench (43) is formed by the insulating dielectric layer (42).

4. The trench-gate IGBT according to claim 1, characterized by, The IGBT further includes a first P-type base region (51), a second P-type base region (53), and an N-type source region (52), wherein, The first P-type base region (51), the second P-type base region (53), and the N-type source region (52) are covered by the emitter conductor (2) and connected to the E potential through a wire; the second type of trench (43) is covered by the emitter conductor (2) and connected to the E potential through a wire.

5. The trench-gate IGBT according to claim 4, characterized by The first type of trench (40) and the second type of trench (43) are separated, and the first P-type base region (51) and the second P-type base region (53) are spaced apart in the middle.

6. The trench gate IGBT according to claim 4, characterized in that, The IGBT further includes a P-type collector region (10), an N-type buffer region (20), and an N-type withstand voltage region (30), wherein, The P-type collector region (10), N-type buffer region (20) and N-type withstand voltage region (30) are arranged in sequence so that the N-type withstand voltage region (30) contacts the first type trench (40), the second type trench (43), the P-type doped deep junction region (50) and the first P-type base region (51).

7. The trench gate IGBT according to claim 6, characterized in that, The P-type doped deep junction region (50), the first P-type base region (51), and the second P-type base region (53) are arranged to cover the N-type breakdown voltage region (30) and not to contact the P-type collector region (10) and the N-type buffer region (20) to guide hole flow.

8. The trench gate IGBT according to claim 6, characterized in that, The P-type collector region (10) is covered with a collector conductor (1); the first type of trench (40) is covered with a gate conductor (3) and connected to the G potential via a wire.

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