Asymmetric MSM tunnel junction diode with high rectification ratio and method of manufacturing the same

Abstract

The application discloses an asymmetric MSM tunnel junction diode with high rectification ratio and a preparation method thereof. The asymmetric MSM tunnel junction diode comprises a first metal layer, an insulating layer, a second metal layer and a semiconductor layer. The first metal layer is configured as a lower electrode and has a front surface and a back surface. The insulating layer is configured to be formed on the front surface of the first metal layer, and a part of the front surface of the first metal layer is not covered by the insulating layer to form a semiconductor channel forming area. The second metal layer is configured as an upper electrode and is formed on the front surface of the insulating layer away from the first metal layer, and the second metal layer completely covers the front surface of the insulating layer. The semiconductor layer is configured to be formed between the semiconductor channel forming area and a side wall of the second metal layer facing the semiconductor channel forming area. The asymmetric MSM tunnel junction diode has the advantages of super-high rectification ratio, wide temperature working range and the like, and the preparation method is simple, low in cost, easy to implement, safe and environmentally friendly.

Description

Technical Field

[0001] This invention relates to the field of diode technology, and in particular to an asymmetric MSM tunnel junction diode with a high rectification ratio and its fabrication method. Background Technology

[0002] High-frequency rectifier diodes are crucial for applications such as solar energy harvesting, terahertz mixers, and infrared detectors. Nanoscale MIM rectifier diodes (MIM stands for "Metal-Insulator-Metal," a common industry abbreviation) benefit from their ultrafast quantum electron transport mechanism and typical femtosecond tunneling time (~10^6 seconds). -15 s), has been extensively studied in the high-frequency region.

[0003] The performance of MIM rectifier diodes under DC power is considered an important indicator of their high-frequency performance, mainly reflected in current asymmetry, nonlinearity, current density, and forward voltage. To obtain high-performance MIM rectifier diodes, many research institutions both domestically and internationally are currently focusing their research and development on improving the selection and combination of the device's metal electrodes and insulating layers.

[0004] However, through comprehensive research on the impact of insulation layer thickness and the absolute value of the work function difference between the two electrodes on the rectification performance of MIM rectifier diodes, it has been found that, due to limitations in manufacturing capabilities and other compatibility considerations, the materials currently considered are limited to TiO2, ZrO2, and Nb2O5. These materials, however, introduce poor thermodynamic stability at the metal / insulator interface, resulting in poor rectification characteristics. Therefore, improving the structure of MIM rectifier diodes to enhance material compatibility is a challenge for improving their performance.

[0005] Furthermore, current research has shown that introducing multiple insulating layers into the high-frequency rectifier diode structure to form a MIIM rectifier diode structure (MIIM is an abbreviation for "metal-insulator-insulator-metal," also a common industry term) can further improve current asymmetry and nonlinearity. However, due to the use of multiple insulating layers, different material combinations bring more difficulties to device manufacturing. To date, commercially available rectifier diode products, whether based on MIM or MIIM structures, still exhibit poor current asymmetry performance, typically below 10. 3 .

[0006] In view of this, the present invention is hereby proposed. Summary of the Invention

[0007] To overcome the above-mentioned defects, the present invention provides an asymmetric MSM tunnel junction diode with high rectification ratio and its fabrication method. The diode device has the advantages of ultra-high rectification ratio and wide operating temperature range, and the fabrication method is simple, low-cost, easy to implement, safe and environmentally friendly.

[0008] The technical solution adopted by this invention to solve its technical problem is: an asymmetric MSM tunnel junction diode with a high rectification ratio, comprising:

[0009] A first metal layer is configured as a lower electrode, having a front side and a back side arranged opposite to the front side.

[0010] An insulating layer is configured to be formed on the front side of the first metal layer, while a portion of the front side of the first metal layer is not covered by the insulating layer to form a semiconductor channel forming region.

[0011] A second metal layer, configured as an upper electrode, is formed on the front side of the insulating layer opposite to the first metal layer, while the second metal layer completely covers the front side of the insulating layer; and...

[0012] A semiconductor layer is configured to be formed between the semiconductor channel forming region and a sidewall of the second metal layer facing the semiconductor channel forming region.

[0013] As a further improvement of the present invention, the semiconductor layer covers the semiconductor channel forming region, the sidewall of the insulating layer facing the semiconductor channel forming region, the sidewall of the second metal layer facing the semiconductor channel forming region, and the front side of the second metal layer facing away from the insulating layer.

[0014] As a further improvement of the present invention, an insulating substrate layer is also provided, the first metal layer is formed on the insulating substrate layer, and the side of the first metal layer facing away from the insulating substrate layer is the front side of the first metal layer.

[0015] As a further improvement of the present invention, the materials of the first metal layer and the second metal layer are each selected from one of metal electrode materials, metal nitride electrode materials and oxide electrode materials; wherein, the metal electrode material is selected from at least one of gold, silver, copper, aluminum, cobalt, chromium, hafnium, indium, iridium, magnesium, manganese, molybdenum, nickel, lead, palladium, platinum, rhodium, tantalum, titanium, tungsten, zinc and gadolinium; the metal nitride electrode material is selected from at least one of titanium nitride, tantalum nitride, nickel nitride, chromium nitride, lithium manganese nitride, lithium cobalt nitride, vanadium nitride and niobium nitride; the oxide electrode material is selected from indium tin oxide.

[0016] As a further improvement of the present invention, the material of the insulating layer is selected from organic insulating materials or inorganic insulating materials, wherein the organic insulating material is selected from one of polyvinyl alcohol, polymethyl methacrylate and polyvinylidene fluoride; and the inorganic insulating material is selected from one of alumina, silicon dioxide and hafnium oxide.

[0017] As a further improvement of the present invention, the material of the semiconductor layer is selected from inorganic semiconductor materials, organic semiconductor materials, and two-dimensional semiconductor materials; wherein, the inorganic semiconductor material is selected from silicon, germanium, silicon-germanium, aluminum antimony, gallium antimony, indium antimony, gallium arsenide, indium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, cadmium selenide, cadmium telluride, cadmium sulfide, zinc selenide, zinc telluride, zinc sulfide, zinc oxide, titanium oxide, lead sulfide, and lead telluride; the organic semiconductor material is selected from pentacene, copper phthalocyanine, and 6,13-bis(triisopropylsilylethynyl)pentacene; the two-dimensional semiconductor material is selected from molybdenum disulfide, tungsten diselenide, rhenium disulfide, platinum diselenide, niobium diselenide, indium selenide, tin sulfide, and tin disulfide.

[0018] As a further improvement of the present invention, the material of the insulating substrate layer is selected from one of silicon plates, silicon dioxide plates, quartz glass plates and ceramic plates.

[0019] As a further improvement of the present invention, the first metal layer is formed on the insulating substrate by deposition; the insulating layer is formed on the front side of the first metal layer by deposition; the second metal layer is formed on the front side of the insulating layer by deposition; and the semiconductor layer is formed between the semiconductor channel forming region and the sidewall of the second metal layer facing the semiconductor channel forming region by deposition.

[0020] As a further improvement of the present invention, the thickness of the first metal layer is 30-60 nm; the thickness of the insulating layer is 1-10 nm; the thickness of the second metal layer is 30-60 nm; and the thickness of the semiconductor layer is 10-30 nm.

[0021] This invention also provides a method for fabricating an asymmetric MSM tunnel junction diode with a high rectification ratio, comprising the following fabrication steps:

[0022] S1: Provide an insulating substrate layer and pre-treat the insulating substrate layer to make the surface of the insulating substrate layer clean;

[0023] S2: A first metal layer is deposited on the clean front side of the insulating substrate layer, the first metal layer being used as the lower electrode;

[0024] S3: Deposit an insulating layer on the front side of the first metal layer that is opposite to the insulating substrate layer;

[0025] S4: A second metal layer is deposited on the front side of the insulating layer opposite to the first metal layer, and the second metal layer is used as the upper electrode;

[0026] S5: Remove the portion of the insulating layer located on the front side of the first metal layer that is not covered by the second metal layer, so as to form a semiconductor channel forming region not covered by the insulating layer on the front side of the first metal layer;

[0027] S6: Deposit a semiconductor layer between the semiconductor channel forming region and the sidewall of the second metal layer facing the semiconductor channel forming region; thus, the asymmetric MSM tunnel junction diode is obtained.

[0028] As a further improvement of the present invention, the method for pre-treating the insulating substrate layer in S1 above is as follows: first, the insulating substrate layer is ultrasonically cleaned, and then the insulating substrate layer is dried with a nitrogen gun.

[0029] As a further improvement of the present invention, the deposition methods used in S2, S3, S4 and S6 above are selected from either physical vapor deposition or chemical vapor deposition.

[0030] As a further improvement of the present invention, in S5 above, an etching technique is used to remove the portion of the insulating layer located on the front side of the first metal layer that is not covered by the second metal layer.

[0031] The beneficial effects of this invention are: 1) This invention innovates the diode device structure by using an insulating layer to separate the upper and lower electrodes, and forming a semiconductor layer between the front side of the lower electrode and the sidewall of the upper electrode, resulting in an asymmetric MSM tunnel junction structure composed of a "metal layer (upper electrode) - insulating layer - semiconductor layer - metal layer (lower electrode)". This structural design replaces multiple insulating layers with a thin semiconductor layer, which effectively avoids the disadvantages of low thermal stability and poor current asymmetry performance in traditional directly stacked metal / insulator / metal (MIM) rectifier diodes, giving the diode device advantages such as ultra-high rectification ratio and wide operating temperature range. In addition, this asymmetric MSM tunnel junction structure can also avoid damage to the semiconductor, making it applicable to a wide range of semiconductors. 2) The fabrication method used in this invention is simple, low-cost, easy to implement, and safe and environmentally friendly. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of the asymmetric MSM tunnel junction diode with high rectification ratio described in this invention;

[0033] Figure 2This is a process flow diagram of the fabrication process of the asymmetric MSM tunnel junction diode with high rectification ratio described in this invention;

[0034] Figure 3 The current-voltage characteristic curve of the asymmetric MSM tunnel junction diode obtained in this invention is shown.

[0035] Figure 4 The curves showing the current-voltage characteristics of the asymmetric MSM tunnel junction diode obtained in this invention as a function of temperature are shown.

[0036] Referring to the accompanying drawings, the following explanations are provided:

[0037] 1. Insulating substrate layer; 2. First metal layer; 3. Insulating layer; 4. Second metal layer; 5. Semiconductor layer. Detailed Implementation

[0038] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Example 1:

[0040] This embodiment 1 provides an asymmetric MSM tunnel junction diode structure with a high rectification ratio. See attached diagram. Figure 1 As shown, the asymmetric MSM tunnel junction diode includes an insulating substrate layer 1, a first metal layer 2, an insulating layer 3, a second metal layer 4, and a semiconductor layer 5. The first metal layer 2 is formed on the insulating substrate layer 1 and configured as the lower electrode. The first metal layer 2 has a front side and a back side arranged opposite to the front side, and the side of the first metal layer 2 facing away from the insulating substrate layer 1 is the front side of the first metal layer 2. The insulating layer 3 is configured to be formed on the front side of the first metal layer 2, and a portion of the front side of the first metal layer 2 is not covered by the insulating layer 3 to form a semiconductor channel forming region. The second metal layer 4 is configured as the upper electrode, formed on the front side of the insulating layer 3 facing away from the first metal layer 2, and the second metal layer 4 completely covers the front side of the insulating layer 3. The semiconductor layer 5 is configured to be formed between the semiconductor channel forming region and a sidewall of the second metal layer 4 facing the semiconductor channel forming region. That is, the first metal layer (lower electrode), the insulating layer, the semiconductor layer, and the second metal layer (upper electrode) constitute the asymmetric MSM tunnel junction structure.

[0041] Compared to traditional directly stacked metal / insulator / metal (MIM) rectifier diode structures, this invention replaces the insulating layer with a thin semiconductor layer. This semiconductor layer, with its unique bending energy band, concentrates the electric field at the tunneling point during tunneling, resulting in a higher current density than existing MIM structures (which can be derived from the tunneling current formula). This effectively avoids the drawbacks of existing MIM structures, such as lower thermal stability and poor current asymmetry performance, giving the diode device advantages such as ultra-high rectification ratio and a wide operating temperature range. Furthermore, this asymmetric MSM tunnel junction structure avoids damage to the semiconductor, making it applicable to a wider range of semiconductors.

[0042] The following provides a detailed description of the material selection, molding method, specific structure and / or structural dimensions of each layer in this asymmetric MSM tunnel junction diode.

[0043] Regarding the specific material selection for the above five layers, preferably, the insulating substrate layer 1 is selected from one of silicon plates, silicon dioxide plates, quartz glass plates, and ceramic plates. For example, silicon dioxide plates are preferably used for the insulating substrate layer 1. Of course, the material selection for the insulating substrate layer 1 is not limited to the above materials; any material that can meet the advantages of good insulation performance, high temperature resistance, and high flatness can be used as the insulating substrate layer 1.

[0044] The materials of the first metal layer 2 and the second metal layer 4 are each selected from one of the following: metal electrode materials, metal nitride electrode materials, and oxide electrode materials; wherein, the metal electrode materials are selected from at least one of gold (Au), silver (Ag), copper (Cu), aluminum (Al), cobalt (Co), chromium (Cr), hafnium (Hf), indium (In), iridium (Ir), magnesium (Mg), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), tantalum (Ta), titanium (Ti), tungsten (W), zinc (Zn), and gadolinium (Gd); the metal nitride electrode materials are selected from at least one of titanium nitride (TiN), tantalum nitride (N5Ta3), nickel nitride (N2Ni3), chromium nitride (CrN), lithium manganese nitride, lithium cobalt nitride, vanadium nitride (NV), and niobium nitride (NbN); and the oxide electrode materials are selected from indium tin oxide.

[0045] Furthermore, the materials used for the first metal layer 2 and the second metal layer 4 can be the same or different. For example, the first metal layer 2 can preferably be made of titanium nitride (TiN), and the second metal layer 4 can preferably be made of platinum (Pt). Of course, the materials used for the first metal layer 2 and the second metal layer 4 are not limited to those listed above; any material suitable for use as a conductor electrode is acceptable.

[0046] The material of the insulating layer 3 is selected from organic or inorganic insulating materials. Specifically, the organic insulating material is selected from polyvinyl alcohol (PVA), polymethyl methacrylate (PMMA), and polyvinylidene fluoride (PVDF); the inorganic insulating material is selected from alumina (Al2O3), silicon dioxide (SiO2), and hafnium oxide (HfO2). For example, alumina (Al2O3) is preferably used for the insulating layer 3. However, the selection of the material for the insulating layer 3 is not limited to the materials listed above; any material that meets the product requirements is acceptable.

[0047] The material of the semiconductor layer 5 is selected from inorganic semiconductor materials, organic semiconductor materials, and two-dimensional semiconductor materials; wherein, the inorganic semiconductor material is selected from silicon (Si), germanium (Ge), silicon-germanium-SiGe, aluminum antimonide (AlSb), gallium antimonide (GaSb), indium antimonide (InSb), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), indium phosphide (InP), cadmium selenide (CdSe), cadmium telluride (CdTe), cadmium sulfide (CdS), zinc selenide (ZnSe), zinc telluride (ZnTe), zinc sulfide (ZnS), zinc oxide (ZnO), titanium oxide (TiO2), lead sulfide (PbS), and lead telluride (PbTe); the organic semiconductor material is selected from pentacene C 22 H 14 The semiconductor material is selected from one of copper phthalocyanine (CuPc) and 6,13-bis(triisopropylsilylethynyl)pentaphenyl (TIPS-pentaphenyl); the two-dimensional semiconductor material is selected from one of molybdenum disulfide (MoS2), tungsten diselenide (WSe2), rhenium disulfide (ReS2), platinum diselenide (PtSe2), niobium diselenide (NbSe2), indium selenide (InSe), tin sulfide (SnS), and tin disulfide (SnS2). For example, zinc oxide (ZnO) is preferably used for the semiconductor layer 5. Similarly, the selection of the semiconductor layer 5 is not limited to the materials listed above, as long as the product requirements are met.

[0048] Regarding the forming method of the first metal layer 2, insulating layer 3, second metal layer 4 and semiconductor layer 5, preferably, the first metal layer 2 is formed on the insulating substrate layer 1 by deposition; the insulating layer 3 is formed on the front side of the first metal layer 2 by deposition; the second metal layer 4 is formed on the front side of the insulating layer 3 by deposition; and the semiconductor layer 5 is formed between the semiconductor channel forming region and the sidewall of the second metal layer 4 facing the semiconductor channel forming region by deposition.

[0049] Regarding the aforementioned deposition method, any one of physical vapor deposition (PCD) and chemical vapor deposition (CVD) can be selected. Furthermore, the deposition method can preferably be any one of evaporation deposition, magnetron sputtering deposition, ion plating, plasma chemical vapor deposition, low-pressure chemical vapor deposition, thermochemical vapor deposition, and atomic layer deposition. That is, the deposition methods for the first metal layer 2, insulating layer 3, second metal layer 4, and semiconductor layer 5 can be the same or different; this invention does not impose excessive restrictions, as long as a metal layer / insulating layer / semiconductor layer can be formed.

[0050] Regarding the specific structure and dimensions of the above five layers, preferably, the first metal layer 2, the insulating layer 3, and the second metal layer 4 are all planar bodies with uniform thickness, and the thickness of the first metal layer 2 is 30-60nm (preferably 50nm), the thickness of the insulating layer 3 is 1-10nm (preferably 10nm), and the thickness of the second metal layer 4 is 30-60nm (preferably 50nm).

[0051] The semiconductor layer 5 covers the semiconductor channel forming region, the sidewall of the insulating layer 3 facing the semiconductor channel forming region, the sidewall of the second metal layer 4 facing the semiconductor channel forming region, and the front side of the second metal layer 4 facing away from the insulating layer 3. The semiconductor layer 5 has a smooth transition connection with the insulating layer 3, the second metal layer 4, and the semiconductor channel forming region; that is, the semiconductor layer 5 has an overall Z-shaped structure. The thickness of the semiconductor layer 5 is 10–30 nm (preferably 20 nm).

[0052] Example 2:

[0053] This embodiment 2 provides a method for fabricating an asymmetric MSM tunnel junction diode with a high rectification ratio, see attached figure. Figure 2 As shown, the production steps include the following:

[0054] S1: Provide an insulating substrate layer 1 and pre-treat the insulating substrate layer 1 to make the surface of the insulating substrate layer 1 clean.

[0055] Specifically, the pretreatment method for the insulating substrate layer 1 is as follows: first, the insulating substrate layer 1 is ultrasonically cleaned, and then dried with a nitrogen gun. During ultrasonic cleaning of the insulating substrate layer 1, it can be cleaned multiple times with different cleaning media and parameters as needed. For example, the insulating substrate layer 1 can be first placed in acetone and ultrasonically cleaned for 3 minutes at a working frequency of 40 kHz and a working power of 100 W; then, the insulating substrate layer 1 can be placed in an alcohol solution and ultrasonically cleaned for 3 minutes under the same working conditions; finally, the insulating substrate layer 1 can be placed in deionized water and ultrasonically cleaned for 3 minutes under the same working conditions to ensure the surface of the insulating substrate layer 1 is as clean as possible, which is beneficial for the fabrication of the first metal layer 2.

[0056] S2: A first metal layer 2 with a thickness of 30-60 nm is deposited on the clean front side of the insulating substrate layer 1. The first metal layer 2 is used as the lower electrode.

[0057] Specifically, the deposition method used to fabricate the first metal layer 2 can be selected from either physical vapor deposition (PCD) or chemical vapor deposition (CVD), with magnetron sputtering deposition being a preferred method. Taking the fabrication of a 50 nm thick titanium nitride (TiN) layer as a reference, the specific processing parameters for magnetron sputtering deposition are: power 150 W, argon flow rate 50 sccm, working pressure 0.8 Pa, and deposition rate...

[0058] S3: An insulating layer 3 with a thickness of 1 to 10 nm is deposited on the front side of the first metal layer 2 facing away from the insulating substrate layer 1.

[0059] Specifically, the deposition method used to fabricate the insulating layer 3 can be selected from either physical vapor deposition (PCD) or chemical vapor deposition (CVD), with atomic layer deposition (ALD) being a preferred method. Taking the fabrication of a 10 nm thick alumina (Al2O3) layer as a baseline, the specific processing parameters for ALD are as follows: using [Al(CH3)]3 as the metal precursor and water as the oxidant in an argon atmosphere with a background pressure of 0.25 Pa, a relatively dense alumina thin film layer is prepared by 100 cycles.

[0060] S4: A second metal layer 4 with a thickness of 30-60 nm is deposited on the front side of the insulating layer 3 facing away from the first metal layer 2. The second metal layer 4 is used as the upper electrode.

[0061] Specifically, the deposition method used to fabricate the second metal layer 4 can be any one of physical vapor deposition (PCD) and chemical vapor deposition (CVD), with magnetron sputtering being a preferred method. Taking the fabrication of a 50 nm thick platinum (Pt) layer as a reference, the specific processing parameters for magnetron sputtering deposition are as follows: DC magnetron sputtering, power of 100 W, argon flow rate of 50 sccm, working pressure of 0.3 Pa, and deposition rate of...

[0062] S5: Remove the portion of the insulating layer 3 located on the front side of the first metal layer 2 that is not covered by the second metal layer 4, so as to form a semiconductor channel forming region on the front side of the first metal layer 2 that is not covered by the insulating layer 3.

[0063] Specifically, an etching technique is used to remove part of the insulating layer 3, and the etching technique is preferably oxygen ion etching or argon ion etching. Based on argon ion etching, the specific processing parameters are as follows: etching for 15 minutes in an argon atmosphere with a working pressure of 0.02 Pa, a cathode current of 5 A, an anode voltage of 60 V, a neutralization current of 60 mA, an accelerating voltage of 160 V, and a grid energy of 500 eV, thereby completing the removal of part of the insulating layer 3.

[0064] S6: Deposit a semiconductor layer 5 with a thickness of 10-30 nm between the semiconductor channel forming region and the sidewall of the second metal layer 4 facing the semiconductor channel forming region; thus, the asymmetric MSM tunnel junction diode is obtained.

[0065] Specifically, the deposition method used to fabricate the semiconductor layer 5 can be selected from either physical vapor deposition (PCD) or chemical vapor deposition (CVD), with radio frequency magnetron sputtering being a preferred method. Taking the fabrication of a 20nm thick zinc oxide (ZnO) layer as a reference, the specific processing parameters for radio frequency magnetron sputtering deposition are as follows: radio frequency sputtering for 10 minutes under the conditions of a cavity pressure of 0.8 Pa, an Ar flow rate of 50 sccm, and a working power of 80 W.

[0066] As can be seen from the above, the preparation method used in this invention is simple, low-cost, easy to implement, and safe and environmentally friendly.

[0067] The asymmetric MSM tunnel junction diode prepared in Example 1 was subjected to electrical performance testing. The test methods and results are as follows.

[0068] Test method: The asymmetric MSM tunnel junction diode prepared in Example 1 was placed in a vacuum probe station. A special tungsten probe was used to press on the upper and lower electrodes of the diode. A Keithley 4200 was used to scan the diode at ±2V, specifically providing scan data every 0.1V. The current-voltage characteristic curve of the asymmetric MSM tunnel junction diode was then obtained based on the obtained scan data (see Appendix). Figure 3 (as shown), and the current-voltage characteristic curve of the asymmetric MSM tunnel junction diode as a function of temperature (see Appendix). Figure 4 (As shown).

[0069] Test results: From the attached Figure 3 As can be seen from the data, the rectification ratio of this asymmetric MSM tunnel junction diode is 10. 4 It is very high, to the left and right.

[0070] From the appendix Figure 4 As can be seen, the volt-ampere characteristic of this asymmetric MSM tunnel junction diode changes very little as the test temperature increases from 100K to 400K. Therefore, this asymmetric MSM tunnel junction diode has excellent thermal stability and a wide operating temperature range.

[0071] In summary, the asymmetric MSM tunnel junction diode prepared by this invention has advantages such as ultra-high rectification ratio and wide operating temperature range. Moreover, its preparation method is simple, low-cost, easy to implement, safe and environmentally friendly.

[0072] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. An asymmetric MSM tunnel junction diode with a high rectification ratio, characterized in that: include: The first metal layer (2) is configured as a lower electrode, having a front side and a back side arranged opposite to the front side; An insulating layer (3) is configured to be formed on the front side of the first metal layer (2), wherein a portion of the front side of the first metal layer (2) is not covered by the insulating layer (3) to form a semiconductor channel forming region; the thickness of the insulating layer (3) is 1 to 10 nm, and the material of the insulating layer (3) is selected from organic insulating materials or inorganic insulating materials, wherein the organic insulating material is selected from one of polyvinyl alcohol, polymethyl methacrylate and polyvinylidene fluoride, and the inorganic insulating material is selected from one of alumina, silicon dioxide and hafnium oxide; A second metal layer (4), configured as an upper electrode, is formed on the front side of the insulating layer (3) facing away from the first metal layer (2), while the second metal layer (4) completely covers the front side of the insulating layer (3); and, The semiconductor layer (5) is configured to be formed on the semiconductor channel forming region, the sidewall of the insulating layer (3) facing the semiconductor channel forming region, the sidewall of the second metal layer (4) facing the semiconductor channel forming region, and the front side of the second metal layer (4) facing away from the insulating layer (3); that is, the semiconductor layer (5) is a smooth Z-shaped structure and its thickness is 10-30 nm. By combining the insulating layer (3) with the semiconductor layer (5) having a bent energy band, the electric field is concentrated at the tunneling point during tunneling, resulting in a rectification ratio of 10 for the diode. 4 The operating temperature range is 100K to 400K.

2. The asymmetric MSM tunnel junction diode with high rectification ratio according to claim 1, characterized in that: An insulating substrate layer (1) is also provided, and the first metal layer (2) is formed on the insulating substrate layer (1), and the side of the first metal layer (2) facing away from the insulating substrate layer (1) is the front side of the first metal layer (2).

3. The asymmetric MSM tunnel junction diode with high rectification ratio according to claim 1, characterized in that: The materials of the first metal layer (2) and the second metal layer (4) are each selected from one of the following: metal electrode materials, metal nitride electrode materials, and oxide electrode materials; wherein, The metal electrode material is selected from at least one of gold, silver, copper, aluminum, cobalt, chromium, hafnium, indium, iridium, magnesium, manganese, molybdenum, nickel, lead, palladium, platinum, rhodium, tantalum, titanium, tungsten, zinc and gadolinium; The metal nitride electrode material is selected from at least one of titanium nitride, tantalum nitride, nickel nitride, chromium nitride, lithium manganese nitride, lithium cobalt nitride, vanadium nitride, and niobium nitride. The oxide electrode material is selected from indium tin oxide.

4. The asymmetric MSM tunnel junction diode with high rectification ratio according to claim 1, characterized in that: The material of the semiconductor layer (5) is selected from one of inorganic semiconductor materials, organic semiconductor materials and two-dimensional semiconductor materials; The inorganic semiconductor material is selected from one of silicon, germanium, silicon-germanium, aluminum antimony, gallium antimony, indium antimony, gallium arsenide, indium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, cadmium selenide, cadmium telluride, cadmium sulfide, zinc selenide, zinc telluride, zinc sulfide, zinc oxide, titanium oxide, lead sulfide, and lead telluride. The organic semiconductor material is selected from one of pentacene, copper phthalocyanine, and 6,13-bis(triisopropylsilylethynyl)pentacene; The two-dimensional semiconductor material is selected from one of molybdenum disulfide, tungsten diselenide, rhenium disulfide, platinum diselenide, niobium diselenide, indium selenide, tin sulfide, and tin disulfide.

5. The asymmetric MSM tunnel junction diode with high rectification ratio according to claim 2, characterized in that: The material of the insulating substrate layer (1) is selected from one of silicon plates, silicon dioxide plates, quartz glass plates and ceramic plates.

6. The asymmetric MSM tunnel junction diode with high rectification ratio according to claim 2, characterized in that: The first metal layer (2) is formed on the insulating substrate layer (1) by deposition; The insulating layer (3) is formed on the front side of the first metal layer (2) by deposition; The second metal layer (4) is formed on the front side of the insulating layer (3) by deposition; The semiconductor layer (5) is formed by deposition between the semiconductor channel forming region and the sidewall of the second metal layer (4) facing the semiconductor channel forming region.

7. The asymmetric MSM tunnel junction diode with high rectification ratio according to claim 1, characterized in that: The thickness of the first metal layer (2) is 30-60 nm; the thickness of the second metal layer (4) is 30-60 nm.

8. A method for fabricating an asymmetric MSM tunnel junction diode with a high rectification ratio, characterized in that: The production process includes the following steps: S1: Provide an insulating substrate layer (1) and pre-treat the insulating substrate layer (1) to make the surface of the insulating substrate layer (1) clean; S2: A first metal layer (2) is deposited on the clean front side of the insulating substrate layer (1), and the first metal layer (2) is used as the lower electrode; S3: An insulating layer (3) with a thickness of 1 to 10 nm is deposited on the front side of the first metal layer (2) facing away from the insulating substrate layer (1); and the material of the insulating layer (3) is selected from organic insulating materials or inorganic insulating materials, wherein the organic insulating material is selected from one of polyvinyl alcohol, polymethyl methacrylate and polyvinylidene fluoride, and the inorganic insulating material is selected from one of alumina, silicon dioxide and hafnium oxide; S4: A second metal layer (4) is deposited on the front side of the insulating layer (3) opposite to the first metal layer (2), and the second metal layer (4) is used as the upper electrode; S5: Remove the portion of the insulating layer (3) located on the front side of the first metal layer (2) that is not covered by the second metal layer (4) to form a semiconductor channel forming region not covered by the insulating layer (3) on the front side of the first metal layer (2); S6: A semiconductor layer (5) with a thickness of 10-30 nm is deposited on the semiconductor channel forming region, the sidewall of the insulating layer (3) facing the semiconductor channel forming region, the sidewall of the second metal layer (4) facing the semiconductor channel forming region, and the front side of the second metal layer (4) facing away from the insulating layer (3), that is, the semiconductor layer (5) has a Z-shaped structure; that is, a rectification ratio of 10 is obtained. 4 Asymmetric MSM tunnel junction diode with an operating temperature range of 100K to 400K.

9. The method for fabricating an asymmetric MSM tunnel junction diode with a high rectification ratio according to claim 8, characterized in that: The method for pre-treating the insulating substrate layer (1) in S1 above is as follows: first, the insulating substrate layer (1) is ultrasonically cleaned, and then the insulating substrate layer (1) is dried with a nitrogen gun.

10. The method for fabricating an asymmetric MSM tunnel junction diode with a high rectification ratio according to claim 8, characterized in that: The deposition methods used in S2, S3, S4 and S6 above are selected from either physical vapor deposition or chemical vapor deposition.

11. The method for fabricating an asymmetric MSM tunnel junction diode with a high rectification ratio according to claim 8, characterized in that: In S5 above, etching technology is used to remove the portion of the insulating layer (3) located on the front side of the first metal layer (2) that is not covered by the second metal layer (4).

Images