Edge emitting laser implemented for on-chip generation of spatial light beams

Abstract

The application provides a preparation method of a spatial light beam on-chip generated edge-emitting laser, comprising the following steps: obtaining a tunnel cascade semiconductor laser epitaxial structure, and packaging according to the tunnel cascade semiconductor laser epitaxial structure to obtain a large optical cavity edge-emitting laser; using FDTD unit parameter scanning and a spatial light field distribution function in combination with MATLAB to obtain a superstructure surface phase distribution integrated on the large optical cavity edge-emitting laser, and selecting nano pillars of different sizes to generate a corresponding structure layout; and according to the corresponding structure layout, using a focused ion beam process to etch a superstructure surface on an active region end face of light emission of the large optical cavity edge-emitting laser to construct a superstructure surface edge-emitting laser. The application solves the problems of small output power, excessively large divergence angle, low beam quality and single function of the laser in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor lasers, and in particular to an edge-emitting laser that realizes on-chip generation of spatial beams. Background Technology

[0002] Lasers are another major invention of humankind in the 20th century, following nuclear energy, computers, and semiconductors. Compared with ordinary light sources, lasers possess high monochromaticity, high directionality, high brightness, and good coherence, thus attracting widespread attention. In recent years, with the rapid development of science and technology, compact semiconductor lasers have played a very important role in fields such as facial recognition, lidar, and optical communication due to their superior characteristics.

[0003] Based on the beam emission method, common semiconductor lasers can be divided into two types: edge-emitting lasers, where the beam exits parallel to the substrate surface and perpendicular to the cleavage plane; and vertical-cavity surface-emitting lasers (VCSELs), where the beam exits perpendicular to the substrate. While VCSELs produce a well-distributed circular beam, their output power is generally low. Edge-emitting lasers, although possessing higher power, exhibit an elliptical beam distribution due to the large aspect ratio of their gain region, which is detrimental to fiber coupling. Currently, fields such as lidar demand pulsed laser sources with requirements for small size, high efficiency, high power, and narrow divergence angles. However, conventional semiconductor lasers have a quantum efficiency below 1, limiting power increases with increasing injection current. This not only easily leads to optical catastrophic damage but also releases excessive Joule heat, causing thermal burnout. Quantum well structures are frequently used in the active region of conventional semiconductor lasers. Their small lateral dimensions result in a large vertical divergence angle and low beam quality.

[0004] In summary, existing lasers suffer from problems such as low output power, excessive divergence angle, low beam quality, and limited functional structure. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, the present invention aims to provide a method for fabricating an on-chip edge-emitting laser that generates spatial beams. This method utilizes conventional semiconductor fabrication processes to achieve the generation and manipulation of the target beam at the chip level. The developed method solves the problems of traditional spatial beam generation devices, such as complex structure, large size, low efficiency, and difficulty in operation. This has the potential to promote the development of ultra-compact, high-efficiency, and scalable multifunctional semiconductor lasers, with broad application prospects.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] A method for constructing an on-chip edge-emitting laser for generating a spatial beam includes:

[0008] Obtain the epitaxial structure of a tunnel cascaded semiconductor laser, and package it according to the epitaxial structure of the tunnel cascaded semiconductor laser to obtain a large cavity side-emitting laser;

[0009] Phase information of each position of the large cavity side-emitting laser layout was obtained by combining FDTD unit parameter scanning and spatial optical field distribution function with MATLAB calculation, and corresponding structural layouts were generated by selecting nanopillars of different sizes.

[0010] Based on the corresponding structural layout, a metasurface structure is etched on the active region end face of the large optical cavity edge-emitting laser using focused ion beam technology to construct a metasurface edge-emitting laser.

[0011] Preferably, the method for constructing the tunnel cascaded semiconductor laser includes:

[0012] Three active quantum well lasers are connected in series using two heavily doped tunnel junctions to obtain the tunnel cascaded semiconductor laser.

[0013] Preferably, the metasurface edge-emitting laser has a stripe width of 200 μm and a cavity length of 1 mm.

[0014] Preferably, it further includes:

[0015] An antireflection film and a high reflectivity film are respectively deposited on the end faces of the resonant cavity at both ends of the metasurface edge-emitting laser.

[0016] Preferably, the antireflective film is amorphous silicon and the high reflective film is silicon dioxide.

[0017] Preferably, the focused ion beam current is 12 PA.

[0018] Preferably, a metasurface edge-emitting laser is obtained by packaging the tunnel cascaded semiconductor laser epitaxial structure, comprising:

[0019] The cleavage direction and light emission direction of the epitaxial structure are determined, and then it is cleaned.

[0020] A hard mask was obtained using vapor deposition; the hard mask was a SiO2 layer.

[0021] The dual grooves were isolated using photolithography with 5214 reverse resist;

[0022] Remove the mask above the isolation double trench and etch the isolation double trench to a depth of 9μm using ICP dry etching process. After etching, etch the remaining SiO2 mask with BOE solution.

[0023] A 600 nm thick SiO2 passivation layer was obtained using vapor deposition.

[0024] The P-side electrode window was lithographically patterned using 5214 positive photoresist photolithography, and then the SiO2 on the electrode window was etched using BOE etching solution. The photoresist was then removed and cleaned using acetone-ethanol heating.

[0025] Cleavage lines were lithographically created using 5214 reverse adhesive and sputtered. Ti / Au ohmic contact electrodes, ultrasonically stripped and cleaned;

[0026] The device was thinned to 110-130 μm using a back-side substrate thinning process;

[0027] Sputtering AuGeNi / Au electrode, and rapidly thermally annealed for 40 seconds;

[0028] The prepared edge-emitting chip was dissected into individual devices along the cleavage line using a cleavage machine, and an anti-reflection film and a high-reflection film were deposited on the two end faces of the resonant cavity using a coating machine.

[0029] The cleaved individual components are placed on a heat sink, sintered, and then pressure-bonded for encapsulation.

[0030] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] This invention provides a method for constructing an on-chip edge-emitting laser for generating spatial beams. The method involves building the laser using a tunnel-cascaded semiconductor laser as an epitaxial structure, and fabricating a metasurface structure at the light-emitting end face of the active region resonant cavity using focused ion beam etching at a current of 12 PA. Through conventional semiconductor fabrication processes, the generation and manipulation of the target spatial beam are achieved at the chip level. This method solves the problems of traditional spatial beam generation devices, such as complex structure, large size, low efficiency, and difficulty in operation. This has the potential to promote the development of ultra-compact, high-efficiency, and scalable multifunctional semiconductor lasers, with broad application prospects.

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart illustrating a method for constructing a metasurface edge-emitting laser that generates a space beam on a chip, as provided in an embodiment of the present invention.

[0034] Figure 2 A cross-sectional view of the structure of a metasurface edge-emitting laser device for on-chip generation of a space beam, provided in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the tunnel cascaded semiconductor laser epitaxial wafer structure obtained by MOCVD epitaxial growth, provided in an embodiment of the present invention.

[0036] Figure 4 A schematic diagram of a 300nm thick SiO2 mask deposited using PECVD, provided for an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of a dual-groove isolation lithography using 5214 reverse resist provided in an embodiment of the present invention;

[0038] Figure 6 A schematic diagram of removing the SiO2 mask above the isolation double trench using BOE solution through chemical etching, provided in an embodiment of the present invention;

[0039] Figure 7 A schematic diagram of an isolation double trench etched to a depth of 9μm using ICP dry etching process, provided for an embodiment of the present invention;

[0040] Figure 8 A schematic diagram showing the residual silicon dioxide mask after BOE wet etching and the redeposition of a 600nm thick SiO2 passivation layer using PECVD, provided in an embodiment of the present invention.

[0041] Figure 9 This is a schematic diagram illustrating the fabrication of a P-side electrode window using 5214 positive photoresist photolithography and BOE wet etching processes, as provided in an embodiment of the present invention.

[0042] Figure 10 This is a schematic diagram of a photolithographic sputtered P-side electrode provided in an embodiment of the present invention;

[0043] Figure 11 This is a schematic diagram of the N-side electrode sputtered after the device is thinned according to an embodiment of the present invention;

[0044] Figure 12 This is a schematic diagram of device coating and pressure bonding packaging provided in an embodiment of the present invention;

[0045] Figure 13 This is a schematic diagram illustrating the on-chip generation of a space beam using a metasurface structure etched by focused ion beam technology, as provided in an embodiment of the present invention.

[0046] Explanation of reference numerals in the attached figures:

[0047] (1) P-plane metal electrode, (2) SiO2 passivation protective layer, (3) P-type heavily doped ohmic contact layer, (4) confinement layer, (5) waveguide layer, (6) quantum well active region, (7) tunnel junction, (8) GaAs substrate, (9) N-plane metal electrode, (10) metasurface. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, including a series of steps, processes, methods, etc., is not limited to the steps listed, but may optionally include steps not listed, or may optionally include other steps inherent to these processes, methods, products, or devices.

[0051] The purpose of this invention is to provide a method for constructing an on-chip edge-emitting laser that realizes spatial beam generation. This invention solves the problems of low output power, excessive divergence angle, low beam quality, and simple functional structure of lasers in the prior art.

[0052] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] like Figure 1 As shown, the present invention provides a method for constructing an on-chip edge-emitting laser for generating a spatial beam, comprising:

[0054] Step 100: Obtain the epitaxial structure of the tunnel cascaded semiconductor laser, and package it according to the epitaxial structure of the tunnel cascaded semiconductor laser to obtain a large cavity side-emitting laser;

[0055] Step 200: The phase distribution of the metasurface integrated on the large cavity side-emitting laser is obtained by combining FDTD unit parameter scanning and spatial optical field distribution function with MATLAB calculation, and nanopillars of different sizes are selected to generate corresponding structural patterns; the metasurface can be directionally programmed to design micro / nano patterned arrays to achieve different functions. To simplify fabrication, the metasurface structural unit is generally of fixed height for the same material.

[0056] Step 300: Based on the corresponding structural layout, a metasurface structure is etched on the active region end face of the large cavity edge-emitting laser using focused ion beam technology to construct a metasurface edge-emitting laser. The electric or magnetic field of the laser's emitted light resonates with the subwavelength unit structure of the metasurface, causing abrupt changes in its phase, polarization, or amplitude, thereby effectively controlling the optical field. By combining the phase distribution of the spatial beam and rationally designing the metasurface structure, Gaussian beams with small divergence angles, vortex beams, Bessel beams and Airy beams with diffraction-free transmission can be generated, as well as holographic pattern displays can be realized. The metasurface unit can be cylindrical, elliptical, rectangular, and not limited to these structures. The height of the metasurface unit must meet the following conditions:

[0057] H > H min =λ / (n max -n min )

[0058] Where λ is the wavelength of the laser output light, and n max Let n be the refractive index of the medium surrounding the nanopillar. min H is the refractive index of the nanopillar. min Minimum nanopillar height to meet phase requirements.

[0059] Furthermore, such as Figure 2 As shown, the method for constructing the tunnel cascaded semiconductor laser includes:

[0060] Three active quantum well lasers are connected in series using two heavily doped tunnel junctions (7) to obtain the tunnel cascaded semiconductor laser, namely LD1, LD2, and LD3, which are epitaxially grown layer by layer on the same GaAs substrate (8) using an MOCVD system. The tunnel cascaded semiconductor laser consists of: a P-plane metal electrode, a SiO2 passivation protective layer, a P-type heavily doped ohmic contact layer, a confinement layer, a waveguide layer, a quantum well active region, a tunnel junction, a GaAs substrate, an N-plane metal electrode, and a metasurface.

[0061] Furthermore, the metasurface edge-emitting laser has a stripe width of 200 μm and a cavity length of 1 mm. This effectively increases the effective spot size, improves the cavity surface COD threshold power density, and also reduces the device size and increases the slope efficiency.

[0062] like Figure 12 , 13 As shown, further, it also includes:

[0063] An antireflection film and a high reflectivity film are respectively deposited on the end faces of the resonant cavity at both ends of the metasurface edge-emitting laser.

[0064] Furthermore, the antireflective film is made of amorphous silicon, and the high-reflectivity film is made of silicon dioxide. The deposition thicknesses required to achieve high transmittance in amorphous silicon and high reflectance in silicon dioxide were calculated and simulated using Matlab.

[0065] Furthermore, in order to shape the elliptical spot emitted by the edge-emitting laser and realize the generation of the metasurface on the space beam sheet, after the device is prepared and packaged, we obtain the corresponding layout structure design through reasonable simulation calculation. Finally, the metasurface is etched on the light-emitting end face of the active region resonant cavity by a focused ion beam with an ion beam current of 12 PA (10).

[0066] Furthermore, by packaging the aforementioned tunnel cascaded semiconductor laser epitaxial structure, a metasurface edge-emitting laser is obtained, comprising:

[0067] The cleavage direction and light emission direction of the epitaxial structure are determined, and then it is cleaned.

[0068] A hard mask was obtained using vapor deposition; the hard mask was a SiO2 layer.

[0069] The dual grooves were isolated using photolithography with 5214 reverse resist;

[0070] The mask above the isolation double trench is removed, and a 9μm deep isolation double trench is etched using ICP dry etching. After etching, the remaining SiO2 mask is etched with BOE solution. Etching the isolation double trench to a depth of approximately 9μm suppresses lateral current and carrier expansion effects, ensuring that the current density of the upper and lower active regions remains as consistent as possible, converting as much injected current as possible into optical power output. This avoids differences in current density between different active regions due to expansion, which could lead to different lasing wavelengths or even failure to lasing. Compared to a traditional single ridge, the introduction of the double trench design makes the height of the unetched area on the P-side consistent with the height of the ridge, resulting in a larger contact area with the heat sink. This is more conducive to improving the adhesion between the device and the heat sink in subsequent packaging processes, and also increases the device's heat dissipation area, suppressing electrothermal burn-out and improving device reliability.

[0071] A 600 nm thick SiO2 passivation protective layer was obtained by vapor deposition (2);

[0072] The P-side metal electrode window was lithographically patterned using a 5214 positive photoresist process, and then the SiO2 on the electrode window was etched using BOE etchant. The photoresist was removed and cleaned using acetone-ethanol heating. An electrode window structure was introduced during the fabrication of the P-side metal electrode (1). This structure, through edge SiO2 confinement, forms a current-non-injection region near the cavity surface, thereby reducing direct current injection at the cavity surface, increasing the cavity surface COD threshold power density, and thus improving the device's output power.

[0073] Cleavage lines were lithographically created using 5214 reverse adhesive and sputtered. Ti / Au ohmic contact electrodes, ultrasonically stripped and cleaned;

[0074] The device was thinned to 110-130 μm using a back-side substrate thinning process;

[0075] Sputtering AuGeNi / Au electrode, forming N-face electrode (9), and rapidly thermally annealed for 40s;

[0076] The prepared edge-emitting chip was dissected into individual devices along the cleavage line using a cleavage machine, and an anti-reflection film and a high-reflection film were deposited on the two end faces of the resonant cavity using a coating machine.

[0077] The cleaved individual components are placed on a heat sink, sintered, and then pressure-bonded for encapsulation.

[0078] The top of the side-emitting laser package is welded with gold wire and gold-plated ceramic sheet, the sides are plated with indium heat sink, a tunnel-level semiconductor laser is set inside, and an anti-reflection film is plated on the light-emitting end face.

[0079] This implementation also discloses detailed steps for obtaining a metasurface edge-emitting laser:

[0080] Step 1: The epitaxially grown 905nm tunnel cascade semiconductor laser is composed of three active quantum well lasers connected in series by two heavily doped tunnel junctions (7), namely LD1, LD2, and LD3. After obtaining the epitaxial wafer, confirm its cleavage direction and light emission direction, and mark them. Clean the epitaxial wafer with acetone and ethanol by heating.

[0081] Step 2: Deposit a 300nm thick SiO2 layer using PECVD as a hard mask.

[0082] Step 3: Use 5214 reverse resist to photolithographically isolate the dual grooves.

[0083] Step 4: Use BOE solution to chemically etch away the SiO2 mask above the isolation double trench, and clean the remaining photoresist mask with acetone and ethanol.

[0084] Step 5: Use ICP dry etching process to etch isolation double trenches to a depth of 9μm. After etching, use BOE solution to etch the remaining SiO2 mask.

[0085] Step 6: Then use PECVD to deposit a 600nm thick SiO2 passivation protective layer (2).

[0086] Step 7: Use 5214 positive photoresist photolithography to photolithographically etch the P-side metal electrode window, then use BOE etching solution to etch the SiO2 on the electrode window, and then use acetone ethanol heating to remove the photoresist and clean it.

[0087] Step 8: Use 5214 reverse adhesive to photolithographically cleavage lines and sputter. Ti / Au ohmic contact electrodes are ultrasonically stripped and cleaned to form P-face metal electrodes (1).

[0088] Step 9: Use a backside substrate thinning process to thin the device to approximately 110-130 μm.

[0089] Step 10: Sputtering AuGeNi / Au electrode is formed into N-face metal electrode (9), and finally rapidly annealed at 400℃ for 40s.

[0090] Step 11: Use a cleaving machine to cut the prepared edge-emitting chip into individual devices along its cleaving lines, and then use a coating machine to coat the two end faces of the resonant cavity with an anti-reflection film and a high-reflection film.

[0091] Step 12: Electroplating a layer of indium about 1mm thick is used to plate the cleaned copper heat sink. Then, the cleaved individual components are placed on the heat sink, sintered, and then pressure-bonded for encapsulation.

[0092] Step 13: Test the prepared devices, and then select the devices with better performance for micro-nano fabrication. Use a focused ion beam with an ion beam current of 12 PA to etch the metasurface (10).

[0093] The beneficial effects of this invention are as follows:

[0094] 1. This invention uses a tunnel cascade semiconductor laser epitaxial structure, which greatly improves the output power of the laser.

[0095] 2. The metasurface structure integrated on the laser end face of this invention is compact, has a simple processing technology, and is highly reliable.

[0096] 3. By rationally designing and integrating metasurface structures, the chip will be endowed with great optical field manipulation capabilities, enabling on-chip generation of various spatial beams (Gaussian beams, vortex beams, Bessel beams, Airy beams).

[0097] 4. The method described in this invention is applicable to all edge-emitting chips and can also be extended to other random optical emission chips.

[0098] 5. The generation and manipulation of target laser beams are achieved at the chip level using conventional semiconductor fabrication processes. The developed method solves the problems of complex structure, large size, low efficiency, and difficulty in operation associated with traditional spatial beam generation devices. This has the potential to promote the development of ultra-compact, high-efficiency, and scalable multifunctional semiconductor lasers, with broad application prospects.

[0099] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0100] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for constructing an on-chip edge-emitting laser for realizing spatial beam generation, characterized in that, include: Obtain the epitaxial structure of a tunnel cascaded semiconductor laser, and package it according to the epitaxial structure of the tunnel cascaded semiconductor laser to obtain a large cavity side-emitting laser; The phase distribution of the metasurface integrated on the side-emitting laser of a large cavity was obtained by combining FDTD unit parameter scanning and spatial optical field distribution function with MATLAB calculation, and the corresponding structural layout was generated by selecting nanopillars of different sizes. Based on the corresponding structural layout, a metasurface structure is etched on the active region end face of the large optical cavity edge-emitting laser using focused ion beam technology to construct a metasurface edge-emitting laser. The method for constructing the tunnel cascaded semiconductor laser includes: Three active quantum well lasers are connected in series using two heavily doped tunnel junctions to obtain the tunnel cascaded semiconductor laser. A metasurface edge-emitting laser is obtained by packaging the aforementioned tunnel cascaded semiconductor laser epitaxial structure, comprising: The cleavage direction and light emission direction of the epitaxial structure are determined, and then it is cleaned. A hard mask was obtained using vapor deposition; the hard mask was a SiO2 layer. The dual grooves were isolated using photolithography with 5214 reverse resist; Remove the mask above the isolation double trench and etch the isolation double trench to a depth of 9μm using ICP dry etching process. After etching, etch the remaining SiO2 mask with BOE solution. A 600 nm thick SiO2 passivation layer was obtained using vapor deposition. The P-side electrode window was lithographically patterned using 5214 positive photoresist photolithography, and then the SiO2 on the electrode window was etched using BOE etching solution. The photoresist was then removed and cleaned using acetone-ethanol heating. Cleavage lines were lithographically created using 5214 reverse adhesive and sputtered. Ti / Au ohmic contact electrodes, ultrasonically stripped and cleaned; The device was thinned to 110-130 μm using a back-side substrate thinning process; Sputtering AuGeNi / Au electrode, and rapidly thermally annealed for 40 seconds; The prepared edge-emitting chip was dissected into individual devices along the cleavage line using a cleavage machine, and an anti-reflection film and a high-reflection film were deposited on the two end faces of the resonant cavity using a coating machine. The cleaved individual components are placed on a heat sink, sintered, and then pressure-bonded for encapsulation.

2. The method for constructing an on-chip edge-emitting laser for generating a spatial beam according to claim 1, characterized in that, The metasurface edge-emitting laser has a stripe width of 200 μm and a cavity length of 1 mm.

3. The method for constructing an on-chip edge-emitting laser for realizing spatial beam generation according to claim 1, characterized in that, Also includes: An antireflection film and a high reflectivity film are respectively deposited on the end faces of the resonant cavity at both ends of the metasurface edge-emitting laser.

4. The method for constructing an on-chip edge-emitting laser for generating a spatial beam according to claim 3, characterized in that, The antireflective film is made of amorphous silicon, and the high reflective film is made of silicon dioxide.

5. The method for constructing an on-chip edge-emitting laser for realizing spatial beam generation according to claim 3, characterized in that, The focused ion beam has a current of 12 PA.

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