A current limiting protection circuit and method

Abstract

This invention discloses a current-limiting protection circuit and method for a current-limiting protection circuit. The current-limiting protection circuit includes a buffer stage input terminal and an output stage PMOS transistor MP0, with the drain voltage of MP0 being the output voltage VREF. The current-limiting protection circuit includes: a first current-limiting circuit connected between the gate and source of MP0; when the current on MP0 is greater than or equal to a preset current-limiting value, it suppresses the drop in the gate voltage of MP0, achieving primary current limiting; and a second current-limiting circuit connected between the gate of MP0 and the buffer stage input terminal; when the current on MP0 is less than the preset current-limiting value, it performs secondary current limiting on the current on MP0 and provides a discharge path to ground for the buffer stage input voltage VO1, ensuring that VO1 follows VREF during the current-limiting activation process. In addition to the traditional primary current-limiting circuit, this invention adds another current-limiting circuit to suppress overshoot and optimize the circuit's settling time.

Description

Technical Field

[0001] This invention belongs to the field of current limiting protection circuit technology, and relates to a current limiting protection circuit and method. Background Technology

[0002] In bandgap or LDO circuits, traditional current-limiting circuits often exhibit output voltage VREF overshoot during circuit startup or when the circuit recovers from a current-limiting state to a normal state. The reason for this is: Figure 1 As shown, a traditional current-limiting circuit typically uses a current-limiting circuit composed of diode D1 and resistor R1 for initial current limiting. When the current on MP0 is too large, the current-limiting circuit suppresses the drop in the gate voltage of MP0, reducing the current flowing through MP0. When the current on MP0 is less than the preset current limit value, D1 is turned off, and the current-limiting circuit composed of diode D1 and resistor R1 is shut down. At this time, the input voltage VO1 of the circuit buffer stage is charged to a higher voltage, while VREF is gradually built up from 0. This causes VO1 and VREF to change asynchronously during the circuit setup process. When VREF reaches the preset value, the voltage of VO1 is close to the power rail, and the voltage state is incorrect. The circuit still needs to wait for VO1 to recover to its preset value. During this period, the output stage PMOS is still charging the load, causing output signal overshoot. This seriously affects the setup time of the output signal and may lead to potential overvoltage problems, resulting in a large overshoot of VREF. Summary of the Invention To address the shortcomings of existing technologies, this invention provides a current limiting protection circuit and method.

[0003] To achieve the above objectives, the present invention adopts the following technical solution: A current limiting protection circuit is used for a current limiting protection circuit. The current limiting protection circuit includes a buffer stage input terminal and an output stage PMOS transistor MP0, and the drain voltage of MP0 is the output voltage VREF. The current limiting protection circuit includes a first current limiting circuit and a second current limiting circuit. The first current limiting circuit is connected between the gate and source of MP0. When the current on MP0 is greater than or equal to the preset current limiting value, it suppresses the drop in the gate voltage of MP0, reduces the current flowing through MP0, and achieves a first current limiting. The second current limiting circuit is connected between the gate of MP0 and the input terminal of the buffer stage. It is used to limit the current on MP0 for the second time when the current on MP0 is less than the preset current limit value, and to provide a discharge path to ground for the input voltage VO1 of the buffer stage, so as to ensure that VO1 changes with VREF during the current limiting protection circuit to be started.

[0004] The present invention further includes the following preferred embodiments: Preferably, the current limiting protection circuit is a Bandgap or LDO circuit.

[0005] Preferably, the current limiting protection circuit specifically includes an amplifier, a buffer stage Gm, an output stage PMOS transistor MP0, and an output stage NMOS transistor MN0; The amplifier's positive input terminal is connected to the Bandgap output VBG, its negative input terminal is connected to the load resistor, and its output terminal is connected to the gates of MP0 and MN0 respectively through the buffer stage Gm. The drains of MP0 and MN0 are connected, the drain voltage is the output voltage VREF, and they are connected to the load resistor. The source of MP0 is connected to the power supply voltage VDD, and the source of MN0 is grounded.

[0006] Preferably, the first current limiting circuit includes a diode D1 and a resistor R1; In this circuit, the positive terminal of diode D1 is connected to the source of MP0, the negative terminal is connected to one end of resistor R1, and the other end is connected to the gate of MP0.

[0007] Preferably, the second current limiting circuit includes NMOS transistors MN1 and MN2, PMOS transistor MP1, and current source I1; Among them, the gate of MP1 is connected to the gate of MP0, the source of MP1 is connected to the source of MP0, the drain of MP1 is connected to the positive terminal of current source I1, and the drain of MN1 and the gates of MN1 and MN2 are connected. The negative terminal of current source I1 and the source terminals of MN1 and MN2 are grounded; The drain of MN2 is connected to the input of the buffer stage.

[0008] Preferably, MN1 and MN2 form a current mirror with a mirror ratio of [value missing]. ; MP0 and MP1 form a current mirror with a mirror ratio of 1: .

[0009] Preferably, when the current limiting protection circuit is in a short-circuit state, the MP0 transistor outputs a large current greater than or equal to the preset current limiting value IL1. The first current limiting circuit restricts the output current of the MP0 transistor to a fixed preset current limiting value IL1. At this time, in the second current limiting circuit, MP1 mirrors the current of the MP0 transistor according to the ratio M. After comparing the mirrored current with the current source I1, the remaining current flows into MN1, and the current on MN1 is then proportionally... The image is mirrored to MN2. The drain of MN2 is connected to VO1, which adds a discharge path to ground for VO1. When the current limiting protection circuit is in a short circuit state, the voltage of VO1 is pulled down by MN2.

[0010] Preferably, when the current limiting protection circuit recovers from the current limiting state, as VREF increases, the current of the output MP0 transistor gradually decreases, and the current of MN2 related to it also gradually decreases. That is, the current discharged to ground by VO1 through MN2 gradually decreases, and the voltage of VO1 slowly increases, so as to realize the synchronization of VO1 and VREF and realize the suppression of overshoot of the output signal. When the current of MP0 transistor decreases to the current limiting threshold of the second current limiting circuit, no current flows through MN2 transistor. At this time, the second current limiting circuit is turned off, and the current limiting protection circuit is started normally.

[0011] Preferably, the current limiting threshold of the second current limiting circuit is: ; in, The current is the current mirror current.

[0012] A current limiting protection method based on the above-mentioned current limiting protection circuit includes: When the current on MP0 is greater than or equal to the preset current limit value, the first current limiting circuit suppresses the drop in the gate voltage of MP0, reduces the current flowing through MP0, and achieves primary current limiting. When the current on MP0 is less than the preset current limit value, the first current limiting circuit is turned off, the second current limiting circuit limits the current on MP0 for a second time, and provides a discharge path to ground for the buffer stage input voltage VO1, ensuring that VO1 of the current limiting protection circuit changes with VREF during the current limiting start-up process.

[0013] The beneficial effects of this invention are compared with those of the prior art: For current limiting protection circuits such as Bandgap or LDO, in addition to setting a traditional primary current limiting circuit, an additional current limiting circuit is added to sense the changes in the gate voltage and current of the PMOS of the output stage of the current limiting protection circuit, and output a signal to control the VO1 terminal, so that the VO1 of the current limiting protection circuit is established approximately synchronously with VREF, thereby suppressing overshoot and optimizing the circuit's setup time. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a traditional current limiting circuit; Figure 2 This is a schematic diagram of the current limiting protection circuit of the present invention; Figure 3 This is a structural diagram of the current limiting protection circuit of the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0016] like Figure 1 As shown, Embodiment 1 of the present invention provides a current-limiting protection circuit for a current-limiting protection circuit. The current-limiting protection circuit includes a buffer stage input terminal and an output stage PMOS transistor MP0, and the drain voltage of MP0 is the output voltage VREF. In a preferred but non-limiting embodiment of the present invention, during the overshoot of circuit power-on or current-limiting recovery, the output stage PMOS transistor will experience a transient large current, which gradually decreases as the output voltage is established; that is, the gate voltage and current of the output stage PMOS transistor are variable. Therefore, as... Figure 2 As shown, a current limiting circuit can be added to sense this change and output a signal to control the VO1 terminal, so that VO1 and VREF are established approximately synchronously, thereby suppressing overshoot and optimizing the circuit's setup time.

[0017] More preferably, the current limiting protection circuit includes a first current limiting circuit and a second current limiting circuit; The first current limiting circuit is connected between the gate and source of MP0. When the current on MP0 is greater than or equal to the preset current limiting value, it suppresses the drop in the gate voltage of MP0, reduces the current flowing through MP0, and achieves a first current limiting. The second current limiting circuit is connected between the gate of MP0 and the input terminal of the buffer stage. It is used to limit the current on MP0 for the second time when the current on MP0 is less than the preset current limit value, and to provide a discharge path to ground for the input voltage VO1 of the buffer stage, so as to ensure that VO1 changes with VREF during the current limiting protection circuit to be started.

[0018] The current limiting protection circuit to be used is a bandgap or LDO circuit. Those skilled in the art will understand that... Figure 1-3 The specific circuit structure is applicable to both Bandgap and LDO.

[0019] The current limiting protection circuit specifically includes an amplifier, a buffer stage Gm, and output stage PMOS transistor MP0 and output stage NMOS transistor MN0. The amplifier's positive input is connected to the Bandgap output VBG, and its negative input is connected to the load resistor. The amplifier's output is connected to the gates of MP0 and MN0 via the buffer stage Gm. The drains of MP0 and MN0 are connected, with the drain voltage being the output voltage VREF, and are connected to the load resistor. The source of MP0 is connected to the power supply voltage VDD, and the source of MN0 is grounded.

[0020] The first current limiting circuit includes diode D1 and resistor R1; In this circuit, the positive terminal of diode D1 is connected to the source of MP0, the negative terminal is connected to one end of resistor R1, and the other end is connected to the gate of MP0.

[0021] Figure 2 The working principle is as follows: During circuit startup, the first current limiting circuit, composed of diode D1 and resistor R1, limits the current on MP0 once, restricting its output current to a relatively large current value IL1 (i.e., the preset current limiting value). When the current on MP0 is less than IL1, the first current limiting circuit no longer works, and the Current limit2 circuit (i.e., the second current limiting circuit) performs a second current limiting. The two current limitings ensure a more stable start-up of the circuit.

[0022] In addition, the second current limiting circuit is connected to VO1, providing VO1 with a discharge path to ground, ensuring that VO1 follows the changes in VREF during the current limiting start-up process.

[0023] The specific structure of the Current Limit 2 circuit (i.e., the second current limiting circuit) is as follows: Figure 3 As shown, it mainly consists of a current mirror and a current source. Specifically, the two current limiting circuits include NMOS transistors MN1 and MN2, PMOS transistor MP1, and current source I1. In this configuration, the gate of MP1 is connected to the gate of MP0, the source of MP1 is connected to the source of MP0, the drain of MP1 is connected to the positive terminal of current source I1, the drain of MN1, and the gates of MN1 and MN2 are connected; the negative terminal of current source I1 and the sources of MN1 and MN2 are grounded; and the drain of MN2 is connected to the input terminal of the buffer stage.

[0024] MN1 and MN2 form a current mirror with a mirror ratio of . MP0 and MP1 form a current mirror with a mirror ratio of . .

[0025] Figure 3 The circuit shown works as follows: When the circuit is in a short-circuit state, the MP0 transistor outputs a large current. The first current limiting circuit will limit the output current of the MP0 transistor to a fixed value IL1. At this time, MP1 mirrors the current of the MP0 transistor through a certain ratio M. After comparing it with the current source I1, the remaining current flows into MN1. The current on MN1 is then mirrored to MN2 through a certain ratio. The drain of the MN2 transistor is connected to VO1, which adds a discharge path to ground for VO1. When the circuit is in a short-circuit state, VO1 is pulled to a lower voltage value by the MN2 transistor.

[0026] When the circuit recovers from the current-limiting state, as VREF increases, the current of the output MP0 transistor gradually decreases, and the related current of MN2 also gradually decreases. That is, the current discharged from VO1 to ground through MN2 gradually decreases, and the voltage of VO1 rises at a slower rate. Ideally, VO1 and VREF are established synchronously, thereby suppressing overshoot of the output signal. The operating current value of Current Limit 2 is... ,in, Let MN2 be the drain current. This is the current mirror current. When the current of the MP0 transistor decreases to the current limiting threshold of Current limit 2... When the current stops flowing through MN2, the current limiting circuit is turned off, and the circuit starts normally.

[0027] The current limiting protection method based on the above current limiting protection circuit includes: When the current on MP0 is greater than or equal to the preset current limit value, the first current limiting circuit suppresses the drop in the gate voltage of MP0, reduces the current flowing through MP0, and achieves primary current limiting. When the current on MP0 is less than the preset current limit value, the first current limiting circuit is turned off, the second current limiting circuit limits the current on MP0 for a second time, and provides a discharge path to ground for the buffer stage input voltage VO1, ensuring that VO1 of the current limiting protection circuit changes with VREF during the current limiting start-up process.

[0028] The beneficial effects of this invention are compared with those of the prior art: For current limiting protection circuits such as Bandgap or LDO, in addition to setting a traditional primary current limiting circuit, an additional current limiting circuit is added to sense the changes in the gate voltage and current of the PMOS of the output stage of the current limiting protection circuit, and output a signal to control the VO1 terminal, so that the VO1 of the current limiting protection circuit is established approximately synchronously with VREF, thereby suppressing overshoot and optimizing the circuit's setup time.

[0029] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A current-limiting protection circuit for use in a current-limiting protection circuit, the current-limiting protection circuit including a buffer stage input terminal and an output stage PMOS transistor MP0, wherein the drain voltage of MP0 is the output voltage VREF, characterized in that: The current limiting protection circuit includes a first current limiting circuit and a second current limiting circuit. The first current limiting circuit is connected between the gate and source of MP0. When the current on MP0 is greater than or equal to the preset current limiting value, it suppresses the drop in the gate voltage of MP0, reduces the current flowing through MP0, and achieves a first current limiting. The second current limiting circuit is connected between the gate of MP0 and the input terminal of the buffer stage. It is used to limit the current on MP0 for the second time when the current on MP0 is less than the preset current limiting value, and to provide a discharge path to ground for the input voltage VO1 of the buffer stage, so as to ensure that VO1 of the current limiting protection circuit follows the change of VREF during the current limiting start-up process. The second current limiting circuit includes NMOS transistors MN1 and MN2, PMOS transistor MP1, and current source I1; wherein, the gate of MP1 is connected to the gate of MP0, the source of MP1 is connected to the source of MP0, the drain of MP1 is connected to the positive terminal of current source I1, the drain of MN1, and the gates of MN1 and MN2 are connected; the negative terminal of current source I1 and the sources of MN1 and MN2 are grounded; the drain of MN2 is connected to the input terminal of the buffer stage.

2. The current limiting protection circuit according to claim 1, characterized in that: The current limiting protection circuit to be used is either a bandgap or an LDO circuit.

3. The current limiting protection circuit according to claim 1, characterized in that: The current limiting protection circuit specifically includes an amplifier, a buffer stage Gm, and an output stage PMOS transistor MP0 and an output stage NMOS transistor MN0. The amplifier's positive input terminal is connected to the Bandgap output VBG, the negative input terminal is connected to the load resistor, and the amplifier's output terminal is the buffer stage input terminal, which is connected to the gates of MP0 and MN0 through the buffer stage Gm. The drains of MP0 and MN0 are connected, the drain voltage is the output voltage VREF, and they are connected to the load resistor. The source of MP0 is connected to the power supply voltage VDD, and the source of MN0 is grounded.

4. The current limiting protection circuit according to claim 1, characterized in that: The first current limiting circuit includes diode D1 and resistor R1; In this circuit, the positive terminal of diode D1 is connected to the source of MP0, the negative terminal is connected to one end of resistor R1, and the other end is connected to the gate of MP0.

5. A current-limiting protection circuit according to claim 1, characterized in that: MN1 and MN2 form a current mirror with a mirror ratio of . ; MP0 and MP1 form a current mirror with a mirror ratio of 1: .

6. A current limiting protection circuit according to claim 5, characterized in that: When the current limiting protection circuit is in a short-circuit state, the MP0 transistor outputs a large current greater than or equal to the preset current limit value IL1. The first current limiting circuit restricts the MP0 transistor output current to a fixed preset current limit value IL1. At this time, in the second current limiting circuit, MP1 mirrors the current of the MP0 transistor according to the ratio M. After comparing the mirrored current with the current source I1, the remaining current flows into MN1. The current in MN1 is then proportionally... The image is mirrored to MN2. The drain of MN2 is connected to VO1, which adds a discharge path to ground for VO1. When the current limiting protection circuit is in a short circuit state, the voltage of VO1 is pulled down by MN2.

7. A current-limiting protection circuit according to claim 5, characterized in that: When the current limiting protection circuit recovers from the current limiting state, as VREF increases, the current of the output MP0 transistor gradually decreases, and the current of MN2 related to it also gradually decreases. That is, the current discharged to ground by VO1 through MN2 gradually decreases, and the voltage of VO1 slowly increases, so as to realize the synchronization between VO1 and VREF and suppress the overshoot of the output signal. When the current of MP0 transistor decreases to the current limiting threshold of the second current limiting circuit, no current flows through MN2 transistor. At this time, the second current limiting circuit is turned off, and the current limiting protection circuit is started normally.

8. A current limiting protection circuit according to claim 7, characterized in that: The current limiting threshold of the second current limiting circuit is ; in, The current is the current mirror current.

9. A current limiting protection method based on the current limiting protection circuit according to any one of claims 1-8, characterized in that: When the current on MP0 is greater than or equal to the preset current limit value, the first current limiting circuit suppresses the drop in the gate voltage of MP0, reduces the current flowing through MP0, and achieves primary current limiting. When the current on MP0 is less than the preset current limit value, the first current limiting circuit is turned off, the second current limiting circuit limits the current on MP0 for a second time, and provides a discharge path to ground for the buffer stage input voltage VO1, ensuring that VO1 of the current limiting protection circuit changes with VREF during the current limiting start-up process.

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