Circuit chip with power supply noise rejection

Abstract

A circuit chip with power supply noise rejection includes a switching unit, an energy storage unit, and an operating circuit. The switching unit has a first connection end and a second connection end. The first connection end is adapted to receive a power supply voltage. The switching unit is configured to selectively turn on a first link path between the first connection end and the second connection end according to a clock signal. The energy storage unit is coupled to the second connection end. When the switching unit turns on the first link path, the energy storage unit is configured to generate a storage voltage at the second connection end according to the power supply voltage. The operating circuit is coupled to the second connection end. The operating circuit is configured to operate according to the storage voltage.

Description

Technical Field

[0001] This application relates to noise suppression technology, and in particular to a circuit chip with power supply noise suppression. Background Technology

[0002] Traditionally, power supply noise is suppressed using low-pass filters composed of resistors and capacitors. However, resistors typically occupy a large area in the chip layout. This is especially true in circuit designs requiring very low frequencies, where larger resistor values ​​are needed, further increasing the required layout area. Furthermore, the presence of resistors can also lead to a longer settling time for the power supply voltage. Summary of the Invention

[0003] This application provides a circuit chip with power supply noise suppression. In one embodiment, the circuit chip with power supply noise suppression includes a switching unit, an energy storage unit, and an operating circuit. The switching unit has a first connection terminal and a second connection terminal. The first connection terminal of the switching unit is adapted to receive a power supply voltage. The switching unit is used to selectively conduct a first link path between the first connection terminal and the second connection terminal according to a clock signal. The energy storage unit is coupled to the second connection terminal of the switching unit. When the switching unit conducts the first link path, the energy storage unit is used to generate a stored voltage at the second connection terminal according to the power supply voltage. The operating circuit is coupled to the second connection terminal and is used to operate according to the stored voltage.

[0004] The following detailed description of the features and advantages of this application is sufficient to enable any person skilled in the art to understand the technical content of this application and implement it accordingly. Based on the content disclosed in this specification, the scope of the patent application and the drawings, any person skilled in the art can easily understand the related objectives and advantages of this application. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0006] Figure 2 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0007] Figure 3 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0008] Figure 4 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0009] Figure 5 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0010] Figure 6 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0011] Figure 7 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0012] Figure 8 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0013] Figure 9 This is a schematic diagram of one embodiment of the operating circuit.

[0014] Figure 10 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression.

[0015] Figure 11 This is a schematic diagram of an embodiment of a circuit chip with power supply noise suppression. Detailed Implementation

[0016] To make the above-mentioned objects, features and advantages of the embodiments of this application more apparent and understandable, a detailed description is provided below in conjunction with the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of a circuit chip 100 with power supply noise suppression. Please refer to [link / reference]. Figure 1 The circuit chip 100 with power supply noise suppression includes a switching unit 110, an energy storage unit 120, and an operating circuit 130. The switching unit 110 has a first connection terminal, a second connection terminal, and a clock control terminal. The first connection terminal of the switching unit 110 is adapted to receive a power supply voltage VDD. The clock control terminal of the switching unit 110 is adapted to receive a clock signal CLK. The energy storage unit 120 is coupled between the second connection terminal of the switching unit 110 and the ground voltage GND. Furthermore, the operating circuit 130 is coupled to the second connection terminal of the switching unit 110.

[0018] Switching unit 110 is used to selectively connect the first connection path from the first connection terminal to the second connection terminal according to the clock signal CLK received by the clock control terminal. Energy storage unit 120 is used to store energy when the first connection path is connected, and to use its stored energy as a voltage source when the first connection path is not connected. Furthermore, operating circuit 130 can operate using the voltage provided by energy storage unit 120.

[0019] In some embodiments, the switching unit 110 may activate the first link path according to the clock signal CLK. For example, the switching unit 110 may activate the first link path when the logic value of the clock signal CLK is "1". When the first link path is activated, the first connection terminal of the switching unit 110 may be electrically connected to the second connection terminal, and the power supply voltage VDD on the first connection terminal will be transmitted to the second connection terminal, so that the energy storage unit 120 can generate a stored energy according to the power supply voltage VDD, and this stored energy will generate a stored voltage VS on the second connection terminal.

[0020] Furthermore, the switching unit 110 can disconnect (i.e., de-conduct) the first connection path according to the clock signal CLK. For example, the switching unit 110 can disconnect the first connection path when the logic value of the clock signal CLK is "0". When the first connection path is disconnected, the first connection terminal of the switching unit 110 is not electrically connected to the second connection terminal, and the power supply voltage VDD on the first connection terminal is not transmitted to the second connection terminal. At this time, the energy storage unit 120 can use its stored electrical energy as the voltage source of the operating circuit 130, and the operating circuit 130 can operate using the stored voltage VS provided by the energy storage unit 120 on the second connection terminal.

[0021] It should be noted that how the switching unit 110 selectively activates the first link path according to the clock signal CLK depends on the design requirements and is not limited to the aforementioned embodiments. For example, the switching unit 110 may also disconnect the first link path when the logic value of the clock signal CLK is "1" and activate the first link path when the logic value of the clock signal CLK is "0".

[0022] In some embodiments, power supply noise exists on the power supply voltage VDD. The circuit chip 100 of this application can control the switching unit 110 to temporarily conduct the first connection path via the clock signal CLK, allowing the power supply voltage VDD with power supply noise to be temporarily transmitted to the second connection terminal to supply the energy storage unit 120 to generate stored energy. The circuit chip 100 can then control the switching unit 110 to disconnect the first connection path via the clock signal CLK, preventing the power supply voltage VDD with power supply noise from being transmitted to the second connection terminal. In this way, the power supply noise on the power supply voltage VDD can only be transmitted to the second connection terminal when the first connection path is conducting, significantly reducing the power supply noise of the stored voltage VS of the energy storage unit 120 at the second connection terminal, thus achieving a power supply noise suppression effect. Furthermore, the operating circuit 130, which operates based on the stored voltage VS of the energy storage unit 120, has a good power supply rejection ratio (PSRR) due to the lower power supply noise of the stored voltage VS. Furthermore, compared to the design of using a traditional low-pass filter composed of resistors and capacitors to filter out power supply noise, the circuit chip 100 of this application saves a significant amount of layout area because it does not require resistors, and can also avoid the excessively long settling time caused by large resistors.

[0023] In some embodiments, the degree of power supply noise suppression by the circuit chip 100 is related to the duty cycle of the clock signal CLK. Specifically, the smaller the duty cycle of the clock signal CLK, the higher the degree of power supply noise suppression by the circuit chip 100. For example, when the duty cycle of the clock signal CLK is 10%, the power supply noise of the storage voltage VS can be 10% of the power supply noise of the power supply voltage VDD.

[0024] In some embodiments, the switching unit 110 may include at least one transistor. Furthermore, the energy storage unit 120 may include at least one capacitor. In some embodiments, the transistor may be implemented using, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a gallium nitride field-effect transistor (GaN FET), or an insulated gate bipolar transistor (IGBT).

[0025] Figure 2 This is a schematic diagram of one embodiment of a circuit chip 100 with power supply noise suppression. Please refer to [link / reference]. Figure 2In some embodiments, the clock signal CLK may be generated by internal components of the circuit chip 100. Here, the circuit chip 100 may further include a clock generation unit 140. The clock generation unit 140 is coupled to the clock control terminal of the switching unit 110, and the clock generation unit 140 is used to generate the clock signal CLK for the switching unit 110. In some embodiments, the clock generation unit 140 may be, but is not limited to, an oscillator, a clock generator, etc.

[0026] Please see Figure 1 In other embodiments, the clock signal CLK may also be generated by an external component of the circuit chip 100 and input to the circuit chip 100. Here, the circuit chip 100 may further include a clock input pin P1. The clock input pin P1 is coupled to the clock control terminal of the switching unit 110, and the clock input pin P1 is used to receive the clock signal CLK input from an external component of the circuit chip 100 to the switching unit 110. In some embodiments, the external component generating the clock signal CLK may be, but is not limited to, a signal generator.

[0027] Figure 3 and Figure 4 This is a schematic diagram of one embodiment of a circuit chip 100 with power supply noise suppression. Please refer to [link / reference]. Figure 3 and Figure 4 In some embodiments, circuit chip 100 may further include clock adjustment unit 150. For example... Figure 3 As shown, the clock adjustment unit 150 can be coupled between the clock input pin P1 and the clock control terminal of the switching unit 110. Alternatively, as... Figure 4 As shown, the clock adjustment unit 150 can be coupled between the clock generation unit 140 and the clock control terminal of the switching unit 110. The clock adjustment unit 150 can be used to adjust the clock signal CLK, and the switching unit 110 selectively turns on the first link path according to the clock signal CLK adjusted by the clock adjustment unit 150. In some embodiments, the adjustment may include, but is not limited to, time correction, duty cycle adjustment, clock adjustment, etc.

[0028] Please see Figures 1 to 4 In some embodiments, the circuit chip 100 may further include a power input pin P2, and the power input pin P2 is coupled to a first connection terminal of the switching unit 110. In some embodiments, the power input pin P2 can be used to receive a power supply voltage VDD input from an external source to the circuit chip 100. However, this application is not limited thereto.

[0029] Please see Figures 5 to 8In other embodiments, the power input pin P2 is used to receive the input voltage VIN from an external source to the circuit chip 100. Furthermore, the circuit chip 100 may include a voltage conversion unit 160. The voltage conversion unit 160 is coupled between the power input pin P2 and the first connection terminal of the switching unit 110, and the voltage conversion unit 160 is used to convert the input voltage VIN into a power supply voltage VDD, and then output the power supply voltage VDD to the first connection terminal of the switching unit 110. Components and operations identical to those in the aforementioned embodiments will not be described again.

[0030] In some embodiments, the voltage conversion unit 160 may be implemented using, but is not limited to, a low-dropout linear regulator (LDO), a buck converter, a boost converter, or a combination thereof.

[0031] In some embodiments, the operating circuit 130 may be any type of circuit that requires a cleaner voltage (i.e., less noise) to operate in order to obtain a good power supply voltage rejection ratio. Figure 9 This is a schematic diagram of one embodiment of the operating circuit. Please refer to [link / reference]. Figures 1 to 9 The following description will use the operating circuit 130 as an example of a unit gain buffer with bypass mode.

[0032] In some embodiments, the operating circuit 130 may include a buffer unit 131, an operational amplifier 132, and a bypass unit 133. The buffer unit 131 may have a buffer input terminal, a buffer output terminal, and a power connection terminal, and the power connection terminal of the buffer unit 131 is coupled to a second connection terminal of the switching unit 110. The operational amplifier 132 has a positive input terminal (+), a negative input terminal (-), and an operational output terminal, and the negative input terminal (-) of the operational amplifier 132 is coupled to the operational output terminal. The bypass unit 133 has a control terminal, a third connection terminal, and a fourth connection terminal. The control terminal of the bypass unit 133 is coupled to the buffer output terminal of the buffer unit 131. The third connection terminal of the bypass unit 133 is coupled to the positive input terminal (+) of the operational amplifier 132, and the fourth connection terminal of the bypass unit 133 is coupled to the operational output terminal of the operational amplifier 132.

[0033] The buffer unit 131 can operate using the stored voltage VS received at the power connection terminal. Here, the buffer unit 131 buffers the bypass signal B1 received at the buffer input terminal to generate a buffer signal B2, and outputs the buffer signal B2 to the control terminal of the bypass unit 133 via the buffer output terminal. The bypass unit 133 is used to selectively connect the second link path from the third connection terminal to the fourth connection terminal based on the buffer signal B2 received at the control terminal.

[0034] In some embodiments, the bypass unit 133 can activate the second link path when the logic value of the buffer signal B2 is "1". When the second link path is activated, the first voltage V1 on the positive input terminal + of the operational amplifier 132 (or the third connection terminal of the bypass unit 133) can be bypassed to the operational output terminal (or the fourth connection terminal of the bypass unit 133) of the operational amplifier 132 via the second link path of the bypass unit 133. Furthermore, the bypass unit 133 can deactivate the second link path when the logic value of the buffer signal B2 is "0". When the second link path is deactivated, the operational amplifier 132 operates as a conventional unit gain buffer.

[0035] It should be noted that how the bypass unit 133 selectively activates the second link path based on the buffer signal B2 depends on the design requirements. For example, the bypass unit 133 may also disconnect the second link path when the logic value of the buffer signal B2 is "1" and activate the second link path when the logic value of the buffer signal B2 is "0".

[0036] In some embodiments, although there are parasitic capacitances between the control terminal and the third connection terminal and between the control terminal and the fourth connection terminal of the bypass unit 133, the power supply noise of the storage voltage VS of the energy storage unit 120 at the second connection terminal has been greatly reduced. Therefore, the noise transmitted to the operational output terminal of the operational amplifier 132 via the parasitic capacitance of the bypass unit 133 is also greatly reduced, thereby enabling the operating circuit 130 to have a good power supply voltage rejection ratio.

[0037] In some embodiments, buffer unit 131 may comprise one or more cascaded inverters. While only two stages are shown here, the number is not limited to this and may be determined depending on the required drive force and / or logic value. Furthermore, bypass unit 133 may comprise at least one transistor. In some embodiments, the transistor may be implemented using, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a gallium nitride field-effect transistor (GaN FET), or an insulated gate bipolar transistor (IGBT).

[0038] In some embodiments, the duty cycle, clock frequency, and capacitance of the energy storage unit 120 of the clock signal CLK can be adjusted according to the required load of the operating circuit 130. For example, in an embodiment where the operating circuit 130 is a unit gain buffer with a bypass mode, assuming that the load clock of the buffer unit 131 of the operating circuit 130 is 3 MHz and the load is small, the duty cycle of the clock signal CLK can be 8.3%, the clock frequency of the clock signal CLK can be 3 MHz, and the capacitance of the energy storage unit 120 can be 1 pF, but this application is not limited thereto.

[0039] Figure 10 This is a schematic diagram of one embodiment of a circuit chip 100 with power supply noise suppression. Please refer to [link / reference]. Figure 10 In some embodiments, the circuit chip 100 may further include an operation detection unit 170. The operation detection unit 170 is coupled to the operation circuit 130 and the switching unit 110. The operation detection unit 170 is used to detect whether the operation circuit 130 is operating normally, and can cause the switching unit 110 to conduct the first connection path when it is determined that the operation is abnormal, so that the energy storage unit 120 can re-store energy according to the power supply voltage VDD transmitted to the second connection terminal.

[0040] In some embodiments, the operation detection unit 170 may be coupled to the buffer input and buffer output of the buffer unit 131 to determine whether the operation circuit 130 is operating normally based on the logic values ​​of the bypass signal B1 and the buffer signal B2. When the operation is determined to be abnormal, the operation detection unit 170 may generate a conduction signal S1 to the switching unit 110 so that the switching unit 110 conducts the first connection path.

[0041] In some embodiments, the operation detection unit 170 may be implemented using digital logic gates. For example, when the buffer unit 131 is composed of two stages of inverters, the operation detection unit 170 may be implemented using an XOR gate, but this application is not limited thereto.

[0042] Figure 11 This is a schematic diagram of one embodiment of a circuit chip 100 with power supply noise suppression. Please refer to [link / reference]. Figure 11In some embodiments, the circuit chip 100 may further include a voltage detection unit 180. The voltage detection unit 180 is coupled to the clock control terminal of the switching unit 110 and the second connection terminal. The voltage detection unit 180 is used to detect the storage voltage VS generated by the energy storage unit 120 at the second connection terminal and determine whether the storage voltage VS exceeds a voltage threshold. When it is determined that the storage voltage VS does not exceed the voltage threshold, the voltage detection unit 180 may generate a conduction signal S2 to the switching unit 110, causing the switching unit 110 to conduct the first connection path, thereby enabling the energy storage unit 120 to re-store energy based on the power supply voltage VDD transmitted to the second connection terminal.

[0043] In some embodiments, the voltage detection unit 180 may be implemented via, for example, but not limited to, a comparator. Furthermore, the voltage threshold may be, but is not limited to, half of the power supply voltage VDD.

[0044] In summary, the circuit chip with power supply noise suppression in this application embodiment temporarily turns on the first connection path of the switching unit, so that the energy storage unit generates a stored voltage at the second connection terminal based on the power supply voltage during the conduction period, and then turns off the first connection path of the switching unit, so that power supply noise on the power supply voltage can no longer be transmitted to the second connection terminal. In this way, the power supply noise of the stored voltage can be greatly reduced, thus achieving a power supply noise suppression effect. Furthermore, the operating circuit that operates based on the stored voltage can have a good power supply voltage rejection ratio due to the lower power supply noise of the stored voltage. Moreover, compared with the design of using a traditional low-pass filter composed of resistors and capacitors to filter out power supply noise, the circuit chip with power supply noise suppression in this application embodiment can save a significant amount of layout area by eliminating the need for resistors, and can also avoid the excessively long stabilization time caused by large resistors.

[0045] Although the technical content of this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any modifications and refinements made by those skilled in the art without departing from the spirit of this application should be included within the scope of this application. Therefore, the scope of protection of this application shall be determined by the appended claims.

Claims

1. A circuit chip with power supply noise suppression, comprising: A switching unit has a first connection terminal and a second connection terminal, the first connection terminal being adapted to receive a power supply voltage, and the switching unit being configured to selectively conduct a first link path from the first connection terminal to the second connection terminal according to a clock signal. An energy storage unit, coupled to the second connection terminal of the switching unit, generates a storage voltage at the second connection terminal based on the power supply voltage when the switching unit is activated by the first connection path; and An operating circuit, coupled to the second connection terminal, is used to operate according to the stored voltage. The operating circuit includes: A buffer unit has a buffer input terminal and a buffer output terminal, wherein the buffer input terminal receives a bypass signal, and the buffer unit is used to operate according to the stored voltage to buffer the bypass signal as a buffer signal. An operational amplifier having a positive input terminal, a negative input terminal and an operational output terminal, wherein the negative input terminal is coupled to the operational output terminal; as well as A bypass unit has a control terminal, a third connection terminal and a fourth connection terminal. The control terminal is coupled to the buffer output terminal, the third connection terminal is coupled to the positive input terminal, and the fourth connection terminal is coupled to the operational output terminal. The bypass unit is used to selectively connect a second link path from the third connection terminal to the fourth connection terminal according to the buffer signal received by the control terminal.

2. The circuit chip with power supply noise suppression according to claim 1, further comprising: A clock generation unit is used to generate the clock signal.

3. The circuit chip with power supply noise suppression according to claim 1 further comprises: A clock input pin is provided for receiving the clock signal input from an external source.

4. The circuit chip with power supply noise suppression according to claim 2 or 3 further comprises: A clock adjustment unit is used to adjust the clock signal, wherein the switching unit selectively connects the first link path from the first connection terminal to the second connection terminal according to the clock signal adjusted by the clock adjustment unit.

5. The circuit chip with power supply noise suppression according to claim 4, further comprising: A power input pin is provided for receiving the power supply voltage input from an external source.

6. The circuit chip with power supply noise suppression according to claim 4, further comprising: A power input pin is used to receive an input voltage from an external source; and A voltage conversion unit is used to convert the input voltage into the power supply voltage.

Images