A half-bridge three-level DAB asymmetric voltage-sharing control circuit, method and system

Abstract

The application discloses a kind of half-bridge three-level DAB asymmetric voltage-sharing control circuits, methods and systems, the circuit includes primary side three-level circuit, secondary side full-bridge circuit and isolation transformer module, primary side three-level circuit includes capacitor C1 and C2, switch tube Q1~Q4, anti-parallel diode D Q1 ~ Q4 , upper and lower clamping diode D1 and D2;Secondary side full-bridge circuit includes capacitor C3, switch tube S1~S4, anti-parallel diode D S1 ~ S4 ;Isolation transformer module includes high-frequency transformer T r , high-frequency transformer T r There is leakage inductor L r And dc blocking capacitor C r , the application is by calculating the unbalance degree of midpoint potential, real-time control carrier valley value phase and the duty cycle of modulated wave two degrees of freedom, realize the unbalance control of midpoint potential in the case of no load or load;At the same time, without increasing additional voltage balancer circuit, and has strong unbalance control ability, can also restore DAB alternating current symmetry after unbalance factor disappears, maximum degree guaranteeing the soft switching working condition of switch tube.

Description

Technical Field

[0001] This invention relates to a half-bridge three-level DAB asymmetric voltage equalization control circuit, method, and system, belonging to the field of power electronics technology. Background Technology

[0002] In most currently operational projects, DC transformers typically employ an input series-parallel output topology. The number of series modules on the high-voltage side directly impacts the size and cost of the DC transformer. Therefore, increasing the DC voltage level at the medium-voltage side outlet can significantly reduce the overall size and system cost of the DC transformer. Since a three-level topology can double the DC bus voltage using the same voltage-level switching devices, it means the number of series modules on the medium-voltage side of the DC transformer can be halved. Therefore, introducing three-level technology into the DC transformer field is essential. However, three-level technology must address the midpoint potential balance issue, ensuring that the upper and lower bus capacitors in the topology maintain equal voltage or a low voltage deviation level at all times.

[0003] Three-level midpoint potential balance control has been extensively studied in three-phase AC applications, but its application in DC, especially in DAB-related circuits, is less researched. Patents [CN111371337A] and [CN114285304A] target diode-clamped three-level inverter circuits, which are AC applications and differ from the DC applications of half-bridge three-level DAB circuits. Patent [CN112886822B] proposes a midpoint potential balance control method and system based on an ANPC full-bridge three-level DAB, but it focuses on a full-bridge circuit topology. The controllable degrees of freedom in the midpoint potential control method differ from those in half-bridge three-level circuits, and it does not address no-load conditions. Patent [CN109742968B] proposes a control method and device for diode-clamped hybrid three-level DAB converters. Its main innovation lies in the control strategy during normal operation, primarily aimed at optimizing efficiency and current stress, without addressing midpoint imbalance control. Patent [CN112051484A] uses a voltage balancer to solve the midpoint potential balance problem. This technology can also be used in DAB-related DC application scenarios, especially under no-load conditions. However, the voltage balancer adds additional large magnetic components or has the problem of weak imbalance control capability. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a half-bridge three-level DAB asymmetric voltage equalization control circuit, method and system, which solves the problems disclosed in the background art.

[0005] To achieve the above objectives, the present invention is implemented using the following technical solution:

[0006] In a first aspect, the present invention provides a half-bridge three-level DAB asymmetric voltage equalization control circuit, comprising a primary-side three-level circuit, a secondary-side full-bridge circuit, and an isolation transformer module, wherein:

[0007] The primary-side three-level circuit includes capacitors C1 and C2, switching transistors Q1 to Q4, and anti-parallel diodes D. Q1 ~D Q4 Upper and lower clamping diodes D1 and D2; capacitors C1 and C2 are connected to the upper and lower DC buses of the three-level circuit, and the connection point of the bus capacitors C1 and C2 is the neutral point B; the switching transistors Q1 and Q2 form the upper arm of the half-bridge circuit, connected to the positive terminal of the DC bus and the neutral point; Q3 and Q4 form the lower arm of the half-bridge circuit, connected to the neutral point and the negative terminal of the DC bus. The D... Q1 ~D Q4 The diodes are Q1 to Q4, which are anti-parallel diodes. D1 and D2 are connected in series and then in parallel across the switching transistors Q2 and Q3. The secondary-side full-bridge circuit includes capacitor C3, switching transistors S1 to S4, and anti-parallel diodes D1 and D2. S1 ~D S4 The capacitor C3 is connected to the upper and lower DC buses of the secondary full-bridge circuit. S1 and S2 are connected in series and then in parallel with S3 and S4, and then in parallel with capacitor C3.

[0008] The isolation transformer module includes a high-frequency transformer T. r The high-frequency transformer T r There is leakage inductance L r and DC blocking capacitor C r The primary side of the high-frequency transformer T is connected to the emitter of Q2 and the neutral point B, respectively, and the secondary side is connected to the emitters of S1 and S3, respectively. Secondly, the present invention provides a control method based on the aforementioned half-bridge three-level DAB asymmetric voltage equalization control circuit, comprising:

[0009] Obtain the voltage V between capacitors C1 and C2 C1 and V C2 The duty cycle adjustment Δd is obtained by the output of the first PI controller;

[0010] Based on the strong correlation between the unbalanced phase shift angle θ′ and Δd, the carrier information of each switch is calculated using the corresponding calculation method.

[0011] Obtain the output voltage V Co The overall outward phase shift angle is obtained by the output of the third PI controller. Among them, the overall outward phase angle Defined as Q1 compensated phase shift angle The phase shift angle between point B at the corresponding point and point C at the rising edge of S1;

[0012] Based on the overall outward phase angle The positive and negative relationships are used to obtain the duty cycle of each switch using the corresponding duty cycle generation method;

[0013] The duty cycle and carrier information of each switch are input into a preset pulse generator module to obtain the trigger pulse signal of all switches.

[0014] The trigger pulse signal is transmitted to each switching transistor to achieve voltage equalization control of the upper and lower capacitors.

[0015] Furthermore, based on the strong correlation between the unbalanced phase shift angle θ′ and Δd, the carrier information of each switch is calculated using corresponding calculation methods, including:

[0016] If an unbalanced phase shift angle θ′ and Δd are set to weak correlation, the voltage V will be... C1 and V C2 The valley phase θ of the carrier wave of the first switch Q1 is obtained through the output of the second PI controller. The unbalanced phase shift angle θ′ and the compensation phase shift angle are then calculated from the valley phase θ.

[0017] If the unbalanced phase shift angle θ′ and Δd are set to be strongly correlated, the unbalanced phase shift angle θ′ can be obtained by calculating the duty cycle adjustment Δd, and the carrier valley phase θ and compensation phase shift angle can be obtained by calculating the unbalanced phase shift angle θ′.

[0018] The carrier information of the second switch Q2, the third switch Q3, and the fourth switch Q4 is obtained through the carrier information of the first switch Q1. The carrier of the second switch Q2 is the same as that of Q1, the carrier of the fourth switch Q4 is complementary to that of Q1, and the carrier of the third switch Q3 is the same as that of Q4.

[0019] Furthermore, the unbalanced phase shift angle θ′ and the compensation phase shift angle are obtained by calculating the carrier valley phase θ. The calculation formula is as follows:

[0020]

[0021] Furthermore, the unbalanced phase shift angle θ′ is obtained by calculating the duty cycle adjustment Δd, and the carrier valley phase θ and the compensation phase shift angle are obtained by calculating the unbalanced phase shift angle θ′. The calculation formula is as follows:

[0022]

[0023] Furthermore, the statement based on the overall outward phase angle... The positive and negative relationships are determined, and the duty cycle of each switch is obtained using the corresponding duty cycle generation method, including:

[0024] when The formula for calculating the duty cycle of each switching transistor is as follows:

[0025]

[0026] when The formula for calculating the duty cycle of each switching transistor is as follows:

[0027]

[0028] Where d1, d2, d3, and d4 are the duty cycles of switching transistors Q1 to Q4, respectively, and d1 ≤ 0.5 and d4 ≤ 0.5.

[0029] Thirdly, the present invention provides a control system based on the aforementioned half-bridge three-level DAB asymmetric voltage equalization control circuit, comprising:

[0030] The duty cycle adjustment acquisition module is used to acquire the voltage V between capacitors C1 and C2. C1 and V C2 The duty cycle adjustment Δd is obtained by the output of the first PI controller;

[0031] The carrier information acquisition module is used to calculate the carrier information of each switch transistor according to the strong correlation between the unbalanced phase shift angle θ′ and Δd using the corresponding calculation method.

[0032] The overall external phase angle acquisition module is used to obtain the output voltage V. Co The difference between the voltage and the set voltage is input to the third PI controller, which outputs the overall outward phase shift angle. Among them, the overall outward phase angle Defined as Q1 compensated phase shift angle The phase shift angle between point B at the corresponding point and point C at the rising edge of S1;

[0033] The duty cycle acquisition module is used to determine the overall outward phase angle. The positive and negative relationships are used to obtain the duty cycle of each switch using the corresponding duty cycle generation method;

[0034] The pulse signal generation module is used to input the duty cycle and carrier information of each switch transistor into the preset pulse generator module to obtain the trigger pulse signal of all switches transistors.

[0035] The communication module transmits the trigger pulse signal to each switching transistor to achieve voltage equalization control of the upper and lower capacitors.

[0036] Furthermore, the carrier information acquisition module includes a first calculation unit, a second calculation unit, and a third calculation unit, wherein:

[0037] The first calculation unit is used to calculate the voltage V when the unbalanced phase shift angle θ′ and Δd are weakly correlated. C1 and V C2 The valley phase θ of the carrier wave of the first switch Q1 is obtained through the output of the second PI controller. The unbalanced phase shift angle θ′ and the compensation phase shift angle are then calculated from the valley phase θ.

[0038] The second calculation unit is used to calculate the unbalanced phase shift angle θ′ using the duty cycle adjustment Δd when the unbalanced phase shift angle θ′ and Δd are strongly correlated, and to calculate the carrier valley phase θ and the compensation phase shift angle using the unbalanced phase shift angle θ′.

[0039] The third computing unit is used to obtain the carrier information of the second switch Q2, the third switch Q3, and the fourth switch Q4 through the carrier information of the first switch Q1, wherein the carrier of the second switch Q2 is the same as that of Q1, the carrier of the fourth switch Q4 is complementary to that of Q1, and the carrier of the third switch Q3 is the same as that of Q4.

[0040] Furthermore, in the first calculation unit, the unbalanced phase shift angle θ′ and the compensation phase shift angle are calculated using the carrier valley phase θ. The calculation formula is as follows:

[0041]

[0042] Furthermore, in the second calculation unit, the unbalanced phase shift angle θ′ is calculated using the duty cycle adjustment Δd, and the carrier valley phase θ and the compensation phase shift angle are calculated using the unbalanced phase shift angle θ′. The calculation formula is as follows:

[0043]

[0044] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0045] This invention provides a half-bridge three-level DAB asymmetric voltage equalization control circuit, method, and system. It can realize midpoint potential balance control of the half-bridge three-level DAB circuit under no-load conditions through a control strategy. By calculating the degree of imbalance of the midpoint potential, it controls the two degrees of freedom of carrier valley phase and modulation wave duty cycle in real time. It can achieve midpoint potential imbalance control under both no-load and load conditions, without the need for additional voltage balancer circuits. It also has strong imbalance control capability and can restore the symmetry of DAB AC current after the imbalance factor disappears, so as to maximize the soft switching operation conditions of the switching transistor under load. Attached Figure Description

[0046] Figure 1This is the circuit topology diagram involved in the asymmetric control of a half-bridge DAB.

[0047] Figure 2 This is a schematic diagram of the pulse drive generation method for the Q1 transistor in the half-bridge DAB asymmetric control.

[0048] Figure 3 This is a schematic diagram of the overall control method for half-bridge DAB asymmetric control.

[0049] Figure 4 This is a diagram of the asymmetric control logic framework for a half-bridge DAB.

[0050] Figure 5 This is a diagram illustrating the effect of half-bridge DAB asymmetric control and voltage equalization control. Detailed Implementation

[0051] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0052] Example 1

[0053] This embodiment describes a half-bridge three-level DAB asymmetric voltage equalization control circuit, including: a primary-side three-level circuit, a secondary-side full-bridge circuit, and an isolation transformer module, wherein:

[0054] The primary-side three-level circuit includes capacitors C1 and C2, switching transistors Q1 to Q4, and anti-parallel diodes D. Q1 ~D Q4 Upper and lower clamping diodes D1 and D2; capacitors C1 and C2 are connected to the upper and lower DC buses of the three-level circuit, and the connection point of the bus capacitors C1 and C2 is the neutral point B; the switching transistors Q1 and Q2 form the upper arm of the half-bridge circuit, connected to the positive terminal of the DC bus and the neutral point; Q3 and Q4 form the lower arm of the half-bridge circuit, connected to the neutral point and the negative terminal of the DC bus. The D... Q1 ~D Q4 These are anti-parallel diodes Q1 to Q4, with D1 and D2 connected in series and then in parallel across the switching transistors Q2 and Q3.

[0055] The secondary-side full-bridge circuit includes capacitor C3, switching transistors S1 to S4, and anti-parallel diode D. S1 ~D S4 The capacitor C3 is connected to the upper and lower DC buses of the secondary full-bridge circuit. S1 and S2 are connected in series and then in parallel with S3 and S4, and then in parallel with capacitor C3.

[0056] The isolation transformer module includes a high-frequency transformer T. r The high-frequency transformer T r There is leakage inductance L rand DC blocking capacitor C r The primary side of the high-frequency transformer T is connected to the emitter of Q2 and the neutral point B, respectively, and the secondary side is connected to the emitters of S1 and S3, respectively.

[0057] The involved three-level half-bridge dual-active bridge (TLHB-DAB) circuit is as follows: Figure 1 As shown, C1 and C2 are the upper and lower DC bus capacitors of the three-level circuit, respectively, and Q1 to Q4 are the four switching transistors of the primary-side three-level circuit, respectively. Q1 ~D Q4 These are the anti-parallel diodes Q1 through Q4, D1 and D2 are the upper and lower clamping diodes in the three-level circuit, and S1 through S4 are the four switching transistors in the secondary-side full-bridge circuit. S1 ~D S4 S1 to S4 are anti-parallel diodes, and C3 is the DC bus capacitor of the secondary-side full-bridge circuit. r This is a high-frequency transformer with a turns ratio of and an excitation inductance of L. m Leakage inductance is L r The leakage inductance is used as the transmission inductance for the DAB. C r This is a DC blocking capacitor, configured as needed to prevent transformer saturation. V C1 V is the voltage across capacitor C1. C2 This is the voltage across capacitor C2.

[0058] Asymmetric control pulse generation methods, such as Figure 2 and Figure 3 As shown. Figure 2 This refers to the asymmetric pulse generation method using transistors Q1 and S1. Figure 3 The diagram shows the overall drive pulses for the three-level and two-level sides of the TLHB-DAB circuit. Figure 2 (d) corresponds to Figure 3 The bolded parts of Q1 and S1 drivers in the text. Figure 2 The images (a) to (c) show the phase shift of the carrier valley phase θ from 0 phase to π phase. d1 is based on... Figure 4 The duty cycle information of the controlled Q1 transistor is obtained, and the duty cycle range is [0, 0.5]. The unbalance phase shift angle is denoted as θ′, which is obtained by θ′ = π - θ. A corresponding compensation phase shift angle is generated based on different carrier valley phase shift angles, denoted as... pass Obtain. Note that asymmetric control can be divided into left-side asymmetric control and right-side asymmetric control, corresponding to θ∈[0,π / 2] and θ∈[π / 2,π] respectively. In this example, left-side asymmetric control is used, so the phase range of asymmetry is [0,π / 2].

[0059] Asymmetric control strategies, such as Figure 4 As shown, it can be divided into two voltage equalization closed loops and an overall output closed loop. The purpose of both voltage equalization closed loops is to achieve voltage equalization control of the upper and lower bus capacitors. The two will not conflict in control; as long as θ′≠0, adjusting Δd alone can achieve voltage equalization control. As long as Δd≠0, adjusting θ′ alone can achieve voltage equalization control. Simultaneous adjustment of both can enhance each other; in actual implementation, a certain degree of correlation can be set as needed. Asymmetrical control can smoothly switch to symmetrical control mode (where θ′=0, Δd=0) when no imbalance occurs, to maximize the soft-switching operating conditions of the switching transistor under load. The overall output closed loop is used to stabilize the output voltage, obtaining the overall outward phase shift angle. Since θ and Δd are independent of the equalization control, they can be freely controlled.

[0060] This example uses a left-side asymmetric control strategy, and the specific steps are as follows:

[0061] Step 1, according to Figure 4 Real-time acquisition of voltage V of upper and lower capacitors C1 and V C2 The required duty cycle adjustment information is obtained through the first PI calculation. The duty cycle adjustment amount Δd has a range of [-0.5, 0.5].

[0062] Step two, according to Figure 4 If θ′ and Δd are set to be weakly correlated, then the voltage V of the upper and lower capacitors can be collected in real time. C1 and V C2 The required carrier valley phase θ is obtained through the second PI calculation, corresponding to... Figure 2 Point A in the diagram has a carrier valley phase range of [0, π]. This step obtains the required carrier, including the carrier valley phase θ of the first switch Q1, the unbalanced phase shift angle θ′, and the compensation phase shift angle.

[0063]

[0064] Step 3: If θ′ and Δd are set to be strongly correlated, then step 2 can be omitted, and the following formula can be used directly.

[0065]

[0066] The required unbalanced phase shift angle θ′, carrier valley phase θ, and compensation phase shift angle are obtained.

[0067] Step four: Based on steps two and three, the carrier information of the first switch Q1 has been obtained. The carrier of the second switch Q2 is the same as that of Q1. The carrier of the fourth switch Q4 is complementary to that of Q1, and the carrier of the third switch Q3 is the same as that of Q4.

[0068] Step 5, according to Figure 4 Real-time acquisition of output voltage V Co By combining the set voltage with a third PI calculation, the overall outward phase shift angle can be obtained. The definition of the outward phase angle is as follows: Figure 2 (d) and Figure 3 As shown, it is defined as the Q1 compensation phase shift angle. The phase shift angle between point B at the corresponding edge of S1 and point C at the corresponding edge of S1. Based on the phase shift angle... There are two methods for generating the duty cycle, one for positive and one for negative. At that time, according to

[0069]

[0070] Obtain the duty cycle of each switch. Where d1 ≤ 0.5, d4 ≤ 0.5. When At that time, according to

[0071]

[0072] Obtain the duty cycle of each switch. Where d1≤0.5, d4≤0.5.

[0073] Step six: Based on the above steps, the carrier and duty cycle information for Q1 to Q4 has been obtained, and the required pulses can be generated. S1 to S4 maintain a single-phase shift control method, generating square wave information with a 50% duty cycle. Closed-loop control using the external phase shift angle can stabilize the output voltage. By controlling the carrier valley phase θ and the duty cycle adjustment Δd, voltage equalization control can be performed on the upper and lower capacitors. The voltage equalization control effect is as follows: Figure 5 As shown. In V C2 A 1kΩ resistor is connected in parallel to simulate external imbalance factors, causing the TLHB-DAB circuit to operate under no-load, positive rated power, and negative rated power for 0-2 seconds, 2-3 seconds, and 3-4 seconds respectively. The waveform diagram is shown below. Figure 5 As shown, the asymmetric control method is effective under both no-load and loaded conditions, and achieves a good pressure equalization effect.

[0074] Example 2

[0075] This embodiment provides a control method based on the aforementioned half-bridge three-level DAB asymmetric voltage equalization control circuit, including:

[0076] Obtain the voltage V between capacitors C1 and C2 C1 and V C2 The duty cycle adjustment Δd is obtained by the output of the first PI controller;

[0077] Based on the strong correlation between the unbalanced phase shift angle θ′ and Δd, the carrier information of each switch is calculated using the corresponding calculation method.

[0078] Obtain the output voltage V Co The overall outward phase shift angle is obtained by the output of the third PI controller. Among them, the overall outward phase angle Defined as Q1 compensated phase shift angle The phase shift angle between point B at the corresponding point and point C at the rising edge of S1;

[0079] Based on the overall outward phase angle The positive and negative relationships are used to obtain the duty cycle of each switch using the corresponding duty cycle generation method;

[0080] The duty cycle and carrier information of each switch are input into a preset pulse generator module to obtain the trigger pulse signal of all switches.

[0081] The trigger pulse signal is transmitted to each switching transistor to achieve voltage equalization control of the upper and lower capacitors.

[0082] The application process of the half-bridge three-level DAB asymmetric voltage equalization control circuit provided in this embodiment involves the following steps:

[0083] Step 1, according to Figure 4 Real-time acquisition of voltage V of upper and lower capacitors C1 and V C2 The required duty cycle adjustment information is obtained through the first PI calculation. The duty cycle adjustment amount Δd has a range of [-0.5, 0.5].

[0084] Step two, according to Figure 4 If θ′ and Δd are set to be weakly correlated, then the voltage V of the upper and lower capacitors can be collected in real time. C1 and V C2 The required carrier valley phase θ is obtained through the second PI calculation, corresponding to... Figure 2 Point A in the diagram has a carrier valley phase range of [0, π]. This step obtains the required carrier, including the carrier valley phase θ of the first switch Q1, the unbalanced phase shift angle θ′, and the compensation phase shift angle.

[0085]

[0086] Step 3: If θ′ and Δd are set to be strongly correlated, then step 2 can be omitted, and the following formula can be used directly.

[0087]

[0088] The required unbalanced phase shift angle θ′, carrier valley phase θ, and compensation phase shift angle are obtained.

[0089] Step four: Based on steps two and three, the carrier information of the first switch Q1 has been obtained. The carrier of the second switch Q2 is the same as that of Q1. The carrier of the fourth switch Q4 is complementary to that of Q1, and the carrier of the third switch Q3 is the same as that of Q4.

[0090] Step 5, according to Figure 4 Real-time acquisition of output voltage V Co By combining the set voltage with a third PI calculation, the overall outward phase shift angle can be obtained. The outer phase angle is defined as follows: Figure 3 As shown, it is defined as the Q1 compensation phase shift angle. The phase shift angle between point B at the corresponding edge of S1 and point C at the corresponding edge of S1. Based on the phase shift angle... There are two methods for generating the duty cycle, one for positive and one for negative. At that time, according to

[0091]

[0092] Obtain the duty cycle of each switch. Where d1 ≤ 0.5, d4 ≤ 0.5. When At that time, according to

[0093]

[0094] Obtain the duty cycle of each switch. Where d1≤0.5, d4≤0.5.

[0095] Step six: Based on the above steps, the carrier and duty cycle information for Q1 to Q4 has been obtained, and the required pulses can be generated. S1 to S4 maintain a single-phase shift control method, generating square wave information with a 50% duty cycle. Closed-loop control using the external phase shift angle can stabilize the output voltage. By controlling the carrier valley phase θ and the duty cycle adjustment Δd, voltage equalization control can be performed on the upper and lower capacitors. The voltage equalization control effect is as follows: Figure 5 As shown. In V C2 A 1kΩ resistor is connected in parallel to simulate external imbalance factors, causing the TLHB-DAB circuit to operate under no-load, positive rated power, and negative rated power for 0-2 seconds, 2-3 seconds, and 3-4 seconds respectively. The waveform diagram is shown below. Figure 5 As shown, the asymmetric control method is effective under both no-load and loaded conditions, and achieves a good pressure equalization effect.

[0096] Example 3

[0097] This embodiment provides a control system based on the aforementioned half-bridge three-level DAB asymmetric voltage equalization control circuit, including:

[0098] The duty cycle adjustment acquisition module is used to acquire the voltage V between capacitors C1 and C2. C1 and V C2 The duty cycle adjustment Δd is obtained by the output of the first PI controller;

[0099] The carrier information acquisition module is used to calculate the carrier information of each switch transistor according to the strong correlation between the unbalanced phase shift angle θ′ and Δd using the corresponding calculation method.

[0100] The overall external phase angle acquisition module is used to obtain the output voltage V. Co The difference between the input voltage and the set voltage is used to obtain the overall outward phase shift angle through the output of the third PI controller. Among them, the overall outward phase angle Defined as Q1 compensated phase shift angle The phase shift angle between point B at the corresponding point and point C at the rising edge of S1;

[0101] The duty cycle acquisition module is used to determine the overall outward phase angle. The positive and negative relationships are used to obtain the duty cycle of each switch using the corresponding duty cycle generation method;

[0102] The pulse signal generation module is used to input the duty cycle and carrier information of each switch transistor into the preset pulse generator module to obtain the trigger pulse signal of all switches transistors.

[0103] The communication module transmits the trigger pulse signal to each switching transistor to achieve voltage equalization control of the upper and lower capacitors.

[0104] Specifically, the carrier information acquisition module includes a first calculation unit, a second calculation unit, and a third calculation unit, wherein:

[0105] The first calculation unit is used to calculate the voltage V when the unbalanced phase shift angle θ′ and Δd are weakly correlated. C1 and V C2 The valley phase θ of the carrier wave of the first switch Q1 is obtained through the output of the second PI controller. The unbalanced phase shift angle θ′ and the compensation phase shift angle are then calculated from the valley phase θ.

[0106] The second calculation unit is used to calculate the unbalanced phase shift angle θ′ using the duty cycle adjustment Δd when the unbalanced phase shift angle θ′ and Δd are strongly correlated, and to calculate the carrier valley phase θ and the compensation phase shift angle using the unbalanced phase shift angle θ′.

[0107] The third computing unit is used to obtain the carrier information of the second switch Q2, the third switch Q3, and the fourth switch Q4 through the carrier information of the first switch Q1, wherein the carrier of the second switch Q2 is the same as that of Q1, the carrier of the fourth switch Q4 is complementary to that of Q1, and the carrier of the third switch Q3 is the same as that of Q4.

[0108] Specifically, in the first calculation unit, the unbalanced phase shift angle θ′ and the compensation phase shift angle are calculated using the carrier valley phase θ. The calculation formula is as follows:

[0109]

[0110] Specifically, in the second calculation unit, the unbalanced phase shift angle θ′ is calculated using the duty cycle adjustment Δd, and the carrier valley phase θ and the compensation phase shift angle are calculated using the unbalanced phase shift angle θ′. The calculation formula is as follows:

[0111]

[0112] Specifically, in the duty cycle acquisition module, based on the overall outward phase angle... The positive and negative relationships are determined, and the duty cycle of each switch is obtained using the corresponding duty cycle generation method, including:

[0113] when The formula for calculating the duty cycle of each switching transistor is as follows:

[0114]

[0115] when The formula for calculating the duty cycle of each switching transistor is as follows:

[0116]

[0117] Where d1, d2, d3, and d4 are the duty cycles of switching transistors Q1 to Q4, respectively, and d1 ≤ 0.5 and d4 ≤ 0.5.

[0118] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A control method for a half-bridge three-level DAB asymmetric voltage equalization control circuit, comprising: Obtain the capacitance of the primary-side three-level circuit and voltage and The duty cycle adjustment is obtained by the output of the first PI controller. ; Based on the unbalanced phase shift angle and The strong or weak correlation relationship is determined, and the carrier information of each switch is calculated using corresponding methods; including: The voltage and The first switching transistor of the primary-side three-level circuit is obtained through the output of the second PI controller. Carrier valley phase Through carrier valley phase Calculate the unbalanced phase shift angle and compensated phase shift angle ; And / or, by adjusting the duty cycle amount Calculate the unbalanced phase shift angle Through unbalanced phase shift angle Calculate the carrier valley phase and compensated phase shift angle ; Through the first switching transistor The carrier information is used to obtain the second switching transistor of the primary three-level circuit. Third switching transistor Fourth switching transistor The carrier information, in which the second switch transistor carrier and Same, fourth switching transistor carrier and Complementary, third switching transistor carrier and same; Obtain the output voltage The overall outward phase shift angle is obtained by the output of the third PI controller. Among them, the overall outward shift phase angle Defined as Compensation phase angle Point B, corresponding to the secondary full-bridge circuit, and the switching transistor. The phase shift angle between point C corresponding to the rising edge; Based on the overall outward phase angle The positive and negative relationships are used to obtain the duty cycle of each switch using the corresponding duty cycle generation method; The duty cycle and carrier information of each switch are input into a preset pulse generator module to obtain the trigger pulse signal of all switches. The trigger pulse signal is transmitted to each switching transistor to achieve voltage equalization control of the upper and lower capacitors.

2. The control method for the half-bridge three-level DAB asymmetric voltage equalization control circuit according to claim 1, characterized in that, The phase through carrier valley Calculate the unbalanced phase shift angle and compensated phase shift angle The calculation formula is as follows: ； in, The range is .

3. The control method for the half-bridge three-level DAB asymmetric voltage equalization control circuit according to claim 1, characterized in that, The duty cycle adjustment amount Calculate the unbalanced phase shift angle Through unbalanced phase shift angle Calculate the carrier valley phase and compensated phase shift angle The calculation formula is as follows: ； in, The range is .

4. The control method for the half-bridge three-level DAB asymmetric voltage equalization control circuit according to claim 1, characterized in that, The overall outward phase angle The positive and negative relationships are determined, and the duty cycle of each switch is obtained using the corresponding duty cycle generation method, including: when The formula for calculating the duty cycle of each switching transistor is as follows: when The formula for calculating the duty cycle of each switching transistor is as follows: in, , , , They are switching transistors The duty cycle, of which, , .

5. A control system employing the control method of the half-bridge three-level DAB asymmetric voltage equalization control circuit as described in claim 1, characterized in that, include: The duty cycle adjustment acquisition module is used to acquire the capacitance. and voltage and The duty cycle adjustment is obtained by the output of the first PI controller. ; The carrier information acquisition module is used to determine the unbalanced phase shift angle. and The strong or weak correlation relationship is determined, and the carrier information of each switch is calculated using the corresponding calculation method. The overall external phase angle acquisition module is used to obtain the output voltage. The difference between the voltage and the set voltage is input to the third PI controller, which outputs the overall outward phase shift angle. Among them, the overall outward shift phase angle Defined as Compensation phase angle Point B at the corresponding location and The phase shift angle between point C corresponding to the rising edge; The duty cycle acquisition module is used to determine the overall outward phase angle. The positive and negative relationships are used to obtain the duty cycle of each switch using the corresponding duty cycle generation method; The pulse signal generation module is used to input the duty cycle and carrier information of each switch transistor into the preset pulse generator module to obtain the trigger pulse signal of all switches transistors. The communication module transmits the trigger pulse signal to each switching transistor to achieve voltage equalization control of the upper and lower capacitors; The carrier information acquisition module includes a first calculation unit, a second calculation unit, and a third calculation unit, wherein: The first calculation unit is used to calculate the voltage and The first switching transistor is obtained through the output of the second PI controller. Carrier valley phase Through carrier valley phase Calculate the unbalanced phase shift angle and compensated phase shift angle ; The second calculation unit is used to adjust the amount by the duty cycle. Calculate the unbalanced phase shift angle Through unbalanced phase shift angle Calculate the carrier valley phase and compensated phase shift angle ; The third computing unit is used to control the first switching transistor. The carrier information is used to obtain the second switch. Third switching transistor Fourth switching transistor The carrier information, in which the second switch transistor carrier and Same, fourth switching transistor carrier and Complementary, third switching transistor carrier and same.

6. The control system according to claim 5, characterized in that, In the first calculation unit, the carrier valley phase is used. Calculate the unbalanced phase shift angle and compensated phase shift angle The calculation formula is as follows: ； in, The range is .

7. The control system according to claim 5, characterized in that, In the second calculation unit, the duty cycle is adjusted. Calculate the unbalanced phase shift angle Through unbalanced phase shift angle Calculate the carrier valley phase and compensated phase shift angle The calculation formula is as follows: ； in, The range is .

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