NOR-type memory device, method of manufacturing the same, and electronic device including the memory device

Abstract

A NOR-type memory device, a manufacturing method thereof, and an electronic device including the same are disclosed. According to an embodiment, the NOR-type memory device can include a plurality of device layers disposed on a substrate, each device layer including a stack of a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer; a gate stack extending vertically with respect to the substrate to pass through the stack in each device layer, the gate stack including a gate conductor layer and a storage function layer disposed between the gate conductor layer and the stack, defining two storage cells stacked on each other at an intersection of the gate stack and the stack; and an isolation layer disposed between adjacent device layers. The first source / drain layer and the third source / drain layer in each device layer are electrically connected to different bit lines, respectively, and the second source / drain layer is electrically connected to a source line.

Description

[0001] This application is a divisional application of invention patent application 202110252927.4 entitled “NOR type memory device and method of manufacturing the same and electronic device including the memory device”, filed on March 8, 2021. Technical Field

[0002] This disclosure relates to the semiconductor field, and more specifically to NOR-type memory devices, methods of manufacturing the same, and electronic devices including such memory devices. Background Technology

[0003] In horizontal devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), the source, gate, and drain are arranged in a direction generally parallel to the substrate surface. Due to this arrangement, horizontal devices are not easily miniaturized further. In contrast, in vertical devices, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical devices are easier to miniaturize than horizontal devices.

[0004] For vertically oriented devices, integration density can be increased by stacking them on top of each other. However, this can lead to performance degradation. This is because polysilicon is typically used as the channel material to facilitate stacking multiple devices, resulting in higher resistance compared to monocrystalline silicon channel materials. Furthermore, it is desirable to be able to individually adjust the doping levels in the source / drain regions and the channel. Summary of the Invention

[0005] In view of this, the purpose of this disclosure is at least in part to provide a NOR-type memory device with improved performance, a method for manufacturing the same, and an electronic device including such a memory device.

[0006] According to one aspect of this disclosure, a vertical memory device is provided, comprising: a plurality of device layers disposed on a substrate, each device layer including a stack of a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer; a gate stack extending vertically relative to the substrate through the stack of the respective device layers, the gate stack including a gate conductor layer and a memory function layer disposed between the gate conductor layer and the stack, defining two stacked memory cells at the intersection of the gate stack and the stack; and an isolation layer disposed between adjacent device layers. The first source / drain layer and the third source / drain layer in each device layer are electrically connected to different bit lines, while the second source / drain layer is electrically connected to a source line.

[0007] According to another aspect of this disclosure, a method for manufacturing a vertical memory device is provided, comprising: forming a plurality of device layers on a substrate, each device layer including a stack of a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer, and a sacrificial layer between adjacent device layers; forming a processing channel extending vertically relative to the substrate to pass through the stack in each device layer; replacing the sacrificial layer with an isolation layer via the processing channel; forming a gate stack in the processing channel, the gate stack including a gate conductor layer and a memory function layer disposed between the gate conductor layer and the stack, defining a memory cell at the intersection of the gate stack and the stack; electrically connecting the first source / drain layer and the third source / drain layer in each device layer to different bit lines, and electrically connecting the second source / drain layer to a source line.

[0008] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned NOR-type memory device.

[0009] According to embodiments of this disclosure, a stack of single-crystal materials can be used as building blocks to construct three-dimensional (3D) NOR memory devices. Therefore, when multiple memory cells are stacked on top of each other, the increase in resistance can be suppressed. Furthermore, each layer can be doped separately, thereby enabling separate adjustment of the doping levels in the source / drain regions and the channel region. Attached Figure Description

[0010] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0011] Figures 1 to 11(c) A schematic diagram of some stages in the process of manufacturing a NOR-type memory device according to an embodiment of the present disclosure is shown;

[0012] Figure 12(a) and 12(b) A schematic diagram of some stages in the process of manufacturing a NOR-type memory device according to another embodiment of the present disclosure is shown;

[0013] Figure 13 A schematic diagram of some stages in the process of manufacturing a NOR-type memory device according to another embodiment of the present disclosure is shown;

[0014] Figure 14 and 15 A schematic diagram of some stages in the process of manufacturing a NOR-type memory device according to another embodiment of the present disclosure is shown;

[0015] Figures 16(a) to 17(b) A schematic diagram of some stages in the process of manufacturing a NOR-type memory device according to an embodiment of the present disclosure is shown;

[0016] Figure 18An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is shown schematically.

[0017] in, Figure 2(a) , 7(a) Figures 11(a) and 12(a) are top views. Figure 2(a) shows the positions of lines AA′ and BB′.

[0018] Figure 1 , 2(b) Figures 3 to 6, 7(b), 8(a), 9(a), 10(a), 11(b), 12(b), 16(a), and 17(a) are cross-sectional views along line AA′.

[0019] Figure 7(c) , 8(b) Figures 9(b), 10(b), 11(c), 13 to 15, 16(b), and 17(b) are cross-sectional views along line BB′.

[0020] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0021] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0023] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0024] The memory device according to embodiments of this disclosure is based on a vertical device. The vertical device may include an active region disposed on a substrate in a vertical direction (generally perpendicular to the substrate surface), including source / drain regions at the top and bottom ends and a channel region located between the source / drain regions. A conductive path can be formed between the source / drain regions through the channel region. In the active region, the source / drain regions and the channel region can be defined, for example, by doping concentration.

[0025] According to embodiments of this disclosure, the active region can be defined by a stack of a first source / drain layer, a first channel layer, and a second source / drain layer on a substrate. The source / drain regions can be formed in the first and second source / drain layers, respectively, while the channel region can be formed in the first channel layer. A gate stack can extend through the stack, so that the active region can surround the periphery of the gate stack. Here, the gate stack can include at least one of a storage functional layer, such as a charge trapping material or a ferroelectric material, to realize a storage function. Thus, the gate stack cooperates with the opposing active region to define a memory cell. Here, the memory cell can be a flash memory cell.

[0026] Multiple gate stacks can be arranged to extend through the stack, thereby defining multiple memory cells at the intersections of the multiple gate stacks with the stack. These memory cells are arranged in an array (e.g., typically a two-dimensional array arranged in rows and columns) in the plane of the stack, corresponding to the multiple gate stacks.

[0027] Due to the ease of stacking vertical devices, the memory devices according to embodiments of this disclosure can be three-dimensional (3D) arrays. Specifically, multiple such stacks can be arranged in the vertical direction. The gate stack can extend vertically through these multiple stacks. Thus, for a single gate stack, it intersects with these multiple stacks stacked in the vertical direction to define multiple memory cells stacked in the vertical direction.

[0028] In NOR ("NOR") type memory devices, each memory cell can be connected to a common source line. Given this configuration, to save wiring, in the vertical direction, every two adjacent memory cells can share the same source line connection. For example, the above stack-up can further include a second channel layer and a third source / drain layer. Thus, the first source / drain layer, the first channel layer, and the second source / drain layer can cooperate with the gate stack as described above to define a first memory cell, and similarly, the second source / drain layer, the second channel layer, and the third source / drain layer can cooperate with the gate stack to define a second memory cell. The first and second memory cells are stacked on top of each other and share the same second source / drain layer, which can be electrically connected to the source line.

[0029] The aforementioned stack can be formed by epitaxial growth on a substrate and can be a single-crystal semiconductor material. Compared to conventional processes that form multiple gate stacks stacked on top of each other and then form vertical active regions through these gate stacks, it is easier to form single-crystal active regions (especially channel layers). Furthermore, during growth, each layer in the stack can be in-situ doped separately, and doping concentration interfaces can exist between layers with different doping concentrations. This allows for better control of the doping distribution in the vertical direction. The stack of the first source / drain layer, the channel layer, and the second source / drain layer can constitute a bulk material, and thus the channel region is formed within the bulk material. In this case, the process is relatively simple.

[0030] Such vertical memory devices can be manufactured, for example, as follows. Specifically, multiple device layers can be formed on a substrate, each device layer comprising a stack of a first source / drain layer, a first channel layer, and a second source / drain layer (and optionally, a second channel layer and a third source / drain layer as described above). These layers can be provided, for example, by epitaxial growth. During epitaxial growth, the thickness of each grown layer, particularly the channel layer, can be controlled. Furthermore, during epitaxial growth, in-situ doping can be performed to achieve the desired doping polarity and doping concentration. Here, each layer in the stack can comprise the same material. In this case, the term "layer" can be defined by the doping concentration interfaces between them.

[0031] A sacrificial layer can be formed between at least some or all of adjacent device layers. This sacrificial layer can then be replaced with an isolation layer to electrically isolate adjacent bit lines. The sacrificial layer can be etch-selective relative to the device layers.

[0032] Processing channels can be formed that extend vertically relative to the substrate to penetrate the stacked layers in each device layer. Within these processing channels, the sidewalls of the sacrificial layer can be exposed, allowing it to be replaced with an isolation layer. Gate stacks can be formed within these processing channels.

[0033] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation.

[0034] Figures 1 to 11(c)A schematic diagram of some stages in the process of manufacturing a NOR-type memory device according to an embodiment of the present disclosure is shown.

[0035] like Figure 1 As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate, such as a Si wafer, will be used as an example.

[0036] On substrate 1001, a memory device, such as NOR flash memory, can be formed as described below. The memory cell in the memory device can be an n-type device or a p-type device. Here, an n-type memory cell is described as an example, for which a p-type well can be formed in substrate 1001. Therefore, the following description, particularly regarding the doping type, is for the formation of n-type devices. However, this disclosure is not limited thereto.

[0037] On substrate 1001, a sacrificial layer 10031 for defining an isolation layer, a first source / drain layer 10051 for defining a source / drain region, a first channel layer 10071 for defining a channel region, a second source / drain layer 10091 for defining a source / drain region, a second channel layer 10111 for defining a channel region, and a third source / drain layer 10131 for defining a source / drain region can be formed, for example, by epitaxial growth. The first source / drain layer 10051, the first channel layer 10071, the second source / drain layer 10091, the second channel layer 10111, and the third source / drain layer 10131 will then define the active region of the device, which can be referred to as the "device layer", denoted as L1 in the figure.

[0038] The layers grown on the substrate 1001 can be single-crystal semiconductor layers. Because these layers are grown or doped separately, they can have crystal interfaces or doping concentration interfaces with each other.

[0039] The sacrificial layer 10031 can then be replaced with an isolation layer for isolating the device from the substrate, the thickness of which can correspond to the desired thickness of the isolation layer, for example, about 10 nm to 50 nm. Depending on the circuit design, the sacrificial layer 10031 may also be omitted. The first source / drain layer 10051, the second source / drain layer 10091, and the third source / drain layer 10131 can be doped (e.g., in-situ doping during growth) to form source / drain regions, the thickness of which can be, for example, about 20 nm to 50 nm. The first channel layer 10071 and the second channel layer 10111 can define a gate length, the thickness of which can correspond to the desired gate length, for example, about 15 nm to 100 nm.

[0040] These semiconductor layers can include a variety of suitable semiconductor materials, such as elemental semiconductor materials like Si or Ge, compound semiconductor materials like SiGe, etc. Consider the following process of replacing the sacrificial layer 10031 with an isolation layer, where the sacrificial layer 10031 can have etch selectivity relative to the device layer. For example, the sacrificial layer 10031 can include SiGe (the atomic percentage of Ge is, for example, about 15%-30%), and the device layer can include Si. In this example, both the source / drain layer and the channel layer in the device layer include Si, but this disclosure is not limited thereto. For example, etch selectivity can also exist between adjacent layers in the device layer.

[0041] During the growth of the first source / drain layer 10051, the second source / drain layer 10091, and the third source / drain layer 10131, they can be in-situ doped to subsequently form the source / drain regions. For example, for n-type devices, n-type doping can be performed, with a doping concentration of, for example, about 1E19-1E21 cm⁻¹. -3 Additionally, the first channel layer 10071 and the second channel layer 10111 may not be intentionally doped, or may be lightly doped through in-situ doping during growth, in order to improve the short-channel effect and adjust the device threshold voltage (V). t For example, for n-type devices, p-type doping can be performed, with a doping concentration of approximately 1E17-1E19 cm⁻¹. -3 .

[0042] To increase integration density, multiple device layers can be configured. For example, device layer L2 can be fabricated on device layer L1 via epitaxial growth, with the device layers spaced apart by a sacrificial layer 10032 used to define isolation layers. Although Figure 1 Only two device layers are shown, but this disclosure is not limited thereto. Depending on the circuit design, some device layers may not have isolation layers. Similarly, device layer L2 may have a first source / drain layer 10052, a first channel layer 10072, a second source / drain layer 10092, a second channel layer 10112, and a third source / drain layer 10132. The corresponding layers in each device layer may have the same or similar thickness and / or material, or they may have different thicknesses and / or materials. Here, for the sake of convenience, it is assumed that each device layer L1 and L2 has the same configuration.

[0043] On these layers formed on the substrate 1001, a hard mask layer 1015 can be disposed to facilitate patterning. For example, the hard mask layer 1015 may include a nitride (e.g., silicon nitride) with a thickness of about 50 nm to 200 nm.

[0044] A sacrificial layer 10033 for defining the isolation layer may also be provided between the hard mask layer 1015 and the device layer L2. For details about sacrificial layers 10032 and 10033, please refer to the description of sacrificial layer 10031 above.

[0045] Therefore, on the one hand, a processing channel is needed to reach the sacrificial layer in order to replace the sacrificial layer with an isolation layer; on the other hand, it is necessary to define the area for forming the gate. According to embodiments of this disclosure, these two can be combined. Specifically, the processing channel can be used to define the gate area.

[0046] For example, such as Figure 2(a) and 2(b) As shown, photoresist 1017 can be formed on a hard mask layer 1015 and patterned by photolithography to have a series of openings that define the locations of processing channels. The openings can be of various suitable shapes, such as circles, rectangles, squares, polygons, etc., and have suitable sizes, such as diameters or side lengths of approximately 20 nm to 500 nm. Here, these openings (particularly in the device region) can be arranged in an array, for example, a two-dimensional array along the horizontal and vertical directions in the plane of the paper in FIG. 2(a). This array can then define an array of memory cells. Although the openings are shown in FIG. 2(a) as being formed on the substrate (including the device region where memory cells will subsequently be fabricated and the contact region where contacts will subsequently be fabricated) with substantially uniform size and a generally uniform density, this disclosure is not limited thereto. The size and / or density of the openings can be varied; for example, the density of openings in the contact region can be less than the density of openings in the device region to reduce resistance in the contact region.

[0047] like Figure 3 As shown, photoresist 1017, configured as an etching mask, is used to etch layers on substrate 1001 using anisotropic etching such as reactive ion etching (RIE) to form processing channels T. RIE can be performed in a generally vertical direction (e.g., perpendicular to the substrate surface) and can extend into substrate 1001. This leaves a series of vertical processing channels T on substrate 1001. The processing channels T in the device region also define the gate region. Afterward, photoresist 1017 can be removed.

[0048] Currently, the sidewalls of the sacrificial layer are exposed in the processing channel T. Therefore, the sacrificial layer can be replaced with an isolation layer via the exposed sidewalls. Considering the support function for device layers L1 and L2 during replacement, a support layer can be formed.

[0049] For example, such as Figure 4As shown, a support material layer can be formed on substrate 1001 by deposition, for example, chemical vapor deposition (CVD). The support material layer can be formed in a generally conformal manner. Considering etching selectivity, especially relative to the hard mask layer 1015 (nitride in this example) and the subsequently formed isolation layer (oxide in this example), the support material layer can include, for example, SiC. The support material layer in part of the processing channel T can be removed, for example, by forming photoresist 1021 and selectively etching, such as RIE, in conjunction with the photoresist 1021, while retaining the support material layer in the remaining processing channels T. The remaining support material layer forms support layer 1019. In this way, on the one hand, the sacrificial layer can be replaced by the processing channel in which support layer 1019 is not formed, and on the other hand, the device layers L1 and L2 can be supported by support layer 1019 in other processing channels. Afterwards, photoresist 1021 can be removed.

[0050] The arrangement of processing channels with and without support layers 1019 can be achieved through the patterning of photoresist 1021, and for the sake of process consistency and uniformity, they can be distributed approximately evenly. Figure 4 As shown, the processing channels in which the support layer 1019 is formed can be arranged alternately with the processing channels in which the support layer 1019 is not formed.

[0051] Then, as Figure 5 As shown, sacrificial layers 10031, 10032, and 10033 can be removed via selective etching through processing channel T. The presence of the support layer 1019 prevents device layers L1 and L2 from collapsing. In the voids left by the removal of the sacrificial layers, dielectric material can be filled to form isolation layers 10231, 10232, and 10233 using a process such as deposition (e.g., atomic layer deposition (ALD) for better control of film thickness) followed by etching back (e.g., vertical RIE). Suitable dielectric materials, such as oxides, nitrides, SiC, or combinations thereof, can be selected for various purposes, such as optimizing isolation reliability, leakage current, or capacitance. Here, considering etching selectivity, isolation layers 10231, 10232, and 10233 may comprise oxides (e.g., silicon oxide).

[0052] Afterwards, the support layer 1019 can be removed by selective etching.

[0053] Gate stacks can be formed in the processing channels, particularly in the device area. To form a memory device, the memory function can be achieved through the gate stack. For example, the gate stack can include memory structures such as charge trapping layers or ferroelectric materials.

[0054] like Figure 6As shown, the memory functional layer 1025 and the gate conductor layer 1027 can be formed sequentially, for example, by deposition. The memory functional layer 1025 can be formed in a generally conformal manner, and the gate conductor layer 1027 can fill the gaps remaining in the processing channel T after the memory functional layer 1025 is formed. The formed gate conductor layer 1027 and memory functional layer 1025 can be planarized, such as by chemical mechanical polishing (CMP, for example, stopping at the hard mask layer 1015), so that the gate conductor layer 1027 and memory functional layer 1025 can remain in the processing channel T, forming a gate stack.

[0055] The storage functional layer 1025 can be based on dielectric charge trapping, ferroelectric material effects, or engineered charge storage (SONOS). For example, the storage functional layer 1025 may include a dielectric tunneling layer (e.g., an oxide layer with a thickness of about 1 nm to 5 nm, which can be formed by oxidation or ALD) - a band shift layer (e.g., a nitride layer with a thickness of about 2 nm to 10 nm, which can be formed by CVD or ALD) - an isolation layer (e.g., an oxide layer with a thickness of about 2 nm to 6 nm, which can be formed by oxidation, CVD, or ALD). This three-layer structure can result in a band structure that traps electrons or holes. Alternatively, the storage functional layer 1025 may include a ferroelectric material layer, such as HfZrO2 with a thickness of about 2 nm to 20 nm.

[0056] The gate conductor layer 1027 may include, for example, (doped, such as p-type doped in the case of an n-type device) polysilicon or a metal gate material.

[0057] like Figure 6 As shown, the gate stack (1025 / 1027) with memory functional layers is surrounded by active regions. The gate stack, in conjunction with the active regions (a stack of source / drain layers, channel layers, and source / drain layers), defines the memory cells, such as... Figure 6 As shown by the dashed circle in the diagram. The channel region formed in the channel layer can connect to the source / drain regions formed in the source / drain layers at opposite ends, and the channel region can be controlled by the gate stack.

[0058] The gate stack extends vertically in a columnar shape, intersecting with multiple device layers, thereby defining multiple memory cells stacked on top of each other in the vertical direction. Memory cells associated with a single gate stack pillar can form a memory cell string. Corresponding to the layout of the gate stack pillars (corresponding to the layout of the aforementioned processing channel T, such as a two-dimensional array), multiple such memory cell strings are arranged on the substrate to form a three-dimensional (3D) array of memory cells.

[0059] In this embodiment, a single gate stack pillar can define two memory cells in a single device layer, such as Figure 6The two dashed coils in the device layer L1 are shown. In a NOR memory device, these two memory cells can share the same source / drain layer (the middle second source / drain layer 10091 or 10092) and are electrically connected to the source line. Additionally, these two memory cells are electrically connected to the bit line via the upper and lower source / drain layers (the first source / drain layer 10051 or 10052 and the third source / drain layer 10131 or 10132), respectively.

[0060] This completes the fabrication of the memory cell (in the device area). Then, various electrical contacts can be fabricated (in the contact area) to achieve the required electrical connections.

[0061] To achieve electrical connections to various device layers, a stepped structure can be formed in the contact area. Various methods exist in the art for forming such a stepped structure. According to embodiments of this disclosure, the stepped structure can be formed, for example, as follows.

[0062] like Figure 6 As shown, the current gate stack is exposed at the surface of hard mask layer 1015. To protect the gate stack (in the device area) during the fabrication of the stepped structure, another hard mask layer 1029 can be formed first on hard mask layer 1015, as shown below. Figure 7(a) , 7(b) As shown in 7(c). For example, the hard mask layer 1029 may include oxide. Photoresist 1031 may be formed on the hard mask layer 1029 and patterned by photolithography to expose the contact area by masking the device region. The photoresist 1031 can be used as an etching mask to selectively etch the hard mask layer 1029, hard mask layer 1015, isolation layer 10233, and gate stack by means of RIE to expose the device layer. The etching depth can be controlled so that the surface exposed by the photoresist 1031 in the contact area after etching is substantially flat. For example, the hard mask layer 1029 can be etched first; then the gate conductor layer 1027 can be etched, with the etching of the gate conductor layer 1027 stopping near the top surface of the device layer L2; then, the hard mask layer 1015 and the isolation layer 10233 can be etched sequentially; after this etching, the top of the storage function layer 1025 can protrude above the top surface of the device layer L2 and can be removed by RIE. This creates a step between the contact area and the device area. Afterwards, the photoresist 1031 can be removed.

[0063] like Figure 8(a) and 8(b)As shown, a sidewall 1033 can be formed at the step between the contact area and the device area using a spacer forming process. For example, a dielectric layer, such as oxide, can be deposited in a generally conformal manner, followed by anisotropic etching, such as a vertical RIE, of the deposited dielectric to remove the lateral extensions of the deposited dielectric, leaving only its vertical extensions, thereby forming the sidewall 1033. Here, considering that the hard mask layer 1029 also includes oxide, the etching depth of the RIE can be controlled to be substantially equal to or slightly greater than the deposition thickness of the dielectric to avoid completely removing the hard mask layer 1029. The width of the sidewall 1033 (in the horizontal direction in the figure) can be substantially equal to the deposition thickness of the dielectric. The width of the sidewall 1033 defines the size of the landing pad for the contact portion of the third source / drain layer 10132 subsequently in device layer L2.

[0064] Using the sidewall 1033 thus formed as an etching mask, the exposed third source / drain layer 10132 and gate stack can be etched by selective etching such as RIE to expose the second channel layer 10112 in device layer L2. The etching depth can be controlled so that the surface exposed by the sidewall 1033 in the contact area after etching is approximately flat. For example, the third source / drain layer 10132 and the gate conductor layer 1027 (e.g., Si and polysilicon, respectively; if the gate conductor layer 1027 includes a metal gate, they can be etched separately) can be etched first, and the etching can stop near the top surface of the second channel layer 10112; after such etching, the top of the storage function layer 1025 can protrude above the top surface of the second channel layer 10112 and can be removed by RIE. In this way, another step is formed in the contact area between the third source / drain layer 10132 and the surface exposed by the sidewall 1033.

[0065] You can combine the above methods. Figure 8(a) and 8(b) The described process involves forming sidewalls and using these sidewalls as etching masks to create multiple steps in the contact area, such as... Figure 9(a) and 9(b) As shown. These steps form a stepped structure such that for each layer in the device layer that requires electrical connection, such as the aforementioned source / drain layer and optional ground channel layer, its ends protrude relative to the layer above, defining landing pads for the contact portion of that layer. Figure 9(a) and 9(b) The 1035 in the diagram represents the portion of the sidewalls formed in each stage that remains after processing. Since these sidewalls 1035 and the insulating layer are both oxides, they are shown as a single unit here.

[0066] After that, the contact parts can be made.

[0067] For example, such as Figure 10(a) and 10(b) As shown, the interlayer dielectric layer 1037 can be formed by depositing oxides and planarizing them, such as with CMP. Here, since both are oxides, the previous insulating layer and sidewalls 1035 are shown as integral with the interlayer dielectric layer 1037. Then, as... Figure 11(a) , 11(b) As shown in 11(c), contacts 1039 and 1041 can be formed in the interlayer dielectric layer 1037. Specifically, contact 1039 is formed in the device region and electrically connected to the gate conductor layer 1027 in the gate stack; contact 1041 is formed in the contact region and electrically connected to the respective source / drain layers and channel layers. Contact 1041 in the contact region can avoid residual gate stacking in the contact region. These contacts can be formed by etching vias in the interlayer dielectric layer 1037 and filling them with a conductive material such as a metal.

[0068] Here, contact 1039 can be electrically connected to the word line. A gate control signal can be applied to the gate conductor layer 1027 via the word line and contact 1039. For two memory cells stacked on top of each other in the same device layer, the middle source / drain layer, i.e., the second source / drain layers 10091 and 10092, is shared by the two memory cells and can be electrically connected to the source line via contact 1041; the upper and lower source / drain layers, i.e., the first source / drain layers 10051 and 10052 and the third source / drain layers 10131 and 10132, can be electrically connected to the bit line via contact 1041 respectively. This results in a NOR-type configuration. A contact to the channel layer is also formed here. This contact can be called a body contact and can receive body bias to adjust the device threshold voltage.

[0069] Here, forming two memory cells in a single device layer can reduce the number of wiring connections. However, this disclosure is not limited to this. For example, only a single memory cell can be formed in a single device layer. In this case, only a first source / drain layer, a first channel layer, and a second source / drain layer can be provided in the device layer, without the need for a second channel layer and a third source / drain layer.

[0070] Figure 18 An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is shown schematically.

[0071] exist Figure 18 The example schematically shows three word lines WL1, WL2, WL3 and eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8. However, the specific number of bit lines and word lines is not limited to this. A memory cell MC is located at the intersection of the bit lines and word lines. Figure 18The diagram also shows four source lines SL1, SL2, SL3, and SL4. As mentioned above, adjacent memory cells in any two layers vertically can share the same source line connection. Furthermore, the source lines can be interconnected, allowing each memory cell MC to be connected to a common source line. Figure 18 The optional body connections to each memory cell are also schematically shown in dashed lines. As described below, the body connection of each memory cell can be electrically connected to the source line connection of that memory cell.

[0072] For illustrative purposes only, a two-dimensional array of storage cells MC is shown here. Multiple such two-dimensional arrays can be arranged in directions intersecting with this two-dimensional array (e.g., the direction perpendicular to the plane of the paper in the figure) to obtain a three-dimensional array.

[0073] Figure 18 The extension direction of the bit lines WL1 to WL3 can correspond to the extension direction of the gate stack, that is, the vertical direction relative to the substrate in the aforementioned embodiments. In this direction, adjacent bit lines are isolated from each other. This is also the reason why an isolation layer is provided between adjacent device layers in the vertical direction in the above embodiments.

[0074] In the above embodiments, the contact portion 1041 in the contact area needs to avoid the residual gate stack in the contact area. According to another embodiment of this disclosure, an insulating material such as a dielectric material can be formed on the top of the residual gate stack in the contact area, thereby eliminating the need to deliberately avoid these residual gate stacks.

[0075] For example, such as Figure 12(a) and 12(b) As shown, in combination as described above Figures 7(a) to 9(b) After forming the stepped structure in the contact region, the isolation layer and sidewalls 1035 can be removed by selective etching, such as RIE, to expose the tops of each gate stack (in the device region and the contact region). The gate stacks in the device region can be masked by a masking layer, such as photoresist, while exposing the gate stacks in the contact region. For the exposed gate stacks in the contact region, selective etching, such as RIE, can be used to recess the gate conductor layer, for example, by about 50 nm to 150 nm. The masking layer can then be removed. In the voids formed in the contact region due to the recess of the gate conductor layer, a dielectric material such as SiC can be filled by, for example, deposition followed by etching back, to form isolation plugs 1043.

[0076] Then, an interlayer dielectric layer can be formed according to the above embodiment, and contacts 1039 and 1041' can be formed therein. In this example, contact 1041' in the contact area can extend into the isolation plug 1043. Therefore, contact 1041' is not limited to the form of the plug described above, but can be formed as a strip to reduce contact resistance. The strip-shaped contact 1041' can extend along the landing pad of the corresponding layer (i.e., the step in the stepped structure).

[0077] In the above embodiments, due to the light doping or lack of intentional doping of the channel layer, the contact resistance between the body contact and the channel layer may be relatively large. According to another embodiment of this disclosure, a relatively highly doped region can be formed at the contact point between the channel layer and the body contact to reduce the contact resistance. For example, after forming an interlayer dielectric layer as described above and etching holes for the contact in the interlayer dielectric layer, a photoresist 1045 can be formed, and the photoresist 1045 can be patterned by photolithography to expose the holes for which the body contact is to be formed. A highly doped region 1047 can be formed in the landing pad of the channel layer via these holes, for example, by ion implantation. The doping type in the highly doped region 1047 can be the same as the doping type in the channel layer, but the doping concentration is higher than at least a portion of the rest of the channel layer. The photoresist 1045 can then be removed. The contact can then be formed in the holes of the interlayer dielectric layer.

[0078] In the above embodiments, the body contact portion is provided separately. According to other embodiments of this disclosure, the body contact portion can be integrated with the source line contact portion to save area. For example, as... Figure 14 and 15 As shown, the contact portions 1041″ and 1041″′ can contact the second source / drain layer and the first channel layer and second channel layer above and below the second source / drain layer in each device layer. Figure 14 and 15 The difference in the embodiment lies in the different stepped structure in the contact area. Figure 14 In the illustrated embodiment, steps can be formed both between the second source / drain layer and the first channel layer, and between the second source / drain layer and the second channel layer. However, in Figure 15 In the illustrated embodiment, no step may be formed between the second source / drain layer and the second channel layer to further save area.

[0079] In the above embodiments, the contact portion is in direct contact with the corresponding landing pad. According to other embodiments of this disclosure, silicide can be formed at the landing pad to reduce contact resistance. More specifically, at each step in the contact area, the transverse surface of the step serves as the landing pad, and silicide can be formed thereon. On the other hand, silicide may not be formed on the vertical surface of the step to avoid short circuits between the landing pads of adjacent steps.

[0080] For example, such as Figure 16(a) and 16(b) As shown, in combination as described above Figures 7(a) to 9(b) After forming the stepped structure in the contact area, the isolation layer and sidewalls 1035 can be removed by selective etching, such as RIE, to expose the surfaces of each step in the contact area. Dielectric sidewalls 1049, such as nitrides, can be formed on the vertical surfaces of each step using a sidewall forming process to shield these vertical surfaces from subsequent silicide reactions. Then, the exposed lateral surfaces of each step can be silicided. For example, a metal such as NiPt can be deposited and annealed, causing the deposited metal to silicide with the semiconductor material (e.g., Si) at the lateral surfaces of each step, thereby generating conductive metal silicides 1051, such as NiPtSi. Unreacted metal can then be removed.

[0081] In the example shown, the gate conductor layer 1027 is, for example, polysilicon, so its top can also undergo a silicide reaction and be covered by silicide. If the gate conductor layer 1027 is a metal gate, a protective layer (e.g., nitride) can be formed on the device region to cover the gate stack before silicide processing. This prevents the gate conductor layer 1027 from being etched and damaged during the metal removal process in the silicide processing.

[0082] After that, as Figure 17(a) and 17(b) As shown, an interlayer dielectric layer can be formed as described above, and contacts 1039 and 1041 can be formed therein. When etching the holes for the contacts, silicide 1051 can be used as an etching stop layer. Therefore, the etching depth of the holes can be better controlled.

[0083] The storage device according to embodiments of this disclosure can be applied to various electronic devices. For example, the storage device can store various programs, applications, and data required for the operation of the electronic device. The electronic device may also include a processor that cooperates with the storage device. For example, the processor can operate the electronic device by running programs stored in the storage device. Such electronic devices include smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, or power banks.

[0084] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0085] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A NOR-type storage device, comprising: Multiple device layers disposed on a substrate, each device layer comprising a stack of a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer; A gate stack extending vertically relative to the substrate through the stack of layers in each of the device layers, the gate stack including a gate conductor layer and a memory function layer disposed between the gate conductor layer and the stack, defining two memory cells stacked on top of each other at the intersection of the gate stack and the stack; An isolation layer is placed between adjacent device layers. In each of the device layers, the first source / drain layer and the third source / drain layer are electrically connected to different bit lines, while the second source / drain layer is electrically connected to the source line.

2. The NOR-type storage device according to claim 1, wherein, The storage functional layer includes at least one of a charge trapping material or a ferroelectric material.

3. The NOR-type storage device according to claim 1, wherein, The stacked layers comprise single-crystal semiconductor materials.

4. The NOR-type storage device according to claim 1, wherein, The stack surrounds the outer periphery of the gate stack.

5. The NOR-type storage device according to claim 1, wherein, The storage function layer is formed on the bottom surface and sidewalls of the gate conductor layer, and the storage function layer surrounds the sidewalls of the gate conductor layer.

6. The NOR-type memory device of claim 1, comprising a plurality of said gate stacks arranged in an array.

7. The NOR-type storage device according to claim 1, wherein, The first source / drain layer, the first channel layer, the second source / drain layer, the second channel layer, and the third source / drain layer comprise the same semiconductor material, wherein there is a doping concentration interface between adjacent layers.

8. The NOR-type storage device according to claim 1, further comprising: To the first contact portion of the first source / drain layer in each of the device layers; To the second contact portion of the second source / drain layer in each of the device layers; as well as To the third contact portion of the third source / drain layer in each of the device layers, The first contact portion and the third contact portion are electrically connected to the corresponding bit lines, and the second contact portion is electrically connected to the corresponding source line.

9. The NOR-type storage device according to claim 8, further comprising: To the fourth contact portion of the first channel layer in each of the device layers; as well as To the fifth contact portion of the second channel layer in each of the device layers.

10. The NOR-type storage device according to claim 9, wherein, The first contact portion to the fifth contact portion are formed as strips that extend substantially parallel to each other.

11. The NOR-type memory device according to claim 9, further comprising: The highly doped region in the first channel layer that contacts the fourth contact portion has a higher doping concentration than at least a portion of the rest of the first channel layer; as well as The highly doped region in the second channel layer that contacts the fifth contact portion has a higher doping concentration than at least a portion of the rest of the second channel layer.

12. The NOR-type storage device according to claim 8, wherein, The second contact portion of the second source / drain layer in each of the device layers is also electrically connected to the first channel layer and the second channel layer in the corresponding device layer.

13. The NOR-type storage device according to claim 12, wherein, The ends of the second source / drain layer are substantially aligned with the ends of the second channel layer, while the ends of the first channel layer protrude relatively. or The end of the first channel layer protrudes relative to the end of the second source / drain layer, and the end of the second source / drain layer protrudes relative to the end of the second channel layer.

14. The NOR-type storage device according to claim 8 or 9, wherein, The substrate includes a device region and a contact region adjacent to the device region, the memory cell is formed on the device region, and the contact portion is formed on the contact region.

15. The NOR-type storage device according to claim 14, wherein, The first source / drain layer, the first channel layer, the second source / drain layer, the second channel layer, and the third source / drain layer in each of the device layers form a stepped structure in the contact area.

16. The NOR-type storage device according to claim 15, wherein, The stepped structure includes steps with horizontal and vertical surfaces, and the NOR-type storage device further includes: The silicide on the transverse surface of the step; and Dielectric sidewalls on the vertical surface of the step.

17. The NOR-type memory device according to claim 1, further comprising: Word lines; as well as The sixth contact of the gate conductor layer is electrically connected to the word line.

18. A method for manufacturing a NOR-type memory device, comprising: Multiple device layers are disposed on a substrate, each device layer comprising a stack of a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer and a third source / drain layer, and a sacrificial layer is disposed between adjacent device layers; Forming processing channels that extend vertically relative to the substrate to pass through the stack in each of the device layers; The sacrificial layer is replaced with an isolation layer via the processing channel; A gate stack is formed in the processing channel. The gate stack includes a gate conductor layer and a storage function layer disposed between the gate conductor layer and the stack. A storage cell is defined at the intersection of the gate stack and the stack. The first source / drain layer and the third source / drain layer in each of the device layers are electrically connected to different bit lines, and the second source / drain layer is electrically connected to the source line.

19. The method according to claim 18, wherein, The stack is formed by epitaxial growth.

20. The method according to claim 19, wherein, Each layer in the stack is doped in situ during epitaxial growth.

21. The method according to claim 18, wherein, Replacing the sacrificial layer with an isolation layer includes: A support layer is formed in a portion of the processing channels, while the sacrificial layer is exposed in the remaining processing channels; The sacrificial layer is replaced with the isolation layer via the remaining processing channels; and Remove the support layer.

22. The method according to claim 18, wherein, The processing channel is a hole passing through each of the device layers, and the formation of the gate stack includes: The storage functional layer is formed on the bottom surface and sidewalls of the processing channel in a substantially conformal manner; and The gate conductor layer is filled in the processing channel in which the storage function layer is formed.

23. The method according to claim 18, wherein, Multiple processing channels are formed and arranged in an array.

24. The method according to claim 18, wherein, The substrate includes a device region and a contact region adjacent to the device region, and the memory cell is formed on the device region. The method further includes: A first contact portion to the first source / drain layer, a second contact portion to the second source / drain layer, and a third contact portion to the third source / drain layer are formed on the contact area.

25. The method of claim 24, further comprising: A fourth contact portion to the first channel layer and a fifth contact portion to the second channel layer are formed on the contact area.

26. The method of claim 25, wherein, The first contact portion to the fifth contact portion are formed into strips that extend substantially parallel to each other.

27. The method of claim 25, further comprising: A highly doped region with a higher doping concentration than at least a portion of the rest of the first channel layer is formed at the point where the first channel layer contacts the fourth contact portion. as well as A highly doped region with a higher doping concentration than at least a portion of the rest of the second channel layer is formed at the point where the second channel layer contacts the fifth contact portion.

28. The method according to claim 24, wherein, The second contact portion is also formed to be electrically connected to the first channel layer and the second channel layer.

29. The method of claim 24, further comprising: The first source / drain layer, the first channel layer, the second source / drain layer, the second channel layer, and the third source / drain layer in each of the device layers are patterned into a stepped structure in the contact area.

30. The method according to claim 29, wherein, The stepped structure includes steps having a transverse surface and a vertical surface, and the method further includes: A dielectric sidewall is formed on the vertical surface of the step; and The transverse surface of the step is subjected to siliconization treatment.

31. An electronic device comprising a NOR-type memory device as claimed in any one of claims 1 to 17.

32. The electronic device according to claim 31, wherein, The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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