Semiconductor memory element
CN116234316BActive Publication Date: 2026-06-05UNITED MICROELECTRONICS CORP
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2021-12-01
- Publication Date
- 2026-06-05
AI Technical Summary
Technical Problem
When the source line contact is set on the strip cell between two adjacent control gate lines in the existing ESF3 memory cell, it is easy to cause a short circuit between the erase gate line and the source line.
Method used
A semiconductor memory element is designed with an asymmetric active region layout structure, including longer and shorter active regions, and source line contacts are set on the strip cell to avoid creating discontinuities on the erase gate line. A thick second gate dielectric layer is used to isolate the erase gate line and the source line.
Benefits of technology
This effectively avoids the problem of short circuits in the gate and source lines, improving the reliability and stability of the components.
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Smart Images
Figure CN116234316B_ABST
Abstract
A semiconductor memory device includes a substrate, a plurality of memory cells arranged in a first direction and at least one strip cell between the plurality of memory cells, a plurality of bit line contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the at least one strip cell, wherein the at least one source line contact and the plurality of bit line contacts are aligned in the first direction.
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