Interface-enhanced organic inverse bipolar transistor devices and their fabrication methods
By introducing a single-layer N-type semiconductor interface induction layer and encapsulation layer into the organic inverse bipolar transistor device, combined with inverse bipolar heterojunction technology, the problems of poor device performance and stability were solved, and transistor performance with high stability and multi-level logic was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGZHOU UNIV
- Filing Date
- 2023-03-22
- Publication Date
- 2026-07-17
AI Technical Summary
Existing organic inverse bipolar transistor devices suffer from poor device performance and stability, making it difficult to meet the high performance and power consumption requirements of integrated circuits.
By employing interface enhancement technology, a single-layer N-type semiconductor interface induction layer and encapsulation layer are introduced into the transistor unit, combined with anti-bipolar heterojunction technology, to optimize the device structure and improve charge transport capability and stability.
It achieves high stability and multi-level logic (0, 1/2, 1) transistor performance, reduces power consumption, and improves the device's air, water, and oxygen stability.
Smart Images
Figure CN116234325B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of transistor device technology, and in particular to an interface-enhanced organic inverse bipolar transistor device and its fabrication method. Background Technology
[0002] In recent years, with the rapid development of big data and artificial intelligence, higher requirements have been placed on the performance and power consumption of integrated circuits. Constrained by Moore's Law, advanced processes for silicon-based integrated circuits are approaching their limits. Novel organic inverse bipolar transistors (IBTS) can break through the traditional 1-bit logic (0, 1) to achieve multi-level logic, thus significantly improving logic density and reducing power consumption, driving the development of next-generation integrated circuit technologies. However, IBTTS suffers from poor device performance and instability, which urgently need to be addressed.
[0003] The information disclosed in this background section is intended only to enhance the understanding of the general background of this disclosure and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide an interface-enhanced organic anti-bipolar transistor device and its fabrication method, so as to solve the problems mentioned in the background art.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is: an interface-enhanced organic inverse bipolar transistor device, comprising a substrate and a plurality of transistor units located on the substrate, wherein the transistor units include:
[0006] A gate electrode is located on the substrate, and there is a gap between adjacent gate electrodes;
[0007] A gate dielectric layer that covers all the gate electrodes and covers the top surface of the substrate exposed between the gate electrodes;
[0008] A single-layer N-type semiconductor interface induction layer is located on the gate dielectric layer and its vertical projection covers a portion of the gate electrode;
[0009] An N-type organic semiconductor layer is located on the monolayer N-type semiconductor interface induction layer;
[0010] A P-type organic semiconductor layer includes a bottom section and a top section. The bottom section is located on the gate dielectric layer and its vertical projection covers the remaining portion of the gate electrode. The top section covers a portion of the N-type organic semiconductor layer and extends downward near the end of the bottom section and is connected to the bottom section.
[0011] The device comprises a source, a drain, and an output electrode, wherein the source is located on the N-type organic semiconductor layer, and the drain and the output electrode are disposed on the P-type organic semiconductor layer at intervals.
[0012] An encapsulation layer covers the gate dielectric layer, the N-type organic semiconductor layer, the P-type organic semiconductor layer, the source electrode, the drain electrode, and the output electrode.
[0013] Another type of organic inverse bipolar transistor device based on interface enhancement includes a substrate and a plurality of transistor units located on the substrate, the transistor units comprising:
[0014] A single-layer N-type semiconductor interface induction layer is located on the substrate;
[0015] An N-type organic semiconductor layer is located on the monolayer N-type semiconductor interface induction layer;
[0016] A P-type organic semiconductor layer includes a bottom section and a top section, the bottom section being located on the substrate, and the top section covering a portion of the N-type organic semiconductor layer and extending downward near the end of the bottom section and connecting to the bottom section;
[0017] The device comprises a source, a drain, and an output electrode, wherein the source is located on the N-type organic semiconductor layer, and the drain and the output electrode are disposed on the P-type organic semiconductor layer at intervals.
[0018] An encapsulation layer covers the substrate, the N-type organic semiconductor layer, the P-type organic semiconductor layer, the source electrode, the drain electrode, and the output electrode;
[0019] The gate electrode is located on the packaging layer, and its vertical projection covers the N-type organic semiconductor layer and the P-type organic semiconductor layer.
[0020] Furthermore, the gate electrodes are arranged in a matrix on the substrate.
[0021] Furthermore, the drain electrode is located on the bottom section, and the output electrode is located on the top section.
[0022] Furthermore, both the drain electrode and the output electrode are located on the bottom section.
[0023] Furthermore, the material of the gate electrode is one or more of ITO, Au, Al, Cu, Mo, Cr, Ti, W, Ag and Ta.
[0024] Furthermore, the material of the gate dielectric layer is one or more of SiO2, HfO2, SiN, Ta2O5, Al2O3, TiO2, ZrO2, PM, PVP, PMMA, PS, PVA and SAM.
[0025] Further, the material of the monolayer N-type semiconductor interface inducing layer is 7,7,8,8-tetracyanoquinone dimethane, tetracyanoquinoline dimethane, dianhydride and diimide of naphthalenetetracarboxylic acid, trithiophene, ComPouNd 6-dicyanomethylene, isomethyl [6,6]-phenyl-C61-butyrate, N,N'-diphenyl-3,4,9,10-perylenetetracarboxylic diimide, N,N'-di(3-fluorophenyl)-3,4,9,10-perylenetetracarboxylic diimide, C60, 3,4,9,10-perylenetetracarboxylic dianhydride, N,N'-diphenyl-3,4,9,10-perylenetetracarboxylic diamine, tetracyanodimethylquinone, 1,4 One or more of the following: 5,8-naphthalenetetracarboxylic acid dianhydride, 1,4,5,8-naphthalenetetracarboxylic acid diamine, 11,11,12,12-tetracyanodimethylnaphthoquinone, tetramethyltetraselenofulvalene, naphthimide, trifluoromethyltriphenyldioxazine compound 5, naphthimide, peryleneimide, PTCDIF-CN2, DFPCO4T, perfluorophthalocyanine copper, diindolepyrazinedione 4, and trifluoromethyltriphenyldioxazine compound 5.
[0026] Furthermore, the N-type organic semiconductor layer is composed of N-type organic semiconductor material.
[0027] Furthermore, the P-type organic semiconductor layer is composed of P-type organic semiconductor material.
[0028] Furthermore, the source electrode, the drain electrode, and the output electrode are made of the same or different materials, all derived from one or more of ITO, Au, Ag, Mo, Al, Cu, Cr, Ti, Mg, or Ca.
[0029] This invention also discloses a method for fabricating an organic anti-bipolar transistor device based on interface enhancement, comprising the following steps:
[0030] S1: Using photolithography or mask technology, 50-100 gate electrodes are grown on the substrate by thermal evaporation or electron beam evaporation;
[0031] S2: Deposit the gate dielectric layer using the ALD method;
[0032] S3: A single-layer N-type semiconductor interface-induced layer was prepared using spin coating and thermal annealing.
[0033] S4: N-type small molecule organic thin films were prepared on a monolayer N-type semiconductor interface-induced layer as N-type organic semiconductor layers using a mask and thermal evaporation process.
[0034] S5: Prepare P-type organic small molecule thin films as P-type organic semiconductor layers using thermal evaporation process;
[0035] S6: The source, drain, and output electrodes are fabricated using thermal evaporation and masking processes;
[0036] S7: Prepare the encapsulation layer.
[0037] In addition, the present invention also discloses a method for fabricating an organic anti-bipolar transistor device based on interface enhancement, comprising the following steps:
[0038] S1: A single-layer N-type semiconductor interface-induced layer was prepared using spin coating and thermal annealing.
[0039] S2: N-type small molecule organic thin films were prepared on a monolayer N-type semiconductor interface-induced layer as N-type organic semiconductor layers using a mask and thermal evaporation process.
[0040] S3: Prepare P-type organic small molecule thin films as P-type organic semiconductor layers using thermal evaporation process;
[0041] S4: The source, drain, and output electrodes are fabricated using thermal evaporation and masking processes;
[0042] S5: Prepare the encapsulation layer;
[0043] S6: Using photolithography or mask technology, 50-100 gate electrodes are grown on the substrate by thermal evaporation or electron beam evaporation.
[0044] The beneficial effects of this invention are as follows: by setting a single-layer N-type semiconductor interface induction layer, the charge transport capability of the device is significantly enhanced, which can effectively improve the performance of organic inverse bipolar transistors. This invention combines interface enhancement technology with inverse bipolar heterojunction technology to achieve multi-level logic (0, 1 / 2, 1) and three-level logic inverter design with high stability characteristics. In this scheme, the encapsulation layer is also used to improve the air, water and oxygen stability of the device, thereby obtaining a stable and optimized transistor. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 This is a schematic diagram of the organic anti-bipolar transistor device based on interface enhancement in Embodiment 1 of the present invention;
[0047] Figure 2 This is a top view of the interface-enhanced organic anti-bipolar transistor device (encapsulation layer omitted) in Embodiment 1 of the present invention;
[0048] Figure 3 This is a diagram illustrating step S1 in Embodiment 1 of the present invention;
[0049] Figure 4 This is a diagram illustrating step S2 in Embodiment 1 of the present invention;
[0050] Figure 5 This is a diagram illustrating step S3 in Embodiment 1 of the present invention;
[0051] Figure 6 This is a diagram illustrating step S4 in Embodiment 1 of the present invention;
[0052] Figure 7 This is a diagram illustrating step S5 in Embodiment 1 of the present invention;
[0053] Figure 8 This is a diagram illustrating step S6 in Embodiment 1 of the present invention;
[0054] Figure 9 This is a diagram illustrating step S7 in Embodiment 1 of the present invention;
[0055] Figure 10 The output characteristic curve of the organic inverse bipolar transistor in Embodiment 1 of the present invention;
[0056] Figure 11 This is a graph showing the output voltage of the inverter constructed from an organic inverse bipolar transistor in Embodiment 1 of the present invention as a function of the input voltage.
[0057] Figure 12 This is a schematic diagram of the organic anti-bipolar transistor in Embodiment 2 of the present invention;
[0058] Figure 13 This is a schematic diagram of the organic anti-bipolar transistor in Embodiment 3 of the present invention;
[0059] Figure 14 This is a schematic diagram of the transistor structure in Comparative Example 1 of the present invention;
[0060] Figure 15 This is a graph showing the output characteristic of the transistor in Comparative Example 1 of the present invention;
[0061] Figure 16 The diagram shows the variation of the maximum drain-source current of the transistors in Embodiment 1 and Comparative Example 2 over time.
[0062] Figure reference numerals: 1. SiO2 / Si substrate; 2. Gate electrode; 3. Gate dielectric layer; 4. Monolayer N-type semiconductor interface induction layer; 5. N-type organic semiconductor layer; 6. P-type organic semiconductor layer; 7a. Source electrode; 7b. Drain electrode; 7c. Output electrode; 8. Encapsulation layer. Detailed Implementation
[0063] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0064] Unless otherwise specified, all materials used in the following embodiments are commercially available, and the electrical performance tests of the prepared transistors are conducted using conventional testing methods in the art.
[0065] Example 1
[0066] like Figure 1 and 2 The interface-enhanced organic inverse bipolar transistor device shown includes a SiO2 / Si substrate 1, a gate electrode 2, a gate dielectric layer 3, a monolayer N-type semiconductor interface-induced layer 4, an N-type organic semiconductor layer 5, a P-type organic semiconductor layer 6, a source electrode 7a, a drain electrode 7b, an output electrode 7c, and a packaging layer 8. Its fabrication method includes the following steps:
[0067] S1: As Figure 3 As shown, using photolithography or mask technology, a 50nm-100nm Au electrode is grown on a SiO2 / Si substrate 1 by thermal evaporation or electron beam evaporation, which serves as the gate electrode 2;
[0068] S2: As Figure 4 As shown, a 20nm HfO2 layer was deposited by ALD as the gate dielectric layer 3;
[0069] S3: As Figure 5 As shown, the substrate is hydrophobically treated using a surface pretreatment process. Then, hydrophilic patterning is performed using UV-ozone technology through a mask. Next, an N-type semiconductor solution is dropped onto the substrate using a spin-coating process, followed by a DMF solution. The spin-coating is performed at a speed of 2000–3000 RPM for 30–60 seconds to obtain an array-patterned monolayer N-type semiconductor interface-inducing layer 4. Finally, the grown monolayer N-type semiconductor interface-inducing layer 4 is subjected to thermal annealing at a temperature of 100–120°C for 5–15 minutes.
[0070] S4: As Figure 6 As shown, an N-type small molecule organic film of 20-30 nm was grown on a single-layer N-type semiconductor interface-induced layer 4 by thermal evaporation using a mask. Then, the N-type small molecule organic film was subjected to high-temperature annealing treatment at a temperature of 100-120 °C for 5-15 min to obtain the N-type organic semiconductor layer 5.
[0071] S5: As Figure 7As shown, a P-type organic small molecule thin film with a thickness of 20-50 nm was grown using a photomask and a thermal evaporation method, serving as the P-type organic semiconductor layer 6.
[0072] S6: As Figure 8 As shown, on the N-type organic semiconductor layer 5, a 50-100 nm metal electrode is grown as the source electrode 7a by thermal evaporation and a mask. Using the same technique, a 50-100 nm metal electrode is grown on the top section as the output electrode 7c, which serves as the voltage output terminal of the inverter. A 50-100 nm metal electrode is grown on the bottom section as the drain electrode 7b.
[0073] S7: As Figure 9 As shown, the encapsulation layer 8 was prepared, and the prepared transistor device was tested and optimized.
[0074] Example 2
[0075] like Figure 12 The interface-enhanced organic inverse bipolar transistor device shown includes a SiO2 / Si substrate 1, a gate electrode 2, a monolayer N-type semiconductor interface-induced layer 4, an N-type organic semiconductor layer 5, a P-type organic semiconductor layer 6, a source electrode 7a, a drain electrode 7b, an output electrode 7c, and a packaging layer 8. The gate electrode 2 is located on the upper surface of the packaging layer 8, and its fabrication method includes the following steps:
[0076] S1: The substrate is hydrophobically treated using a surface pretreatment process. Then, hydrophilic patterning is performed using UV-ozone technology through a mask. Next, an N-type semiconductor solution is dropped onto the substrate using a spin-coating process, followed by a DMF solution. The spin-coating is performed at a speed of 2000–3000 RPM for 30–60 seconds to obtain an array-patterned monolayer N-type semiconductor interface induction layer 4. Finally, the grown monolayer N-type semiconductor interface induction layer 4 is subjected to thermal annealing at a temperature of 100–120°C for 5–15 minutes.
[0077] S2: Using a mask, a 20-30 nm N-type small molecule organic film is grown on a single-layer N-type semiconductor interface induction layer 4 by thermal evaporation. Then, the N-type small molecule organic film is subjected to high-temperature annealing treatment at a temperature of 100-120℃ for 5-15 min to obtain the N-type organic semiconductor layer 5.
[0078] S3: Using a photomask and a thermal evaporation method, a P-type organic small molecule thin film with a thickness of 20-50 nm is grown, which serves as the P-type organic semiconductor layer 6.
[0079] S4: On the N-type organic semiconductor layer 5, a 50-100 nm metal electrode is grown as the source electrode 7a by thermal evaporation and a mask. Using the same technique, a 50-100 nm metal electrode is grown on the top section as the output electrode 7c. The output electrode 7c serves as the voltage output terminal of the inverter. A 50-100 nm metal electrode is grown on the bottom section as the drain electrode 7b.
[0080] S5: Prepare encapsulation layer 8;
[0081] S6: Using photolithography or mask technology, grow a 50nm-100nm Au electrode on the packaging layer 8 by thermal evaporation or electron beam evaporation as the gate electrode 2.
[0082] Example 3
[0083] like Figure 13 The interface-enhanced organic inverse bipolar transistor device shown includes a SiO2 / Si substrate 1, a gate electrode 2, a gate dielectric layer 3, a monolayer N-type semiconductor interface-induced layer 4, an N-type organic semiconductor layer 5, a P-type organic semiconductor layer 6, a source electrode 7a, a drain electrode 7b, an output electrode 7c, and a packaging layer 8. Its fabrication method includes the following steps:
[0084] S1: Using photolithography or mask technology, grow a 50nm-100nm Au electrode on SiO2 / Si substrate 1 by thermal evaporation or electron beam evaporation, as the gate electrode 2;
[0085] S2: A 20nm HfO2 layer is deposited by ALD as the gate dielectric layer 3;
[0086] S3: Using a surface pretreatment process, the substrate is treated to be hydrophobic. Then, using UV-ozone technology, hydrophilic patterning is performed through a mask. Next, using a spin-coating process, an N-type semiconductor solution is first dropped onto the substrate, followed by a DMF solution. Spin-coating is performed at a speed of 2000-3000 RPM for 30-60 seconds to obtain an array-patterned monolayer N-type semiconductor interface induction layer 4. Finally, the grown monolayer N-type semiconductor interface induction layer 4 is subjected to thermal annealing at a temperature of 100-120℃ for 5-15 minutes.
[0087] S4: Using a mask, a 20-30 nm N-type small molecule organic film is grown on a single-layer N-type semiconductor interface induction layer 4 by thermal evaporation. Then, the N-type small molecule organic film is subjected to high-temperature annealing treatment at a temperature of 100-120℃ for 5-15 min to obtain the N-type organic semiconductor layer 5.
[0088] S5: Using a mask, a P-type organic small molecule thin film is grown by thermal evaporation. The thickness of the film is 20-50 nm, which serves as the P-type organic semiconductor layer 6.
[0089] S6: On the N-type organic semiconductor layer 5, a 50-100 nm metal electrode is grown as the source electrode 7a by thermal evaporation and a mask. Using the same technique, two 50-100 nm metal electrodes are grown at intervals in the bottom section, with the one closer to the source electrode 7a serving as the output electrode 7c and the other serving as the drain electrode 7b.
[0090] S7: Prepare the packaging layer 8, and test and optimize the prepared transistor device.
[0091] Comparative Example 1
[0092] like Figure 14 The transistor device shown includes a SiO2 / Si substrate 1, a gate electrode 2, a gate dielectric layer 3, an N-type organic semiconductor layer 5, a P-type organic semiconductor layer 6, a source electrode 7a, a drain electrode 7b, an output electrode 7c, and a packaging layer 8. Its fabrication method includes the following steps:
[0093] S1: Using photolithography or mask technology, grow a 50nm-100nm Au electrode on SiO2 / Si substrate 1 by thermal evaporation or electron beam evaporation, as the gate electrode 2;
[0094] S2: A 20nm HfO2 layer is deposited by ALD as the gate dielectric layer 3;
[0095] S3: Using a mask, a 20-30 nm N-type small molecule organic thin film is grown on the gate dielectric layer 3 by thermal evaporation. Then, the N-type small molecule organic thin film is subjected to high-temperature annealing treatment at a temperature of 100-120℃ for 5-15 min to obtain the N-type organic semiconductor layer 5.
[0096] S4: Using a photomask and a thermal evaporation method, a P-type organic small molecule thin film with a thickness of 20-50 nm is grown, which serves as the P-type organic semiconductor layer 6.
[0097] S5: On the N-type organic semiconductor layer 5, a 50-100 nm metal electrode is grown as the source electrode 7a by thermal evaporation and a mask. Using the same technique, a 50-100 nm metal electrode is grown on the top section as the output electrode 7c. The output electrode 7c serves as the voltage output terminal of the inverter. A 50-100 nm metal electrode is grown on the bottom section as the drain electrode 7b.
[0098] S6: Prepare the packaging layer 8, and test and optimize the prepared transistor device.
[0099] Comparative Example 2
[0100] The structure of this comparative example can be referred to Figure 8 As shown, the transistor device includes a SiO2 / Si substrate 1, a gate electrode 2, a gate dielectric layer 3, a monolayer N-type semiconductor interface induction layer 4, an N-type organic semiconductor layer 5, a P-type organic semiconductor layer 6, a source electrode 7a, a drain electrode 7b, an output electrode 7c, and a packaging layer 8. Its fabrication method includes the following steps:
[0101] S1: Using photolithography or mask technology, grow a 50nm-100nm Au electrode on SiO2 / Si substrate 1 by thermal evaporation or electron beam evaporation, as the gate electrode 2;
[0102] S2: A 20nm HfO2 layer is deposited by ALD as the gate dielectric layer 3;
[0103] S3: Using a surface pretreatment process, the substrate is treated to be hydrophobic. Then, using UV-ozone technology, hydrophilic patterning is performed through a mask. Next, using a spin-coating process, an N-type semiconductor solution is first dropped onto the substrate, followed by a DMF solution. Spin-coating is performed at a speed of 2000-3000 RPM for 30-60 seconds to obtain an array-patterned monolayer N-type semiconductor interface induction layer 4. Finally, the grown monolayer N-type semiconductor interface induction layer 4 is subjected to thermal annealing at a temperature of 100-120℃ for 5-15 minutes.
[0104] S4: Using a mask, a 20-30 nm N-type small molecule organic film is grown on a single-layer N-type semiconductor interface induction layer 4 by thermal evaporation. Then, the N-type small molecule organic film is subjected to high-temperature annealing treatment at a temperature of 100-120℃ for 5-15 min to obtain the N-type organic semiconductor layer 5.
[0105] S5: Using a mask, a P-type organic small molecule thin film is grown by thermal evaporation. The thickness of the film is 20-50 nm, which serves as the P-type organic semiconductor layer 6.
[0106] S6: On the N-type organic semiconductor layer 5, a 50-100 nm metal electrode is grown as the source electrode 7a by thermal evaporation and a mask. Using the same technique, a 50-100 nm metal electrode is grown on the top section as the output electrode 7c. The output electrode 7c serves as the voltage output terminal of the inverter. A 50-100 nm metal electrode is grown on the bottom section as the drain electrode 7b.
[0107] S7: Perform performance testing on the obtained transistor device.
[0108] Results and Discussion
[0109] The working mechanism of an inverse bipolar transistor (IRB) is based on the formation of a partially overlapping pn heterojunction in the transistor channel, which controls the device current. Under a certain range of gate bias voltage, the pn heterojunction is modulated by the gate voltage, resulting in a sharp increase and decrease in leakage current. When an output electrode is added to the device channel, the organic IRB behaves as an inverter. This design combines interface enhancement technology with IR heterojunction technology to achieve multi-level logic with high stability. Figure 11 As shown, the inverter exhibits three levels of logic: 0, 1 / 2, and 1.
[0110] By comparing Example 2 and Example 1, it can be seen that Example 2 places the gate electrode 2 on the packaging layer 8. In this way, the gate dielectric layer 3 can be omitted, and the gate electrode 2 is located on the top, which can also simplify the process flow and improve the reliability and stability of the device.
[0111] By comparing Example 3 and Example 1, it can be seen that Example 3 changes the output electrode 7c from above the PN junction to above the P-type semiconductor. On the one hand, this can reduce the thickness of the packaging layer 8 and save costs. On the other hand, it can change the voltage value of the output voltage, so that the multi-stage inverted output electrical behavior of the transistor can be more effectively controlled.
[0112] By comparing Comparative Example 1 and Example 1, it can be seen that the transistor prepared in Comparative Example 1 does not have a single-layer N-type semiconductor interface inducing layer 4. The transfer characteristic curves of the prepared transistor and the transistor in Example 1 are compared with those of Example 1. Figure 10 and Figure 15 The absence of a single-layer N-type semiconductor interface induction layer 4 in the transistor leads to crystallinity cross-linking in the N-type organic semiconductor layer 5, resulting in increased source-drain current (I0). DS Although it can change with the gate voltage (V) G The current changes with the change of N-type semiconductor, but the current is relatively small. However, the presence of a single-layer N-type semiconductor interface induction layer 4 improves the crystal quality of the N-type semiconductor, which significantly enhances the charge transport capability of the device and thus improves the device performance.
[0113] like Figure 16 As shown, by comparing Comparative Example 2 and Example 1, it can be seen that the source-drain current (IDS) of the transistor without encapsulation layer 8 decreases rapidly over time, and the device degrades rapidly, exhibiting air instability. In contrast, the source-drain current of the transistor in the device encapsulated with encapsulation layer 8 remains basically unchanged over time, exhibiting excellent air stability.
[0114] Those skilled in the art should understand that this invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to this invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.
Claims
1. An interface-enhanced organic inverse bipolar transistor device, comprising a substrate and a plurality of transistor units located on the substrate, characterized in that, The transistor unit includes: A gate electrode is located on the substrate, and there is a gap between adjacent gate electrodes; A gate dielectric layer that covers all the gate electrodes and covers the top surface of the substrate exposed between the gate electrodes; A single-layer N-type semiconductor interface induction layer is located on the gate dielectric layer and its vertical projection covers a portion of the gate electrode; An N-type organic semiconductor layer is located on the monolayer N-type semiconductor interface induction layer; A P-type organic semiconductor layer includes a bottom section and a top section. The bottom section is located on the gate dielectric layer and its vertical projection covers the remaining portion of the gate electrode. The top section covers a portion of the N-type organic semiconductor layer and extends downward near the end of the bottom section and is connected to the bottom section. The device comprises a source, a drain, and an output electrode, wherein the source is located on the N-type organic semiconductor layer, and the drain and the output electrode are disposed on the P-type organic semiconductor layer at intervals. An encapsulation layer covers the gate dielectric layer, the N-type organic semiconductor layer, the P-type organic semiconductor layer, the source electrode, the drain electrode, and the output electrode.
2. An interface-enhanced organic inverse bipolar transistor device, comprising a substrate and a plurality of transistor units located on the substrate, characterized in that, The transistor unit includes: A single-layer N-type semiconductor interface induction layer is located on the substrate; An N-type organic semiconductor layer is located on the monolayer N-type semiconductor interface induction layer; A P-type organic semiconductor layer includes a bottom section and a top section. The bottom section is located on the substrate, and the top section covers a portion of the N-type organic semiconductor layer and extends downward near the end of the bottom section and is connected to the bottom section. The device comprises a source, a drain, and an output electrode, wherein the source is located on the N-type organic semiconductor layer, and the drain and the output electrode are disposed on the P-type organic semiconductor layer at intervals. An encapsulation layer covers the substrate, the N-type organic semiconductor layer, the P-type organic semiconductor layer, the source electrode, the drain electrode, and the output electrode; The gate electrode is located on the packaging layer, and its vertical projection covers the N-type organic semiconductor layer and the P-type organic semiconductor layer.
3. The interface-enhanced organic anti-bipolar transistor device according to claim 1 or 2, characterized in that, The gate electrodes are arranged in a matrix on the substrate.
4. The interface-enhanced organic anti-bipolar transistor device according to claim 3, characterized in that, The drain electrode is located on the bottom section, and the output electrode is located on the top section.
5. The interface-enhanced organic anti-bipolar transistor device according to claim 3, characterized in that, Both the drain electrode and the output electrode are located on the bottom section.
6. The interface-enhanced organic anti-bipolar transistor device according to claim 3, characterized in that, The gate electrode is made of one or more of ITO, Au, Al, Cu, Mo, Cr, Ti, W, Ag, and Ta.
7. The interface-enhanced organic anti-bipolar transistor device according to claim 3, characterized in that, The material of the gate dielectric layer is one or more of SiO2, HfO2, SiN, Ta2O5, Al2O3, TiO2, ZrO2, PM, PVP, PMMA, PS, PVA and SAM.
8. The interface-enhanced organic anti-bipolar transistor device according to claim 3, characterized in that, The material of the monolayer N-type semiconductor interface inducing layer is 7,7,8,8-tetracyanoquinone dimethyl ether, tetracyanoquinoline dimethyl ether, naphthalenetetracarboxylic acid dianhydride and diimide, trithiophene, ComPouNd 6-dicyanomethylene, [6,6]-phenyl-C61-butyrate isomethyl ester, N,N'-diphenyl-3,4,9,10-perylenetetracarboxylic acid diimide, N,N'-bis(3-fluorophenyl)-3,4,9,10-perylenetetracarboxylic acid diimide, C60, 3,4,9,10-perylenetetracarboxylic acid dianhydride, N,N'-diphenyl-3,4,9,10-perylenetetracarboxylic acid diamine, One or more of the following: tetracyanodimethylquinone, 1,4,5,8-naphthalenetetracarboxylic acid dianhydride, 1,4,5,8-naphthalenetetracarboxylic acid diamine, 11,11,12,12-tetracyanodimethylnaphthoquinone, tetramethyltetraselenofulvalene, naphthimide, trifluoromethyltriphenyldioxazine compound, peryleneimide, PTCDIF-CN2, DFPCO4T, perfluorocopper phthalocyanine, and diindolepyrazinedione.
9. The method for fabricating an organic anti-bipolar transistor device based on interface enhancement as described in claim 1, characterized in that, Includes the following steps: S1: Using photolithography or mask technology, a 50-100nm gate electrode is grown on the substrate by thermal evaporation or electron beam evaporation; S2: Deposit the gate dielectric layer using the ALD method; S3: A single-layer N-type semiconductor interface-induced layer was prepared using spin coating and thermal annealing. S4: N-type small molecule organic thin films were prepared on a monolayer N-type semiconductor interface-induced layer as N-type organic semiconductor layers using a mask and thermal evaporation process. S5: Prepare P-type organic small molecule thin films as P-type organic semiconductor layers using thermal evaporation process; S6: The source, drain, and output electrodes are fabricated using thermal evaporation and masking processes; S7: Prepare the encapsulation layer.
10. The method for fabricating an organic anti-bipolar transistor device based on interface enhancement as described in claim 2, characterized in that, Includes the following steps: S1: A single-layer N-type semiconductor interface-induced layer was prepared using spin coating and thermal annealing. S2: N-type small molecule organic thin films were prepared on a monolayer N-type semiconductor interface-induced layer as N-type organic semiconductor layers using a mask and thermal evaporation process. S3: Prepare P-type organic small molecule thin films as P-type organic semiconductor layers using thermal evaporation process; S4: The source, drain, and output electrodes are fabricated using thermal evaporation and masking processes; S5: Prepare the encapsulation layer; S6: Using photolithography or mask technology, 50-100nm gate electrodes are grown on the substrate by thermal evaporation or electron beam evaporation.