Junction isolated semiconductor strain gauge

Abstract

Apparatuses including junction-isolated semiconductor strain gauges and methods for manufacturing junction-isolated semiconductor strain gauges are disclosed. In a particular embodiment, an apparatus includes a silicon chip including a silicon substrate and a semiconductor strain gauge. In this embodiment, the semiconductor strain gauge includes a plurality of resistors formed by locally doping the silicon substrate and biasing the silicon substrate such that a resistor of the plurality of resistors is junction-isolated. The silicon chip also includes a field shielding layer that isolates an output signal of the semiconductor strain gauge from an external electric field.

Description

Technical Field Background Technology

[0001] Semiconductor strain gauges are widely used in various industries. For example, in the automotive industry, semiconductor strain gauges are used in pressure sensors, with applications ranging from brake, transmission, and fuel pressure sensors to passenger gravity sensing. These pressure sensors typically consist of a silicon strain gauge element with glass bonded to a diaphragm. Wheatstone bridges or other strain gauge configurations are sometimes used to generate a linear voltage output that is proportional to the pressure applied to the diaphragm. The manufacturing cost and ease of use of these pressure sensors can depend in part on the manufacturing method of the semiconductor strain gauge and the configuration of its components. Summary of the Invention

[0002] An apparatus including a junction-isolated semiconductor strain gauge and a method for manufacturing the junction-isolated semiconductor strain gauge are disclosed. In a particular embodiment, the apparatus includes a silicon chip comprising a silicon substrate and a semiconductor strain gauge. In this embodiment, the semiconductor strain gauge includes a plurality of resistors formed by locally doping and biasing the silicon substrate, such that the resistors among the plurality of resistors are junction-isolated. The silicon chip also includes a field shielding layer that isolates the output signal of the semiconductor strain gauge from an external electric field. As will be explained below, forming the resistors by locally doping the silicon substrate has many advantages over prior art designs. One of these is that a standard silicon wafer can be used as the substrate, rather than the more expensive custom substrate typically required to manufacture semiconductor strain gauges in prior art designs. Furthermore, applying a field shielding layer can have the advantages of isolating the resistors and improving the performance of the semiconductor strain gauge.

[0003] In another embodiment, an apparatus is disclosed comprising a silicon chip having a silicon substrate and a junction-isolated semiconductor strain gauge. In this embodiment, the semiconductor strain gauge has a plurality of junction-isolated resistors. The plurality of resistors includes a first resistor electrically connected between a first bonding pad and a second bonding pad. The plurality of resistors also includes a second resistor electrically connected between a second bonding pad and a third bonding pad. In this example embodiment, the plurality of resistors includes a third resistor electrically connected between a third bonding pad and a fourth bonding pad. In this embodiment, the plurality of resistors includes a fourth resistor electrically connected between a fourth bonding pad and a first bonding pad. As will be explained below, the semiconductor strain gauge in this embodiment allows for a more minimized design. Minimizing the design of the semiconductor strain gauge can improve mechanical performance, reduce the negative impact of thermal gradients, and reduce the required package size. Furthermore, the minimized design can also allow for easier increases in the resistance of the semiconductor strain gauge, which can be advantageous for low-power applications.

[0004] The foregoing and other objects, features, and advantages of the invention will become apparent from the following more specific description of exemplary embodiments of the invention as illustrated in the accompanying drawings, wherein like reference numerals generally denote like parts of exemplary embodiments of the invention. Attached Figure Description

[0005] Figure 1A An isometric view of an apparatus including a junction-isolated semiconductor strain gauge according to at least one embodiment of the present invention is shown;

[0006] Figure 1B It shows Figure 1A A more detailed view of the device;

[0007] Figure 1C It shows Figure 1A Another view of a part of the device;

[0008] Figure 2 A graph illustrating the location of the junction-isolated semiconductor strain gauge of FIG1 on the film is shown, according to at least one embodiment of the present invention; and

[0009] Figure 3 It shows Figure 1A A simplified circuit diagram of a junction-isolated semiconductor strain gauge. Detailed Implementation

[0010] For the purpose of describing specific examples, the terminology used herein is not intended to limit other examples. Whenever the use of singular forms such as “a,” “an,” and “the,” and the use of only a single element is neither explicitly nor implicitly defined as mandatory, other examples may use multiple elements to achieve the same functionality. Similarly, when a function is subsequently described as being implemented using multiple elements, further examples may use a single element or processing entity to achieve the same functionality. It will be further understood that the terms “comprising,” “including,” “encompassing,” and / or “having,” when used, specify the presence of the stated feature, integral, step, operation, process, action, element, and / or component, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, processes, actions, elements, components, and / or any group thereof.

[0011] It will be understood that when one element is referred to as "connected" or "coupled" to another element, these elements can be directly connected or coupled, or connected or coupled via one or more intermediate elements. If "or" is used to combine two elements A and B, it should be understood to disclose all possible combinations, i.e., only A, only B, and A and B. An alternative wording for the same combination is "at least one of A and B." The same applies to combinations of more than two elements.

[0012] Therefore, while the other examples are capable of various modifications and alternatives, certain specific examples are shown in the accompanying drawings and subsequently described in detail. However, this detailed description does not limit the other examples to the specific forms described. The other examples may cover all modifications, equivalents, and alternatives falling within the scope of this disclosure.

[0013] from Figure 1A Beginning with reference to the accompanying drawings, an apparatus including a junction-isolated semiconductor strain gauge and a method for manufacturing the junction-isolated semiconductor strain gauge according to this disclosure are described. For further explanation, Figure 1A , Figure 1B and Figure 1C Different views of a device 100 according to at least one embodiment of the present invention are shown, the device 100 including a junction-isolated semiconductor strain gauge 101 on a silicon chip 103.

[0014] exist Figures 1A-1C In the example, silicon chip 103 includes a silicon substrate 105 and a semiconductor strain gauge 101. In a particular embodiment, silicon chip 103 may be attached to the top of a diaphragm (not shown), for example, by an adhesive or a glass substrate layer. To monitor the pressure applied to the diaphragm, semiconductor strain gauge 101 includes a plurality of sensing elements, such as resistors or piezoresistive elements having resistance that varies with the bending of the diaphragm. This resistance may be calculated, for example, by configuring semiconductor strain gauge 101 and its components (resistors and bonding pads) to form a configuration (e.g., a Wheatstone bridge), which operates to generate a voltage output signal from which the resistance of one or more resistors of semiconductor strain gauge 101 can be determined. That is, in this embodiment, the linear voltage output of semiconductor strain gauge 101 is proportional to the pressure applied to the diaphragm. For example, when pressure is applied to the diaphragm coupled to semiconductor strain gauge 101, bending of the diaphragm causes a change in the resistance of one or more resistors of semiconductor strain gauge 101. Continuing this example, a constant voltage can be input to the semiconductor strain gauge 101, such that a change in the resistance of one of the resistors will cause a corresponding change in the output voltage of the semiconductor strain gauge 101. This change in output voltage can be used to calculate the amount of bending in the diaphragm. As will be explained further below, Figures 1A-1C The specific configuration of the semiconductor strain gauge 101 can provide several advantages over existing technology designs.

[0015] exist Figures 1A-1CIn the example, the semiconductor strain gauge 101 has multiple resistors (first resistor 150, second resistor 151, third resistor 152, and fourth resistor 153) formed by locally doping and biasing the silicon substrate 105, such that the resistors are junction-isolated. In contrast to forming resistors by locally doping and biasing the silicon substrate, prior art designs may rely on forming resistors by etching a uniformly doped silicon substrate. Because prior art designs typically form resistors for semiconductor strain gauges by etching a uniformly doped silicon substrate, these prior art designs may require special silicon substrates, which can be expensive and difficult to obtain. However, according to embodiments of the invention, forming resistors by locally doping the silicon substrate 105 allows the use of inexpensive and widely available industry-standard silicon wafers, thus eliminating the need for these special silicon substrates. For example, standard silicon wafers can be used for the silicon substrate 105 instead of the more expensive custom substrates as in prior art designs.

[0016] In addition to the advantages of using cheaper and more readily available source materials Figures 1A-1C The semiconductor strain gauge 101 can also be more compact and minimized than other existing technology designs. Minimizing the semiconductor strain gauge design improves mechanical performance, reduces the negative impact of thermal gradients, and reduces the required package size. Furthermore, the minimized design allows for easier increases in the resistance of the semiconductor strain gauge, which can be advantageous for low-power applications.

[0017] To achieve this minimized design, the resistors of the semiconductor strain gauge 101 are positioned between bonding pads on the silicon chip. For example, the plurality of resistors in the semiconductor strain gauge 101 includes a first resistor 150 electrically connected between a first bonding pad 120 and a second bonding pad 121. The plurality of resistors also includes a second resistor 151 electrically connected between the second bonding pad 121 and a third bonding pad 122. Furthermore, the plurality of resistors also includes a third resistor 152 electrically connected between the third bonding pad 122 and a fourth bonding pad 123. In this embodiment, the plurality of resistors also includes a fourth resistor 153 electrically connected between the fourth bonding pad 123 and the first bonding pad 120.

[0018] In this example embodiment, a first resistor 150 is located on the top surface 161 of the silicon chip 103 between the first bonding pad 120, the second bonding pad 121, and the center 160 of the top surface 161 of the silicon chip 103. A second resistor 151 is located on the top surface 161 of the silicon chip 103 between the second bonding pad 121, the third bonding pad 122, and the center 160 of the top surface 161 of the silicon chip 103. In this example embodiment, a third resistor 152 is located on the top surface 161 of the silicon chip 103 between the third bonding pad 122, the fourth bonding pad 123, and the center 160 of the top surface 161 of the silicon chip 103. According to this embodiment, a fourth resistor 153 is located on the top surface 161 of the silicon chip 103 between the fourth bonding pad 123, the first bonding pad 120, and the center 160 of the top surface 161 of the silicon chip 103.

[0019] exist Figures 1A-1C In the example, the configuration of resistors (i.e., first resistor 150, second resistor 151, third resistor 152, and fourth resistor 153) and bonding pads (i.e., first bonding pad 120, second bonding pad 121, third bonding pad 122, and fourth bonding pad 123) forms a full Wheatstone bridge. Although in Figures 1A-1C The illustration shows a specific configuration with four pads and two resistors, but other configurations are possible according to one or more embodiments of the invention. For example, a half-bridge configuration with three pads and two resistors or a single-resistor configuration with two pads and one resistor is also possible. In these alternative examples, the resistors may be located between the bonding pads to minimize the design, and a field shielding layer may also be applied to isolate the output signal from the electric field.

[0020] As explained above, this minimalist design allows for more flexible placement of semiconductor strain gauges on the membrane to be monitored. For example, Figure 2 A graph 200 according to at least one embodiment of the present invention is shown, illustrating the position 202 of a junction-isolated semiconductor strain gauge (also referred to as a "small gauge") on the membrane. Graph 200 also shows radial strain 220 and tangential strain 221 on the membrane. The position 204 of a prior art semiconductor strain gauge is also shown to demonstrate that the junction-isolated semiconductor strain gauge 101 has similar sensitivity to prior art designs, but occupies a smaller area, and the position of the semiconductor strain gauge is different from some prior art semiconductor strain gauge designs (e.g., in...). Figure 2 The radial position on the membrane shown in the prior art measurement instrument is not very important.

[0021] return Figures 1A-1CThe silicon chip 103 is shown having a first set of tails 170 and a second set of tails 171 formed by non-functional portions of a silicon substrate 105. In this example, the first set of tails 170 extends outward in a direction from the center 160 of the top surface 161 of the silicon chip 103 and extends beyond the first bonding pad 120 and the second bonding pad 121. The second set of tails 171 extends outward in a direction from the center 160 of the top surface 161 of the silicon chip 103 and extends beyond the third bonding pad 122 and the fourth bonding pad 123. In a particular embodiment, the tails 170, 171 may be removed.

[0022] Figures 1A-1C The example embodiment also shows a silicon chip 103, which includes a junction 109 surrounding each of a plurality of resistors. Figures 1A-1C In the example, silicon chip 103 includes a field shielding layer 108 that isolates the output signal of semiconductor strain gauge 101 from an external electric field. Furthermore, device 100 may include a glass substrate (not shown) for coupling silicon substrate 105 to a contact surface (not shown). According to this embodiment, the glass substrate does not contact the plurality of resistors of semiconductor strain gauge 101. Because the glass substrate does not contact the sensing portion of the semiconductor strain gauge, this design has the advantage of eliminating strain gauge output drift (so-called P2 drift) caused by ion contamination in the glass substrate during various high-temperature tests, which may occur in prior art designs where the glass substrate is coupled to the sensing element of the semiconductor strain gauge.

[0023] To further explain, Figure 3 It shows Figure 1A A simplified circuit diagram of the junction-isolated semiconductor strain gauge 101. As described above, in Figure 1A In the example, the resistors (150, 151, 152, 153) of the junction-isolated semiconductor strain gauge 101 form a first Wheatstone bridge. Those skilled in the art of electrical work know that a Wheatstone bridge circuit has two input nodes and two output nodes. The output voltage of the Wheatstone bridge will vary with changes in resistor values ​​caused by pressure, temperature variations, thermal mismatch, etc. Figure 3 In the example, a voltage source can be applied to the bridge configuration circuit at the second terminal 321, and grounded at the fourth terminal 323. In a particular embodiment, the two outputs of the circuit at the first terminal 320 and terminal lead 322 are proportional to the voltage change caused by the resistance change of these resistors.

[0024] exist Figure 3In the example, the voltage at the first terminal (320) and the third terminal (322) can form an output associated with the semiconductor strain gauge (101). In operation, the resistance of the semiconductor strain gauge (101) can vary based on the amount of pressure coupled to the diaphragm of the semiconductor strain gauge (101). The resistance of the semiconductor strain gauge (101) can be determined by measuring the voltage difference between the first terminal (320) and the third terminal (322). It should be understood that... Figure 3 Only an example configuration of the circuit is shown, and those skilled in the art will recognize that other configurations can be used.

[0025] The figures and designs disclosed herein offer a variety of performance and cost reduction benefits, including the following:

[0026] • The solder glass of the MSH sensor no longer comes into contact with the silicon sensing part, which will eliminate the failure mode of output drift (so-called P2 drift) caused by ion contamination in the glass during various high-temperature tests.

[0027] • The design of strain gauges can be minimized, thereby improving mechanical properties, reducing the negative impact of thermal gradients, and enabling smaller package sizes.

[0028] • The minimized design makes it easier to increase the bridge resistance, which is crucial for low-power applications.

[0029] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, apparatuses, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions marked in a block may occur in a different order than those marked in the figures. For example, depending on the function involved, two consecutively shown blocks may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a hardware-based dedicated system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0030] The advantages and features of this disclosure can be further described by the following statements:

[0031] 1. An apparatus comprising: a silicon chip and a field shielding layer; the silicon chip including a silicon substrate and a semiconductor strain gauge having a plurality of resistors formed by locally doping and biasing the silicon substrate, such that the resistors among the plurality of resistors are junction isolated; the field shielding layer isolates the output signal of the semiconductor strain gauge from an external electric field.

[0032] 2. According to the apparatus of statement 1, the plurality of resistors include: a first resistor, a second resistor, a third resistor and a fourth resistor, wherein the first resistor is electrically connected between a first bonding pad and a second bonding pad; the second resistor is electrically connected between a second bonding pad and a third bonding pad; the third resistor is electrically connected between a third bonding pad and a fourth bonding pad; and the fourth resistor is electrically connected between a fourth bonding pad and a first bonding pad.

[0033] 3. The apparatus according to statement 1 or 2 further includes: a junction surrounding each of the plurality of resistors.

[0034] 4. The apparatus according to any one of statements 1-3, wherein the first resistor is located on the top surface of the silicon chip between the first bonding pad, the second bonding pad and the center of the top surface of the silicon chip; the second resistor is located on the top surface of the silicon chip between the second bonding pad, the third bonding pad and the center of the top surface of the silicon chip; the third resistor is located on the top surface of the silicon chip between the third bonding pad, the fourth bonding pad and the center of the top surface of the silicon chip; and the fourth resistor is located on the top surface of the silicon chip between the fourth bonding pad, the first bonding pad and the center of the top surface of the silicon chip.

[0035] 5. The apparatus according to any one of statements 1-4, wherein the silicon chip includes: a first set of tails formed of a silicon substrate and a second set of tails formed of a silicon substrate, the first set of tails extending outward in a direction from the center of the top surface of the silicon chip and beyond a first bonding pad and a second bonding pad; the second set of tails extending outward in a direction from the center of the top surface of the silicon chip and beyond a third bonding pad and a fourth bonding pad.

[0036] 6. An apparatus according to any one of statements 1-5, wherein each of the plurality of resistors is a piezoresistive resistor.

[0037] 7. The apparatus according to any one of statements 1-6 further includes a glass substrate for coupling the silicon substrate to the contact surface.

[0038] 8. An apparatus according to any one of statements 1-7, wherein the glass substrate is not in contact with the plurality of resistors.

[0039] 9. The apparatus according to any one of statements 1-8, wherein the silicon substrate is formed from a silicon wafer.

[0040] 10. An apparatus comprising: a silicon chip, the silicon chip including a silicon substrate and a semiconductor strain gauge, the semiconductor strain gauge having a plurality of junction isolation resistors, the plurality of resistors including: a first resistor, a second resistor, a third resistor and a fourth resistor, the first resistor being electrically connected between a first bonding pad and a second bonding pad; the second resistor being electrically connected between the second bonding pad and the third bonding pad; the third resistor being electrically connected between the third bonding pad and the fourth bonding pad; and the fourth resistor being electrically connected between the fourth bonding pad and the first bonding pad.

[0041] 11. The apparatus according to statement 10 further includes: a field shielding layer for isolating the output signal of the semiconductor strain gauge from an external electric field.

[0042] 12. The apparatus according to any one of statements 10-11, wherein a plurality of resistors are formed by locally doping and biasing a silicon substrate, such that the resistors are junction isolated.

[0043] 13. The apparatus according to any one of statements 10-12 further includes: a junction surrounding each of the plurality of resistors.

[0044] 14. The apparatus according to any one of statements 10-13, wherein a first resistor is located on the top surface of the silicon chip between a first bonding pad, a second bonding pad, and the center of the top surface of the silicon chip; a second resistor is located on the top surface of the silicon chip between a second bonding pad, a third bonding pad, and the center of the top surface of the silicon chip; a third resistor is located on the top surface of the silicon chip between a third bonding pad, a fourth bonding pad, and the center of the top surface of the silicon chip; and a fourth resistor is located on the top surface of the silicon chip between a fourth bonding pad, a first bonding pad, and the center of the top surface of the silicon chip.

[0045] 15. The apparatus according to any one of statements 10-14, wherein the silicon chip includes: a first set of tails formed of a silicon substrate and a second set of tails formed of a silicon substrate, the first set of tails extending outward in a direction from the center of the top surface of the silicon chip and beyond a first bonding pad and a second bonding pad; the second set of tails extending outward in a direction from the center of the top surface of the silicon chip and beyond a third bonding pad and a fourth bonding pad.

[0046] 16. An apparatus according to any one of statements 10-15, wherein each of the plurality of resistors is a piezoresistive resistor.

[0047] 17. The apparatus according to any one of statements 10-16 further includes a glass substrate for coupling the silicon substrate to the contact surface.

[0048] 18. An apparatus according to any one of statements 10-17, wherein the glass substrate is not in contact with the plurality of resistors.

[0049] One or more embodiments may be described herein by means of method steps that illustrate the performance of specific functions and their relationships. For ease of description, the boundaries and order of these functional building blocks and method steps have been arbitrarily defined herein. Alternative boundaries and orders may be defined as long as the specified functions and relationships are properly performed. Therefore, any such alternative boundaries or orders are within the scope and spirit of the claims. Furthermore, for ease of description, the boundaries of these functional building blocks have been arbitrarily defined. Alternative boundaries may be defined as long as certain essential functions are properly performed. Similarly, flowchart blocks may also be arbitrarily defined herein to illustrate certain essential functions.

[0050] Within the scope of use, flowchart block boundaries and sequences can be defined in other ways and still perform certain important functions. Therefore, this substitution of functional building blocks and flowchart blocks and sequences is limited within the scope and spirit of the claims. Those skilled in the art will also recognize that the functional building blocks, as well as other illustrative blocks, modules, and components herein, can be implemented as shown in the figures or by discrete components, application-specific integrated circuits, processors executing appropriate software, or any combination thereof.

[0051] While specific combinations of different functions and features of one or more embodiments are explicitly described herein, other combinations of these features and functions are equally possible. This disclosure is not limited to the specific examples disclosed herein, and these other combinations are explicitly incorporated.

Claims

1. A semiconductor strain gauge device, comprising: Diaphragm; A silicon chip, comprising a silicon substrate and a semiconductor strain gauge, the silicon chip being attached to the top of the diaphragm, the semiconductor strain gauge having a plurality of resistors formed in the silicon substrate by locally doping and biasing the silicon substrate, such that the resistors among the plurality of resistors are junction isolated; The silicon chip further includes a first bonding pad, a second bonding pad, a third bonding pad, and a fourth bonding pad on the top surface of the silicon chip, and the plurality of resistors includes a first resistor, a second resistor, a third resistor, and a fourth resistor. The first resistor is located on the top surface of the silicon chip between the first bonding pad, the second bonding pad, and the center of the top surface of the silicon chip. The second resistor is located on the top surface of the silicon chip between the second bonding pad, the third bonding pad, and the center of the top surface of the silicon chip. The third resistor is located on the top surface of the silicon chip between the third bonding pad, the fourth bonding pad, and the center of the top surface of the silicon chip; and The fourth resistor is located on the top surface of the silicon chip between the fourth bonding pad, the first bonding pad, and the center of the top surface of the silicon chip.

2. The apparatus of claim 1, wherein the plurality of resistors comprises: The first resistor is electrically connected between the first bonding pad and the second bonding pad. The second resistor is electrically connected between the second bonding pad and the third bonding pad. The third resistor is electrically connected between the third bonding pad and the fourth bonding pad. The fourth resistor is electrically connected between the fourth bonding pad and the first bonding pad.

3. The apparatus according to claim 2, further comprising: A junction surrounding each of the plurality of resistors.

4. The apparatus according to claim 2, wherein, The silicon chip also includes: A first set of tail portions, formed from the silicon substrate, extends outwardly from the center of the top surface of the silicon chip and beyond the first bonding pad and the second bonding pad; and The second set of tails, formed by the silicon substrate, extends outward in a direction starting from the center of the top surface of the silicon chip and beyond the third and fourth bonding pads.

5. The apparatus according to claim 1, wherein, Each of the plurality of resistors is a piezoresistive resistor.

6. The apparatus of claim 1, further comprising a glass substrate for coupling the silicon substrate to a contact surface.

7. The apparatus according to claim 6, wherein, The glass substrate does not contact the plurality of resistors.

8. The apparatus according to claim 1, wherein, The silicon substrate is formed from a silicon wafer.

9. A semiconductor strain gauge device, comprising: Diaphragm; A silicon chip, comprising a silicon substrate and a semiconductor strain gauge, the silicon chip being attached to the top of a diaphragm, the semiconductor strain gauge having a plurality of junction isolation resistors, the plurality of junction isolation resistors including: a first resistor, a second resistor, a third resistor, and a fourth resistor, the first resistor being electrically connected between a first bonding pad and a second bonding pad; the second resistor being electrically connected between the second bonding pad and a third bonding pad; the third resistor being electrically connected between the third bonding pad and a fourth bonding pad; and the fourth resistor being electrically connected between the fourth bonding pad and the first bonding pad. The first resistor is located on the top surface of the silicon chip between the first bonding pad, the second bonding pad, and the center of the top surface of the silicon chip. The second resistor is located on the top surface of the silicon chip between the second bonding pad, the third bonding pad, and the center of the top surface of the silicon chip. The third resistor is located on the top surface of the silicon chip between the third bonding pad, the fourth bonding pad, and the center of the top surface of the silicon chip; and The fourth resistor is located on the top surface of the silicon chip between the fourth bonding pad, the first bonding pad, and the center of the top surface of the silicon chip.

10. The apparatus according to claim 9, further comprising: A field shielding layer isolates the output signal of the semiconductor strain gauge from the external electric field.

11. The apparatus according to claim 9, wherein, The plurality of junction isolation resistors are formed in the silicon substrate by locally doping and biasing the silicon substrate, such that the resistors are junction isolated.

12. The apparatus of claim 11, further comprising: The junction of each of the plurality of junction isolation resistors.

13. The apparatus according to claim 9, wherein, The silicon chip also includes: A first set of tail portions, formed from the silicon substrate, extends outwardly from the center of the top surface of the silicon chip and beyond the first bonding pad and the second bonding pad; and The second set of tails, formed by the silicon substrate, extends outward in a direction starting from the center of the top surface of the silicon chip and beyond the third and fourth bonding pads.

14. The apparatus according to claim 9, wherein, Each of the plurality of junction isolation resistors is a piezoresistive resistor.

15. The apparatus of claim 9, further comprising a glass substrate for coupling the silicon substrate to a contact surface.

16. The apparatus according to claim 15, wherein, The glass substrate does not contact the plurality of junction isolation resistors.

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