Memory subword driver circuit and layout

Abstract

In some examples, a sub-word driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains / sources of first and second transistors in a first region; the second active region forms drains / sources of third and fourth transistors in a second region, where the first and second regions are adjacent to each other. The first, second, third, and fourth transistors are coupled to a common non-active potential via a common contact superimposed on a merged region between the first region and the second region. The first and second active regions can comprise N+ diffusion material.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Patent Application No. 17 / 028,929, filed September 22, 2020, which is incorporated herein by reference in its entirety for all purposes. Background Technology

[0003] Semiconductor memory devices (such as dynamic random access memory (DRAM)) include memory cell arrays having memory cells disposed at intersections between word lines and bit lines. The semiconductor memory device may include a hierarchical structure of master word lines (MWLs) and word lines. The master word lines are driven by corresponding master word drivers and located at a higher level, and are selected by a first portion of the row address. The word lines are driven by corresponding sub-word drivers and located at a lower level, and are selected based on the corresponding master word line and a word driver line (FX) selected by a second portion of the row address.

[0004] Due to the scaling down of array access devices in semiconductor manufacturing, local interconnects in memory cell arrays (e.g., word line coupling between sub-word drivers and the memory cell array) can have higher pitch (e.g., more crowded) in some areas due to the layout of the sub-word drivers. It is desirable to reduce the pitch of interconnects within sub-word driver blocks. Summary of the Invention

[0005] Disclosed is a memory subword driver circuit and layout. In one aspect of this disclosure, an example semiconductor device includes a first region of a subword driver block. The first region includes a first active region on which a first transistor and a second transistor are formed, and a second active region on which a third transistor and a fourth transistor are formed. The first region further includes a diffusion region configured to merge the first and second active regions, and a contact coupled to the first active region and a non-active potential. The third and fourth transistors are coupled to the non-active potential via the contact and the diffusion region.

[0006] In another aspect of this disclosure, a device includes a sub-word driver block, a gate electrode layer, and diffusion contacts. The sub-word driver block includes at least first and second active regions extending in a first direction, and one or more common diffusion regions spaced apart in the first direction and configured to merge the first and second active regions. The gate electrode layer includes a first gate electrode extending in a second direction substantially perpendicular to the first direction, wherein the first gate electrode is stacked across the first and second active regions in a plan view to form first and second transistors. The gate electrode layer further includes a second gate electrode extending in the second direction, wherein the second gate electrode is stacked across the first and second active regions in a plan view to form third and fourth transistors. The diffusion contacts are stacked on the first active region and are shared by the second and fourth transistors via corresponding common diffusion regions of the one or more common diffusion regions.

[0007] In another aspect of this disclosure, a device includes a first active region and a second active region of a subword driver block. The first and second active regions are adjacent to each other and extend in a first direction. The first active region forms the drain / source of a first and a second transistor, and the second active region forms the drain / source of a third and a fourth transistor. The first, second, third, and fourth transistors are coupled to a common contact. Attached Figure Description

[0008] Figure 1 This is a block diagram of a semiconductor device based on some examples described in this disclosure.

[0009] Figure 2 This is a diagram showing an example configuration of the memory bank of a semiconductor device based on some examples described in this disclosure.

[0010] Figure 3 This is a schematic diagram of a portion of a storage unit according to some instances described in this disclosure.

[0011] Figure 4 is a schematic diagram of the subword driver and memory unit.

[0012] Figure 5 This is a schematic diagram of an instance subword driver coupled by a cascade connection, based on some examples described in this disclosure.

[0013] Figure 6 This is a schematic diagram of an instance subword driver array coupled in a cascaded connection according to some examples described in this disclosure.

[0014] Figure 7 This is a schematic diagram of an example subword driver array and memory cell coupled in a cascaded connection according to some examples described in this disclosure.

[0015] Figure 8 This is an example block diagram of a memory device based on some of the examples described in this disclosure.

[0016] Figure 9A It is a plan view of an instance layout diagram of a subword driver of a demonstration scope, based on some examples described in this disclosure.

[0017] Figure 9B This is an example of an additional layer shown based on some instances described in this disclosure. Figure 9A A plan view of the instance layout of the subword driver in the diagram.

[0018] Figure 9C This is to demonstrate some or additional layers based on some examples described in this disclosure. Figure 9A and 9B A plan view of the instance layout of the subword driver in the diagram.

[0019] Figure 10A It is a plan view of an instance layout diagram of a subword driver of a demonstration scope, based on some examples described in this disclosure.

[0020] Figure 10B This is an example of an additional layer shown based on some instances described in this disclosure. Figure 10A A plan view of the instance layout of the subword driver in the diagram.

[0021] Figure 10C This is to demonstrate some or additional layers based on some examples described in this disclosure. Figure 10A and 10B A plan view of the instance layout of the subword driver in the diagram.

[0022] Figure 11A It is a plan view of an instance layout diagram of a subword driver of a demonstration scope, based on some examples described in this disclosure.

[0023] Figure 11B This is an example of an additional layer shown based on some instances described in this disclosure. Figure 11A A plan view of the instance layout of the subword driver in the diagram.

[0024] Figure 11C This is to demonstrate some or additional layers based on some examples described in this disclosure. Figure 11A and 11B A plan view of the instance layout of the subword driver in the diagram. Detailed Implementation

[0025] Specific details are set forth below to provide a full understanding of examples of various embodiments of this disclosure. However, it should be understood that the examples described herein can be practiced without these specific details. Furthermore, the specific examples of this disclosure described herein should not be construed as limiting the scope of this disclosure to those specific examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail to avoid unnecessarily obscuring the embodiments of this disclosure. Additionally, terms such as “coupled” and “via coupled” mean that two components can be electrically coupled directly or indirectly. Indirect coupling may mean that two components are coupled through one or more intermediate components. The shapes and dimensions of the various semiconductor structures shown in the figures are not to scale. For example, layout diagrams are provided only as examples, and shapes and dimensions may be modified for actual semiconductor devices.

[0026] Figure 1 This is a block diagram of a semiconductor device 10 according to some examples described in this disclosure. In some embodiments of this disclosure, the semiconductor device 10 may be a dynamic random access memory (DRAM). The semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of data lines DL that intersect each other, wherein memory cells (MC) are disposed at the intersection points. The WL can be driven by corresponding sub-word drivers SWD. For clarity, Figure 1 Only one WL, SWD, DL, and MC are shown. Multiple master word lines MWL and word driver lines FX can be provided to the corresponding SWD in the memory cell array 11. For example, the selection of master word lines MWL and word driver lines FX is implemented by row decoder circuitry 12, and the selection of data lines DL and / DL is implemented by column decoder circuitry 13. In some instances, word driver lines FX can be driven by corresponding word drivers FXD 46. Master word lines MWL can be driven by corresponding master word drivers (MWD) 44. For example, a memory device may have 128 master word lines and 128 master word drivers providing the corresponding master word lines.

[0027] In some instances, the semiconductor device 10 may include multiple memory cell arrays 11 arranged as multiple memory banks. The semiconductor device 10 may also include multiple row decoder circuits 12 and multiple column decoder circuits, each coupled to a corresponding memory cell array 11.

[0028] Further reference Figure 1 The sense amplifier 18 is coupled to the corresponding data lines DL and / DL and to the local I / O line pair LIOT / B. The local I / O line pair LIOT / B is coupled to the main I / O line pair MIOT / B via a transfer gate TG 19, which serves as a switch for the read / write amplifier and buffer 15.

[0029] Turning to the description of a plurality of external terminals included in semiconductor device 10, the plurality of external terminals include command and address terminal 21, clock terminal 23, data terminal 24, and power supply terminals 25 and 26. Command and address terminal 21 is supplied with command and address signals CA. The CA signal provided to command and address terminal 21 contains the command and address. The address contained in the CA signal is transmitted to address decoder circuit 32 via command / address input circuit 31. Address decoder circuit 32 receives the address and supplies the decoded row address signal RA to row decoder circuit 12, and supplies the decoded column address signal COL to column decoder circuit 13.

[0030] The command contained in the CA signal provided to the command and address terminals 21 is input to the command decoder circuit 34 via the command / address input circuit 31. The command decoder circuit 34 decodes the command to provide various internal command signals. For example, the internal command may include a row command signal for selecting a word line and a column command signal for selecting a data line (e.g., a read command or a write command).

[0031] When an activation command is issued and a row address is supplied in a timely manner along with a read command, and a column address is supplied in a timely manner along with a read command, read data is read from the memory cell MC in the memory cell array 11 specified by these row and column addresses. More specifically, the row decoder circuit 12 selects the master word line MWL, word driver line FX, and word line WL indicated by the row address RA, such that the associated memory cell MC is subsequently connected to the data line DL or / DL. Furthermore, when the memory cell MC is selected via the row address and the associated row is activated via the activation command, the master word line MWL is active and the word driver line FX is active. This causes the word line WL to be active. Conversely, when the memory cell MC is not selected, for example, during a precharge operation, the word driver line FX may not be active, and the master word line MWL may also not be active. This drives the word line WL to an inactive potential, for example, the off-state word line voltage VNWL. Further reference Figure 1 The read data DQ is output from the data terminal 24 via the read / write amplifier 15 and the input / output circuit 17.

[0032] Similarly, when an activation command is issued and the row address is supplied in a timely manner along with the write command, and the column address is supplied in a timely manner along with the write command, the input / output circuit 17 can receive the write data DQ at the data terminal 24. The write data DQ is supplied to the memory cell array 11 via the input / output circuit 17 and the read / write amplifier 15 and written to the memory cell MC specified by the row address and column address.

[0033] Clock terminals 23 are supplied with external clock signals CK and / CK, respectively. These external clock signals CK and / CK are complementary to each other and supplied to clock input circuit 35. Clock input circuit 35 receives external clock signals CK and / CK and provides an internal clock signal ICLK. The internal clock signal ICLK is supplied to internal clock generator 36, and thus provides a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and the clock enable signal CKE from command / address input circuit 31. In a non-limiting example, a DLL circuit may be used as internal clock generator 36. The phase-controlled internal clock signal LCLK is supplied to input / output circuit 17 and used as a timing signal for determining the output timing of read data DQ.

[0034] Power supply terminal 25 is supplied with power supply voltages VDD1, VDD2, and VSS. These power supply voltages VDD1, VDD2, and VSS are supplied to the internal voltage generator circuit 39. The internal voltage generator circuit 39 provides various internal voltages, such as VPP, VARY, VPERI, VEQ, VCCP, and VNWL.

[0035] The internal potentials VCCP and VNWL are primarily used in the line decoder circuit 12, the master word driver MWD 44, and the word driver FXD 46. For example, when the address signal ADD is selected, the word driver FXD can be configured to drive the potential on the word driver line FX to the VCCP level corresponding to a high potential (e.g., 3.1V). When the line is in a pre-charge state, in response to the inactive signal on the master word line (MWL) and the inactive signal on the word driver lines (e.g., FXT, FXB), the associated sub-word drivers can be configured to pull the word line (WL) down to the internal voltage VNWL (e.g., an inactive potential, which may be negative).

[0036] Internal potentials VARY and VEQ are the potentials to be used by the sense amplifier 18, the transfer gate 19, and / or the read / write amplifier 15. When the sense amplifier 18 is activated, data is amplified and read out by driving one of the paired data lines to the VARY level and the other to the VSS level. The internal potential VPERI is used as the power supply potential for most peripheral circuits (e.g., command / address input circuit 31). By using the internal potential VPERI, which has a lower potential than the external potential VDD, as the power supply potential for these peripheral circuits, the power consumption of the semiconductor device 10 can be reduced.

[0037] Power supply terminal 26 is supplied with power supply voltages VDDQ and VSSQ. These power supply voltages VDDQ and VSSQ are supplied to input / output circuit 17. The power supply voltages VDDQ and VSSQ can be the same voltages as the power supply voltages VDD2 and VSS supplied to power supply terminal 25, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in input / output circuit 17 to prevent power supply noise generated by input / output circuit 17 from propagating to other circuit blocks of device 10.

[0038] Figure 2 This is a diagram illustrating an example configuration of the memory bank of a semiconductor device according to some examples described in this disclosure. For example, in some embodiments of this disclosure, device 10 ( Figure 1 Each of the memory cell arrays 11 may contain Figure 2 The configuration of the storage unit 200.

[0039] In some instances, memory bank 200 may contain multiple memory mat areas, such as MAT0 to MAT3. Figure 2 In the example shown, memory cell 200 has four storage pad areas, but in other examples, memory cell 200 may contain more or fewer storage pad areas. As indicated by the dashed lines in storage pad area MAT1, each storage pad area may be divided into multiple sub-areas, for example, SUBMAT1-0 to SUBMAT1-3. Although Figure 2 The example shown contains four sub-regions, but in other examples, storage pad regions MAT0 through MAT3 may contain more or fewer sub-regions. Each sub-region SUBMAT1-0 through SUBMAT1-3 may contain multiple storage pads aligned in the Y direction (e.g., 64). For simplicity, Figure 2 Individual storage pads are not shown. Subword drive SWD block ( Figure 2 (Not shown) can be arranged, for example, on both sides of each storage pad in the X direction. The sensing amplifier SA block can be arranged, for example, on both sides of each storage pad in the Y direction. In some embodiments, the storage pads of each sub-region SUBMAT1-0 to SUBMAT1-3 can be provided to the corresponding IO (e.g., DQ pad).

[0040] Subword driver operations can be performed via line decoder circuitry (e.g.) Figure 1 The line decoder circuit 12) is controlled. When the line address RA is received, the line decoder selects the word line WL by activating the appropriate master word driver (MWD) and the appropriate word driver (FXD) indicated by the line address RA. Figure 2The example shown illustrates one block of primary word driver (MWD); however, a primary word driver (MWD) block can contain multiple primary word driver (MWDs). Similarly, two blocks of word driver (FXD) are shown, but each word driver (FXD) block can contain multiple word driver (FXDs). For example, if each storage pad region (MAT) contains four subregions and each subregion contains 64 storage pads, then a primary word driver (MWD) block can contain 128 MWDs, which are configured to activate the corresponding primary word line (MWL). Continuing this example, each word driver (FXD) block can contain eight word driver (FXDs), which are configured to activate the corresponding word driver line (FX). Figure 2 In the example shown, bits 3 to 15 of row address RA encode the main word line MWL, and bits 0 to 2 of row address RA encode the word driver line FX. However, other encoding schemes can be used.

[0041] Figure 3 This is a schematic diagram of a portion of storage 300 according to some examples described in this disclosure. In some embodiments of this disclosure, Figure 3 A portion of the storage unit 300 shown may be included Figure 2 storage 200 and / or Figure 1 In the memory cell array 11.

[0042] Memory section 300 may include multiple word lines 310, each provided via a corresponding sub-word driver SWDj. For example, word line 314 may be provided via a corresponding sub-word driver SWD5, which is associated with the main word line driven by master word driver MWD1 and also with word driver line 302 (e.g., FX5) associated with word driver 308. In other words, for each sub-word driver, a corresponding master word line MWL and word driver line FX are provided, along with an inactive potential (e.g., the off-state word line voltage VNWL). Signals on master word line MWL and word driver line FX may be provided via master word drivers MWD0 to MWDN and word driver FXD 304 based on row address RA, as referenced. Figure 2 describe.

[0043] The master word line MWL may extend above the array area of ​​the corresponding storage pad to provide the master word signal to the sub-word driver rows SWD0 to SWD7 of the storage pad and activate the sub-word drivers SWD0 to SWD7. That is, when the master word driver MWD is activated, it can provide the active master word signal to all sub-word drivers SWD0 to SWD7 of the pad. As will be described below, the word driver line FX may include FXT and FXB. In some instances, when FXT is active, the FXB line is not active. Conversely, when FXT is not active, FXB may be active. Each word driver line 302 of the word driver FXD 304 provides a word driver line to at least one sub-word driver SWD in each storage pad. Figure 3 In the example shown, the word driver FXD 304 includes an even-numbered driver 306 and an odd-numbered driver 308. The even-numbered driver 306 provides corresponding word driver lines to the even-numbered sub-word drivers SWD0, SWD2, SWD4, and SWD6 of each storage pad, and the odd-numbered driver 308 provides corresponding word driver lines to the odd-numbered sub-word drivers SWD1, SWD3, SWD5, and SWD7 of each storage pad. However, other arrangements may be used in other examples. Figure 3 In the example shown, each word driver line of word driver 304 can be coupled to a corresponding sub-word driver SWD0 to SWD7 in each storage pad. For example, FX line 5 can be coupled to sub-word driver SWD5 in each storage pad.

[0044] exist Figure 3 In the example operation shown, row address RA indicates that MWD1 should be activated and the odd-number driver 308 associated with word driver line FX5 should be activated. As shown by shaded area 312, word line 310 associated with non-active master word drivers MWD0 and MWDn remains inactive, even though the sub-word line associated with word driver line FX5 is active. However, among word lines 322 associated with activated MWD1, word line 314 driven by sub-word driver SWD5 associated with activated MWD1 and FX5 is activated. By way of example, activated MWD can be configured to provide an active signal on the associated master word line, and activated word driver FXD can be configured to provide an active signal on word driver lines (e.g., FXT, FXB). Similarly, activated sub-word drivers can be configured to provide an active signal on the associated word line. Therefore, the selected word line WL of the selected storage pad associated with MWD1 is driven to an active potential by the corresponding activated sub-word driver SWD5.

[0045] In some instances, other sub-word drivers SWD of the selected storage pad drive the corresponding unselected word line WL to an inactive potential (e.g., VNWL) to remain inactive. The sub-word drivers SWD of the unselected storage pad MAT (e.g., the storage pads associated with MWD0 and MWDn) remain disabled, and the word line WL of the unselected storage pad MAT is not supplied with voltage, or in some instances, is instead supplied with an inactive potential (e.g., VNWL). However, the sub-word driver SWD is coupled to the word driver FXD and the main word driver MWD; to activate the word line WL associated with the sub-word driver SWD, both the associated word driver FXD and the main word driver MWD must be activated.

[0046] Figure 4 is a schematic diagram of a conventional subword driver and memory cell. As shown in Figure 4, the output of subword driver 402 is coupled to word line WL, which is coupled to memory cell 412. Memory cell 412 includes at least one transistor and a capacitor. Word line WL is connected to the gate of the transistor, and data line DL is connected to the drain / source (drain or source) of the transistor. The memory cell is capable of storing 1 bit of data. Memory cell 412 is coupled to sense amplifier 410, which is configured to sense the signal of memory cell 412 on data line DL and drive the signal to a desired voltage.

[0047] The sub-word driver 402 includes two transistors of different conductivity types (e.g., p-channel transistor 404 and n-channel transistor 406) series coupled at the word line WL. The main word line MWL is coupled to the gates of transistors 404 and 406. The word driver line FXT is coupled to the drain / source of transistor 404 and provides an unactive potential VNWL to the drain / source of transistor 406. The word line WL is also coupled to the unactive potential VNWL via n-channel transistor 408. The word driver line FXB is coupled to the gate of transistor 408.

[0048] The word line of memory cell 412 is coupled to a sub-word driver 402, which operates in response to signals on the main word line MWL and the word driver line FXT. During operation, transistors 404 and 406 are configured to provide active / inactive signals on the word line WL. An n-channel transistor 408 is used to prevent unselected word lines from floating. For example, when the main word line MWLB is low, transistor 404 is on and transistor 406 is off. If FXT is not active, then FXB will be active to turn on transistor 408, which pulls the potential at the word line WL down to VNWL, thus preventing word line floating. As shown in Figure 4, the sub-word driver 402 in a conventional circuit contains at least three transistors.

[0049] Figure 5This is a schematic diagram of an example subword driver coupled in a cascaded connection according to some examples described in this disclosure. The cascaded connection example may include the outputs of two or more circuits coupled together. For example, subword drivers 502 and 504 can be cascaded and coupled together, such as... Figure 5 Detailed explanation follows. In some instances, Figure 5 The sub-word drivers 502 and 504 shown can be used in sub-word driver 42 (in Figure 1 (in Chinese) or SWD0 to SWD7 (in Figure 3 Implemented in ( ). Sub-word drivers 502 and 504 may be coupled to different main word lines. For example, sub-word driver 502 is coupled to main word line MWLBn, while sub-word driver 504 is coupled to main word line MWLBn+1. In some instances, sub-word driver 502 may include two transistors of different conductivity types (e.g., p-channel transistor 508 and n-channel transistor 506) coupled at their source / drain (source or drain), the two transistors being coupled together to output OUTm. Output OUTm may be coupled to word line WLm. The gates of transistors 506 and 508 may be coupled to a common main word line (e.g., MWLBn). The source / drain of n-channel transistor 506 may be coupled to the non-active potential VNWL, while the source / drain of p-channel transistor 508 may be coupled to word driver line FXT (e.g., FXT0). Subword driver 502 may also include a common transistor 514 shared with another subword driver (e.g., subword driver 504).

[0050] In some instances, sub-word driver 504 may have a structure similar to sub-word driver 502, and its description will not be repeated. Sub-word driver 504 may be coupled to a main word line (e.g., MWLBn+1) different from the main word line MWLBn coupled to sub-word driver 502. Two transistors of different conductivity types (e.g., p-channel transistor 510 and n-channel transistor 512) may be commonly coupled to output OUTm+1 at their source / drain, and output OUTm+1 may be coupled to word line WLm+1. In some instances, the corresponding outputs OUTm and OUTm+1 of sub-word drivers 502 and 504 may be coupled to a common transistor 514 shared by the two sub-word drivers. In some instances, common transistor 514 may be an n-channel transistor, with its gate coupled to the corresponding word driver line FXB (e.g., FXB0). In some instances, the drain / source of the p-channel transistors (in this case, 508, 510) of the sub-word drivers 502, 504 can be coupled to a common word driver line (e.g., FXT0). Figure 5As shown, the two sub-word drivers 502 and 504 are cascaded and share a common transistor 514 at their respective outputs OUTm and OUTm+1. Therefore, the two sub-word drivers now contain a total of five transistors, averaging 2.5 transistors per sub-word driver. Compared to the conventional sub-word drivers shown in Figure 4, the number of transistors used for the sub-word drivers can be reduced, resulting in a reduction in the memory die size.

[0051] Figure 5 The diagram shows two subword drivers 502 and 504; however, other subword drivers in the memory device can be configured in a similar manner. For example, an additional subword driver (e.g., 520) may also be coupled to the main word line MWLBn coupled to subword driver 502. Similarly, an additional subword driver (e.g., 522) may also be coupled to the main word line MWLBn+1 coupled to subword driver 504. Figure 5 In the example shown, one main word line (MWL) drives four sub-word drivers to provide signals on four word lines (only one is shown). However, other numbers of sub-word drivers can be coupled to the same main word line driver, as will be... Figure 6 It is displayed in the middle.

[0052] Figure 6 This is a schematic diagram of an example subword driver array coupled in a cascaded connection according to some examples described in this disclosure. The subword driver array 600 can be configured in any subword driver (e.g., Figure 1 42 in the middle, Figure 3 Implemented in SWD0 to SWD7. The sub-word driver array 600 may include multiple main word lines (e.g., MWLB0, MWLB1, ...), each main word line being coupled to a corresponding sub-word driver group to drive the group of sub-word drivers to drive the corresponding word line. For example, sub-word drivers 602, 606, 618, and 622 are coupled to and driven by main word line MWLB1. Sub-word drivers 604, 608, 610, and 614 are coupled to and driven by main word line MWLB2.

[0053] In some instances, the subword driver array 600 may contain multiple pairs of subword drivers coupled in a cascaded connection, such as Figure 5 As illustrated in the examples. In some configurations, subword drivers associated with the first main word line can be cascaded and coupled to subword drivers associated with a second main word line different from the first main word line. For example, subword drivers 602 and 606 are associated with main word line MWLB1 and have outputs coupled to word lines WL8 and WL10, respectively. Subword drivers 604 and 608 are associated with a different main word line MWLB2 and have outputs coupled to word lines WL16 and WL18, respectively.

[0054] In the example shown, two sub-word drivers 602 and 606 are cascaded and coupled to two sub-word drivers 604 and 608, respectively. For example, the outputs of sub-word driver 602 and sub-word driver 604 are cascaded and coupled through a common transistor Q5. Therefore, sub-word drivers 602 and 604 form as shown in the example. Figure 5 A similar pair is configured, in which the outputs of sub-word drivers 602 and 604 are coupled to word lines WL8 and WL16, respectively. Similarly, the outputs of sub-word drivers 606 and 608 are cascaded and coupled via a common transistor Q10. Therefore, sub-word drivers 606 and 608 form... Figure 5 A similar pair is shown in the image, in which the outputs of subword drivers 606 and 608 are coupled to word lines WL10 and WL18, respectively.

[0055] In some instances, two subword drivers associated with physically adjacent main word lines can be cascaded and coupled. For example, in the case of two subword drivers 602 and 604 cascaded and coupled, the associated main word lines (e.g., MWLB1 and MWLB2) of the subword drivers can be physically adjacent to each other. It should be understood that in some embodiments of this disclosure, the associated main word lines of two subword drivers coupled in a cascaded connection may not be physically adjacent to each other.

[0056] In some instances, subword drivers associated with a given main word line can be cascaded and coupled to subword drivers associated with two other main word lines in an alternating manner. In a non-limiting configuration, the subword drivers associated with a first main word line may comprise at least a first set of subword drivers and a second set of subword drivers. The first set of subword drivers may be cascaded and coupled to one or more subword drivers associated with a second main word line, and the second set of subword drivers may be cascaded and coupled to one or more subword drivers associated with a third main word line.

[0057] In a non-limiting example, the sub-word drivers associated with a main word line (e.g., MWLB1) may include a first group (e.g., 602, 606) and a second group (e.g., 618, 622). As described above, sub-word drivers 602 and 606 may be cascaded with sub-word drivers 604 and 608, respectively, wherein sub-word drivers 604 and 608 are associated with a second main word line (e.g., MWLB2). Figure 6The diagram further illustrates that the second set of subword drivers 618, 622 can be cascaded with subword drivers 620, 624 associated with the third main word line (e.g., MWLB0). In this configuration, among the multiple subword drivers associated with word line MWLB1, two subword drivers 602, 606 are cascaded with two subword drivers 604, 608, respectively, with subword drivers 604, 608 positioned relative to subword drivers 602, 606 in a first direction (e.g., in the Y direction), wherein subword drivers 604, 608 are associated with the second word line (e.g., MWLB2). Two additional sub-word drivers (e.g., 618, 622) associated with word line MWLB1 are coupled in a cascaded connection to two sub-word drivers 620, 624, respectively, with sub-word drivers 620, 624 positioned in a second direction (e.g., in the X direction) relative to sub-word drivers 618, 622, wherein sub-word drivers 620, 624 are associated with a third word line (e.g., MWLB0).

[0058] In a similar configuration, two sub-word drivers 604 and 608 associated with the main word line MWLB2 are cascaded and coupled to two sub-word drivers 602 and 606, respectively, with the sub-word drivers 602 and 606 positioned in a second direction relative to the sub-word drivers 604 and 608, wherein the sub-word drivers 602 and 606 are associated with the main word line MWLB1. Similarly, two other sub-word drivers (e.g., sub-word drivers 610 and 614) associated with the main word line MWLB2 are cascaded and coupled to two sub-word drivers 612 and 616, respectively, with the sub-word drivers 612 and 616 positioned in a first direction relative to the sub-word drivers 610 and 614, wherein the sub-word drivers 612 and 616 are associated with a fourth main word line (e.g., MWLB3).

[0059] exist Figure 6 In the example provided, the first primary word line (e.g., MWLB1) may be physically adjacent to the second primary word line (e.g., MWLB2). The first primary word line (e.g., MWLB1) may also be physically adjacent to the third primary word line (e.g., MWLB0). In other scenarios, the first primary word line may not be physically adjacent to either the second or third primary word line. It should be understood that the terms "first direction" and "second direction" are only relative opposites. For example, "first direction" may refer to a connection in the X direction, while "second direction" may refer to a connection in the Y direction, which is opposite to the X direction. Alternatively, "first direction" may refer to a connection in the X direction, while "second direction" may refer to a connection in the Y direction. It should be further understood that... Figure 6 The configuration variations shown in the document are possible.

[0060] Figure 7This is a schematic diagram of an example subword driver array and memory cell coupled in a cascaded connection according to some examples described in this disclosure. In some examples, such as Figure 5 and 6 The cascading connection of the subword drivers shown in the figure can be Figure 7 The memory device 700 is implemented in a sub-word driver array. For example, the memory device 700 may include a memory cell block 702 arranged in two arrays 708, 710, which respectively extend in a first direction (e.g., "x"). Each of the memory cell arrays 708, 710 includes a corresponding data line (e.g., DL_Tk-1, DL_Tk) and a plurality of memory cells coupled to the corresponding data line. Each memory cell on the data line has a corresponding word line extending in a second direction (e.g., "y") substantially perpendicular to the first direction, wherein each word line is driven by a corresponding sub-word driver in either side of the memory cell block 702. The memory cell block 702 may include a DRAM memory array. The memory cells in the memory cell block 702 may include a capacitor and a transistor (e.g., an n-channel MOSFET) connected in series and configured to store one data bit.

[0061] In a non-limiting example, memory cells associated with even-numbered word lines (e.g., WLm-14, WLm-12, ...WLm, ...WLm+14, WLm+16) are coupled to a first data line (e.g., DL_Tk-1), wherein the even-numbered word lines are coupled to a first sub-driver block 704 located on a first side (e.g., the left side) of memory cell block 702. Similarly, memory cells associated with odd-numbered word lines (e.g., WLm-15, WLm-13, ...WLm-1, WLm+1, ...WLm+13, WLm+15) are coupled to a second data line (e.g., DL_Tk), wherein the odd-numbered word lines are coupled to a second sub-driver block 706 located on a second side (e.g., the right side) of memory cell block 702 opposite to the first side.

[0062] exist Figure 7In the configuration, the first subword driver block 704 may include multiple sets of subword drivers 720, 722, 724, 726 to drive corresponding even-numbered word lines (e.g., WLm-14, WLm-12, ...). Each of the word lines is coupled to a corresponding memory cell. Each set of subword drivers is associated with a corresponding main word line. For example, a set of even-numbered subword drivers 720 (not fully shown) is coupled to even-numbered word lines WLm-14, WLm-12, WLm-10, and WLm-8 associated with the main word line MWLBn-1. Similarly, a set of odd-numbered subword drivers 728 (not fully shown) is coupled to odd-numbered word lines WLm-15, WLm-13, WLm-11, and WLm-9 associated with the same main word line MWLBn-1. Subword driver sets 720 and 728 are respectively arranged on two opposite sides of the memory cell block 702. Figure 7 In this configuration, the main word line drives eight sub-word drivers to drive eight word lines. Each of the eight sub-word drivers is coupled to the main word line and a corresponding word driver line (FXT, FXB). For example, signals provided on the main word line MWLBn-1 and the eight word driver lines FXT0 to FXT7 drive the eight sub-word drivers (on any side of memory cell block 702). Each of the eight sub-word drivers drives a corresponding word line (e.g., WLM-8, WLM-9, ... WLM-15).

[0063] Further reference Figure 7 On the left side of memory cell block 702, even-numbered sub-word drivers are driven by main word line MWLBm-1 and word driver line signals FXT0 / FXB0, FXT2 / FXB2, FXT4 / FXB4, and FXT6 / FXB6, respectively, to drive word lines WLm-14, WLm-12, WLm-10, and WLm-8. On the right side of memory cell block 702, odd-numbered sub-word drivers are driven by main word line MWLBm-1 and word driver lines FXT1 / FXB1, FXT3 / FXB3, FXT5 / FXB5, and FXT7 / FXB7, respectively, to drive word lines WLm-15, WLm-13, WLm-11, and WLm-9.

[0064] The remaining blocks in the circuit are arranged in a similar manner and will not be described again. Although Figure 7Only the main word lines MWLBn-1, MWLBn, MWLBn+1, and MWLBn+2 are shown in this diagram; however, it should be understood that a memory device can have hundreds of main word lines, and each main word line can be coupled to any appropriate number of sub-word drivers to drive multiple word lines. For example, in a non-limiting example, a memory device can have 128 main word lines driven by 128 main word drivers (MWDs). Each main word line can be associated with eight word lines, which are selected together by signals on the main word line and the corresponding word driver lines FXT / B0 to FXT / B7. In this case, there are 1024 word lines in the memory cell array.

[0065] Further reference Figure 7 This allows for cascading connections between sub-word drivers. For example, on the left side of memory cell array 702, word lines WLm-4 and WLm-6 are driven by corresponding sub-word drivers associated with the main word line MWLBn (see block 722); word lines WLm-10 and WLm-8 are driven by corresponding sub-word drivers associated with the adjacent main word line MWLBn-1 (see block 720). As shown, the sub-word drivers for driving word lines WLm-4 and WLm-10, respectively, associated with the adjacent main word lines MWLBn and MWLBn-1, respectively, include a common n-channel transistor Q8 coupled to the output of the sub-word driver in a cascaded connection. The corresponding sub-word drivers for word lines WLm-4 and WLm-10 are also coupled to the same word driver line FXT4. The gate of transistor Q8 is coupled to word driver line FXB4.

[0066] Similarly, the sub-word drivers driving word lines WLm-6 and WLm-8 are coupled in a cascaded connection via a common n-channel transistor Q9. The respective sub-word drivers for word lines WLm-6 and WLm-8 are also coupled to the same word driver line FXT6. Transistor Q9 is coupled to word driver line FXB6. Detailed descriptions are provided for each of the sub-word drivers (or sub-word driver pairs in a cascaded connection). Figure 5 and 6 In the middle, multiple odd-numbered subword drivers (in block 706) are also cascaded and coupled in the same manner as the even-numbered subword drivers (in block 704) as previously described.

[0067] refer to Figure 6 and 7 , Figure 5 The operation of sub-word drivers 502 and 504 in the middle can be performed Figure 6 and 7This is implemented in any sub-word driver. For example, among multiple main word lines MWLB, only one main word line is selected (e.g., in operation) while all other main word lines are not selected (e.g., out of operation). Furthermore, among multiple word driver lines FXT / FXB, only one word driver line is in operation. For a sub-word driver associated with a selected main word line, the supply of the out-of-operation potential VNWL from its own circuitry is cut off due to the n-channel transistor being turned off (attributed to the selected main word line being in operation). However, if the FXT supplied to the sub-word driver is not in operation, the out-of-operation potential VNWL is still supplied to the word line to prevent word line floating. For example, VNWL can be supplied from another sub-word driver connected via a common transistor cascade.

[0068] For example, refer to Figure 6 One main word line (e.g., MWLB1) can be selected (e.g., at logic low) while other main word lines are not selected (e.g., at logic high); and one word driver line (e.g., FXT0 / FXB0) can be active while other word driver lines are not active. In this case, all sub-word drivers 602, 606, 618, and 622 are disconnected from VNWL in their respective circuits due to the selected main word line MWLB1. When FXT2 / FXB2, FXT4 / FXB4, and FXT6 / FXB6 are not active, the VNWL supply for the corresponding sub-word drivers 606, 618, and 612 is provided to their adjacent sub-word drivers via cascading connections. For example, VNWL is supplied from sub-word driver 608 to sub-word driver 606, which is associated with the unselected main word line MWLB2. When MWLB2 is not selected, transistor Q9 in sub-word driver 608 is turned on, and VNWL is coupled to common transistor Q10 through transistor Q9. Similarly, the VNWL supply for sub-word drivers 618 and 612 is provided from sub-word drivers 620 and 624, respectively.

[0069] Figure 8 This is an example block diagram of a portion of a memory device according to some of the embodiments described in this disclosure. In some embodiments, a portion of the memory device (e.g., 800) may be present in memory device 10 ( Figure 1 Implemented in memory device 800. A portion of memory device 800 may include multiple memory cell arrays (e.g., 806). Memory cell array 806 may be arranged in rows and columns. Each memory cell array 806 may include multiple memory cells. A portion of memory device 800 also includes multiple sub-word driver (SWD) blocks 810 and multiple sense amplifier (SA) blocks 808. In some instances, memory cell array 806, SWD blocks 810, and SA blocks 808 may be implemented in memory cell array 11 ( Figure 1 (Internal implementation)

[0070] In some instances, the SWD block 810 is arranged on the side of the memory cell array 806. In a non-limiting instance, a sub-word driver may be placed on the side of the memory cell array and adjacent to the memory cell array to provide signals on corresponding word lines of the memory cell array. In another non-limiting instance, a sub-word driver may be placed on both sides of the memory cell array and adjacent to the memory cell array to provide signals on corresponding word lines of the memory cell array. For example, the word lines of the memory cell array may be divided into even-numbered and odd-numbered word lines. The sub-word driver for the even-numbered word lines may be arranged adjacent to a first side (e.g., the left side) of the memory cell array, while the sub-word driver for the odd-numbered word lines may be arranged adjacent to a second side (e.g., the right side) opposite to the first side of the memory cell array.

[0071] exist Figure 8 In the example, each of the SWD blocks can serve adjacent memory cell arrays on either side of the SWD block. Each of the SWD blocks can serve adjacent memory cell arrays on both sides of the SWD block. For example, an SWD block may have a first portion and a second portion, wherein the first portion is coupled to a word line of a memory cell array adjacent to a first side (e.g., the left side) of the SWD block, and the second portion is coupled to a word line of a memory cell array adjacent to a second side (e.g., the right side) opposite to the first side of the SWD block.

[0072] In some instances, the subword driver block (810) may be positioned on the side of the memory cell array (806) in a first direction (e.g., X), while the SA block 808 may be arranged on the side of the memory cell array 806 in a second direction (e.g., Y) substantially perpendicular to the first direction. For example, as Figure 8 As shown, the SWD block can be arranged adjacent to the left and / or right side of the memory cell block 806, while the SA block can be arranged adjacent to the top and / or bottom side of the memory cell block 806.

[0073] A portion of the memory device 800 may further include a master word driver (MWD) block 804. In some instances, the MWD block may include multiple MWDs, each coupled to a plurality of master word lines. In a non-limiting instance, the MWD block may include 128 MWDs to provide signaling on 128 master word lines (e.g., MWLBn to MWLBn+128). It should be understood that other suitable numbers of master word lines may be implemented.

[0074] In some instances, a portion of memory device 800 may also include an array control block (ACTL) 802, configured to provide signals to SA block 810 on multiple word driver lines FXTj / FXBj. In some instances, MWD block 804 may be present in memory device 10 ( Figure 1Implemented internally. In some instances, the ACTL block 802 can be implemented within one or more line decoder circuits 12 ( Figure 1 ) and / or memory device 10 Figure 1 Implemented in additional circuitry within memory device 800. A portion of memory device 800 may be integrated with memory device 10. Figure 1 ), 600 Figure 6 ) or 700 Figure 7 The operation is the same, therefore, it will not be repeated. Figure 8 The operation of the memory device is shown in the figure.

[0075] Figure 9A This is a plan view of an example layout of a sub-word driver for a demonstration area, based on some examples described in this disclosure. In some instances, the sub-word driver layout 900 may include implementations of multiple sub-word drivers (e.g., memory device 700). Figure 7 The active region of the sub-word driver in a transistor. The active region may contain one or more drains, sources, and channels. For example, the active region may contain P+ diffused material or N+ diffused material to form a p-channel or n-channel transistor, respectively. (See reference...) Figure 9A The layout 900 may include a p-channel MOSFET region 902 and an n-channel region 904 adjacent to the p-channel region. The p-channel region 902 may include an active region with P+ diffused material and implement a p-channel transistor in a sub-word driver. The n-channel region 904 may include an active region with N+ diffused material and implement an n-channel transistor in a sub-word driver. For example... Figure 9A As shown, the p-channel region has multiple sub-regions (e.g., 906A to 906D) that extend in a first direction (e.g., in the column). The n-channel region has multiple sub-regions (e.g., 910A to 910D) that extend in the first direction. It should be understood that although only four sub-regions are shown, both the p-channel and n-channel regions can have any suitable number of sub-regions. Separating the n-channel and p-channel transistors in the sub-word driver can provide advantages in optimizing the layout, as will be further explained in this disclosure. In some instances, the n-channel region (e.g., 904) may have two n-channel sub-regions (e.g., 910C, 910D) that may have one or more common diffusion regions 920 that combine the source / drain of two or more transistors. This will be explained in... Figure 9B Further explanation is provided below.

[0076] Figure 9B This is an example of an additional layer shown based on some instances described in this disclosure. Figure 9AThis is a plan view of an example layout of a sub-word driver. In some instances, layout 900 may include additional layers, such as those superimposed on p-channel region 902 and n-channel region 904, to form gate layers for p-channel or n-channel transistors. In some instances, the gate layer may include multiple gate electrodes. Each gate electrode may be coupled to a corresponding main word line MWLB. Figure 9B The diagram shows four gate electrodes for the main word lines MWLBn-1, MWLBn, MWLBn+1, and MWLBn+2, respectively. Although layout 900 only shows a portion of the memory device, it should be understood that additional gate electrodes for other main word lines may be included.

[0077] Further reference Figure 9B The layout 900 may also include contacts for the active region or a gate layer superimposed on the corresponding active region in the plan view. As shown, diffused contacts may be arranged in the active region on each side of the gate. In the p-channel region (902), the gate electrode may overlap with the active region containing P+ diffused material to form a corresponding p-channel transistor. The contacts on the active region may be coupled to word line WLm+j or word driver line (e.g., FXTj). FXT word driver lines (e.g., FXT0, FXT1, FXT2, FXT3) are connected to a common source / drain between adjacent main word lines (MWLB).

[0078] For example, FXT0 and FXT2 are coupled to the corresponding common source / drain between adjacent gate electrodes associated with MWLBn-1 and MWLBn. FXT0 and FXT2 are also coupled to the corresponding common source / drain between adjacent main word lines MWLBn+1 and MWLBn+2. FXT4 and FXT6 are coupled to the corresponding common drain / source between adjacent main word lines MWLBn and MWLBn+1. For each gate, on the side opposite the common source / drain, the corresponding word line is coupled to the drain / source. For example, along the gate electrode associated with MWLBn, word line WLm is coupled to the drain of transistor Q16, opposite the common source of transistor Q1. Similarly, along the gate electrode associated with main word line MWLBn+1, word line WLm+2 is coupled to the drain of transistor Q17, opposite the common source of transistor Q19. This pattern is repeated for additional word lines.

[0079] In the n-channel region 904, the gate electrode is superimposed on the N+ diffuser region to form the corresponding n-channel transistor. Contacts on the active region can be coupled to the word line WLm+i or the non-active potential VNWL. In other words, the corresponding word line and the non-active potential VNWL are coupled to the drain / source of each transistor. For example, transistor Q30 is formed and coupled to the main word line MWLBn-1 at its gate, and further coupled to VNWL and WLm-12 at its drain / source. Similarly, transistor Q31 is formed and coupled to the main word line MWLBn at its gate, and further coupled to VNWL and WLm-2 at its drain / source.

[0080] like Figure 9B As shown, transistors Q30 and Q31 can be formed in a first n-channel sub-region (e.g., 910C), wherein the drain or source of transistors Q30 and Q31 can be coupled together to a common VNWL contact. In some instances, transistors Q5 and Q12 can be formed in a second n-channel sub-region (e.g., 910D) in a similar manner to transistors Q30 and Q31, wherein each of Q5 and Q12 is coupled at its gate to main word lines MWLBn-1 and MWLBn, respectively, and further coupled at its respective drain or source to VNWL and WLm.

[0081] In some instances, the first active region (e.g., an N+ diffusion region) of the drain / source of transistors Q30 and Q31 forming the n-channel sub-region 910C merges with the second active region (e.g., an N+ diffusion region) of transistors Q5 and Q12 forming the n-channel sub-region 910D at a common diffusion region 920. In other words, the drain / source of transistors Q30, Q31, Q5, and Q12 are merged via the common diffusion region 920 and share contacts for VNWL. For example... Figure 9B As shown, the common contact for VNWL can be coupled to a first functional area in a first n-channel sub-region 910C. Alternatively, the common contact for VNWL can be coupled to a second functional area in a second n-channel sub-region 910D. In some instances, the n-channel region 904 may include other n-channel sub-regions (e.g., 910A and 910B). In some embodiments, the layout of 910A and 910B can be configured in a manner similar to that of 910C and 910D.

[0082] Further reference Figure 9BTransistors Q13 and Q18 may be formed in a second n-channel sub-region (e.g., 910D) and coupled to the main word lines MWLBn+1 and MWLBn+2 at their gates, respectively, and further coupled to a common VNWL and WLm+16 at their drains / sources. The common VNWL may be in a first n-channel sub-region (e.g., 910C), wherein the drains / sources of Q13 and Q18 are coupled together to the common VNWL via corresponding common diffusion regions 920.

[0083] Further reference Figure 9B The common transistor in the sub-word driver (e.g., Figures 5 to 7 A common transistor (Q15) can be formed in an n-channel region 904 between two adjacent gate electrodes, wherein each common transistor can be coupled to a corresponding drain / source at the output of a different sub-word driver, wherein the output is coupled to a corresponding word line. For example, between gate electrode MWLBn+1 and adjacent gate electrode MWLBn+2, another gate is disposed to superimpose on the N+ diffused sub-region 910A to form a common n-channel transistor. The common n-channel transistor is coupled to the word driver line at the gate and the two drains / sources of the different sub-word drivers. For example, a common transistor Q15 is formed between the different drains / sources at the outputs of different sub-word drivers, respectively coupled to word lines WLm+8 and WLm+10. The common transistor Q15 can be coupled to word driver line FXB6 at the gate. Now refer to Figure 7 , Figure 9B The transistor Q15 in the middle also corresponds to Figure 7 Transistor Q15 is shown in the diagram. Similarly, between adjacent main word lines MWLBn+1 and MWLBn+2, on the N+ diffused sub-region 910B, a gate is positioned between the drain / source of the outputs of different sub-word drivers coupled to word lines WLm+6 and WLm+12, respectively, and coupled to word driver line FXB4. This forms another common transistor Q14, which is coupled between the drain / source of the outputs of the different sub-word drivers coupled to word lines WLm+6 and WLm+12, respectively. This transistor corresponds to... Figure 7 Transistor Q14 in the middle.

[0084] Return to Figure 9BThe width of an N+ diffused sub-region (e.g., N+ diffused sub-region 910A) may include a portion 912 at the intersection of gates FXB6, which is narrower than the rest of the sub-region. The narrower portion 912 may at least partially define a recessed region to accommodate the layout space of gate FXB6. Similarly, another N+ diffused sub-region 910B may also include a portion 914 at the intersection of gates FXB4, which is narrower than the rest of the sub-region. The narrower portion 914 may at least partially define a recessed region to accommodate the layout space of gate FXB4. In the illustrated example, the two recessed regions formed by the narrower portions 912 and 914 of adjacent N+ diffused sub-regions 910A and 910B may be adjacent to each other, thereby allowing the two adjacent N+ diffused sub-regions to be close to each other while accommodating the gates of common transistors Q14 and Q15. This facilitates a reduction in layout size.

[0085] Further reference Figure 9B , Figure 7 Additional common transistors in the circuit can be formed in the n-channel region 904, such as Q6, Q7, Q8, Q9, Q10, and Q11. Furthermore, other n-channel transistors in the sub-word driver can be formed in the n-channel region 904 on each gate electrode coupled to the corresponding main word line. For example, n-channel transistor Q5 (corresponding to...) Figure 7 Transistor Q5 is formed above the gate electrode associated with the main word line MWLBn-1, where the drain / source is coupled to word line WLm-14 and the non-active potential VNWL, respectively. In another example, n-channel transistor Q18 (corresponding to...) Figure 7 Transistor Q18 is formed above the gate electrode associated with the main word line MWLBn+2. Sub-word driver block 704 ( Figure 7 The additional n-channel transistors in the layout 900 can be formed in the n-channel region 904 in a similar manner.

[0086] In some instances, n-channel transistors formed above two adjacent gate electrodes may share a common contact. For example, transistors Q5 and Q12 share a common diffusion contact coupled to the non-operating potential VNWL. In another instance, transistors Q10 and Q12 share a common contact coupled to the corresponding word line (e.g., WLm).

[0087] Further reference Figure 9BThe p-channel transistors in the sub-word driver block 704 can be formed in the p-channel region 902 of the layout 900. For example, p-channel transistors Q1, Q16, Q17, and Q19 (corresponding to transistors Q1, Q16, Q17, and Q19) can be formed above the respective gate electrodes in the P+ diffused sub-region 906B. For example, p-channel transistor Q1 is formed above the gate electrode associated with MWLBn-1, and has two contacts on each side of the gate electrode, wherein the two contacts are coupled to the word line (e.g., WLm-14) and the word driver line (e.g., FXT0), respectively.

[0088] exist Figure 9B In the example, even-numbered word lines are shown in layout 900, which can implement subword driver block 704. Figure 7 ). refer to Figure 7 , 8 Regarding 9B, it should be understood that the circuitry implemented in layout 900 may implement one or more SWD blocks 810. For example, for a given memory cell array 806, the sub-word driver associated with the even-numbered word lines for the given memory cell array may be as follows: Figure 9B A similar layout to that shown in the diagram, arranged adjacent to the left side of the memory cell array. Similarly, the sub-word drivers associated with the odd-numbered word lines used for the memory cell array can be arranged as follows: Figure 9B The layout is similar to that shown in the diagram, and is arranged adjacent to the right side of the memory cell array. In some embodiments of this disclosure, the layout of the subword drivers associated with odd-numbered word lines may be arranged in a mirror arrangement relative to the subword drivers associated with even-numbered word lines.

[0089] Figure 9C This is to demonstrate some or additional layers based on some examples described in this disclosure. Figure 9A and 9B A plan view of an example layout of a sub-word driver. In some instances, layout 900 may further include one or more metal wiring layers above the active region and gate layers and contacts for multiple word lines (e.g., Figure 9B (As shown in the diagram), the gate layer and contacts are coupled to the wiring layer to couple to the corresponding memory cells in the memory cell array.

[0090] like Figure 9CAs shown, the drain / source coupling of the transistor at the common diffusion region 920 allows for coupling to, for example, n-channel subregions 910C and 910D using VNWL contacts. In some embodiments of this disclosure, the common diffusion region 920 allows for the elimination of VNWL contacts from the second n-channel subregion 910D (as shown). This facilitates a simpler layout of interconnects 924, 926, 928, 930, 932, 934, 936, 938, 940 (e.g., for word line wiring). For example, when the contacts for word lines WLm-12 and WLm-14 are pitched close to each other in the lateral direction (e.g., the first direction X), the associated interconnects 924, 926 coupled to the contacts can be arranged in a manner that accommodates the contact locations. For example, interconnect 924 can be wider in at least a portion of the n-channel subregion 910D to accommodate the contact for WLm-14, thereby reducing the offset between the contact and the interconnect. In another example, interconnect 926 may include a bend 942 between the first n-channel sub-region 910C and the second n-channel sub-region 910D to allow proper spacing with interconnect 924.

[0091] In some instances, two interconnects 930, 932 adjacent to a common VNWL contact in a plan view can be positioned around the contact wiring 946 coupled to the contact of the common VNWL by forming a recessed region 944 in the middle of the first n-channel sub-region 910C to accommodate wiring 946. The interconnects 930, 932 can further extend from the first n-channel sub-region 910C to the second n-channel sub-region 910D in a second direction (e.g., Y) substantially perpendicular to the first direction (e.g., X) to couple to a memory cell array (e.g., ...). Figure 8 The corresponding memory cell in 806). Interconnects 934 and 936 can be arranged similarly to interconnects 924 and 926 to accommodate contacts for WLm-2 and WLm. Further reference Figure 9C Other interconnects used for word lines WLm+2, +4, ... WLm+16 can be laid out in a similar manner to interconnects WLm-14, -12, ... WLm.

[0092] In some instances, the interconnects used for various word lines WLm+j may include a wiring layer, such as metal 0 (zero). The interconnect layout disclosed herein offers the advantage of reducing word line pitch. For example, interconnect pitch can be measured by the number of interconnects in a distance L in the X direction. A larger number of interconnects results in a larger pitch. Reference Figure 9B and 9C The distance L spans a congested area containing three transistors Q5, Q12, Q10, eight word lines (WLm-14, -12, ..., WLm) and the FXB0 contact. Figure 9CThe layout configuration shown results in a reduction in the number of interconnects of the same size L because VNWL contacts are eliminated in the n-channel sub-region 910D. Instead, the VNWL in the n-channel sub-region 910C is shared via a common diffusion region 920.

[0093] Figures 10A to 10C illustrate Figure 9A The changes to the layout diagram in C. For example, Figure 10A It is a plan view of an instance layout diagram of a subword driver of a demonstration scope, based on some examples described in this disclosure. Figure 10B This is an example of an additional layer shown based on some instances described in this disclosure. Figure 10A A plan view of the instance layout of the subword driver in the diagram. Figure 10C This is to demonstrate some or additional layers based on some examples described in this disclosure. Figure 10A and 10B The layout diagram of the subword driver instance is shown in plan view. Layout 1000 can be implemented in a similar manner. Figure 9A For the same subword driver block in C, the description of the subword driver block layout and operation will not be repeated.

[0094] Figure 10A The changes shown in C include different arrangements of the p-channel and n-channel MOSFET regions. For example... Figure 10A As shown, layout 1000 includes a p-channel region 1003 disposed between adjacent n-channel regions 1002 and 1004. (Comparison) Figure 10A To C and Figure 9A In section C, the n-channel region 1004 in layout 1000 is divided into a first region and a second region of n-channel sub-regions, each region being placed on the opposite side of the p-channel region. For example, the first region of n-channel sub-region 1002 may correspond to... Figure 9A The n-channel sub-regions 910A and 910B are included; and the second region of the n-channel sub-region 1004 can correspond to Figure 9A The n-channel subregions 910C and 910D are similar to those in the example. Figure 9A The interaction regions in adjacent n-channel sub-regions can merge at one or more common diffusion regions. For example, the interaction regions (N+) in n-channel sub-regions 1010A and 1010B can merge at one or more common diffusion regions 1020. Similarly, the interaction regions (N+) in n-channel sub-regions 1010C and 1010D can merge at one or more common diffusion regions 1020.

[0095] refer to Figure 10BIn the first region of the n-type sub-region 1002, common transistors Q10 and Q11 contained in different sub-word drivers are cascaded and formed between different drains / sources at the outputs of the different sub-word drivers, respectively, with similar... Figure 9B It is coupled to the word line in the manner of forming Q10 and Q11. Similar to... Figure 9B The common transistors Q10 and Q11 also correspond to Figure 7 Transistors Q10 and Q11 are included. In the second region of the n-type sub-region 1004, common transistors Q14 and Q15, contained in different sub-word drivers, are cascaded between the different drains / sources at the outputs of the different sub-word drivers, respectively, with similar characteristics to... Figure 9B The Q14 and Q15 are coupled to the word lines in a manner similar to... Figure 9B The common transistors Q14 and Q15 also correspond to Figure 7 Transistors Q14 and Q15 in the example. For instance... Figure 10A As shown in C, layout 1000 becomes symmetrical. This can provide advantages when designing circuit layouts.

[0096] Further reference Figure 10B Similar to Figure 9B The first active region (N+) of the drain / source of transistors Q30 and Q31 in the n-channel sub-region 1010A merges with the second active region (N+) of transistors Q5 and Q12 in the n-channel sub-region 1010B at the common diffusion region 1020. In other words, the drain / source of transistors Q30, Q31, Q5, and Q12 are merged via the common diffusion region 1020 and share a contact for VNWL. Transistors Q30 and Q5 can be coupled to the main word line MWLBn-1 at their respective gates, and transistors Q31 and Q12 can be coupled to the main word line MWLBn at their respective gates. Figure 10B As shown, the common contact for VNWL can be coupled to a first functional area in a first n-channel sub-region 1010A. Alternatively, the common contact for VNWL can be coupled to a second functional area in a second n-channel sub-region 1010B. In some embodiments of this disclosure, the n-channel sub-region in 1004 may include n-channel sub-regions 1010C and 1010D, whose layout may be similar to... Figure 9B The layout of the n-channel sub-regions 910A and 910B.

[0097] Figure 10C The layout shown in the image is similar to Figure 9C The layout in the n-channel sub-region 1010B can be coupled to the corresponding common VNWL contact in the n-channel sub-region 1010A, as shown. The layout of interconnects WLm-14, -12, ..., WLm-8 and WLm-6, -4, ... WLm can be consistent with... Figure 9C The configuration is similar to that in other languages, so it will not be repeated here. Figure 10C The layout variations shown are also possible. For example, the common VNWL contact could be in another n-channel sub-region 1010B instead of 1010A.

[0098] Figure 11A Explanation to C Figure 9A Another change in layout design in C. For example, Figure 11A It is a plan view of an instance layout diagram of a subword driver of a demonstration scope, based on some examples described in this disclosure. Figure 11B This is an example of an additional layer shown based on some instances described in this disclosure. Figure 11A A plan view of the instance layout of the subword driver in the diagram. Figure 11C This is to demonstrate some or additional layers based on some examples described in this disclosure. Figure 11A and 11B The layout diagram of the subword driver instance is shown in plan view. Layout 1100 can be implemented in a similar manner. Figure 9A For the same subword driver blocks in C and 10A to C, the description of the layout and operation of the subword driver blocks will not be repeated.

[0099] Figure 11A The changes shown in C include different arrangements of p-channel and n-channel regions. For example... Figure 11A As shown, layout 1100 includes an n-channel region 1103 disposed between adjacent p-channel regions 1102 and 1104. (Comparison) Figure 11A To C and Figure 9A To C, the p-channel region 902 in the layout 900 is divided into first regions 1106A and 1106B and second regions 1106C and 1106D, which are placed on opposite sides of the n-channel region. For example, Figure 11A The first region 1102 of the p-channel subregions 1106A and 1106B can correspond to Figure 9A p-channel subregions 906A and 906B; and Figure 11A The second region 1104 of the p-channel subregions 1106C and 1106D can correspond to the p-channel subregions 906C and 906D.

[0100] refer to Figure 11A Similar to Figure 9AIn n-channel region 1103, the interaction regions in adjacent n-channel sub-regions can merge at one or more common diffusion regions. For example, the interaction regions (N+) in n-channel sub-regions 1110A and 1110B can merge at one or more common diffusion regions 1120. Similarly, the interaction regions (N+) in n-channel sub-regions 1110C and 1110D can merge at one or more common diffusion regions 1120.

[0101] refer to Figure 11B The n-channel type region 1103 has similar characteristics to Figure 9B The n-channel region 904 is arranged in a layout similar to that in different sub-word drivers. For example, common transistors Q10 and Q11 contained in different sub-word drivers are cascaded between the drain / source at the output of the different sub-word drivers, and are respectively arranged in a manner similar to that of forming... Figure 9B The Q10 and Q11 methods are coupled to the word lines. Similar to... Figure 9B The common transistors Q10 and Q11 also correspond to Figure 7 Transistors Q10 and Q11 are included. In another example, common transistors Q14 and Q15, contained in different sub-word drivers, are cascaded between the drain / source at the outputs of the different sub-word drivers, respectively forming a configuration similar to that of... Figure 9B The Q14 and Q15 methods are coupled to the word lines. Similar to... Figure 9B The common transistors Q14 and Q15 also correspond to Figure 7 Transistors Q14 and Q15 in the example. Figure 11A As shown in Figure C, layout 1100 also becomes symmetrical. This can provide advantages in optimizing circuit layout design. Additionally, when the n-channel region is between two p-channel regions, the p-well can be separated from the other regions, allowing the reverse bias of the n-channel region to change from VBB (-0.5V) to VSS. A shallow reverse bias can provide the advantage of improved resistance to hot carriers in semiconductor devices.

[0102] Further reference Figure 11B Similar to Figure 9B and 10B The first active region (N+) of the drain / source of transistors Q30 and Q31 in the n-channel sub-region 1110B merges with the second active region (N+) of transistors Q5 and Q12 in the n-channel sub-region 1110A at the common diffusion region 1120. In other words, the drain / source of transistors Q30, Q31, Q5, and Q12 are merged via the common diffusion region 1120 and share a contact for VNWL. Transistors Q30 and Q5 can be coupled to the main word line MWLBn-1 at their respective gates, and transistors Q31 and Q12 can be coupled to the main word line MWLBn at their respective gates. Figure 11BAs shown, the common contact for VNWL can be coupled to the first active region in the n-channel sub-region 1010B.

[0103] Alternatively, the common contact for VNWL may be coupled to a second functional area in n-channel sub-region 1010A. In some embodiments of this disclosure, the layout of n-channel sub-regions 1110C, 1110D may be arranged in a mirror arrangement relative to the layout of n-channel sub-regions 910A, 910B. Although the common VNWL contact is in n-channel sub-region 1110C, alternatively, the common VNWL contact may also be in n-channel sub-region 1110D.

[0104] Figure 11C The layout shown in the image is similar to Figure 9C and 10C The layout in the diagram. For example, as shown, a common VNWL contact can be in the n-channel sub-region 1110B, and the corresponding drain / source in the n-channel sub-region 1110A can be coupled to the corresponding common VNWL contact in the n-channel sub-region 1110B. The layout of interconnects WLm-14, -12, ..., WLm-8 and WLm-6, -4, ... WLm can be consistent with... Figure 9C The configuration is similar to that in other languages, so it will not be repeated here. Figure 11C The layout shown in the diagram can also be varied. For example, the common VNWL contact can be in another n-channel sub-region 1110A instead of 1110B.

[0105] Figures 1 to 1 1 provides various advantages for optimizing the layout of sub-word driver blocks by reducing interconnect pitch. For example, a common diffusion region can be formed to merge two active regions. In this configuration, common VNWL contacts for the two active regions are possible, thereby eliminating VNWL contacts in adjacent active regions. This reduction in VNWL contacts reduces the interconnect pitch in the semiconductor layout. Furthermore, Figures 9 (A to C) to 11 (A to C) provide various configurations for the layout of sub-word driver blocks, where wiring and placement can facilitate minimizing complexity and reducing word line pitch in the layout design.

[0106] As will be understood from the foregoing, although specific embodiments of this disclosure have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to any specific embodiments described herein.

Claims

1. A semiconductor device comprising: The first region of the subword driver block, the first region including: A first functional region, on which a first transistor and a second transistor are formed; The second functional region is formed thereon, and the third and fourth transistors are formed thereon; A diffusion region configured to merge the first and second functional regions; and A contact element located on the first active region between the first transistor and the second transistor, and coupled to a non-active potential. The third and fourth transistors are coupled to the non-active potential via the contact and the diffusion region.

2. The semiconductor device of claim 1, wherein the diffusion region is merged with the drain / source of the first transistor, the second transistor, the third transistor, and the fourth transistor.

3. The semiconductor device of claim 1, wherein the contact is coupled to the drain / source of the first transistor and the second transistor.

4. The semiconductor device of claim 3, wherein the drain / source of the first transistor and the second transistor are respectively coupled to the outputs of the first sub-word driver and the second sub-word driver.

5. The semiconductor device of claim 4, wherein the source / drain of the first transistor and the second transistor are further coupled to a first word line and a second word line of the memory cell array, respectively.

6. The semiconductor device according to claim 1, further comprising: A first gate electrode, wherein the first gate electrode overlaps with the first functional region and the second functional region to form the first transistor and the third transistor; and A second gate electrode, wherein the second gate electrode overlaps with the first active region and the second active region to form the second transistor and the fourth transistor.

7. The semiconductor device of claim 6, wherein the first gate electrode is coupled to a first main word line and the second gate electrode is coupled to a second main word line.

8. The semiconductor device of claim 1, further comprising a first interconnect and a second interconnect and wiring between the first interconnect and the second interconnect, wherein the wiring is coupled to the contact.

9. The semiconductor device of claim 8, wherein the first interconnect and the second interconnect are configured to form a recess therein to receive the wiring.

10. The semiconductor device of claim 7, wherein the first functional region and the second functional region extend along a first direction, and the first interconnect and the second interconnect extend along a second direction perpendicular to the first direction.

11. The semiconductor device of claim 7, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are of a first conductivity type.

12. The semiconductor device of claim 9, further comprising a second region of a sub-word driver block, the second region being adjacent to the first region, and comprising: One or more action regions; and Multiple transistors are formed on the corresponding gate electrodes of the one or more active regions and the multiple gate electrodes. The transistors mentioned above belong to the second conductivity type.

13. A semiconductor device comprising: Subword driver block, which includes: At least the first and second functional areas extend in the first direction; and One or more common diffusion regions, which are spaced apart in the first direction and configured to merge the first functional region and the second functional region; Gate electrode layer, comprising: A first gate electrode extends in a second direction perpendicular to the first direction, and the first gate electrode is superimposed across the first and second functional regions in a planar view to form a first transistor and a second transistor; and A second gate electrode extending in the second direction, the second gate electrode being superimposed across the first and second functional regions in the plan view to form a third and a fourth transistor; and A diffusion contact is superimposed on the first functional region, wherein the diffusion contact is between the first transistor and the third transistor, and wherein the diffusion contact is shared by the second transistor and the fourth transistor via corresponding common diffusion regions of the one or more common diffusion regions.

14. The semiconductor device of claim 13, further comprising a wiring layer including a plurality of interconnects extending in the second direction and coupled to respective word lines of the memory cell array.

15. The semiconductor device of claim 14, wherein the wiring layer comprises a metal zero layer.

16. The semiconductor device of claim 14, further comprising contact wiring coupled to the diffusion contact, wherein the contact wiring is positioned between a first interconnect and a second interconnect of the plurality of interconnects.

17. The semiconductor device of claim 16, wherein the first interconnect and the second interconnect define a recess surrounding the wiring of the contact.

18. A semiconductor device comprising: The first and second functional areas of the subword driver block are adjacent to each other and extend in a first direction, wherein: The first active region forms the drain / source of the first transistor and the second transistor; The second active region forms the drain / source of the third and fourth transistors; and The first transistor, the second transistor, the third transistor, and the fourth transistor are coupled to a common contact, wherein the common contact is located between the first transistor and the second transistor.

19. The semiconductor device of claim 18, wherein the common contact is superimposed on the first active region and coupled to a common non-active potential.

20. The semiconductor device of claim 19, further comprising: A fifth transistor is formed in the first active region and coupled to the first transistor at the output of the first sub-word driver; and A sixth transistor is formed in the second active region and coupled to the third transistor at the output of the second subword driver.

21. The semiconductor device of claim 20, further comprising: A seventh transistor is formed in the first active region and coupled to the second transistor at the output of the third sub-word driver; and An eighth transistor is formed in the second active region and coupled to the fourth transistor at the output of the fourth subword driver.

22. The semiconductor device of claim 21, wherein the outputs of the first sub-word driver, the second sub-word driver, the third sub-word driver, and the fourth sub-word driver are respectively coupled to a first word line, a second word line, a third word line, and a fourth word line of the memory cell array.

23. The semiconductor device according to claim 22, wherein: The gates of the fifth transistor and the seventh transistor are coupled to the first word driver line; and The gates of the sixth transistor and the eighth transistor are coupled to the second word driver line.

24. The semiconductor device of claim 19, further comprising: The third and fourth functional areas of the subword driver block are adjacent to each other and extend in the first direction, and the third functional area is further adjacent to the first functional area, wherein: The drain / source of the fifth and sixth transistors are formed in the third active region; The drain / source of the seventh and eighth transistors are formed in the fourth active region; and The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are coupled to another contact superimposed on the third active region, wherein the other contact is coupled to another common non-active potential.

Images