Apparatus and method for supply control of a sense amplifier for threshold voltage compensation

Abstract

Devices including threshold voltage compensated sense amplifiers and methods for compensating the same are disclosed. An example threshold voltage compensated sense amplifier according to the present disclosure includes a circuit, e.g., a first transistor, having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and a third node; a plurality of transistors coupled to the second node and further configured to receive a supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and additionally provides a plurality of signals indicative of a second drive strength in a second memory operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 17 / 037,467, filed September 29, 2020, which is incorporated herein by reference in its entirety for any purpose. Background Technology

[0003] A memory device is structured as an array of one or more memory cells logically arranged in rows and columns. Each memory cell stores data as a charge for access on a digital line associated with the memory cell. When a charged memory cell is accessed, it causes a positive voltage change on the associated digital line, and an uncharged accessed memory cell causes a negative voltage change on the associated digital line. A sense amplifier amplifies the voltage changes on the digital lines to indicate the value of the data state stored in the memory cell.

[0004] Conventional sense amplifiers are typically coupled to a pair of complementary digital lines coupled to a large number of memory cells. As is known in the art, when a memory cell is accessed, a row of memory cells is activated, and the sense amplifier amplifies the data state of the corresponding activated column of memory cells by coupling each of the digital lines in the selected column to a voltage supply such that the digital lines have complementary logic levels.

[0005] When a memory cell is accessed, the voltage of one of the digital lines increases or decreases slightly, depending on whether the memory cell coupled to the digital line is charged. This creates a voltage difference between the digital lines. When the voltage of one digital line increases or decreases slightly, the other digital line acts as a reference for a sense amplifier. A corresponding transistor is activated due to the voltage difference, which in turn couples the slightly higher-voltage digital line to the supply voltage and the other digital line to the reference voltage (e.g., ground), further driving each of the digital lines in the opposite direction and amplifying the signal on the selected digital line.

[0006] The digital line is precharged to a precharge voltage, such as half the supply voltage, during the precharge phase to ensure accurate amplification of voltage differences during subsequent access operations. However, due to random threshold voltage mismatches in the transistor components, the digital line can become unbalanced before voltage changes on the amplified digital line are achieved. Such threshold voltage deviations can cause the sense amplifier to incorrectly amplify the input signal.

[0007] To address the aforementioned threshold voltage deviation, a sensing amplifier designed to mitigate threshold voltage mismatch has been developed. However, such voltage compensation for different operations in response to different commands (e.g., the activation command "ACT" and the automatic refresh command "AREF") can introduce undesirable effects. Therefore, voltage compensation for variations across operations is desirable. Summary of the Invention

[0008] This document discloses apparatus and methods for power supply control of a threshold voltage compensated sense amplifier. An example apparatus according to embodiments of this disclosure may include a sense amplifier and a power supply circuit. The sense amplifier may be coupled to a pair of digital lines and further coupled to a first power node. The sense amplifier may amplify the voltage difference between the pair of digital lines. The power supply circuit may receive a power supply voltage. The power supply circuit may provide the power supply voltage based on a first drive strength in a first memory operation, and may additionally provide the power supply voltage based on a second drive strength in a second memory operation.

[0009] Another example device according to an embodiment of this disclosure may include a command decoder circuit, a fuse logic circuit, and a control circuit. The command decoder circuit may provide an internal command signal. The fuse logic circuit may store drive strength information and, based on the drive strength information, provide a first plurality of drive strength control signals, a second plurality of drive strength control signals, and a third plurality of drive strength control signals. The control circuit may include a timing logic circuit, a plurality of selectors, and a control signal generator circuit. The timing logic circuit may receive the internal command signal, provide a first timing signal indicating a threshold voltage compensation phase and a second timing signal indicating a sense amplifier enable phase, and may additionally provide a selection signal in response to the internal command signal. The plurality of selectors may receive the second plurality of drive strength control signals and the third plurality of drive strength control signals, and may additionally provide either the second plurality of drive strength control signals or the third plurality of drive strength control signals in response to the selection signal. The control signal generator circuit may receive the first timing signal, the second timing signal, and the first plurality of drive strength control signals from the fuse logic circuit, and receive either the second plurality of drive strength control signals or the third plurality of drive strength control signals from the plurality of selectors, and may additionally provide a plurality of control signals. The control signal generator circuit can provide the plurality of control signals based on the first plurality of drive strength control signals in response to a first timing signal, and can also provide the plurality of control signals based on the second plurality of drive strength control signals or the third plurality of drive strength control signals from the plurality of selectors in response to a second timing signal.

[0010] An example method for power supply control of a threshold voltage compensated sense amplifier according to embodiments of the present disclosure may include: receiving a power supply through a power supply circuit; setting a first drive strength of the power supply circuit for a first memory operation; setting a second drive strength of the power supply circuit for a second memory operation; and providing power to a first power node based on the drive strength, wherein the first power node is coupled to the sense amplifier. Attached Figure Description

[0011] Figure 1 This is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 This is a schematic diagram of a sense amplifier and a pair of complementary digital lines according to an embodiment of the present disclosure.

[0013] Figure 3A This is a schematic diagram of an apparatus including a sense amplifier and a power supply circuit according to an embodiment of the present disclosure.

[0014] Figure 3B This is a schematic diagram of a power supply circuit according to an embodiment of the present disclosure.

[0015] Figure 3C This is a schematic diagram of a device including a sense amplifier according to an embodiment of the present disclosure.

[0016] Figure 3D This is a path according to embodiments of the present disclosure. Figure 3C The truth table of the combination of control signals of the sensing amplifier.

[0017] Figure 4A This is a schematic diagram of a device including a drive intensity control circuit according to an embodiment of the present disclosure.

[0018] Figure 4B This is a circuit diagram of the control signal generator circuit in the drive intensity control circuit according to an embodiment of the present disclosure.

[0019] Figure 5A and 5B It is a timing diagram of various signals related to the operation of the sense amplifier and the control of voltage compensation intensity according to embodiments of the present disclosure.

[0020] Figure 6A and 6B This is a timing diagram of various signals during the operation of the sense amplifier according to an embodiment of the present disclosure.

[0021] Figure 7 This is a schematic diagram of a drive intensity control circuit according to an embodiment of the present disclosure.

[0022] Figure 8A and 8B It is a timing diagram of various signals related to the operation of the sense amplifier and the control of voltage compensation intensity according to embodiments of the present disclosure. Detailed Implementation

[0023] Various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of this disclosure by means of the illustrations. The detailed description contains sufficient detail to enable those skilled in the art to practice embodiments of this disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made, without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0024] Figure 1 This is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a clock input circuit 105, an internal clock generator 107, an address command input circuit 115, an address decoder 120, a command decoder 125, multiple row (e.g., first access line) decoders 130, a memory cell array 145 including a sense amplifier 150 and a transmission gate 195, multiple column (e.g., second access line) decoders 140, multiple read / write amplifiers 165, input / output (I / O) circuitry 170, and a voltage generator 190. The semiconductor device 100 may include multiple external terminals, including address and command terminals coupled to a command / address bus 110, clock terminals CK_t and CK_c, data terminals DQ, DQS, and DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ. Terminals and signal lines associated with the command and address bus 110 may include common terminals and signal lines configured to receive both command signals and address signals. In some instances, the terminals and signal lines associated with the command and address bus 110 may include a first set of terminals and signal lines configured to receive command signals, and a separate second set of terminals and signal lines configured to receive address signals. The semiconductor device may be mounted on a substrate such as a memory module substrate, a motherboard, etc.

[0025] The memory cell array 145 comprises multiple groups BANK0-N, where N is a positive integer, such as 3, 7, 15, 31, etc. Each group BANK0-N may contain multiple word lines WL, multiple digital lines DL and DLb, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple digital lines DL / DLb. The selection of the word lines WL for each group BANK0-N is performed by the corresponding row decoder 130, and the selection of the digital lines DL / DLb is performed by the corresponding column decoder 140. Multiple sense amplifiers 150 are coupled to their corresponding digital lines DL and DLb, and are coupled to at least one corresponding local I / O line, which is further coupled to a corresponding one of at least two main I / O line pairs via a transmission gate TG 195 acting as a switch. The sense amplifier 150 and the transfer gate TG 195 can operate based on control signals from a decoder circuitry that may include any control circuitry of a command decoder 120, a row decoder 130, a column decoder 140, a memory cell array 145 of groups BANK0-N, or any combination thereof.

[0026] In some instances, multiple sense amplifiers 150 may include a threshold voltage compensation circuitry system that compensates for threshold voltage differences between components of the sense amplifier 150. As circuit components become smaller, clock speeds increase, and voltage / power consumption requirements decrease, performance differences between circuit components of the sense amplifier 150 can reduce the operational reliability of the semiconductor device 100. To mitigate the effects of these variations, compensation for some of these threshold voltage Vt differences may include biasing an internal (sensing) node of the sense amplifier 150, coupled to digital lines DL and DLb and configured to provide amplified data to an output node, before activating the sense amplifier 150 to sense data. The bias of the internal node may be based on the threshold voltage difference between at least two circuit components (e.g., transistors) of the sense amplifier 150. Compensating for the threshold voltage Vt improves reliability by addressing the differences between circuit components within the sense amplifier 150.

[0027] Address / command input circuit 115 can receive address signals and group address signals from the outside via command / address bus 110 at the command / address terminal, and transmit the address signals and group address signals to address decoder 120. Address decoder 120 can decode the address signals received from address / command input circuit 115, and provide row address signal XADD to row decoder 130 and column address signal YADD to column decoder 140. Address decoder 120 can also receive group address signals and provide group address signal BADD to row decoder 130 and column decoder 140.

[0028] Address / command input circuitry 115 can receive command signals from an external source, such as memory controller 105 at the command / address terminal, via command / address bus 110, and provide the command signals to command decoder 125. Command decoder 125 can decode the command signals and generate various internal command signals. Internal command signals can be used to control the operation and timing of various circuits in semiconductor device 100. For example, internal command signals may include row and column command signals (e.g., read commands or write commands) to control circuitry to perform access operations on selected word lines and digital lines.

[0029] Therefore, when activation and read commands are issued and supplied to the row and column addresses in a timely manner, read data is read from the memory cells specified by the row and column addresses in the memory cell array 145. The read / write amplifier 165 receives the read data DQ and provides it to the I / O circuit 170. The I / O circuit 170 provides the read data DQ, along with a data strobe signal at DQS and a data mask signal at DM, to the outside via data terminals DQ, DQS, and DM. Similarly, when activation and write commands are issued and supplied to the row and column addresses in a timely manner, the input / output circuit 170 receives the write data at the data terminals DQ, DQS, and DM, along with a data strobe signal at DQS and a data mask signal at DM, and provides the write data to the memory cell array 145 via the read / write amplifier 165. Therefore, write data can be written to the memory cells specified by the row and column addresses.

[0030] For each memory bank BANK0-7, a group logic circuit 126 may be included. The group logic circuit 126 may allow the local generation of one or more row addresses at memory banks BANK0-7 in response to an auto-refresh command AREF during an auto-refresh operation. In some embodiments, the group logic circuit 126 may receive an internal command signal from a command decoder 125. The group logic circuit 126 may include a timing logic circuit 127 and an AREF detection logic circuit 128. The AREF detection logic circuit 128 may be included in the timing logic circuit 127. The AREF detection logic circuit 128 may determine whether the internal command signal is an auto-refresh command AREF indicative of an auto-refresh operation. A fuse logic circuit 129 may store drive strength information regarding the drive strength of transistors in the sense amplifier 150. The fuse logic circuit 129 may provide drive strength information regarding the drive strength of transistors. For example, the fuse logic circuit 129 may provide drive strength control signals SelNSA and SelPSA indicating drive strength information regarding the drive strength of transistors during a sense amplifier enable phase. The fuse logic circuit 129 may also provide drive strength control signals SelVtcNSA and SelVtcPSA, indicating drive strength information regarding the transistor's drive strength during the threshold voltage compensation (VtC) phase in response to the activation command ACT. Furthermore, the fuse logic circuit 129 may provide drive strength control signals SelVtcAREFNSA and SelVtcAREFPSA, indicating drive strength information regarding the transistor's drive strength during the threshold voltage compensation (VtC) phase in response to the automatic refresh command AREF. The group logic circuit 126 may, in response to the drive strength control signals, provide transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar to the sense amplifier power control circuit 135. The activation of the transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar is controlled by the timing logic circuit 127 and the AREF detection logic circuit 128. The sense amplifier power control circuit 135 can provide control signals PSA1, PSA2, PSA3bar, NSA1, NSA2 and NSA3 to the sense amplifier 150 in the memory cell array 145.

[0031] Turning to the explanation of the external terminals included in semiconductor device 100, clock terminals CK_t and CK_c can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to clock input circuit 105. Clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 105 can provide the internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and a clock start signal CKE from address / command input circuit 115. While not limited thereto, a DLL circuit can be used as internal clock generator 107. Internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to IO circuit 170. IO circuit 170 can use the phase controller internal clock signal LCLK as a timing signal to determine the output timing for reading data.

[0032] The power supply terminals can receive power supply voltages VDD, VPP, and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 190. Voltage generator circuit 190 can generate various internal voltages VDD2, VOD, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. Voltage VPP is mainly used in line decoder 130, internal voltages VDD2, VOD, and VARY are mainly used in sense amplifier 150 contained in memory cell array 145, and internal voltage VPERI is used in many other circuit blocks. I / O circuit 170 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in I / O circuit 170.

[0033] Figure 2 This is a schematic diagram of a portion of a memory 200 including a sense amplifier 210 and a pair of complementary digital lines DL 220 and DLb221 according to an embodiment of the present disclosure. Figure 2As shown, the sense amplifier 210 is coupled to the pair of true and complementary digital (or bit) lines DL 220 and DLb 221 at sense nodes 230 and 231, respectively. Memory cells 240(0)-(N) can be selectively coupled to digital line DL 220 via corresponding access devices (e.g., transistors) 250(0)-(N), and memory cells 241(0)-(N) can be selectively coupled to digital line DLb 221 via corresponding access devices (e.g., transistors) 251(0)-(N). Word lines WL 260(0)-(N) can be controlled to determine which of the memory cells 240(0)-(N) is coupled to digital line DL 220 by controlling the gate of the corresponding access device 250(0)-(N). Similarly, word lines WL 261(0)-(N) can control which of the memory cells 241(0)-(N) is coupled to the digital line DLb 221 by controlling the gates of the corresponding access devices 251(0)-(N). The sense amplifier 210 can be controlled via a control signal 270 received through a decoder circuit, which, for example, commands a decoder (e.g., Figure 1 Command decoder 125), line decoder (e.g., Figure 1 The row decoder 130), column decoder (e.g., Figure 1 The column decoder 140), memory array control circuitry (e.g., Figure 1 The control circuitry of the memory cell array 145 of the memory group BANK0-N or any combination thereof.

[0034] In some instances, memory 200 may operate in a general phase or mode. A first phase (e.g., a precharge phase) may be initiated in response to a precharge command. During the precharge phase, word lines WL 260(0)-(N) and 261(0)-(N) may be set to an inactive state, and in response, all access devices 250(0)-(N) and 251(0)-(N) may be disabled. Additionally, digital lines DL 220 and DLb 221 and the internal nodes of sense amplifier 210 may be precharged to a level higher than maintained at a precharge voltage, such as the digital line precharge voltage VBLP, until transition to the second phase.

[0035] In some instances, the sense amplifier 210 includes a threshold voltage compensation circuitry that compensates for threshold voltage mismatch between components of the sense amplifier 210 during a threshold voltage compensation phase. To perform threshold voltage compensation, the sense amplifier 210 may apply a bias to its sensing nodes 230 and 231 during the threshold voltage compensation phase, such that the voltage difference between sensing nodes 230 and 231 is approximately equal to the threshold voltage difference between at least two circuit components of the sense amplifier 210. In some instances, the threshold voltage difference may be based on the threshold voltage of a transistor in the sense amplifier 210. Compensation for the threshold voltage Vt difference between circuit components within the sense amplifier 210 improves reliability and accuracy.

[0036] The third stage can be a cell information sampling stage. During the sampling stage, word lines WL 260(0)-(N) and 261(0)-(N) can be set to an active state, and in response, access devices in access devices 250(0)-(N) and 251(0)-(N) can be enabled to couple the corresponding memory cells in memory cells 240(0)-(N) and 241(0)-(N) to one of digital lines DL 220 and DLb 221. When activated, the memory cells provide the stored data state in the form of voltage (and / or charge) to the digital lines and to the sensing nodes in the sensing amplifier 210 coupled to the digital lines.

[0037] The fourth stage can be the sense amplifier activation stage. The sense amplifier 210 can be activated to perform a sensing operation to sense the data state of the activated memory cell. That is, during the sensing operation, the sense amplifier 210 senses and amplifies the data state stored in the activated memory cell to drive one of the digital lines DL 220 or DLb 221 to a high or low voltage level corresponding to the sensed data state, and drives the other digital line of DL 220 and DLb 221 to a complementary (opposite) voltage level. The circuitry of the memory 200 can remain in the activation stage or can switch back to the precharge stage in response to a precharge command.

[0038] Reference memory cells 240(0)-(N), in response to the corresponding word line 260(0)-(N) becoming active, memory cells in memory cells 240(0)-(N) are coupled to digital line DL 220 via corresponding access means 250(0)-(N). The data state stored in the memory cells is sensed and amplified by sense amplifier 210 to drive digital line DL 220 to a high or low voltage level corresponding to the sensed data state. During sensing operation, another digital line DLb 221 is driven to a complementary voltage level (e.g., high voltage level is complementary to low voltage level, and low voltage level is complementary to high voltage level). Similarly, in response to the corresponding word line 261(0)-(N) becoming active, memory cells in memory cells 241(0)-(N) are coupled to digital line DLb 221 via corresponding access means 251(0)-(N). The data state stored in the memory cell is sensed and amplified by the sensing amplifier 210 to drive the digital line DLb 221 to a high or low voltage level corresponding to the sensed data state. During sensing operation, another digital line DL 220 is driven to a complementary voltage level.

[0039] During threshold voltage compensation operation, sensing nodes 230 and 231 of sensing amplifier 210 may be isolated from each other in response to a control signal 270 (e.g., from decoder circuitry). For example, during a pre-charge phase, sensing nodes 230 and 231 of sensing amplifier 210 may be coupled to each other and coupled to a pre-charge voltage to be pre-charged to that voltage. When sensing nodes 230 and 231 of sensing amplifier 210 are pre-charged, the control signal 270 may configure sensing amplifier 210 to isolate sensing nodes 230 and 231 from each other. A voltage difference may then be generated at sensing nodes 230 and 231 to provide threshold voltage compensation.

[0040] Figure 3A This is a schematic diagram of a device 30 including a sensing amplifier 31 and a power supply circuit 300 according to an embodiment of the present disclosure. The sensing amplifier 31 may be included in... Figure 1 The sensing amplifier 150 and / or Figure 2 One or more of the sensing amplifiers 210. As previously described, sensing amplifier 31 can drive digital line DL to a high or low voltage level corresponding to the sensed data state. Sensing amplifier 31 can also drive another digital line DLb to a complementary voltage level during sensing operation (e.g., a high voltage level is complementary to a low voltage level and a low voltage level is complementary to a high voltage level). In some embodiments of this disclosure, digital line DL may represent Figure 2 The digital line DL 220, and the digital line DLb can represent the digital line DLb 221.

[0041] The sense amplifier 31 can be coupled to a common node PCOM 320 and further coupled to another common node NCOM 330. The common node PCOM 320 can receive the array power supply voltage VARY. The other common node NCOM 330 can receive another power supply voltage VSS (e.g., ground voltage, or a negative power supply voltage). The power supply circuit 300 can provide the array power supply voltage VARY to the common node PCOM 320 during the threshold voltage compensation (VtC) phase and the sense amplifier enable phase. The power supply circuit 300 can also provide another power supply voltage VSS to the common node NCOM 330 during the threshold voltage compensation (VtC) phase and the sense amplifier enable phase. The power supply circuit 300 can provide an equalization voltage VARY / 2 to both the common nodes PCOM 320 and NCOM 330.

[0042] As will be described below, the power supply circuit 300 can provide a power supply voltage to the sense amplifier 31 that is controlled differently depending on memory operations. For example, compared to other sense amplifier designs, the power supply circuit 300 can provide a more finely tuned drive strength to the sense amplifier 31 for different memory operations. In some embodiments of this disclosure, the drive strength is adjustable across a threshold voltage compensation (VtC) phase in response to the activation command ACT, a further VtC phase in response to the automatic refresh operation AREF, and a sense amplifier enable phase in response to a control signal. Therefore, in a device with a sense amplifier according to embodiments of this disclosure (including...) Figure 3A In the device 30), the power supply circuit 300 can operate across different memories, such as memory activation notified by the activation command ACT and automatic refresh operation notified by the automatic refresh command AREF, providing the sense amplifier 31 with a more finely tuned threshold voltage compensation.

[0043] Figure 3B This is a schematic diagram of a power supply circuit 300 according to an embodiment of the present disclosure. The power supply circuit 300 may include a positive power control circuit 32, a negative power control circuit 33, and an equalization circuit 34.

[0044] The positive power supply control circuit 32 may receive a positive power supply voltage, such as the array voltage VARY. The positive power supply control circuit 32 may also receive one or more control signals PSA. Depending on the one or more control signals PSA, the positive power supply control circuit 32 may adjust the drive strength when providing the positive power supply voltage to the common node PCOM. In some embodiments, during the threshold voltage compensation (VtC) phase, the drive strength may be increased in response to the activity command ACT and decreased in response to the automatic refresh command AREF. In another embodiment, during the sense amplifier enable phase, the drive strength may be increased in response to the activity command ACT and decreased in response to the automatic refresh command AREF.

[0045] The negative power supply control circuit 32 may receive a negative power supply voltage VSS (e.g., ground voltage, or negative power supply voltage). The negative power supply control circuit 33 may also receive one or more control signals NSA. Depending on the one or more control signals NSA, the negative power supply control circuit 33 may adjust the drive strength when providing the negative power supply voltage to the common node NCOM. In some embodiments, during a threshold voltage compensation (VtC) phase, the drive strength may be decreased in response to an activity command ACT, and increased in response to an automatic refresh command AREF. In another embodiment, during a sense amplifier enable phase, the drive strength may be increased in response to an activity command ACT, and decreased in response to an automatic refresh command AREF.

[0046] The equalization circuit 34 can receive a control signal SAEQ and an equalization voltage, such as half of the array voltage, VARY / 2. The control signal SAEQ can be activated during the cell information sampling phase, after the threshold voltage compensation (VtC) phase and before the sense amplifier enable phase. In response to the active control signal SAEQ, the equalization circuit 34 can couple common nodes PCOM 320 and NCOM 330 and provide the equalization voltage VARY / 2 to both common nodes PCOM 320 and NCOM 330.

[0047] Figure 3C This is a schematic diagram of a device 30' including a sensing amplifier 31' according to an embodiment of the present disclosure. Device 30' may be... Figure 3A The device 30 and the sensing amplifier 31' can be Figure 3A The sensing amplifier 31. The sensing amplifier 31' may be included in Figure 1 The sensing amplifier 150 and / or Figure 2 One or more of the sensing amplifiers 210.

[0048] The sense amplifier 31' includes transistors 310 and 311 of a first type (e.g., p-type field-effect transistors (PFETs)) having drains coupled to nodes 353 and 354, respectively. The sense amplifier 31' further includes transistors 312 and 313 of a second type (e.g., n-type field-effect transistors (NFETs)) having drains coupled to nodes 353 and 354, respectively. Nodes 353 and 354 may be configured to be coupled to (sensing) nodes 314 and 315, respectively, via isolation transistors 351 and 352. The sources of isolation transistors 351 and 352 are coupled to nodes 314 and 315, respectively, and the drains of transistors 351 and 352 are coupled to nodes 353 and 354, respectively. Nodes 353 and 354 may be further configured to be coupled to (sensing) nodes 315 and 314, respectively, via transistors 355 and 356. The gates of transistors 355 and 356 can receive a control signal BLCP, which becomes active during the pre-charge phase and during the threshold voltage compensation (VtC) phase. The sources of isolation transistors 351 and 352 are coupled to nodes 314 and 315, respectively, and the drains of isolation transistors 351 and 352 are coupled to nodes 353 and 354, respectively. The gates of transistors 312 and 313 are coupled to nodes 315 and 314, respectively. The gates of transistors 310 and 311 are configured to be coupled to nodes 315 and 314, respectively, via isolation transistors 351 and 352. The gates of isolation transistors 351 and 352 can receive an isolation control signal ISO, which becomes inactive during the VtC phase until a phase when the sense amplifier 31' is enabled.

[0049] The sources of transistors 310 and 311 are coupled to a common node PCOM 320, which is configured to receive an array of power supply voltages VARY by providing combined drive strength through a plurality of transistors. For example, in Figure 3C In one embodiment, the positive power supply circuit 32' includes transistors 321, 322, and 323 coupled to a common node PCOM 320. Transistors 321, 322, and 323, when activated, can provide the array power supply voltage VARY to the common node PCOM 320 under combined drive strength. However, with... Figure 3C Compared to the number of transistors shown in the specific examples, other embodiments of this disclosure may include more or fewer transistors coupled to a common node PCOM 320 constituting a positive power supply circuit 32'. The sources of transistors 312 and 313 are coupled to a common node NCOM 330, which is configured to receive another power supply voltage VSS (e.g., ground voltage, or a negative power supply voltage) through a plurality of transistors providing combined drive strength. For example, in Figure 3CIn one embodiment, the negative power supply circuit 33' includes transistors 331, 332, and 333 coupled to a common node NCOM 330. Transistors 331, 332, and 333, when activated, can provide a power supply voltage VSS to the common node NCOM 330 under combined drive strength. However, with... Figure 3C Compared to the number of transistors shown in the specific examples, other embodiments of this disclosure may include more or fewer transistors coupled to the common node NCOM 330 constituting the negative power supply circuit 33'. Digital line DL is coupled to node 314 and digital line DLb is coupled to node 315. In some embodiments of this disclosure, digital line DL may represent... Figure 2 The digital line DL 220 and the digital line DLb can represent the digital line DLb 221, and the nodes 314 and 315 can represent the sensing nodes 230 and 231, respectively.

[0050] The sense amplifier 31' further includes a precharge transistor 319 coupled to node 353. In this embodiment, transistor 319 is coupled to node 353; however, in some embodiments, transistor 319 may additionally or alternatively be coupled to node 354. During the precharge phase, transistor 319 provides a voltage from its source to node 353 when activated by an active control signal BLPR (e.g., a high logic level). In some embodiments of this disclosure, when transistor 319 is active, a voltage VARY / 2, approximately half the array power supply voltage VARY, may be provided to node 353.

[0051] For example, in Figure 3C In this embodiment, the equalization circuit 34' includes transistors 316, 317, and 318 that can be activated by a control signal SAEQ. The control signal SAEQ can be activated first during the pre-charge phase and secondly after the VtC phase is completed and before the sense amplifier enable phase begins. When activated by the active control signal SAEQ, transistor 318 provides a conductive path between the common node PCOM 320 and another common node NCOM 330 to equalize the voltages of the respective nodes. Additionally, transistors 316 and 317, when activated by the active control signal SAEQ, can provide a voltage VARY / 2 to the common nodes PCOM 320 and NCOM 330.

[0052] Transistors 321, 322, and 323 in the positive power supply circuit 32' have one node configured to receive changes in the array power supply voltage and another node coupled to a common node PCOM 320; therefore, transistors 321, 322, and 323 are coupled in parallel to each other. Transistors 321, 322, and 323 have gates that can receive control signals PSA1, PSA2, and PSA3bar, respectively. Control signals PSA1 and PSA2 may have a voltage range (e.g., voltage swing) from another power supply voltage VSS (e.g., ground voltage, or negative power supply voltage) to a power supply voltage VDD2 higher than the power supply voltage VDD. Control signal PSA3bar is complementary to control signal PSA3 and may have a voltage range from the power supply voltage VSS to the power supply voltage VDD. In some embodiments, the drive strength of transistor 321 (e.g., capacitance per unit time) may be about four times that of transistor 323, and the drive strength of transistor 322 (e.g., capacitance per unit time) may be about twice that of transistor 323.

[0053] Transistors 331, 332, and 333 in the negative power supply circuit 33' have one node configured to receive the power supply voltage VSS (e.g., ground voltage, or negative power supply voltage) and another node coupled to a common node NCOM 330, thus transistors 331, 332, and 333 are coupled in parallel to each other. Transistors 331, 332, and 333 have gates that can receive control signals NSA1, NSA2, and NSA3, respectively. Control signals NSA1, NSA2, and NSA3 may have a voltage range (e.g., voltage swing) from the power supply voltage VSS to the power supply voltage VDD. In some embodiments, the drive strength (e.g., capacitance per unit time) of transistor 331 may be about four times that of transistor 333, and the drive strength (e.g., capacitance per unit time) of transistor 332 may be about twice that of transistor 333.

[0054] In some embodiments, transistors 321 and 322 may be NFETs and transistor 323 may be a PFET. In some embodiments, transistors 331, 332, and 333 may be NFETs. Transistors 310 and 311 are shown as PFETs and transistors 312, 313, 316, 317, 318, 319, 351, 352, 355, and 356 are shown as NFETs in FIG3. However, without departing from the scope of this disclosure, one or more of the transistors may be changed to different conductivity types and / or changed to different transistors, changing to different circuits.

[0055] As will be described below, device 30' can provide threshold voltage compensation for sense amplifier 31'. Device 30' can provide advantages over conventional device sense amplifiers through threshold voltage compensation. For example, compared to other sense amplifier designs, device 30' or associated circuitry can provide a more finely tuned drive strength to sense amplifier 31 for different memory operations by activating a combination of transistors 321, 322, 323, 331, 332, and 333. In some embodiments of this disclosure, the drive strength is adjustable across a threshold voltage compensation (VtC) phase in response to the activation command ACT, a VtC phase further in response to the automatic refresh operation AREF, and a sense amplifier enable phase in response to a control signal. Variations including changing any transistor to a different type, a different size, a different circuit, and / or a different number of transistors other than transistors 321, 322, and 323 or transistors 331, 332, and 333 are within the scope of this disclosure. Therefore, devices with sense amplifiers according to embodiments of this disclosure (including Figure 3C The device 30' can operate across different memories, such as memory activation notified by the activation command ACT and automatic refresh operation notified by the automatic refresh command AREF, providing more finely tuned threshold voltage compensation to the sensing amplifier 31'.

[0056] Figure 3D According to embodiments of this disclosure Figure 3C The truth table of the combination of control signals in the sensing amplifier.

[0057] For example, when all control signals PSA1, PSA2, PSA3, NSA1, NSA2, and NSA3 are set to logic low (off) and PSA3 is set to logic high, the combined drive strength is 0%. When control signals PSA3 and NSA3 are set to logic high (on) and the other control signals are set to off, transistors 323 and 333, which have a drive strength of 1 from (4+2+1), are conductive, so the combined drive strength is 1 / 7 = 14.3%. When control signals PSA2 and NSA2 are set to logic high (on) and the other control signals are set to off, transistors 322 and 332, which have a drive strength of 2 from (4+2+1), are conductive, so the combined drive strength is 2 / 7 = 28.6%. When control signals PSA2, PSA3 and NSA2, NSA3 are set to logic high (on) and other control signals are set to off, transistors 322, 332, and 333, with a drive strength of 3 (4+2+1), are conductive. Therefore, the combined drive strength is (1+2) / 7 = 42.9%. When control signals PSA1 and NSA1 are set to logic high (on) and other control signals are set to off, transistors 321 and 331, with a drive strength of 4 (4+2+1), are conductive. Therefore, the combined drive strength is 4 / 7 = 57.1%. When control signals PSA1, PSA3 and NSA1, NSA3 are set to logic high (on) and other control signals are set to off, the combined drive strength is (4+1) / 7 = 71.4%. When control signals PSA1, PSA2 and NSA1, NSA2 are set to logic high (on) and other control signals are set to off, the combined drive strength is (4+2) / 7 = 85.7%. When all control signals PSA1, PSA2, PSA3, NSA1, NSA2, and NSA3 are set to logic high (off) and PSA3 is set to logic low, the combined drive strength is 100%. In this way, the combination of control signals and different drive strengths of the transistors can provide adjustable drive strength. Different drive strengths can be used between the threshold voltage compensation stage and the sense amplifier enable stage. Furthermore, by providing control signals with different activation combinations across different memory operations, different drive strengths can be provided to the sense amplifier during the threshold voltage compensation stage in response to different commands (e.g., activation command ACT and auto-refresh command AREF).

[0058] Figure 4A This is a schematic diagram of a device including a drive intensity control circuit 40 according to an embodiment of the present disclosure. The drive intensity control circuit 40 may be included in Figure 1 In the peripheral region of the semiconductor device 100. For example, Figure 1 The group logic circuit 126 may include drive strength control circuitry 40. Alternatively, Figure 1The line decoder 130 may include group logic circuitry, which includes drive strength control circuitry 40. The command decoder 41 may provide internal command signals to the drive strength control circuitry 40. For example, the command decoder 41 may be... Figure 1 The command decoder 125. For example, the internal command signals may include a command signal indicating activation in response to the activation command ACT and a command signal indicating an automatic refresh (AREF) operation.

[0059] The drive intensity control circuit 40 may include timing logic circuitry 402. Timing logic circuitry 402 may receive internal command signals from command decoder 41. In response to the internal command signals, timing logic circuitry 402 may provide a timing signal SAN / SAP that can be set to active during the sense amplifier enable phase, and a timing signal VtcSAN / VtcSAP that can be set to active during the threshold voltage compensation (VtC) phase.

[0060] The drive intensity control circuit 40 may include AREF detection logic circuit 402. For example, the AREF detection logic circuit may be... Figure 1 The AREF detection logic circuit 402 can receive internal command signals from the command decoder 41. For each internal command signal, the AREF detection logic circuit 402 can determine whether the internal command signal indicates an automatic refresh (AREF) command. If the internal command signal indicates an AREF command, then the AREF detection logic circuit 402 can provide an active selection signal SelVtcRef to multiple selectors 403 in the drive strength control circuit 40. If the internal command signal does not indicate an AREF command (e.g., a command indicating an intrinsic memory access operation), then the AREF detection logic circuit 402 can provide an inactive selection signal SelVtcRef to multiple selectors 403. The fuse logic circuit 42 can store drive strength information about the drive strength of transistors in the sense amplifier associated with the threshold voltage compensation phase and the sense amplifier enable phase. For example, the fuse logic circuit 42 can be fuse logic circuit 126. The fuse logic circuit 42 can provide drive strength control signals about the drive strength of transistors, for example, during the sense amplifier enable phase. Figure 3CDrive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA, and SelPSA3 associated with the drive strength of transistors 331, 332, 333, 321, 322, and 323. Fuse logic circuit 42 may additionally provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 associated with the drive strength of transistors 331, 332, 333, 321, 322, and 323 during the threshold voltage compensation (VtC) phase in response to the activation command ACT when an automatic refresh operation is not performed (e.g., when an intrinsic memory access operation is being performed). Furthermore, the fuse logic circuit 42 can provide drive strength control signals SelVtcAREFNSA1, SelVtcAREFNSA2, SelVtcAREFNSA3, SelVtcAREFPSA1, SelVtcAREFPSA2, and SelVtcAREFPSA3 associated with the drive strength of transistors 331, 332, 333, 321, 322, and 323 during the threshold voltage compensation (VtC) phase of the automatic refresh operation in response to the automatic refresh command AREF.

[0061] Multiple selectors 403 can receive selection signals SelVtcRef from AREF detection logic circuit 402 and drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, SelVtcPSA3, SelVtcAREFNSA1, SelVtcAREFNSA2, SelVtcAREFNSA3, SelVtcAREFPSA1, SelVtcAREFPSA2 and SelVtcAREFPSA3 from fuse logic circuit 42. In response to the inactive state of the selection signal SelVtcRef, which indicates an operation that is not an auto-refresh operation (e.g., in intrinsic memory operation one), multiple selectors 403 can provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3. In response to the active state of the selection signal SelVtcRef, which indicates an auto-refresh operation in response to the auto-refresh command AREF, multiple selectors 403 can provide drive strength control signals SelVtcAREFNSA1, SelVtcAREFNSA2, SelVtcAREFNSA3, SelVtcAREFPSA1, SelVtcAREFPSA2, and SelVtcAREFPSA3.

[0062] The drive intensity control circuit 40 may include multiple control signal generator circuits 404. The multiple control signal generator circuits 404 may receive timing signals, such as timing signals SAN / SAP and VtcSAN / VtcSAP, from the timing logic circuit 401. The multiple control signal generator circuits 404 may receive drive intensity control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 from the fuse logic circuit 42, which will be used during the sense amplifier enable phase. The multiple control signal generator circuit 404 may also receive from the multiple selectors 403 drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2 or drive strength control signals SelVtcAREFNSA1, SelVtcAREFNSA2, SelVtcAREFNSA3, SelVtcAREFPSA1, SelVtcAREFPSA2 and SelVtcAREFPSA3 to be used during the threshold voltage compensation phase. In response to the active timing signal SAN / SAP indicating that the sense amplifier is in the enabled phase, multiple control signal generator circuits 404 can provide inverted signals of drive strength control signals SelPSA1, SelPSA2, SelPSA3, SelNSA1, SelNSA2, and SelNSA3 as inverted transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar, respectively. In response to the active timing signal VtcSAN / VtcSAP indicating that the threshold voltage compensation phase is in the enabled phase, multiple control signal generator circuits 404 can provide inverted signals of the drive strength control signals received from multiple selectors 403 as inverted transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar, respectively.

[0063] Figure 4B This is a circuit diagram of one of the control signal generator circuits 404 in the drive intensity control circuit 40 according to an embodiment of the present disclosure. Figure 4BEach control signal generator circuit 404 in the circuit may receive timing signals from the timing logic circuit 401, such as a timing signal InSA indicating the sense amplifier enable phase and an InVtcSA indicating the threshold voltage compensation phase. The control signal generator circuit 404 may receive a drive strength control signal InSelSA to be used during the sense amplifier enable phase and an InSelVtcSA to be used during the threshold voltage compensation phase. The control signal generator circuit 404 provides an output signal OutSA to the transistor of the sense amplifier. The following logic equation provides the logical relationship between the output signal OutSA and the input signals, i.e., the timing signals InSA and InSelSA, and the drive strength control signals InSelSA and InSelVtcSA.

[0064] OutSA=! ((InVtcSA*InSelVtcSA)+(InSA*InSelSA))

[0065] The sense amplifier power control circuit 44 can receive inverted transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar and provide PSA1, PSA2, PSA3bar, NSA1, NSA2, and NSA3 to the sense amplifier 50 in the memory cell array 45. For example, the sense amplifier power control circuit 44, the memory cell array 45, and the sense amplifier 50 can be... Figure 1 The sensor amplifier power control circuit 135, memory cell array 145, and sensor amplifier 150 are included.

[0066] Multiple selectors 403 and multiple control signal generators 404 can be provided in the preprocessing of each control signal in the generation of control signals, which are transistor activation signals PSA1, PSA2, PSA3bar, NSA1, NSA2, and NSA3 provided from the sense amplifier power supply control circuit 44 to transistors 321, 322, 323, 331, 332, and 333. Therefore, in Figure 4A In the drive intensity control circuit 40, the number of multiple selectors 403 and multiple control signal generators 404 is six. However, the number of these circuits in the drive intensity control circuit 40 may vary depending on the number of transistors used to adjust the drive intensity of the sensing amplifier.

[0067] Figure 5A and 5B This is a timing diagram of various signals related to the operation of the sense amplifier and voltage compensation intensity control according to embodiments of this disclosure. For example, various signals in Figure 4A The drive intensity control circuit 40 is located within and around the drive intensity control circuit or provided with drive intensity control circuitry. Figure 3C The sensing amplifier 31'. In some embodiments, the fuse logic circuit (e.g. Figure 4A The fuse logic circuit 42) can provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2 and SelVtcPSA3 respectively set to logic level "high, high, low, high, high, high" and drive strength control signals SelVtcAREFNSA1, SelVtcAREFNSA2, SelVtcAREFNSA3, SelVtcAREFPSA1, SelVtcAREFPSA2 and SelVtcAREFPSA3 respectively set to logic level "high, high, high, high, high, low" and drive strength control signals SelPSA1, SelPSA2, SelPSA3, SelNSA1, SelNSA2 and SelNSA3 respectively set to logic level "high, high, high, high, high, high".

[0068] Figure 5AThis illustrates the levels of various signals in response to the activation command ACT during an intrinsic memory access operation, but not during an auto-refresh operation. In response to the activation command ACT, the internal command signal for activating the command ACT is set to logic high, while the internal command signal for the auto-refresh command AREF is set to logic low, and the selection signal SelVtcRef is set inactive (e.g., at logic low) by the AREF detection logic circuit 402. In response to the inactive selection signal SelVtcRef, multiple selectors 403 can provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 set to logic levels "high, high, low, high, high". During the threshold voltage compensation (VtC) phase, the timing logic circuit 401 provides timing signals VtcSAN / VtcSAP set to logic high and timing signals SAN / SAP set to logic low. Multiple control signal generator circuits 404 can provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 in response to the active timing signal VtcSAN / VtcSAP. The drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3, set to logic levels "high, high, low, high, high," cause the sense amplifier power supply control circuit 44 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar, respectively set to logic levels "high, high, low, high, high, low," which causes... Figure 3C The combined drive strength of transistors 331, 332, and 333 in the transistors is 85.6%. Figure 3CThe transistors 321, 322, and 323 in the sensor amplifier are driven at 100% combined strength. During the sense amplifier enable phase, timing logic circuit 401 provides timing signals VtcSAN / VtcSAP set to logic low and SAN / SAP set to logic high. Multiple control signal generator circuits 404 can provide drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 in response to the active timing signal SAN / SAP. The drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 set to logic levels "high, high, high, high, high, high" cause the sense amplifier power supply control circuit 44 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar set to logic levels "high, high, high, high, high, low" respectively, which causes Figure 3C The combined drive strength of transistors 331, 332, 333, 321, 322 and 323 in the transistors is 100%.

[0069] Figure 5B This shows the levels of various signals in response to the activation command ACT during automatic refresh operation. For example... Figure 5BAs shown, in response to the auto-refresh command AREF, in addition to the internal command signal for the activation command ACT being set to a logic high level, the internal command signal for the auto-refresh command AREF is also set to a logic high level, and the AREF detection logic circuit 402 provides a selection signal SelVtcRef that is set to be active (e.g., at a logic high level). In response to the active selection signal SelVtcRef, multiple selectors 403 can provide drive strength control signals SelVtcAREFNSA1, SelVtcAREFNSA2, SelVtcAREFNSA3, SelVtcAREFPSA1, SelVtcAREFPSA2, SelVtcAREFPSA3 set to logic levels "high, high, high, high, high, low" instead of drive control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, SelVtcPSA3. During the threshold voltage compensation (VtC) phase, timing logic circuit 401 provides timing signals VtcSAN / VtcSAP set to logic high and SAN / SAP set to logic low. Multiple control signal generator circuits 404 can provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 set to logic levels "high, high, high, high, high, low" in response to the active timing signals VtcSAN / VtcSAP. Figure 5B The drive strength control signals SelVtcAREFNSA1, SelVtcAREFNSA2, SelVtcAREFNSA3, SelVtcAREFPSA1, SelVtcAREFPSA2, and SelVtcAREFPSA3, respectively, cause the sense amplifier power supply control circuit 44 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar, respectively, set to logic levels "high, high, high, high, high, high". This causes... Figure 3C The 100% combined drive strength of transistors 331, 332, and 333 in the middle and Figure 3CThe transistors 321, 322, and 323 in the sensor amplifier have a combined drive strength of 85.6%. During the sense amplifier enable phase, timing logic circuit 401 provides timing signals VtcSAN / VtcSAP set to logic low and timing signal SAN / SAP set to logic high. Multiple control signal generator circuits 404 can provide drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 in response to the active timing signal SAN / SAP. The drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 set to logic levels "high, high, high, high, high, high" cause the sense amplifier power supply control circuit 44 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar set to logic levels "high, high, high, high, high, low" respectively, which causes Figure 3C The combined drive strength of transistors 331, 332, 333, 321, 322 and 323 in the transistors is 100%.

[0070] Figure 6A and 6B This is a timing diagram of various signals during the operation of a sense amplifier according to embodiments of the present disclosure. For example, the sense amplifier may be... Figure 3C The sensing amplifier 30' contains various signals, including control signals PSA1, PSA2, PSA3bar, NSA1, NSA2, and NSA3. Figure 3C The signals on the common nodes PCOM and NCOM within the sensing amplifier 30' and on the signal digital lines DL and DLb.

[0071] Figure 6AThis diagram shows the voltage levels of various signals during the threshold voltage compensation (VtC) phase and sense amplifier enable phase in response to the activation command ACT, when not in automatic refresh operation. Prior to time T1, the sense amplifier and digital lines have been pre-charged during the pre-charge phase. Transistor 319 is activated by the active control signal BLPR to provide voltage to node 353. For example, this voltage could be voltage VARY / 2, approximately half the array power supply voltage VARY. Prior to time T1, transistor 318 is activated by the active control signal SAEQ to provide a conductive path between common node PCOM 320 and another common node NCOM 330 to equalize the voltages of the respective nodes. Additionally, transistors 316 and 317 are activated by the active control signal SAEQ to provide voltage VARY / 2 to common nodes PCOM 320 and NCOM 330. Before time T1, the control signal ISO is at an active level (e.g., a power supply voltage VDD2 higher than the power supply voltage VDD, etc.) to activate transistors 351 and 352 to couple the conductive paths between nodes 314 and 353 and transistors 315 and 354, respectively. Isolation transistors 351 and 352 can couple nodes 353 and 354 to nodes 314 and 315, respectively, via the activated control signal ISO before T1, thus providing a voltage VARY / 2 to node 353 to node 314. Transistors 355 and 356 can be activated by the control signal BLCP, so the voltage VARY / 2 to node 353 is also provided to node 315 via transistor 355, and the voltage VARY / 2 to node 315 can be provided to node 354 via isolation transistor 352.

[0072] The operation in the second phase, the threshold voltage compensation (VtC) phase, between time T1 and T2, is described. After time T1, transistor 319 is deactivated by the inactive control signal BLPR (e.g., at ground level) to no longer supply voltage VARY / 2 to node 353. Transistors 316, 317, and 318 are deactivated by the inactive SAEQ signal to no longer supply voltage VARY / 2 to common nodes PCOM 320 and NCOM 330, and common nodes PCOM 320 and NCOM 330 are disconnected. After activation, control signals PSA1, PSA2, and PSA3bar, set to logic levels "high, high, low" with power supply voltages VDD2, VDD2, and VSS, are immediately supplied to transistors 321, 322, and 323, thereby giving common node PCOM 320 a higher voltage, closer to the array power supply voltage VARY. Upon activation, control signals NSA1, NSA2, and NSA3, set to logic levels "high, high, low" with power supply voltages VDD, VDD, and VSS, are immediately provided to transistors 331, 332, and 333, thereby giving the common node NCOM 330 a lower voltage, closer to the power supply voltage VSS. Here, the combined drive strength provided by transistors 321, 322, and 323 coupled to the common node PCOM 320 is approximately 100%, while the combined drive strength provided by transistors 331, 332, and 333 coupled to the common node NCOM 330 is approximately 85.6%, less than 100%, because transistor 333 is turned off.

[0073] The difference between the corresponding voltages at nodes 314 and 315 represents the sum of the threshold voltage offsets between the threshold voltages of transistors 310, 311, 312, and 313. Threshold voltage compensation can be provided between common nodes PCOM 320 and NCOM 330 (e.g., for transistors 310 and 311 and 312 and 313) by generating voltages at common nodes PCOM 320 and NCOM 330.

[0074] The next stage between time T2 and T3 is the third stage, the cell information sampling stage, where cell information sampling operations are performed. During this stage, control signals PSA1, PSA2, and PSA3, set to logic levels "low, low, high" with power supply voltages VSS, VDD, and VDD, are provided to transistors 321, 322, and 323, which stop providing the array power supply voltage VARY to the common node PCOM 320. Furthermore, control signals NSA1, NSA2, and NSA3, set to logic level "low" with the power supply voltage VSS, are provided to transistors 331, 332, and 333, which stop providing the power supply voltage VSS to the common node NCOM 330. Simultaneously, transistor 318 is activated by the active control signal SAEQ, providing a conductive path between the common nodes PCOM 320 and NCOM 330 to balance the corresponding node voltages. Additionally, transistors 316 and 317 are activated by the active control signal SAEQ, providing a voltage VARY / 2 to the common nodes PCOM 320 and NCOM 330. Therefore, the common nodes PCOM 320 and NCOM 330 have a voltage VARY / 2.

[0075] For example, as previously referenced Figure 2 As described, an access line (e.g., a word line) can be activated after time T2 (e.g., changed to a high voltage level) to couple a memory cell to a digital line DL or DLb. The memory cell coupled to the digital line DL or DLb causes a voltage change on the corresponding digital line based on the data state stored in the memory cell. For example, a memory cell can increase the voltage on the corresponding digital line when the stored data state corresponds to a positive charge stored in the memory cell. The change in the corresponding digital line DL or DLb from the memory cell is reflected at the corresponding node 314 or 315. Node 314 is coupled to the gate of the corresponding transistor 313 and node 315 is coupled to the gate of the corresponding transistor 312. Here, transistors 355 and 356 are continuously activated by the active control signal BLCP before time T2, and the threshold voltage Vt of transistor 312 can be observed at node 315.

[0076] After time T2, transistors 355 and 356 are deactivated by the inactive control signal BLCP after time T2. The drain of transistor 312 is disconnected from the gate and node 315 of transistor 312 through the deactivated transistor 355, and the drain of transistor 313 is disconnected from the gate and node 314 of transistor 313 through the deactivated transistor 356.

[0077] The next operation between times T3 and T4 is the fourth stage, the sense amplifier activation stage. Control signal ISO changes to an active level to activate transistors 351 and 352, thereby coupling the conductive paths between nodes 314 and 353 and nodes 315 and 354, respectively. After time T3, control signals PSA1, PSA2, and PSA3, set to logic levels "high, high, low" with power supply voltages VDD2, VDD2, and VSS, are provided to transistors 321, 322, and 323, giving the common node PCOM 320 a higher voltage, closer to the array power supply voltage VARY. After activation, control signals NSA1, NSA2, and NSA3, set to logic levels "high, high, high" with power supply voltages VDD, VDD2, and VDD3, are immediately provided to transistors 331, 332, and 333, giving the common node NCOM 330 a lower voltage, closer to the power supply voltage VSS. Here, transistors 321, 322, and 323 coupled to the common node PCOM 320 provide a combined drive strength of approximately 100%, while transistors 331, 332, and 333 coupled to the common node NCOM 330 provide a combined drive strength of approximately 100%.

[0078] By driving the sensing node and digital line to opposite voltage levels (e.g., high activation voltage and low) based on the voltage difference between digital lines DL and DLb, the corresponding voltages at common nodes PCOM 320 and NCOM 330 amplify this voltage difference. Transistors 331, 332, and 333 provide a greater drive strength to common node NCOM 330 than the drive strength given at the VtC stage (T1-T2). In this example, when the voltage of digital line DL is increased in the memory cell, transistor 313 is activated more than transistor 312 pulls down node 354. Therefore, digital line DLb begins to be pulled down to the low activation voltage (e.g., VSS) provided to the common power supply node, which in turn activates transistor 310 to pull up node 353. Transistors 321, 322, and 323 provide the same drive strength to common node PCOM 320 as the drive strength given at the VtC stage (T1-T2). Through the positive feedback loops of transistors 313 and 310, node 354 is driven to a low activation voltage and node 353 is driven to a high activation voltage. Before time T4, access line WL becomes inactive (e.g., changes to an inactive (low) voltage level) to isolate the memory cell from digital line DL.

[0079] During the sense amplifier activation phase, the sense amplifier is activated by providing a high activation voltage and a low activation voltage, and the voltage difference between digital lines DL and DLb is amplified by driving digital lines DL and DLb to opposite activation voltages based on the voltage difference (e.g., caused by a memory cell coupled to a digital line). After the sense amplifier activation phase is completed, the operation returns to the pre-charge phase. The sense amplifier 300 is placed in the same pre-charge state as previously described at time T0 and is ready for another access operation.

[0080] Figure 6B This shows the voltage levels of various signals in response to the threshold voltage compensation (VtC) phase and the sense amplifier enable phase during automatic refresh operation in response to the activation command ACT. Before time T1, during the pre-charge phase, the various signals are... Figure 6A The various signals in the signal are activated or deactivated in a similar manner, so they are not repeated.

[0081] The operation in the second phase, the threshold voltage compensation (VtC) phase between time T1 and T2, is described. After time T1, transistor 319 is deactivated by the inactive control signal BLPR (e.g., at ground level) to no longer supply voltage VARY / 2 to node 353. Transistors 316, 317, and 318 are deactivated by the inactive SAEQ signal to no longer supply voltage VARY / 2 to common nodes PCOM 320 and NCOM 330, and common nodes PCOM 320 and NCOM 330 are disconnected. After activation, control signals PSA1, PSA2, and PSA3bar, set to logic levels "high, high, high" with power supply voltages VDD2, VDD2, and VDD, are immediately supplied to transistors 321, 322, and 323, thereby giving common node PCOM 320 a higher voltage, closer to the array power supply voltage VARY. Upon activation, control signals NSA1, NSA2, and NSA3, set to logic levels "high, high, high" with power supply voltages VDD, VDD, and VDD, are immediately provided to transistors 331, 332, and 333, thereby giving the common node NCOM 330 a lower voltage, closer to the power supply voltage VSS. Here, the combined drive strength provided by transistors 321, 322, and 323 coupled to the common node PCOM 320 is approximately 85.6% due to the high logic level of PSA3 bar given to transistor 323, while the combined drive strength provided by transistors 331, 332, and 333 coupled to the common node NCOM 330 is approximately 100%. Because the drive strength given to the common node NCOM 330 is larger and the drive strength given to the common node PCOM is smaller, therefore... Figure 6AAfter the VtC phase in the intrinsic memory access operation, the voltages of the common nodes PCOM320 and NCOM330 are lower than those of the common nodes PCOM320 and NCOM330. By generating voltages at the common nodes PCOM320 and NCOM330, it is possible to... Figure 6A The VtC phase in the inherent memory access operation shown provides threshold voltage compensation between the common nodes PCOM 320 and NCOM 330 in different ways (e.g., for transistors 310 and 311 and 312 and 313), and the voltages of digital lines DL and DLb are lower than those of digital lines DL and DLb in the VtC phase. Figure 6A The voltage following the VtC stage in the intrinsic memory access operation.

[0082] The difference between the corresponding voltages at nodes 314 and 315 can represent the sum of the signal difference on digital lines DL and DLb and the threshold voltage offset between the threshold voltages of transistors 310, 311, 312, and 313 at the common node PCOM 320 and NCOM 330. Therefore, threshold voltage compensation (e.g., for transistors 310 and 311 and 312 and 313) can be provided in addition to the signal difference.

[0083] The next stage between time T2 and T3 is the cell information sampling stage when the cell information sampling operation is performed. During this stage, control signals PSA1, PSA2, and PSA3bar cause transistors 321, 322, and 323 to stop providing the array power supply voltage VARY to the common node PCOM 320, and control signals NSA1, NSA2, and NSA3 cause transistors 331, 332, and 333 to stop providing the power supply voltage VSS to the common node NCOM 330. During operation, control signal SAEQ causes transistor 318 to equalize the corresponding node voltages of PCOM 320 and NCOM 330, and further causes transistors 316 and 317 to provide voltage VARY / 2 to the common nodes PCOM 320 and NCOM 330.

[0084] For example, as previously referenced Figure 2As described, an access line (e.g., a word line) can be activated after time T2 (e.g., changed to a high voltage level) to couple a memory cell to a digital line DL or DLb. The memory cell coupled to the digital line DL or DLb causes a voltage change on the corresponding digital line based on the data state stored in the memory cell. For example, a memory cell can increase the voltage on the corresponding digital line when the stored data state corresponds to a positive charge stored in the memory cell. The change in the corresponding digital line DL or DLb from the memory cell is reflected at the corresponding node 314 or 315. Node 314 is coupled to the gate of the corresponding transistor 313 and node 315 is coupled to the gate of the corresponding transistor 312. Although different segments (e.g., sense amplifiers and memory cell sets in a memory cell array) can be activated together, the voltages at common nodes PCOM 320 and NCOM 330 are set relative to, for example,... Figure 6A The VtC phase shown is closer to the power rail in the VtC phase during auto-refresh operation than during auto-refresh operation, so the sense amplifier reference voltage can be maintained across intrinsic memory access operations and auto-refresh operations.

[0085] exist Figure 6A and 6B In the examples, each of the control signals PSA1, PSA2, PSA3bar, NSA1, NSA2, and NSA3 is shown to have a specific timing and a specific voltage relative to the other voltages and control signals. However, embodiments of this disclosure include those different from the references. Figure 6A and 6B Other voltage and signal timings described are also included. Therefore, the scope of this disclosure is not limited to those voltage and signal timings. Figure 6A and 6B A specific instance of .

[0086] Figure 7 This is a schematic diagram of a drive intensity control circuit 70 according to an embodiment of the present disclosure. The drive intensity control circuit 70 may be included in... Figure 1 In the peripheral region of the semiconductor device 100. For example, Figure 1 The group logic circuit 126 may include drive strength control circuitry 70. Alternatively, Figure 1 The line decoder 130 may include group logic circuitry, which includes drive strength control circuitry 70. The command decoder 71 may provide internal command signals to the drive strength control circuitry 70. For example, the command decoder 71 may be... Figure 1 The command decoder 125. For example, the internal command signals may include a command signal indicating activation in response to the activation command ACT and a command signal indicating an automatic refresh (AREF) operation.

[0087] The drive intensity control circuit 70 may include timing logic circuitry 702. Timing logic circuitry 702 may receive internal command signals from command decoder 71. In response to the internal command signals, timing logic circuitry 702 may provide a timing signal SAN / SAP that can be set to active during the sense amplifier enable phase, and a timing signal VtcSAN / VtcSAP that can be set to active during the threshold voltage compensation (VtC) phase.

[0088] The drive intensity control circuit 70 may include AREF detection logic circuit 702. For example, the AREF detection logic circuit may be... Figure 1 The AREF detection logic circuit 702 can receive internal command signals from the command decoder 71. For each internal command signal, the AREF detection logic circuit 702 can determine whether the internal command signal indicates an automatic refresh (AREF) command. If the internal command signal indicates an AREF command, then the AREF detection logic circuit 702 can provide an active selection signal SelRef to multiple selectors 703 in the drive strength control circuit 70. If the internal command signal does not indicate an AREF command (e.g., a command indicating an intrinsic memory access operation), then the AREF detection logic circuit 702 can provide an inactive selection signal SelRef to multiple selectors 703. The fuse logic circuit 72 can store drive strength information about the drive strength of the transistors in the sense amplifier associated with the threshold voltage compensation phase or the sense amplifier enable phase. For example, the fuse logic circuit 72 can be fuse logic circuit 126. The fuse logic circuit 72 can provide a drive strength control signal regarding the drive strength of the transistor, for example, during the sense amplifier enable phase in response to the activation command ACT when an automatic refresh operation is not performed (e.g., an intrinsic memory access operation is being performed). Figure 3CDrive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA, and SelPSA3 associated with the drive strength of transistors 331, 332, 333, 321, 322, and 323. Fuse logic circuit 72 may additionally provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 associated with the drive strength of transistors 331, 332, 333, 321, 322, and 323 during the threshold voltage compensation (VtC) phase. In addition, fuse logic circuit 72 can provide drive strength control signals SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2 and SelAREFPSA3 associated with the drive strength of transistors 331, 332, 333, 321, 322 and 323 during the sense amplifier enable phase of the automatic refresh operation in response to the automatic refresh command AREF.

[0089] Multiple selectors 703 may receive a selection signal SelRef from AREF detection logic circuitry 702 and drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, SelPSA3, SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2, and SelAREFPSA3 from fuse logic circuitry 72. In response to an inactive state of the selection signal SelRef, indicating an operation that is not an automatic refresh operation (e.g., in intrinsic memory operation), the multiple selectors 703 may provide drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3. In response to the active state of the selection signal SelRef, which indicates the automatic refresh operation in response to the automatic refresh command AREF, multiple selectors 703 can provide drive strength control signals SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2, and SelAREFPSA3.

[0090] The drive intensity control circuit 70 may include multiple control signal generator circuits 704. The multiple control signal generator circuits 704 may receive timing signals from the timing logic circuit 701, such as timing signals SAN / SAP and VtcSAN / VtcSAP. The multiple control signal generator circuits 704 may receive drive intensity control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 or drive intensity control signals SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2, and SelAREFPSA3 from multiple selectors 703 for use during the sense amplifier enable phase. Multiple control signal generator circuits 704 can also receive drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, and SelVtcPSA2 from fuse logic circuit 72 for use during the threshold voltage compensation phase. In response to the active timing signal SAN / SAP indicating that the sense amplifier is in the enable phase, the multiple control signal generator circuits 704 can provide inverted signals of the drive strength control signals received from multiple selectors 703 as inverted transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar, respectively. In response to the active timing signal VtcSAN / VtcSAP indicating that the activity is in the threshold voltage compensation phase, multiple control signal generator circuits 704 can provide the inverted signals of drive strength control signals SelVtcPSA1, SelVtcPSA2, SelVtcPSA3, SelVtcNSA1, SelVtcNSA2, and SelVtcNSA3 as inverted transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar, respectively.

[0091] The sense amplifier power control circuit 74 can receive inverted transistor activation signals PSA1bar, PSA2bar, PSA3bar, NSA1bar, NSA2bar, and NSA3bar and provide PSA1, PSA2, PSA3bar, NSA1, NSA2, and NSA3 to the sense amplifier 80 in the memory cell array 75. For example, the sense amplifier power control circuit 74, the memory cell array 75, and the sense amplifier 80 can be... Figure 1 The sensor amplifier power control circuit 135, memory cell array 145, and sensor amplifier 150 are included.

[0092] Multiple selectors 703 and multiple control signal generators 704 can be provided in the preprocessing of each control signal in the generation of control signals, which are transistor activation signals PSA1, PSA2, PSA3bar, NSA1, NSA2, and NSA3 provided from the sense amplifier power supply control circuit 74 to transistors 321, 322, 323, 331, 332, and 333. Therefore, in Figure 7 In A, the number of multiple selectors 703 and multiple control signal generators 704 in the drive intensity control circuit 70 is six. However, depending on the number of transistors used to adjust the drive intensity of the sensing amplifier, the number of these circuits in the drive intensity control circuit 70 can be different accordingly.

[0093] Figure 8A and 8B This is a timing diagram of various signals related to the operation of the sense amplifier and voltage compensation intensity control according to embodiments of this disclosure. For example, various signals in Figure 7 The drive intensity control circuit 70 is located within and around the drive intensity control circuit or provided with drive intensity control circuitry. Figure 3C Sensing amplifier 30. In some embodiments, fuse logic circuit (e.g. Figure 7 The fuse logic circuit 72) can provide drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2, and SelAREFPSA3, respectively set to logic levels "high, high, low, high, high, low", and SelVtcPSA1, SelVtcPSA2, SelVtcPSA3, SelVtcNSA1, SelVtcNSA2, and SelVtcNSA3, respectively set to logic levels "high, high, low, high, high".

[0094] Figure 8AThis diagram illustrates the levels of various signals in response to the activation command ACT during an intrinsic memory access operation, but not during an auto-refresh operation. In response to the activation command ACT, the internal command signal for activating the command ACT is set to logic high, while the internal command signal for the auto-refresh command AREF is set to logic low, and the select signal SelRef is set inactive (e.g., at logic low) by the AREF detection logic circuit 702. In response to the inactive select signal SelRef, multiple selectors 703 can provide drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 set to logic levels "high, high, low, high, high". During the threshold voltage compensation (VtC) phase, the timing logic circuit 701 provides timing signals VtcSAN / VtcSAP set to logic high and timing signals SAN / SAP set to logic low. Multiple control signal generator circuits 704 can provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 in response to the active timing signals VtcSAN / VtcSAP. The drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3, set to logic levels "high, high, low, high, high," cause the sense amplifier power supply control circuit 74 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar, respectively set to logic levels "high, high, low, high, high, low," which causes... Figure 3C The combined drive strength of transistors 331, 332, and 333 in the transistors is 85.6%. Figure 3CThe transistors 321, 322, and 323 in the sensor amplifier are driven at 100% combined strength. During the sense amplifier enable phase, timing logic circuit 701 provides timing signals VtcSAN / VtcSAP set to logic low and SAN / SAP set to logic high. Multiple control signal generator circuits 704 can provide drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 in response to the active timing signal SAN / SAP. The drive strength control signals SelNSA1, SelNSA2, SelNSA3, SelPSA1, SelPSA2, and SelPSA3 set to logic levels "high, high, high, high, high, high" cause the sense amplifier power supply control circuit 74 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar set to logic levels "high, high, high, high, high, low" respectively, which causes Figure 3C The combined drive strength of transistors 331, 332, 333, 321, 322 and 323 in the transistors is 100%.

[0095] Figure 8B This shows the levels of various signals in response to the activation command ACT during automatic refresh operation. For example... Figure 8BAs shown, in response to the auto-refresh command AREF, in addition to the internal command signal for activating the command ACT being set to a logic high level, the internal command signal for the auto-refresh command AREF is also set to a logic high level, and the AREF detection logic circuit 702 provides a selection signal SelRef that is set to be active (e.g., at a logic high level). In response to the active selection signal SelRef, multiple selectors 703 can provide drive strength control signals SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2, and SelAREFPSA3 set to logic levels "high, high, low, high, high, low" instead of drive control signals SelNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3. During the threshold voltage compensation (VtC) phase, timing logic circuit 701 provides timing signals VtcSAN / VtcSAP set to logic high and SAN / SAP set to logic low. Multiple control signal generator circuits 404 can provide drive strength control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 set to logic levels “high, high, low, high, high” in response to the active timing signals VtcSAN / VtcSAP. The drive intensity control signals SelVtcNSA1, SelVtcNSA2, SelVtcNSA3, SelVtcPSA1, SelVtcPSA2, and SelVtcPSA3 cause the sense amplifier power supply control circuit 74 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar, respectively set to logic levels "high, high, low, high, high, low". This causes... Figure 3C The combined drive strength of transistors 331, 332, and 333 in the transistors is 85.6%. Figure 3C The transistors 321, 322, and 323 in the circuit achieve a 100% combined drive strength. During the sense amplifier enable phase, timing logic circuit 701 provides timing signals VtcSAN / VtcSAP set to logic low and SAN / SAP set to logic high. Multiple control signal generator circuits 704 can provide drive strength control signals SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2, and SelAREFPSA3 in response to the active timing signal SAN / SAP. This is reflected as follows... Figure 8BThe drive strength control signals SelAREFNSA1, SelAREFNSA2, SelAREFNSA3, SelAREFPSA1, SelAREFPSA2, and SelAREFPSA3 shown cause the sense amplifier power supply control circuit 74 to provide control signals NSA1, NSA2, NSA3, PSA1, PSA2, and PSA3bar, respectively, set to logic levels "high, high, low, high, high, high". This causes... Figure 3C The combined drive strength of transistors 331, 332, 333, 321, 322 and 323 is 85.6%.

[0096] As described above, combinations of control signals can operate across different memory operations, such as inherent memory operations and auto-refresh operations that can be provided during the sense amplifier enable phase, providing adjustable drive strength. In particular, different drive strengths can be given to the sense amplifier during the sense amplifier enable phase by providing control signals that respond to different combinations of activations in response to different commands (e.g., activation command ACT and auto-refresh command AREF).

[0097] As should be understood from the foregoing, although specific embodiments of this disclosure have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure should not be limited to any of the specific embodiments described herein.

Claims

1. A device for memory operations, comprising: A sensing amplifier coupled to a pair of digital lines and further coupled to a first power node, the sensing amplifier being configured to amplify the voltage difference between the pair of digital lines; and A power supply circuit configured to receive a power supply voltage; The power supply circuit is configured to provide the power supply voltage based on a first drive strength during a threshold voltage compensation phase prior to the activation of the sense amplifier in a first memory operation, and is further configured to provide the power supply voltage based on a second drive strength during a threshold voltage compensation phase prior to the activation of the sense amplifier in a second memory operation.

2. The device according to claim 1, wherein the first memory operation is an inherent memory operation and the second memory operation is an automatic refresh operation.

3. The device according to claim 1, wherein the power supply circuit comprises: Multiple transistors coupled to the first power node and further configured to receive the power supply voltage and provide the power supply voltage to the sense amplifier based on the combined drive strength of the multiple transistors; The plurality of transistors have a first combined drive strength as the first drive strength in a first memory operation, and the plurality of transistors have a second combined drive strength as the second drive strength in a second memory operation.

4. The device of claim 3, wherein the plurality of transistors comprises a first transistor having a first transistor drive strength and a second transistor having a second transistor drive strength different from that of the first transistor drive strength.

5. The device of claim 3, wherein the plurality of transistors comprises a first transistor having a first conductivity type and a second transistor having a second conductivity type.

6. The device of claim 3, wherein the plurality of transistors includes a first transistor configured to be activated in the first memory operation and further configured to be deactivated in the second memory operation.

7. The device of claim 3, further comprising control circuitry configured to provide a plurality of control signals to the plurality of transistors. The plurality of control signals indicate the first drive strength in the first memory operation and the plurality of control signals indicate the second drive strength in the second memory operation.

8. The device of claim 7, wherein the plurality of transistors comprises a first transistor; The plurality of control signals includes a control signal in which the control signal in a first state is configured to activate the first transistor in the first memory operation and in a second state is configured to deactivate the first transistor in the first memory operation.

9. The device of claim 7, wherein the control circuitry is configured to provide the plurality of control signals during the threshold voltage compensation phase of the first memory operation and the threshold voltage compensation phase of the second memory operation.

10. The device of claim 7, wherein the control circuitry is configured to provide the plurality of control signals when the sense amplifier is enabled in the first memory operation and when the sense amplifier is enabled in the second memory operation.

11. The device of claim 1, wherein the power supply circuit is configured to provide the power supply voltage based on a third drive strength when the sense amplifier is enabled in the first memory operation, and is further configured to provide the power supply voltage based on a fourth drive strength during the second memory operation when the sense amplifier is enabled.

12. A method for memory operations, comprising: Receive power supply through the power supply circuit; During the threshold voltage compensation phase prior to the activation of the sensing amplifier in the first memory operation, the first drive strength of the power supply circuit is set. During the threshold voltage compensation phase prior to the activation of the sensing amplifier, the second drive strength of the power supply circuit is set. and Power is supplied to a first power node based on the drive strength, wherein the first power node is coupled to a sensing amplifier.

13. The method of claim 12, wherein the first memory operation is an intrinsic memory operation and the second memory operation is an automatic refresh operation.

14. The method of claim 12, further comprising: The power supply is received through multiple transistors and power is supplied to the first power node based on a combined drive strength that is the drive strength. The plurality of transistors are given the first drive strength in the first memory operation; and The plurality of transistors are given the second drive strength in the second memory operation.

15. The method of claim 14, further comprising: In the first memory operation, a plurality of control signals indicating the first drive strength are provided to the plurality of transistors; and In the second memory operation, the plurality of control signals indicating the second drive strength are provided to the plurality of transistors.

16. The method of claim 15, further comprising: A first transistor among the plurality of transistors is activated in response to one of the plurality of control signals, wherein the plurality of control signals indicate the first drive strength; and The first transistor is deactivated in response to one of the plurality of control signals, wherein the plurality of control signals indicate the second drive strength.

17. The method of claim 15, further comprising: The plurality of control signals are provided during the threshold voltage compensation phase of the first memory operation and the threshold voltage compensation phase of the second memory operation.

18. The method of claim 15, further comprising: The plurality of control signals are provided when the sensing amplifier is enabled in the first memory operation and when the sensing amplifier is enabled in the second memory operation.

19. The method of claim 12, further comprising: When the sensing amplifier is enabled during the first memory operation, the third drive strength of the power supply circuit is set; as well as When the sensing amplifier is enabled during the second memory operation, the fourth drive strength of the power supply circuit is set.

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