Signaling device, electronic device, vehicle

Abstract

A signal transmission device insulates a primary circuit system from a secondary circuit system, and transmits a drive signal of a transistor for gate driving between the primary circuit system and the secondary circuit system, the signal transmission device having a first external terminal configured to connect a ground terminal of the secondary circuit system, a second external terminal configured such that a terminal voltage varies depending on whether the first external terminal is in an open state, and an open detection circuit that monitors the terminal voltage of the second external terminal to perform open detection of the first external terminal.

Description

Technical Field

[0001] The invention disclosed in this specification relates to a signal transmission device, an electronic device including the signal transmission device, and a vehicle. Background Technology

[0002] In the past, signal transmission devices that electrically insulate the primary circuit system from the secondary circuit system and transmit signals between the primary and secondary circuit systems have been used in various applications (power supply devices or motor drive devices, etc.).

[0003] Furthermore, as an example of prior art related to the above, the patent document 1 of the applicant of this application can be cited.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-011108 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] However, in previous signal transmission devices, there is room for research on GND open-circuit detection in the secondary circuit system.

[0009] In view of the aforementioned problems discovered by the inventors of this application, the object of the invention disclosed in this specification is to provide a signal transmission device capable of detecting a GND open circuit fault in a secondary circuit system, an electronic device using the signal transmission device, and a vehicle.

[0010] Methods for solving problems

[0011] For example, the signal transmission device disclosed in this specification isolates a primary circuit system from a secondary circuit system and transmits a drive signal for a gate drive transistor between the primary and secondary circuit systems. The signal transmission device includes: a first external terminal configured to connect to a ground terminal of the secondary circuit system; a second external terminal configured such that its voltage varies depending on whether the first external terminal is open-circuited; and an open-circuit detection circuit that monitors the voltage of the second external terminal to detect an open circuit in the first external terminal.

[0012] Furthermore, other features, elements, steps, advantages, and characteristics become clearer from the following description of the means of carrying out the invention and the accompanying drawings.

[0013] Invention Effects

[0014] According to the invention disclosed in this specification, a signal transmission device capable of detecting an open-circuit fault in a secondary circuit system, as well as an electronic device and a vehicle using the signal transmission device, can be provided. Attached Figure Description

[0015] Figure 1 It is a diagram showing the basic structure of a signal transmission device.

[0016] Figure 2 This is a diagram showing the basic structure of a transformer chip.

[0017] Figure 3 This is a three-dimensional view of a semiconductor device used as a dual-channel transformer chip.

[0018] Figure 4 yes Figure 3 A top view of the semiconductor device shown.

[0019] Figure 5 It means in Figure 3 A top view of a layer in a semiconductor device in which a low-potential coil is formed.

[0020] Figure 6 It means in Figure 3 A top view of a layer in a semiconductor device in which a high-potential coil is formed.

[0021] Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown.

[0022] Figure 8 It means Figure 7 The diagram shows an enlarged view (separated structure) of region XIII.

[0023] Figure 9 This is a schematic diagram illustrating an example of the layout of a transformer chip.

[0024] Figure 10 This is a diagram illustrating an implementation of a signal transmission device.

[0025] Figure 11 This is a diagram illustrating a structural example of an electronic device equipped with a signal transmission device.

[0026] Figure 12 This diagram shows a first connection example (DESAT method) of the short-circuit detection terminal.

[0027] Figure 13 This diagram shows a second connection example (emitter sensing method) of the short-circuit detection terminal.

[0028] Figure 14 This is a diagram illustrating a structural example of an open-circuit detection circuit.

[0029] Figure 15 This is a diagram illustrating an example of an open-circuit detection action.

[0030] Figure 16 This is a diagram showing the exterior of a vehicle equipped with electronic devices. Detailed Implementation

[0031] <Signal Transmission Device (Basic Structure)>

[0032] Figure 1 This diagram illustrates the basic structure of a signal transmission device. In this example, the signal transmission device 200 is a semiconductor integrated circuit device (so-called an insulated gate driver IC) that insulates the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system), and transmits pulse signals from the primary circuit system 200p to the secondary circuit system 200s to drive the gate of a switching element (not shown) disposed in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing the controller chip 210, driver chip 220, and transformer chip 230 into a single package.

[0033] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (e.g., a maximum of 7V based on GND1). The controller chip 210 integrates, for example, a pulse transmitting circuit 211, buffers 212 and 213.

[0034] The pulse transmitting circuit 211 is a pulse generator that generates transmit pulse signals S11 and S21 based on the input pulse signal IN. More specifically, the pulse transmitting circuit 211 drives the transmit pulse signal S11 (single or multiple transmit pulse outputs) when the input pulse signal IN is high, and drives the transmit pulse signal S21 when the input pulse signal IN is low. That is, the pulse transmitting circuit 211 drives either the transmit pulse signal S11 or S21 according to the logic level of the input pulse signal IN.

[0035] The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and performs pulse drive on the transformer chip 230 (specifically the transformer 231).

[0036] The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and performs pulse drive on the transformer chip 230 (specifically the transformer 232).

[0037] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (e.g., a maximum of 30V based on GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0038] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically the transformer 231) and outputs it to the pulse receiving circuit 223.

[0039] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically the transformer 232) and outputs it to the pulse receiving circuit 223.

[0040] The pulse receiving circuit 223 drives the driver 224 based on the received pulse signals S12 and S22 input via buffers 221 and 222, thereby generating an output pulse signal OUT. More specifically, the pulse receiving circuit 223 drives the driver 224 in such a way that it receives the pulse of the received pulse signal S12 to raise the output pulse signal OUT to a high level, and on the other hand, it receives the pulse of the received pulse signal S22 to lower the output pulse signal OUT to a low level. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. Furthermore, an RS flip-flop can be appropriately used as the pulse receiving circuit 223, for example.

[0041] The driver 224 generates an output pulse signal OUT according to the drive control of the pulse receiving circuit 223.

[0042] Transformer chip 230 uses transformers 231 and 232 to DC-ground insulate the controller chip 210 from the driver chip 220, and outputs the transmit pulse signals S11 and S21 input from the pulse transmit circuit 211 as receive pulse signals S12 and S22 to the pulse receive circuit 223. Furthermore, in this specification, "DC-ground insulation" means that the two objects to be insulated are not connected by a conductor.

[0043] More specifically, transformer 231 outputs a receiving pulse signal S12 from secondary coil 231s based on the transmitting pulse signal S11 input to primary coil 231p. On the other hand, transformer 232 outputs a receiving pulse signal S22 from secondary coil 232s based on the transmitting pulse signal S21 input to primary coil 232p.

[0044] Thus, due to the characteristics of the spiral coil used for communication between insulators, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (equivalent to rising and falling signals), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0045] Furthermore, the signal transmission device 200 of this embodiment differs from the controller chip 210 and the driver chip 220 in that it independently has a transformer chip 230 that only carries transformers 231 and 232, and these three chips are sealed into a single package.

[0046] By adopting this structure, both the controller chip 210 and the driver chip 220 can be formed using general low- to medium-voltage processes (a few volts to tens of volts), thus eliminating the need for a dedicated high-voltage process (a few thousand volts), which reduces manufacturing costs.

[0047] Furthermore, the signal transmission device 200 can be appropriately utilized, for example, by a power supply device or an electric motor drive device of an on-board device mounted on the vehicle. In addition to engine-powered vehicles, the aforementioned vehicles also include electric vehicles (BEV [pure electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV [plug-in hybrid electric vehicle], or FCEV / FCV [fuel cell electric vehicle], etc. xEV).

[0048] <Transformer Chip (Basic Structure)>

[0049] Next, the basic structure of the transformer chip 230 will be explained. Figure 2 This diagram illustrates the basic structure of transformer chip 230. In the transformer chip 230 of this diagram, transformer 231 includes a primary side coil 231p and a secondary side coil 231s opposite each other in the vertical direction. Transformer 232 includes a primary side coil 232p and a secondary side coil 232s opposite each other in the vertical direction.

[0050] Primary side coils 231p and 232p are both formed on the first wiring layer (lower layer) 230a of the transformer chip 230. Secondary side coils 231s and 232s are both formed on the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. Furthermore, the secondary side coil 231s is positioned directly above the primary side coil 231p, opposite to it. Similarly, the secondary side coil 232s is positioned directly above the primary side coil 232p, opposite to it.

[0051] The primary side coil 231p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X21 and spiraling clockwise around the internal terminal X21, with its second end connecting to the internal terminal X22. Conversely, the primary side coil 232p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X23 and spiraling counterclockwise around the internal terminal X23, with its second end connecting to the internal terminal X22. The internal terminals X21, X22, and X23 are arranged in a straight line in the order shown in the diagram.

[0052] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wire Y21 and through-hole Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wire Y22 and through-hole Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wire Y23 and through-hole Z23. Furthermore, external terminals T21 to T23 are arranged in a straight line for wire connection with the controller chip 210.

[0053] The secondary-side coil 231s is spirally arranged around the external terminal T24 in a counter-clockwise direction, starting from the first end connected to the external terminal T24, and the second end, corresponding to its endpoint, is connected to the external terminal T25. On the other hand, the secondary-side coil 232s is spirally arranged around the external terminal T26 in a clockwise direction, starting from the first end connected to the external terminal T26, and the second end, corresponding to its endpoint, is connected to the external terminal T25. Furthermore, the external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure for wire connection to the driver chip 220.

[0054] Secondary coils 231s and 232s are AC connected to primary coils 231p and 232p via magnetic coupling, respectively, and are DC insulated from primary coils 231p and 232p. That is, driver chip 220 is AC connected to controller chip 210 via transformer chip 230, and is DC insulated from controller chip 210 via transformer chip 230.

[0055] <Transformer Chip (Dual-Channel Type)>

[0056] Figure 3 This is a perspective view of a semiconductor device 5 used as a dual-channel transformer chip. Figure 4 yes Figure 3 A top view of the semiconductor device 5 shown. Figure 5 It means in Figure 3 The diagram shows a top view of the semiconductor device 5 in which a low-potential coil 22 (equivalent to the primary coil of a transformer) is formed. Figure 6 It means in Figure 3The diagram shows a top view of the layer in the semiconductor device 5 in which a high-potential coil 23 (equivalent to the secondary coil of a transformer) is formed. Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown.

[0057] Reference Figures 3-7 The semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0058] Wide bandgap semiconductors are composed of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide bandgap semiconductor is preferably 2.0 eV or higher. Wide bandgap semiconductors can also be SiC (silicon carbide). Compound semiconductors can be III-V group compound semiconductors. Compound semiconductors may also contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0059] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a stacked structure comprising a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0060] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed into a quadrilateral shape (rectangular shape in this embodiment) when viewed from their normal direction Z in a top view (hereinafter referred to as "top view").

[0061] The chip sidewalls 44A to 44D include: a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and are opposite each other along a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend along the second direction Y and are opposite each other along the first direction X. The chip sidewalls 44A to 44D are formed by polished surfaces.

[0062] The semiconductor device 5 further includes an insulating layer 51 formed on a first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. In a top view, the insulating main surface 52 is formed into a quadrilateral shape (rectangular shape in this embodiment) that matches the first main surface 42. The insulating main surface 52 extends parallel to the first main surface 42.

[0063] The insulating sidewalls 53A-53D include: a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A-44D. Specifically, the insulating sidewalls 53A-53D are formed flush with the chip sidewalls 44A-44D. The insulating sidewalls 53A-53D form grinding surfaces flush with the chip sidewalls 44A-44D.

[0064] The insulating layer 51 is composed of a multilayer insulating stack structure including a lower insulating layer 55, an upper insulating layer 56, and multiple (11 layers in this embodiment) interlayer insulating layers 57. The lower insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers located between the lower insulating layer 55 and the upper insulating layer 56. In this embodiment, the lower insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the lower insulating layer 55 and the thickness of the upper insulating layer 56 can be more than 1 μm and less than 3 μm (for example, about 2 μm).

[0065] The multiple interlayer insulating layers 57 each have a stacked structure comprising a first insulating layer 58 on the side of the lowest insulating layer 55 and a second insulating layer 59 on the side of the highest insulating layer 56. The first insulating layer 58 may also comprise silicon nitride. The first insulating layer 58 is formed as an etch stop layer relative to the second insulating layer 59. The thickness of the first insulating layer 58 may be greater than 0.1 μm and less than 1 μm (e.g., about 0.3 μm).

[0066] A second insulating layer 59 is formed on top of the first insulating layer 58. It comprises an insulating material different from the first insulating layer 58. The second insulating layer 59 may also comprise silicon oxide. The thickness of the second insulating layer 59 can be 1 μm or more and 3 μm or less (e.g., about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0067] The total thickness DT of the insulating layer 51 can be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the required insulation withstand voltage (insulation breakdown withstand voltage). In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56 and the interlayer insulating layer 57 are arbitrary and not limited to specific insulating materials.

[0068] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (equivalent to the previous transformers). That is, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed at intervals and spaced apart from the insulating sidewalls 53A to 53D inside the insulating layer 51. The multiple transformers 21 are formed at intervals and spaced apart along a first direction X.

[0069] Specifically, in the top view, the plurality of transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed sequentially from the insulating sidewall 53C side toward the insulating sidewall 53D side. The plurality of transformers 21A to 21D each have the same construction. The construction of the first transformer 21A will be described below as an example. The description of the construction of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D, applicable to the construction of the first transformer 21A, is omitted.

[0070] Reference Figures 5-7 The first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within an insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 opposite to the low-potential coil 22 along the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the lowermost insulating layer 55 and the uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0071] The low-potential coil 22 is formed within the insulating layer 51 on the side of the lowest insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 relative to the low-potential coil 22 on the side of the uppermost insulating layer 56 (insulating main surface 52). That is, the high-potential coil 23 is positioned opposite the semiconductor chip 41, separated from the low-potential coil 22. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to be positioned opposite the low-potential coil 22, separated from it by one or more interlayer insulating layers 57.

[0072] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulation 57) is appropriately adjusted according to the insulation withstand voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed in the third layer of interlayer insulation 57 starting from the side of the bottommost insulation layer 55. In this embodiment, the high-potential coil 23 is formed in the first layer of interlayer insulation 57 starting from the side of the topmost insulation layer 56.

[0073] The low-potential coil 22 is embedded in the interlayer insulation layer 57, passing through the first insulation layer 58 and the second insulation layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. In the top view, the first helical portion 26 is wound in a spiral shape extending in an elliptical shape (oblong shape). The portion forming the innermost periphery of the first helical portion 26 divides an elliptical first inner region 66 in the top view.

[0074] The number of turns in the first helical portion 26 can be 5 or more and 30 or less. The width of the first helical portion 26 can also be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction orthogonal to the helical direction. The first winding pitch of the first helical portion 26 can be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction orthogonal to the helical direction.

[0075] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and not limited to any particular shape. Figure 5 As shown in the diagram. The first spiral portion 26 can also be wound into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view. The first inner region 66 can also be divided into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view according to the winding shape of the first spiral portion 26.

[0076] The low-potential coil 22 may also comprise at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may also have a laminated structure comprising a barrier layer and a main body layer. The barrier layer divides recessed spaces within the interlayer insulating layer 57. The barrier layer may comprise at least one of titanium and titanium nitride. The main body layer may comprise at least one of copper, aluminum, and tungsten.

[0077] A high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. In a top view, the second spiral portion 29 is spirally wound in an elliptical shape (oblong shape). In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines an elliptical second inner region 67 in a top view. The second inner region 67 of the second spiral portion 29 is opposite to the first inner region 66 of the first spiral portion 26 along the normal direction Z.

[0078] The number of turns in the second helical section 29 can be 5 or more and 30 or less. The number of turns in the second helical section 29 relative to the number of turns in the first helical section 26 is adjusted according to the voltage value to be boosted. Preferably, the number of turns in the second helical section 29 exceeds the number of turns in the first helical section 26. Of course, the number of turns in the second helical section 29 can be less than the number of turns in the first helical section 26, or it can be equal to the number of turns in the first helical section 26.

[0079] The width of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction orthogonal to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0080] The second winding pitch of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction orthogonal to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0081] The winding shape of the second spiral section 29 and the planar shape of the second inner region 67 are arbitrary and not limited to... Figure 6 As shown in the diagram. The second spiral portion 29 can also be wound into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view. The second inner region 67 can also be divided into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view, depending on the winding shape of the second spiral portion 29.

[0082] The high-potential coil 23 is preferably formed of the same conductive material as the low-potential coil 22. That is, the high-potential coil 23 preferably includes a barrier layer and a main body layer in the same way as the low-potential coil 22.

[0083] Reference Figure 4The semiconductor device 5 includes a plurality of (12 in this figure) low-potential terminals 11 and a plurality of (12 in this figure) high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D.

[0084] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed at intervals along the second direction Y and the multiple transformers 21A to 21D in the region on the insulating sidewall 53B, and are arranged at intervals along the first direction X.

[0085] The plurality of low-potential terminals 11 includes: a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this embodiment, each of the plurality of low-potential terminals 11A to 11F is formed in two. The number of the plurality of low-potential terminals 11A to 11F is arbitrary.

[0086] In the top view, the first low-potential terminal 11A is opposite to the first transformer 21A along the second direction Y. In the top view, the second low-potential terminal 11B is opposite to the second transformer 21B along the second direction Y. In the top view, the third low-potential terminal 11C is opposite to the third transformer 21C along the second direction Y. In the top view, the fourth low-potential terminal 11D is opposite to the fourth transformer 21D along the second direction Y. In the top view, the fifth low-potential terminal 11E is formed in the area between the first low-potential terminal 11A and the second low-potential terminal 11B. In the top view, the sixth low-potential terminal 11F is formed in the area between the third low-potential terminal 11C and the fourth low-potential terminal 11D.

[0087] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0088] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0089] Multiple high-potential terminals 12 and multiple low-potential terminals 11 are formed spaced apart on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple high-potential terminals 12 are formed spaced apart from the multiple low-potential terminals 11 in the region of the insulating sidewall 53A, and are arranged spaced apart along the first direction X.

[0090] In the top view, multiple high-potential terminals 12 are respectively formed in areas close to the corresponding transformers 21A to 21D. The high-potential terminals 12 are close to the transformers 21A to 21D in that the distance between the high-potential terminals 12 and the transformers 21 in the top view is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0091] Specifically, in the top view, a plurality of high-potential terminals 12 are formed at intervals along the first direction X, opposite to a plurality of transformers 21A-21D. More specifically, in the top view, the plurality of high-potential terminals 12 are formed at intervals along the first direction X, located in the second inner region 67 of the high-potential coil 23 and the region between adjacent high-potential coils 23. Thus, in the top view, the plurality of high-potential terminals 12 are arranged side by side in a row with the plurality of transformers 21A-21D along the first direction X.

[0092] The plurality of high-potential terminals 12 includes: a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this embodiment, each of the plurality of high-potential terminals 12A to 12F is formed in two. The number of the plurality of high-potential terminals 12A to 12F is arbitrary.

[0093] In the top view, a first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23). A second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23). A third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23). A fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23). A fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in the top view. A sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in the top view.

[0094] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0095] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0096] Reference Figures 5-7 The semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, respectively formed within an insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0097] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0098] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0099] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low-potential coils 22), respectively. The multiple first low-potential wirings 31 have the same structure. Hereinafter, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the other first low-potential wirings 31 is omitted for the first low-potential wiring 31 connected to the first transformer 21A.

[0100] The first low-potential wiring 31 includes: a through wiring 71, a low-potential connection wiring 72, a lead wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0101] The through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably formed of the same conductive material as the low-potential coil 22. That is, the through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably the same as the low-potential coil 22, each including a barrier layer and a main body layer.

[0102] The through-wire 71 extends through multiple interlayer insulation layers 57 in the insulation layer 51, forming a columnar shape extending along the normal direction Z. In this embodiment, the through-wire 71 is formed in the region between the lowermost insulation layer 55 and the uppermost insulation layer 56 in the insulation layer 51. The through-wire 71 has an upper end portion on the side of the uppermost insulation layer 56 and a lower end portion on the side of the lowermost insulation layer 55. The upper end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the high-potential coil 23 and is covered by the uppermost insulation layer 56. The lower end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the low-potential coil 22.

[0103] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed of the same conductive material as the low-potential coil 22. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80, like the low-potential coil 22, each include a barrier layer and a main body layer.

[0104] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and is opposite to the low-potential terminal 11 (first low-potential terminal 11A) along the normal direction Z. The second electrode layer 79 is formed in an island shape and is opposite to the first electrode layer 78 along the normal direction Z.

[0105] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulation layers 57 located between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowest insulation layer 55 to the highest insulation layer 56 in an electrically interconnected manner, and electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area smaller than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0106] Furthermore, the number of stacked layers of the plurality of wiring plug electrodes 80 is consistent with the number of stacked layers of the plurality of interlayer insulation layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulation layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulation layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 that penetrate multiple interlayer insulation layers 57 can also be formed.

[0107] A low-potential connection wiring 72 is formed within the same interlayer insulation layer 57 as the low-potential coil 22 in the first inner region 66 of the first transformer 21A (low-potential coil 22). The low-potential connection wiring 72 is formed in an island shape, facing the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The low-potential connection wiring 72 preferably has a planar area exceeding the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0108] Lead-out wiring 73 is formed within interlayer insulating layer 57 in the region between semiconductor chip 41 and through wiring 71. In this embodiment, lead-out wiring 73 is formed within interlayer insulating layer 57, which is the first layer starting from the lowest insulating layer 55. Lead-out wiring 73 includes: a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of lead-out wiring 73 is located in the region between semiconductor chip 41 and the lower end of through wiring 71. The second end of lead-out wiring 73 is located in the region between semiconductor chip 41 and low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0109] The first connection plug electrode 74 is formed within the interlayer insulating layer 57 in the region between the through wiring 71 and the lead wiring 73, and is electrically connected to the first end of the through wiring 71 and the lead wiring 73. The second connection plug electrode 75 is formed within the interlayer insulating layer 57 in the region between the low-potential connection wiring 72 and the lead wiring 73, and is electrically connected to the second end of the low-potential connection wiring 72 and the lead wiring 73.

[0110] Multiple pad plug electrodes 76 are formed within the uppermost insulating layer 56 in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through wiring 71, respectively, and are electrically connected to the upper ends of the low-potential terminal 11 and the through wiring 71. Multiple substrate plug electrodes 77 are formed within the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the lead wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first ends of the lead wiring 73, respectively, and are electrically connected to the first ends of the semiconductor chip 41 and the lead wiring 73.

[0111] Reference Figure 6 and Figure 7 Multiple first high-potential wirings 33 are electrically connected to the second inner ends 27 of the corresponding high-potential terminals 12A-12D and the corresponding transformers 21A-21D (high-potential coils 23), respectively. Each of the multiple first high-potential wirings 33 has the same structure. The following description uses the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the other first high-potential wirings 33 is omitted for the first high-potential wiring 33 connected to the first transformer 21A.

[0112] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrodes 82 are preferably formed of the same conductive material as the low-potential coil 22, etc. That is, the high-potential connection wiring 81 and the pad plug electrodes 82 preferably include a barrier layer and a body layer, just like the low-potential coil 22, etc.

[0113] The high-potential connection wiring 81 is formed within the same interlayer insulation layer 57 as the high-potential coil 23 in the second inner region 67 of the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and is positioned opposite the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In the top view, the high-potential connection wiring 81 is formed with a gap from the low-potential connection wiring 72 and is not positioned opposite the low-potential connection wiring 72 along the normal direction Z. Therefore, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the insulation withstand voltage of the insulation layer 51 is improved.

[0114] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, respectively, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81. In a top view, each of the multiple pad plug electrodes 82 has a planar area smaller than the planar area of ​​the high-potential connection wiring 81.

[0115] Reference Figure 7 Preferably, the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 (D2 < D1) between the low-potential coil 22 and the high-potential coil 23. Distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio of distance D2 to distance D1, D2 / D1, can be 0.01 or more and 0.1 or less. Distance D1 is preferably 100 μm or more and 500 μm or less. Distance D2 can be 1 μm or more and 50 μm or less. Distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of distance D1 and distance D2 are arbitrary and appropriately adjusted according to the insulation withstand voltage to be achieved.

[0116] Reference Figure 6 as well as Figure 7 In the top view, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 in a manner that surrounds the transformers 21A to 21D.

[0117] The dummy pattern 85 is formed from a different pattern (a discontinuous pattern) than that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. That is, the dummy pattern 85 does not function as a component of the transformers 21A-21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D, suppressing electric field concentration targeting the high-potential coil 23. In this embodiment, the dummy pattern 85 is wound with a linear density equal to that of the high-potential coil 23 per unit area. The linear density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the linear density of the dummy pattern 85 converges within ±20% of the linear density of the high-potential coil 23.

[0118] The depth of the dummy pattern 85 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The dummy pattern 85 is preferably formed in a region in the normal direction Z that is close to the low-potential coil 22 and the high-potential coil 23. Furthermore, "close to the high-potential coil 23 in the normal direction Z" means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0119] In this case, electric field concentration against the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the better the electric field concentration against the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration against the high-potential coil 23 can be suppressed more appropriately. The dummy pattern 85 comprises multiple dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0120] The depth of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The high-potential dummy pattern 86 is preferably formed in a region in the normal direction Z that is close to the high-potential coil 23 relative to the low-potential coil 22. "Close to the high-potential coil 23 in the normal direction Z" means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0121] The dummy pattern 85 includes a suspended dummy pattern formed in the insulation layer 51 in an electrically suspended state, located around the transformers 21A to 21D.

[0122] In this embodiment, the suspended dummy pattern, in the top view, appears as a densely wound line that partially covers and exposes the area surrounding the high-potential coil 23. The suspended dummy pattern can be formed with ends or without ends.

[0123] The depth position of the suspended dummy pattern inside the insulating layer 51 is arbitrary and can be adjusted according to the electric field strength to be mitigated.

[0124] The number of levitation lines is arbitrary and can be adjusted according to the electric field to be mitigated. A levitation dummy pattern can also be composed of multiple levitation dummy patterns.

[0125] Reference Figure 7 The semiconductor device 5 includes a second functional device 60 formed in the device region 62 on the first main surface 42 of the semiconductor chip 41. The second functional device 60 is formed utilizing the surface portion of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowest insulating layer 55). Figure 7 In the diagram, the second functional device 60 is simplified and shown through the dashed lines on the surface of the first main surface 42.

[0126] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring and to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. Detailed descriptions of the low-potential and high-potential wirings of the second functional device 60 are omitted.

[0127] The second functional device 60 may also include at least one of a passive device, a semiconductor rectifier, and a semiconductor switch. Among the passive devices, the second functional device 60 may also include a circuit network formed by selectively combining any two or more of the passive devices, semiconductor rectifiers, and semiconductor switch devices. The circuit network may also form part or all of an integrated circuit.

[0128] Passive devices may include semiconductor passive devices. Passive devices may also include any one or both of resistors and capacitors. Semiconductor rectifier devices may also include at least one of pn junction diodes, PIN diodes, Zener diodes, Schottky barrier diodes, and fast recovery diodes. Semiconductor switching devices may also include at least one of BJTs (bipolar junction transistors), MISFETs (metal-insulator field-effect transistors), IGBTs (insulated gate bipolar junction transistors), and JFETs (junction field-effect transistors).

[0129] Reference Figures 5-7 The semiconductor device 5 further includes a sealing conductor 61 embedded within an insulating layer 51. In a top view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating sidewalls 53A-53D, dividing the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 inhibits the ingress of moisture from the outer region 63 into the device region 62 and the formation of cracks.

[0130] Device area 62 is the area that includes the following: first functional device 45 (multiple transformers 21), second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, first low-potential wiring 31, second low-potential wiring 32, first high-potential wiring 33, second high-potential wiring 34, and dummy pattern 85. Outer area 63 is the area outside device area 62.

[0131] The sealed conductor 61 is electrically isolated from the device region 62. Specifically, the sealed conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealed conductor 61 is fixed in an electrically levitated state. The sealed conductor 61 does not form a current path connected to the device region 62.

[0132] In the top view, the sealing conductor 61 is formed as a strip along the insulating sidewalls 53A to 53D. In this embodiment, the sealing conductor 61 is formed as a four-sided ring (specifically, a rectangular ring) in the top view. Thus, the sealing conductor 61 divides the device region 62 into a four-sided (specifically, a rectangular) shape in the top view. In addition, the sealing conductor 61 divides the outer region 63 of the four-sided ring (specifically, a rectangular ring) surrounding the device region 62 in the top view.

[0133] Specifically, the sealing conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending in a wall-like shape between the upper end portion and the lower end portion. In this embodiment, the upper end portion of the sealing conductor 61 is formed spaced apart from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end portion of the sealing conductor 61 is covered by the uppermost insulating layer 56. The upper end portion of the sealing conductor 61 may also be covered by one or more interlayer insulating layers 57. The upper end portion of the sealing conductor 61 may also be exposed from the uppermost insulating layer 56. The lower end portion of the sealing conductor 61 is formed spaced apart from the semiconductor chip 41 toward the upper end portion side.

[0134] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 such that it is located on the semiconductor chip 41 side relative to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, the sealing conductor 61 is positioned within the insulating layer 51 opposite to the first functional device 45 (the plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Alternatively, the sealing conductor 61 may be positioned within the insulating layer 51 opposite to a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0135] The sealing conductor 61 comprises a plurality of sealing plug conductors 64 and one or more (in this embodiment, a plurality of) sealing through-hole conductors 65. The number of sealing through-hole conductors 65 is arbitrary. The uppermost sealing plug conductor 64 of the plurality of sealing plug conductors 64 forms the upper end of the sealing conductor 61. The plurality of sealing through-hole conductors 65 respectively form the lower end of the sealing conductor 61. The sealing plug conductors 64 and the sealing through-hole conductors 65 are preferably formed of the same conductive material as the low-potential coil 22. That is, the sealing plug conductors 64 and the sealing through-hole conductors 65 preferably include a barrier layer and a body layer, just like the low-potential coil 22.

[0136] Multiple hermetically sealed plug conductors 64 are embedded in multiple interlayer insulating layers 57, forming, in top view, four-sided rings (specifically rectangular rings) surrounding the device region 62. The multiple hermetically sealed plug conductors 64 are stacked from the bottom insulating layer 55 to the top insulating layer 56 in an interconnected manner. The number of stacks of the multiple hermetically sealed plug conductors 64 is the same as the number of stacks of the multiple interlayer insulating layers 57. Alternatively, one or more hermetically sealed plug conductors 64 may be formed that penetrate through multiple interlayer insulating layers 57.

[0137] If an assembly of multiple sealing plug conductors 64 forms a ring-shaped sealing conductor 61, it is not necessary for all of the multiple sealing plug conductors 64 to be formed in a ring shape. For example, at least one of the multiple sealing plug conductors 64 can also be formed in an end-to-end shape. Alternatively, at least one of the multiple sealing plug conductors 64 can also be divided into multiple end-to-end strip-shaped portions. However, given the risk of moisture ingress and crack formation within the device region 62, it is preferable that the multiple sealing plug conductors 64 be formed in an endless (ring-shaped) shape.

[0138] Multiple sealing via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the sealing plug conductor 64. The multiple sealing via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the sealing plug conductor 64. The multiple sealing via conductors 65 have a planar area smaller than the planar area of ​​the sealing plug conductor 64. In the case where a single sealing via conductor 65 is formed, the single sealing via conductor 65 may also have a planar area greater than or equal to the planar area of ​​the sealing plug conductor 64.

[0139] The width of the sealing conductor 61 can be 0.1 μm or more and 10 μm or less. Preferably, the width of the sealing conductor 61 is 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction orthogonal to the direction in which the sealing conductor 61 extends.

[0140] Reference Figure 7 as well as Figure 8 The semiconductor device 5 further includes a separation structure 130 located between the semiconductor chip 41 and the sealing conductor 61, electrically isolating the sealing conductor 61 from the semiconductor chip 41. The separation structure 130 preferably includes an insulator. In this embodiment, the separation structure 130 is formed of a field insulating film 131 formed on a first main surface 42 of the semiconductor chip 41.

[0141] The field insulating film 131 comprises at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 is composed of a LOCOS (Local Selective Oxidation of Silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary, as long as it is sufficient to insulate the semiconductor chip 41 from the sealing conductor 61. The thickness of the field insulating film 131 can be 0.1 μm or more and 5 μm or less.

[0142] The separation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the sealing conductor 61 in a top view. In this embodiment, the separation structure 130 is formed as a four-sided ring (specifically a rectangular ring) in a top view. The separation structure 130 has a connection portion 132 that connects to the lower end of the sealing conductor 61 (sealing via conductor 65). The connection portion 132 may also be an anchoring portion recessed into the lower end of the sealing conductor 61 (sealing via conductor 65) toward the semiconductor chip 41. Of course, the connection portion 132 may also be formed flush with the main surface of the separation structure 130.

[0143] The separation structure 130 includes: an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. In the top view, the inner end portion 130A divides the region where the second functional device 60 is formed (i.e., device region 62). The inner end portion 130A may also be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0144] The outer end portion 130B exposes from and is connected to the chip sidewalls 44A-44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A-44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A-44D of the semiconductor chip 41 and the insulating sidewalls 53A-53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may also be formed in the first main surface 42 at a distance from the chip sidewalls 44A-44D.

[0145] The main body 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connecting portion 132 that connects to the lower end of the sealing conductor 61 (sealing through-hole conductor 65). The connecting portion 132 is formed in the main body 130C in a portion spaced apart from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can be implemented in various ways other than the field insulating film 131.

[0146] Reference Figure 7 The semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 in a manner that covers the sealing conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from the insulating main surface 52.

[0147] In this embodiment, the inorganic insulating layer 140 has a stacked structure comprising a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may also comprise silicon oxide. Preferably, the first inorganic insulating layer 141 comprises undoped silicon oxide, i.e., USG (undoped silicon glass). The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may also comprise silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the insulation withstand voltage on the high-potential coil 23 can be improved.

[0148] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the insulation breakdown voltage (V / cm) of USG exceeds that of silicon nitride. Therefore, when the inorganic insulating layer 140 is made thicker, it is preferable to form a first inorganic insulating layer 141 that is thicker than the second inorganic insulating layer 142.

[0149] The first inorganic insulating layer 141 may also comprise at least one of BPSG (borosilicate glass) and PSG (phosphosilicate glass), which are examples of silicon oxide. However, in this case, impurities (boron or phosphorus) are contained in the silicon oxide. Therefore, it is particularly preferable to form the first inorganic insulating layer 141 composed of USG in order to improve the insulation withstand voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may also have a single-layer structure composed of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0150] The inorganic insulating layer 140 covers the entire area of ​​the sealing conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed outside the sealing conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11 respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12 respectively. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the high-potential terminals 12.

[0151] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may also contain a photosensitive resin. The organic insulating layer 145 may also contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0152] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Additionally, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. Based on these structures, the thickening of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, while the insulation withstand voltage on the high-potential coil 23 can be appropriately increased through the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0153] The organic insulating layer 145 includes a first portion 146 covering a region on the low-potential side and a second portion 147 covering a region on the high-potential side. The first portion 146 covers the sealing conductor 61 through the inorganic insulating layer 140. The first portion 146 has a plurality of low-potential terminal openings 148 in the region outside the sealing conductor 61, exposing a plurality of low-potential terminals 11 (low-potential pad openings 143). The first portion 146 may also have an overlap (overlap) that overlaps the periphery of the low-potential pad openings 143.

[0154] The second portion 147 is formed spaced apart from the first portion 146, such that the inorganic insulating layer 140 is exposed between the first portion 146 and the second portion 147. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may also have an overlapping portion that overlaps the periphery of the high-potential pad openings 144.

[0155] Part 147 also covers transformers 21A to 21D and dummy pattern 85. Specifically, Part 147 also covers multiple high-potential coils 23, multiple high-potential terminals 12, a first high-potential dummy pattern 87, a second high-potential dummy pattern 88, and a floating dummy pattern 121.

[0156] The present invention can also be implemented in other ways. In the described embodiments, an example having a first functional device 45 and a second functional device 60 has been illustrated. However, it is also possible to employ a configuration that does not have a first functional device 45 and only has a second functional device 60. In this case, the dummy pattern 85 can also be removed. According to this configuration, the second functional device 60 can achieve the same effect as described in the first embodiment (except for the effect of the dummy pattern 85).

[0157] That is, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed. Furthermore, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the low-potential terminal 11 and the sealing conductor 61 can be suppressed.

[0158] Furthermore, in the described embodiment, an example with a second functional device 60 was given. However, the second functional device 60 is not necessary and may be omitted.

[0159] Furthermore, in the described embodiment, an example with a dummy pattern 85 was given. However, the dummy pattern 85 is not necessary and can be removed.

[0160] Furthermore, in the described embodiment, an example of a multi-channel type comprising multiple transformers 21 was given. However, a single-channel type comprising a single transformer 21 may also be used for the first functional device 45.

[0161] <Transformer Arrangement>

[0162] Figure 9 This is a top view (top view) schematically illustrating an example of the transformer arrangement in a dual-channel transformer chip 300 (equivalent to the previous semiconductor device 5). The transformer chip 300 in this figure includes: a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0163] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary side coil L1s forming the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary side coil L1s. Pads a2 and b2 are connected to one end of the secondary side coil L2s forming the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary side coil L2s.

[0164] Additionally, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0165] Furthermore, the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in [the diagram / description]. Figure 9 However, the primary coils have essentially the same structure as the secondary coils L1s to L4s, and are arranged directly below each of the secondary coils L1s to L4s in a manner that is opposite to them.

[0166] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. In addition, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0167] Additionally, pads a7 and b7 are connected to one end of the primary winding of the third transformer 303, and pads c4 and d4 are connected to the other end of the primary winding. Similarly, pads a8 and b8 are connected to one end of the primary winding of the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary winding.

[0168] However, the aforementioned pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the interior of the transformer chip 300 to the surface via through holes not shown.

[0169] Of the aforementioned pads, pads a1 to a8 correspond to the first current supply pads, and pads b1 to b8 correspond to the first voltage measurement pads. Additionally, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0170] Therefore, in the case of the transformer chip 300 of this structural example, the series resistance of each coil can be accurately measured during defect inspection. Thus, not only can defective products with open circuits in each coil be rejected, but defective products with abnormal resistance values ​​in each coil (e.g., short circuits between coils) can also be appropriately rejected, thereby preventing defective products from entering the market.

[0171] Furthermore, for the transformer chip 300 that has passed the aforementioned defective product inspection, it is sufficient to use the aforementioned multiple pads as connection units with the primary-side chip and the secondary-side chip (such as the previously mentioned controller chip 210 and driver chip 220).

[0172] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 can be connected to the signal input or signal output terminals of the secondary-side chip, respectively. In addition, pads c1 and d1, and pads c2 and d2 can be connected to the common voltage application terminal (GND2) of the secondary-side chip, respectively.

[0173] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 can be connected to the signal input or signal output terminals of the primary-side chip, respectively. In addition, pads c3 and d3, and pads c4 and d4 can be connected to the common voltage application terminal (GND1) of the primary-side chip, respectively.

[0174] Here, as Figure 9 As shown, the first transformer 301 to the fourth transformer 304 are coupled together according to their respective signal transmission directions. In conjunction with this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, form a first pair via the first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, form a second pair via the second guard ring 306.

[0175] The reason for this coupling is to ensure a withstand voltage between the primary and secondary coils when the primary and secondary coils that form the first transformer 301 to the fourth transformer 304 are stacked in a vertical configuration on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0176] In addition, the first protection ring 305 and the second protection ring 306 can be connected to low-impedance wiring such as the grounding terminal via pads e1 and e2, respectively.

[0177] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between secondary-side coils L1s and L2s. Pads c2 and d2 are shared between secondary-side coils L3s and L4s. Pads c3 and d3 are shared between primary-side coils L1p and L2p. Pads c4 and d4 are shared with their respective primary-side coils. By adopting this structure, the number of pads can be reduced, enabling miniaturization of the transformer chip 300.

[0178] In addition, such as Figure 9As shown, the primary and secondary coils of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track-like shape with rounded corners) in the top view of the transformer chip 300. By arranging it in this way, the area of ​​the overlapping parts of the primary and secondary coils is increased, which can improve the transmission efficiency of the transformer.

[0179] Of course, the transformer arrangement in this diagram is just one example; the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices that integrate coils onto a semiconductor chip.

[0180] <Signal Transmission Device (Implementation Method)>

[0181] Figure 10 This diagram illustrates an embodiment of the signal transmission device. The signal transmission device 400 of this embodiment is a semiconductor integrated circuit device (so-called an insulated gate driver IC) that electrically isolates the primary circuit system 400p (VCC1-GND1 system) from the secondary circuit system 400s (VCC2-GND2 system), and transmits pulse signals from the primary circuit system 400p to the secondary circuit system 400s to drive the gate of a power transistor (not shown) disposed in the secondary circuit system 400s. Furthermore, the signal transmission device 400 can be understood as equivalent to the previous signal transmission device 200.

[0182] The signal transmission device 400, as a unit for establishing an electrical connection with the outside of the device, has multiple external terminals (in this figure, power supply terminals VCC1 and VCC2, ground terminals GND1 and GND2, negative power supply terminal VEE2, input terminals INA and INB, output terminals OUT1H and OUT1L, fault terminal FLT, ready terminal RDY, and short circuit detection terminal SCPIN).

[0183] On the first side (left side in this figure) of the package forming the signal transmission device 400, from top to bottom, are arranged the ground terminal GND1, the fault terminal FLT, the input terminal INA, the input terminal INB, the ready terminal RDY, the power supply terminal VCC1, and the ground terminal GND1. On the other hand, on the second side of the package (the side opposite to the first side, right side in this figure), from top to bottom, are arranged the negative power supply terminal VEE2, the output terminal OUT1L, the output terminal OUT1H, the power supply terminal VCC2, the short circuit detection terminal SCPIN, the ground terminal GND2, and the negative power supply terminal VEE2.

[0184] In this way, the external terminals (GND1, FLT, INA, INB, RDY, and VCC1) of the primary circuit system 400p can be brought together to the first side of the package, and the external terminals (VEE2, OUT1L, OUT1H, VCC2, SCPIN, and GND2) of the secondary circuit system 400s can be brought together to the second side of the package.

[0185] Additionally, a grounding terminal GND1 and a negative power supply terminal VEE2 can be configured at both ends of the first and second sides of the package. That is, two grounding terminals GND1 and two negative power supply terminals VEE2 can be provided respectively.

[0186] Furthermore, the signal transmission device 400 can be widely used in all applications that require signal transmission between the primary circuit system 400p and the secondary circuit system 400s while maintaining insulation between them (such as high-voltage motor drivers or DC / DC converters).

[0187] Then, while referring to Figure 10 The internal structure of the signal transmission device 400 will be described below. In this example, the signal transmission device 400 is formed by sealing the controller chip 410 (equivalent to the first chip), the driver chip 420 (equivalent to the second chip), and the transformer chip 430 (equivalent to the third chip) in a single package.

[0188] The controller chip 410 is a semiconductor chip that integrates the circuit elements of a primary circuit system 400p that operates upon receiving a power supply voltage VCC1 (e.g., a maximum of 7V based on GND1). Furthermore, the controller chip 410 integrates, for example, logic circuitry 411, UVLO (undervoltage lockout) / OVLO (overvoltage lockout) circuitry 412, and NMOSFETs 413 and 414.

[0189] Logic circuit 411 generates a drive pulse signal PWM for the power transistor (not shown) based on the input pulse signals INA and INB. For example, if INB = H (logic level when disabled), then PWM = L (fixed value); if INB = L (logic level when enabled), then PWM = INA. Additionally, logic circuit 411 also has the following function: monitoring various abnormal detection signals of the signal transmission device 400 (undervoltage, overvoltage, short circuit, open circuit, overheating, abnormal load power supply, etc.), and driving NMOSFETs 413 and 414 based on the monitoring results, thereby determining the logic levels of the fault signal FLT and the ready signal RDY.

[0190] The UVLO / OVLO circuit 412 detects the undervoltage / overvoltage of the power supply voltage VCC1 respectively, and outputs the detection results to the logic circuit 411.

[0191] The NMOSFET 413 turns the fault terminal FLT on / off with the ground terminal according to the instruction from the logic circuit 411. For example, when overheating or an abnormal load power supply is detected in the driver chip 420, the NMOSFET 413 turns on and the fault terminal FLT goes low (the logic level when a fault is detected).

[0192] The NMOSFET 414 turns on / off between the ready terminal RDY and the ground terminal according to the instruction from the logic circuit 411. For example, when an undervoltage or overvoltage is detected in either the controller chip 410 or the driver chip 420, the NMOSFET 414 turns on, and the ready terminal RDY is low (the logic level when a fault is detected).

[0193] The driver chip 420 is a semiconductor chip that integrates the circuit elements of a secondary circuit system 400s that operates upon receiving a power supply voltage VCC2 (e.g., a maximum of 30V based on GND2). Furthermore, the driver chip 420 integrates, for example, logic circuit 421, UVLO / OVLO circuit 422, comparator 423, PMOSFET 424, and NMOSFETs 425 and 426.

[0194] Logic circuit 421 turns PMOSFET 424 and NMOSFET 425 on / off according to the drive pulse signal PWM input via transformer chip 430, thereby driving the gates of power transistors (not shown) connected to output terminals OUT1H and OUT1L. Furthermore, output terminals OUT1H and OUT1L can be shorted to each other externally by the signal transmission device 400. Additionally, logic circuit 421 also has the function of transmitting various abnormal detection signals (undervoltage, overvoltage, short circuit, open circuit, overheating, abnormal load power supply, etc.) from the driver chip 420 side to the controller chip 410 via transformer chip 430.

[0195] The UVLO / OVLO circuit 422 detects the undervoltage / overvoltage of the power supply voltage VCC2 respectively, and outputs the detection results to the logic circuit 421.

[0196] Comparator 423 performs short-circuit detection of the power transistor by monitoring the terminal voltage of the short-circuit detection terminal SCPIN (details to follow).

[0197] PMOSFET 424 is one of the gate drive transistors that turns the power supply terminal and the output terminal OUT1H on / off according to the instruction from logic circuit 421. For example, when the drive pulse signal PWM is high, PMOSFET 424 is turned on, and the output terminal OUT1H (and thus the output pulse signal applied to the gate of the power transistor) is high.

[0198] NMOSFET 425 is one of the gate drive transistors that turns the output terminal OUT1L on / off with the ground terminal according to the instruction from logic circuit 421. For example, when the drive pulse signal PWM is low, NMOSFET 425 is turned on, and the output terminal OUT1L (and thus the output pulse signal applied to the gate of the power transistor) is low.

[0199] In this way, PMOSFET 424 and NMOSFET 425 function as half-bridge output stages (CMOS (complementary MOS) inverter stages) for gate driving.

[0200] The NMOSFET 426 turns on / off between the ground terminal GND2 and the short-circuit detection terminal SCPIN according to the instruction from the logic circuit 421. For example, the NMOSFET 426 is off when OUT1H = H and on when OUT1H = L. Furthermore, the NMOSFET 426 functions as a discharge switch to discharge the capacitor (not shown) placed between SCPIN and GND2 by complementary on / off switching with the PMOSFET 424 (and thus a power transistor not shown) (described in detail later).

[0201] The transformer chip 430 is a semiconductor chip that integrates a transformer that insulates between the controller chip 410 and the driver chip 420 and enables bidirectional signal transmission.

[0202] Furthermore, the signal transmission device 400 of this embodiment, unlike the controller chip 410 and the driver chip 420, independently has a transformer chip 430 that only carries a transformer, and these three chips are sealed into a single package.

[0203] By adopting this structure, both the controller chip 410 and the driver chip 420 can be manufactured using general low- to medium-voltage processes (a few volts to tens of volts), thus eliminating the need for a dedicated high-voltage process (a few thousand volts), which reduces manufacturing costs.

[0204] In addition, both the controller chip 410 and the driver chip 420 can be manufactured using existing, time-proven processes without the need for re-testing for reliability, which helps to shorten the development period and reduce development costs.

[0205] Furthermore, even when using DC-insulated components other than transformers (such as optocouplers), it can be easily handled by simply replacing the transformer chip 430. Therefore, there is no need to redevelop the controller chip 410 and the driver chip 420, which helps to shorten the development period and reduce development costs.

[0206] <Electronic Devices>

[0207] Figure 11 This is a diagram illustrating a structural example of an electronic device equipped with a signal transmission device 400. The electronic device A of this structural example includes an upper gate driver IC 1H (u / v / w), a lower gate driver IC 1L (u / v / w), an upper power transistor 2H (u / v / w), a lower power transistor 2L (u / v / w), an ECU 3, and an electric motor 4.

[0208] The upper gate driver IC 1H (u / v / w) isolates the ECU 3 from the upper power transistor 2H (u / v / w) respectively, and generates an upper gate drive signal based on the upper gate control signal input from the ECU 3, thereby driving the upper power transistor 2H (u / v / w).

[0209] The lower gate driver IC 1L (u / v / w) isolates the ECU 3 from the lower power transistor 2L (u / v / w) and generates a lower gate drive signal based on the lower gate control signal input from the ECU 3, thereby driving the lower power transistor 2L (u / v / w).

[0210] Furthermore, the aforementioned upper gate driver IC 1H (u / v / w) and lower gate driver IC 1L (u / v / w) can preferably use the previously used signal transmission device 400.

[0211] The upper power transistors 2H (u / v / w) serve as the upper switches for forming a 3-phase (U-phase / V-phase / W-phase) half-bridge output stage, respectively, and are connected between the power system power supply terminals (the terminals for applying the load power supply voltage PVDD) and the input terminals of each phase of the motor 4.

[0212] The lower power transistors 2L (u / v / w) serve as the lower switches for forming a 3-phase (U-phase / V-phase / W-phase) half-bridge output stage, and are connected between the input terminals of each phase of the motor 4 and the power system ground terminal.

[0213] In this figure, IGBTs (Insulated Gate Bipolar Transistors) are used as the upper power transistor 2H (u / v / w) and the lower power transistor 2L (u / v / w), but MOSFETs (Metal-Semiconductor Field-Effect Transistors) can also be used instead of IGBTs.

[0214] ECU 3 drives upper power transistor 2H (u / v / w) and lower power transistor 2L (u / v / w) respectively via upper gate driver IC 1H (u / v / w) and lower gate driver IC 1L (u / v / w), thereby controlling the rotation drive of motor 4. In addition, ECU 3 also has the function of monitoring the fault terminal FLT and ready terminal RDY of upper gate driver IC 1H (u / v / w) and lower gate driver IC 1L (u / v / w) respectively, and performing various safety controls based on the monitoring results.

[0215] Motor 4 is a three-phase motor that is driven to rotate by the three-phase drive voltages U / V / W respectively input from the three-phase (U-phase / V-phase / W-phase) half-bridge output stage.

[0216] <Short Circuit (Through-Circuit) Detection>

[0217] Figure 12 This diagram shows a first connection example (DESAT method) of the short-circuit detection terminal SCPIN. For ease of illustration, only one phase of electronic device A is shown.

[0218] As shown in the figure, the lower gate driver IC 1L (signal transmission device 400) performing short-circuit detection in DESAT mode is externally connected to diode D1, resistors R0-R3, and capacitor C1. The first terminal of resistor R0 is connected to both output terminals OUT1H and OUT1L. The second terminal of resistor R0 is connected to the gate of the lower power transistor 2L. The first terminal of resistor R1 is connected to the power supply voltage VCC2 application terminal. The second terminal of resistor R1 and the first terminal of resistor R2 are both connected to the anode of diode D1. The cathode of diode D1 is connected to the junction of the emitter of the upper power transistor 2H and the collector of the lower power transistor 2L. The second terminal of resistor R2, the first terminal of resistor R3, and the first terminal of capacitor C1 are all connected to the short-circuit detection terminal SCPIN. The second terminals of resistor R3 and capacitor C1 are all connected to the ground terminal GND2.

[0219] Additionally, inside the lower gate driver IC 1L, the short-circuit detection terminal SCPIN is connected to comparator 423, NMOSFET 426, and diode 427.

[0220] Comparator 423 compares the short-circuit detection voltage SCPIN (terminal voltage of the short-circuit detection terminal SCP) input to the inverting input (-) with a specified threshold voltage Vth to generate a short-circuit detection signal SCP. The short-circuit detection signal SCP is high (normal logic level) when SCPIN < Vth, and low (abnormal logic level) when SCPIN > Vth.

[0221] The NMOSFET 426, in conjunction with the lower power transistor 2L and PMOSFET 424, turns on / off to switch the connection between the ground terminal GND2 and the short-circuit detection terminal SCPIN, thereby functioning as a discharge switch to discharge the capacitor C1 placed between SCPIN and GND2. For example, the NMOSFET 426 is off during the on-state of the lower power transistor 2L and PMOSFET 424, and on during the off-state of the lower power transistor 2L and PMOSFET 424.

[0222] Diode 427 is an electrostatic discharge protection diode whose anode is connected to the ground terminal GND2 and whose cathode is connected to the short-circuit detection terminal SCPIN.

[0223] Under normal conditions (with the upper power transistor 2H off and the lower power transistor 2L on), the cathode voltage Vx of diode D1 drops approximately to the voltage of the ground terminal GND2. Therefore, diode D1 is forward biased, and thus, the anode voltage Vy of diode D1 is approximately the forward voltage drop Vf. At this time, the short-circuit detection voltage SCPIN (={R3 / (R2+R3)×Vf}) is lower than the threshold voltage Vth, therefore, the short-circuit detection signal SCP is high (the logic level under normal conditions).

[0224] On the other hand, under short-circuit conditions (where both the upper power transistor 2H and the lower power transistor 2L are simultaneously conducting and potentially experiencing excessive short-circuit current), the cathode voltage Vx of diode D1 rises approximately to the load supply voltage PVDD. Therefore, diode D1 is reverse-biased, and its anode voltage Vy is approximately equal to the supply voltage VCC2. At this time, the short-circuit detection voltage SCPIN (={R3 / (R2+R3)×VCC2}) is higher than the threshold voltage Vth; therefore, the short-circuit detection signal SCP is low (the logic level under abnormal conditions).

[0225] Thus, in the DESAT mode, by monitoring the short-circuit detection voltage SCPIN, it is possible to detect whether the collector / emitter of the lower power transistor 2L is in an unsaturated state, that is, whether the upper power transistor 2H and the lower power transistor 2L are in a short-circuit state (and simultaneously in a conducting state).

[0226] Furthermore, logic circuit 421 has a protection function that forcibly cuts off the lower power transistor 2L when the aforementioned short-circuit detection signal SCP is low (the logic level during an abnormality). Additionally, after the lower power transistor 2L is forcibly cut off, logic circuit 421 turns on NMOSFET 426, causing capacitor C1 to discharge, thereby releasing the short-circuit detection state.

[0227] Figure 13This diagram illustrates a second connection example (emitter sensing mode) for the short-circuit detection terminal SCPIN, compared to the previous one. Figure 12 The same applies, but only one phase of electronic device A is shown.

[0228] As shown in the figure, resistors R0, R4, R5, and capacitor C1 are connected externally to the lower gate driver IC 1L (signal transmission device 400) which performs short-circuit detection using emitter sensing. The first terminal of resistor R0 is connected to both the output terminals OUT1H and OUT1L. The second terminal of resistor R0 is connected to the gate of the lower power transistor 2L. The first terminals of resistor R4 and capacitor C1 are each connected to the short-circuit detection terminal SCPIN. The second terminals of resistor R4 and resistor R5 are both connected to the emitter (sensing emitter) of the lower power transistor 2L. The second terminals of resistor R5 and capacitor C1 are each connected to the ground terminal GND2.

[0229] Under normal conditions (with the upper power transistor 2H off and the lower power transistor 2L on), no excessive short-circuit current flows through resistor R5. Therefore, the voltage Vz across resistor R5 drops to approximately the ground voltage GND2. At this time, the short-circuit detection voltage SCPIN (≈Vz) is lower than the threshold voltage Vth. Therefore, the short-circuit detection signal SCP is high (the logic level under normal conditions).

[0230] On the other hand, in a short-circuit state (where both the upper power transistor 2H and the lower power transistor 2L are simultaneously turned on and may experience excessive short-circuit current), the voltage Vz across resistor R5 rises to the voltage value corresponding to the short-circuit current Isc (=Isc×R5). At this time, the short-circuit detection voltage SCPIN (≈Vz) is higher than the threshold voltage Vth; therefore, the short-circuit detection signal SCP is low (the logic level during an abnormal situation).

[0231] In this way, if it is an emitter sensing method, by monitoring the short-circuit detection voltage SCPIN, it is possible to detect whether an excessive short-circuit current Isc flows in the lower power transistor 2L, that is, whether the upper power transistor 2H and the lower power transistor 2L are in a short-circuit state (and simultaneously in a conducting state).

[0232] <Open Circuit Detection Circuit>

[0233] Figure 14This is a diagram illustrating a structural example of an open-circuit detection circuit. The open-circuit detection circuit 429 in this structural example is a circuit block disposed in the driver chip 420 and used to detect whether the ground terminal GND2 of the secondary circuit system 400s is in an open-circuit state. The open-circuit detection circuit 429 includes a comparator 4291 and a shielding unit 4292. Additionally, in this figure, a diode 428 for electrostatic discharge protection is depicted connected between the negative power supply terminal VEE2 and the ground terminal GND2. Furthermore, in the following description, the terminal voltage of the ground terminal GND2 (the voltage inside the IC) is sometimes referred to as internal GND2.

[0234] Comparator 4291 generates a comparison signal SC by comparing the voltage at the ground terminal GND2 (input to the non-inverting input (+)) with the short-circuit detection terminal SCPIN (input to the inverting input (-)). The comparison signal SC is high when the difference between the voltages at the ground terminal GND2 and the short-circuit detection terminal SCPIN (i.e., internal GND2 - SCPIN) is higher than a predetermined threshold, and low when it is lower than the predetermined threshold. Furthermore, the circuit structure of comparator 4291 can be set to be the same as that of comparator 423.

[0235] The shielding processing unit 4292 performs shielding processing on the comparison signal SC during the specified shielding period. In this figure, for ease of illustration, it is depicted as if the fault signal FLT is directly output from the shielding processing unit 4292. However, in a practical context, the output signal of the shielding processing unit 4292 (equivalent to the open circuit detection result of the ground terminal GND2) and other abnormal detection signals in the driver chip 420 (such as overheating or load power abnormality detection signals) are logically processed. The result of the logical operation is then transmitted to the logic circuit 411 of the controller chip 410 via the transformer chip 430. The logic circuit 411 switches the NMOSFET 413 on / off, thereby determining the logic level of the fault signal FLT.

[0236] Thus, the lower gate driver IC 1L (signal transmission device 400) of this structural example has: a first external terminal (e.g., ground terminal GND2), which is configured to connect to the ground terminal of the secondary circuit system 400s; a second external terminal (e.g., short-circuit detection terminal SCPIN), which is configured such that the terminal voltage changes depending on whether the first external terminal is in an open-circuit state; and an open-circuit detection circuit 429, which monitors the terminal voltage of the second external terminal to perform open-circuit detection of the first external terminal.

[0237] The following, with Figure 14 Refer to together Figure 15 The open-circuit detection operation of the open-circuit detection circuit 429 is described in detail.

[0238] Figure 15 This diagram illustrates an example of open-circuit detection operation. From top to bottom, it depicts the input pulse signal INA, the output pulse signal OUT1H, the on / off state of the NMOSFET 426, the terminal voltages (solid and dashed lines) of the ground terminal GND2 and the short-circuit detection terminal SCPIN, the comparison signal SC, and the fault signal FLT. Furthermore, in the following explanation, the terminal voltage of the ground terminal GND2 (the voltage inside the IC) will sometimes be referred to as internal GND2, and the external ground voltage will be referred to as external GND2 for distinction.

[0239] When the input pulse signal INA is low, the output pulse signal OUT1H is also low, therefore, the lower power transistor 2L is turned off (the upper power transistor 2H is turned on). At this time, the NMOSFET 426, which functions as a discharge switch for capacitor C1, is turned on, thus creating a short circuit between the ground terminal GND2 and the short-circuit detection terminal SCPIN. Therefore, the terminal voltages of the ground terminal GND2 and the short-circuit detection terminal SCPIN are approximately the same (SCPIN≈internal GND2). As a result, the comparison signal SC is high (the logic level under normal conditions), and consequently, the fault signal FLT is high (NMOSFET 413 is turned off and the fault terminal FLT is in a high-impedance state).

[0240] On the other hand, when the grounding terminal GND2 is in an open circuit state, such as Figure 14 As shown by the thin dashed arrow, the circuit current IGND2 flows from the power supply terminal VCC2 through the circuit group of the secondary circuit system 400s (marked as GND2SYS in the figure), the internal wiring connected to the ground terminal GND2 (i.e., the ground wire inside the IC), and the NMOSFET 426 in the on state, toward the short-circuit detection terminal SCPIN.

[0241] The circuit current IGND2 flows from the short-circuit detection terminal SCPIN to the outside of the lower gate driver IC 1L (signal transmission device 400), and then through resistors R4 and R5 to the ground terminal of the secondary circuit system 400s. As a result, the terminal voltage of the short-circuit detection terminal SCPIN rises to the voltage value corresponding to the circuit current IGND2 and resistors R4 and R5 (=IGND2×(R4+R5)) with reference to the external GND2. However, during the low level of the output pulse signal OUT1H, the NMOSFET 426 is turned on, so the terminal voltages of the ground terminal GND2 and the short-circuit detection terminal SCPIN remain the same (SCPIN≈internal GND2). Therefore, the comparator signal SC remains high, and consequently, the fault signal FLT also remains high.

[0242] In addition, the resistance values ​​of resistors R4 and R5 should be set appropriately so that even if the terminal voltage of ground terminal GND2 (i.e., internal GND2) rises, it will not exceed the withstand voltage of diode 428 connected between ground terminal GND2 and negative power supply terminal VEE.

[0243] Subsequently, when the input pulse signal INA rises to a high level, the output pulse signal OUT1H also rises to a high level. Therefore, the lower power transistor 2L is turned on (the upper power transistor 2H is turned off). At this time, the NMOSFET 426 is turned off, therefore, the circuit current IGND2 is as follows... Figure 14 As indicated by the thin double-dotted arrow, the flow occurs via the body diode of the forward-biased diode 427 or NMOSFET 426.

[0244] Therefore, the terminal voltage of the ground terminal GND2 is higher than the terminal voltage of the short-circuit detection terminal SCPIN by the forward voltage drop Vf of diode 427 (or the body diode of NMOSFET 426) (internal GND2 = SCPIN + Vf, i.e., internal GND2 > SCPIN). As a result, the comparator signal SC is low (the logic level when an open circuit is detected), and consequently, in the logic circuit 411 of the controller chip 410, the fault signal FLT is latched low (i.e., NMOSFET 413 is in the on state). Furthermore, the threshold in comparator 4291 (i.e., the open-circuit detection voltage of GND2) can be appropriately set to account for the deviation of the forward voltage drop Vf (approximately 0.2V lower than the minimum value of the forward voltage drop Vf).

[0245] In ECU 3, by monitoring the aforementioned fault signal FLT, abnormalities in the lower gate driver IC 1L (including an open circuit in the ground terminal GND2) can be detected. Furthermore, as a condition for releasing the latch of the fault signal FLT, for example, the enable signal of the lower gate driver IC 1L (signal transmission device 400) can be restarted from ECU 3.

[0246] Furthermore, as described above, the open-circuit detection circuit 429 includes a shielding processing unit 4292 that performs shielding processing on the comparison signal SC so that the logic level of the fault signal FLT does not switch from the time the comparison signal SC falls to a low level until the shielding period T2 (e.g., at least 10 μs) has elapsed. Therefore, false open-circuit detection caused by noise can be prevented.

[0247] Furthermore, when NMOSFET 426 is turned on, SCPIN ≈ internal GND2, therefore, open-circuit detection of the ground terminal GND2 cannot be performed. Conversely, open-circuit detection of the ground terminal GND2 needs to be performed when NMOSFET 426 is turned off. NMOSFET 426 is turned off during the high level period of the output pulse signal OUT1H (and consequently the conduction period of the lower power transistor 2L), during which open-circuit detection of the ground terminal GND2 must be performed.

[0248] For example, when the switching frequency of the output pulse signal OUT1H is 10kHz and the duty cycle is 50%, the high-level period of the output pulse signal OUT1H is 50μs (assuming the high-level period T1 of the input pulse signal INA is 50μs or more). Therefore, the shielding period T2 can be set shorter than the conduction period of the lower power transistor 2L (e.g., the high-level period T1 of the input pulse signal INA), preferably T2 = 20μs (maximum 35μs).

[0249] In addition, the delay time from the detection of an open circuit until the fault signal FLT drops to a low level (the time required for transformer transmission and logic processing) can be around 10 to 36 μs.

[0250] Furthermore, the external terminal connected to the open-circuit detection circuit 429 is not limited to the short-circuit detection terminal SCPIN. It can be any external terminal configured such that the terminal voltage changes depending on whether the ground terminal GND2 is in an open-circuit state (for example, an external terminal connected to the ground terminal GND2 via a diode, and in which the circuit current flows out from the ground wire inside the device through a forward-biased diode when the ground terminal GND2 is in an open-circuit state).

[0251] Therefore, in the case that the terminal voltage of the short-circuit detection terminal SCPIN is not monitored in the open-circuit detection circuit 429, in other words, in the case that there is no element that would short-circuit the external terminal that is the monitoring object of the terminal voltage and the ground terminal GND2, the constraint of the shielding period T2 mentioned above does not need to be considered.

[0252] In addition, although not illustrated again, when the input pulse signal INA is high, even when the ground terminal GND2 is open, as mentioned above, the difference between the terminal voltages of the ground terminal GND2 and the short-circuit detection terminal SCPIN (i.e., internal GND2-SCPIN) is higher than the specified threshold, thus enabling open-circuit detection.

[0253] Furthermore, the above description gave an example of using the fault signal FLT to notify the ECU 3 of the open-circuit detection result of the ground terminal GND2, but the same notification can also be made using the ready signal RDY, for example. In this case, the output signal of the shielding processing unit 4292 (equivalent to the open-circuit detection result of the ground terminal GND2) is logically processed into the UVLO / OVLO detection signal in the driver chip 420, and then transmitted to the logic circuit 411 of the controller chip 410 via the transformer chip 430. The logic circuit 411 switches the NMOSFET 414 on / off, thereby determining the logic level of the ready signal RDY.

[0254] <Application to vehicles>

[0255] Figure 16 This is a diagram showing the exterior of a vehicle equipped with electronic devices. The vehicle B in this example is equipped with electronic devices B11 to B18 that operate by receiving power from a battery not shown in the diagram.

[0256] Vehicle B includes not only engine vehicles, but also electric vehicles (BEV [pure electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV [plug-in hybrid electric vehicle], or FCEV / FCV [fuel cell electric vehicle], etc.).

[0257] Furthermore, for ease of illustration, the mounting positions of electronic devices B11 to B18 in this diagram may sometimes differ from their actual positions.

[0258] Electronic device B11 is an electronic control unit that performs controls associated with the engine (injection control, electronic throttle control, idle speed control, oxygen sensor heater control, and cruise control, etc.) or controls associated with the electric motor (torque control and power regeneration control, etc.).

[0259] Electronic device B12 is a lamp control unit that controls the lighting and extinguishing of HID (High Intensity Discharge Lamp) or DRL (Daytime Running Light).

[0260] Electronic device B13 is a transmission control unit that performs controls associated with the transmission.

[0261] Electronic device B14 is a braking unit that performs control related to the motion of vehicle B (ABS [Anti-lock Braking System] control, EPS [Electric Power Steering System] control, electronic suspension control, etc.).

[0262] Electronic device B15 is a safety control unit that performs drive control for door locks or burglar alarms, etc.

[0263] Electronic equipment B16 refers to electronic equipment such as windshield wipers, power door mirrors, power windows, shock absorbers, power sunroofs, and power seats that are assembled into vehicle B at the factory shipment stage as standard equipment or optional items by the manufacturer.

[0264] Electronic device B17 refers to electronic devices such as in-vehicle A / V [audio / video] equipment, car navigation systems, and ETC [electronic toll collection system] that can be arbitrarily installed in vehicle B as user options.

[0265] Electronic equipment B18 refers to electronic devices such as vehicle-mounted blowers, oil pumps, water pumps, and battery cooling fans that have high-voltage electric motors.

[0266] Furthermore, electronic devices B11 to B18 can be understood as specific examples of electronic device A described above. That is, the signal transmission devices 200 and 400 described above can be assembled into any one of electronic devices B11 to B18.

[0267] <Summary>

[0268] The various implementation methods described so far will now be summarized in the following description.

[0269] For example, the signal transmission device disclosed in this specification isolates a primary circuit system from a secondary circuit system and transmits a drive signal for a gate drive transistor between the primary and secondary circuit systems. The signal transmission device is configured to have: a first external terminal configured to be connected to a ground terminal of the secondary circuit system; a second external terminal configured such that its voltage varies depending on whether the first external terminal is in an open-circuit state; and an open-circuit detection circuit that monitors the terminal voltage of the second external terminal to perform open-circuit detection of the first external terminal (first structure).

[0270] Furthermore, the signal transmission device constructed by the first structure described above can also be configured to further include: a diode, the anode of which is connected to the first external terminal and the cathode of which is connected to the second external terminal (second structure).

[0271] In addition, the signal transmission device composed of the first or second structure described above may also be configured to further include: a discharge switch that complements the gate driving transistor to turn on / off between the first external terminal and the second external terminal (third structure).

[0272] Alternatively, in the signal transmission device constructed by the third structure described above, the open-circuit detection circuit may be configured to perform the open-circuit detection when the discharge switch is turned off (fourth structure).

[0273] Alternatively, in a signal transmission device composed of any of the first to fourth structures described above, the open-circuit detection circuit may also be configured to include a comparator that compares the terminal voltages of the first external terminal and the second external terminal to generate a comparison signal (fifth structure).

[0274] Alternatively, in the signal transmission device constructed by the fifth structure described above, the open-circuit detection circuit may also include a shielding processing unit that performs shielding processing on the comparison signal during shielding (sixth structure).

[0275] Alternatively, in a signal transmission device configured with the sixth structure described above, the shielding period may be shorter than the conduction period of the gate driving transistor (seventh structure).

[0276] Alternatively, in a signal transmission device composed of any of the first to seventh structures described above, the open-circuit detection circuit may be configured to perform logical operations on the open-circuit detection result of the first external terminal and other abnormal detection signals, and output the result of the logical operations (eighth structure).

[0277] Alternatively, the signal transmission device composed of any of the first to eighth structures described above can also be configured to seal a first chip integrating the circuit elements of the primary circuit system, a second chip integrating the circuit elements of the secondary circuit system, and a third chip integrating an insulating element that insulates the primary circuit system from the secondary circuit system into a single package (ninth structure).

[0278] Additionally, for example, the electronic device disclosed in this specification has a power transistor and a gate driver IC that drives the gate of the power transistor, the gate driver IC being a signal transmission device (tenth structure) composed of any of the first to ninth structures described above.

[0279] Additionally, for example, the vehicle disclosed in this specification has an electronic device (eleventh structure) constituted by the tenth structure described above.

[0280] <Other variations>

[0281] Furthermore, various modifications can be made to the technical features disclosed in this specification, in addition to the embodiments described above, without departing from the spirit of the invention. That is, the embodiments described above should be considered illustrative rather than restrictive in all respects, and the scope of the invention is not limited to the embodiments described above, but should be understood to include all modifications falling within the meaning and scope equivalent to the claims.

[0282] Symbol Explanation

[0283] 1H (u / v / w) upper gate driver IC

[0284] 1L (u / v / w) lower-side gate driver IC

[0285] 2H(u / v / w) upper power transistor

[0286] 2L(u / v / w) lower-side power transistor

[0287] 3ECU

[0288] 4 Electric motor

[0289] 5 Semiconductor Devices

[0290] 11, 11A~11F low potential terminals

[0291] 12, 12A~12F high potential terminals

[0292] 21. Transformers 21A to 21D (Transformers)

[0293] 22 Low-potential coil (primary side coil)

[0294] 23 High-potential coil (secondary side coil)

[0295] 24 First inner end

[0296] 25 First lateral end

[0297] 26 First spiral section

[0298] 27 Second inner end

[0299] 28 Second lateral end

[0300] 29 Second spiral section

[0301] 31 First low-potential wiring

[0302] 32 Second Low Potential Wiring

[0303] 33 First High-Potential Wiring

[0304] 34 Second High Potential Wiring

[0305] 41 Semiconductor Chips

[0306] 42 First Main Face

[0307] 43 Second Main Face

[0308] 44A~44D chip sidewall

[0309] 45 First functional device

[0310] 51 Insulation layer

[0311] 52 Insulation Main Surface

[0312] 53A~53D Insulating Sidewalls

[0313] 55 Bottom insulation layer

[0314] 56. Topmost insulating layer

[0315] 57 interlayer insulation

[0316] 58 First Insulation Layer

[0317] 59 Second Insulation Layer

[0318] 60 Secondary functional devices

[0319] 61 Sealed conductor

[0320] 62 Device Area

[0321] 63 Outer region

[0322] 64 Sealed plug conductor

[0323] 65 Sealed through-hole conductor

[0324] 66 First inner region

[0325] 67 Second inner region

[0326] 71 Through-wiring

[0327] 72 Low-potential connection wiring

[0328] 73 Lead-out wiring

[0329] 74 First connecting plug electrode

[0330] 75 Second connecting plug electrode

[0331] 76 Pad Plug Electrode

[0332] 77 Substrate plug electrode

[0333] 78 First Electrode Layer

[0334] 79 Second electrode layer

[0335] 80 Wiring plug electrode

[0336] 81 High-potential connection wiring

[0337] 82 Pad Plug Electrode

[0338] 85. Dummy Pattern

[0339] 86 High-potential dummy pattern

[0340] 87 First High Potential Dummy Pattern

[0341] 88 Second High Potential Dummy Pattern

[0342] 89 First District

[0343] 90 Second Zone

[0344] 91 Third Region

[0345] 92 First connecting part

[0346] 93 First Pattern

[0347] 94 Second Pattern

[0348] 95 Third Pattern

[0349] 96 First outer weekly line

[0350] 97 Second outer weekly line

[0351] 98 First median line

[0352] 99 First connecting line

[0353] 100 slits

[0354] 130 Separation Structure

[0355] 140 Inorganic Insulation Layer

[0356] 141 First Inorganic Insulation Layer

[0357] 142 Second Inorganic Insulation Layer

[0358] 143 Low-potential pad opening

[0359] 144 High-potential pad opening

[0360] 145 Organic Insulation Layer

[0361] 146 Part One

[0362] 147 Part Two

[0363] 148 Low-potential terminal opening

[0364] 149 High-potential terminal opening

[0365] 200 Signal Transmission Device

[0366] 200p primary circuit system

[0367] 200s secondary circuit system

[0368] 210 controller chip (first chip)

[0369] 211 Pulse Transmission Circuit (Pulse Generator)

[0370] Buffers 212 and 213

[0371] 220 driver chip (second chip)

[0372] 221, 222 buffers

[0373] 223 Pulse Receiver Circuit (RS Flip-Flop)

[0374] 224 drives

[0375] 230 Transformer Chip (Third Chip)

[0376] 230a First wiring layer (lower layer)

[0377] 230b Second Wiring Layer (Upper Layer)

[0378] Transformers 231 and 232

[0379] 231p, 232p primary side coils

[0380] 231s and 232s secondary coils

[0381] 300 Transformer Chip

[0382] 301 First Transformer

[0383] 302 Second Transformer

[0384] 303 Third Transformer

[0385] 304 Fourth Transformer

[0386] 305 First Protection Ring

[0387] 306 Second Protective Ring

[0388] 400 Signal Transmission Device (Insulated Gate Driver IC)

[0389] 400p primary circuit system

[0390] 400s secondary circuit system

[0391] 410 controller chip

[0392] 411 Logic Circuits

[0393] 412UVLO / OVLO circuit

[0394] 413, 414N MOSFET

[0395] 420 driver chip

[0396] 421 Logic Circuits

[0397] 422UVLO / OVLO circuit

[0398] 423 comparator

[0399] 424P MOSFET

[0400] 425N MOSFET

[0401] 426N MOSFET (Discharge Switch)

[0402] 427 and 428 diodes

[0403] 429 Open Circuit Detection Circuit

[0404] 4291 comparator

[0405] 4292 Shielding Treatment Department

[0406] 430 Transformer Chip

[0407] A electronic device

[0408] Vehicle B

[0409] Electronic equipment (B11-B18)

[0410] C1 capacitor

[0411] D1 diode

[0412] pads a1 to a8 (equivalent to pads for the first current supply)

[0413] pads b1 to b8 (equivalent to pads used for the first voltage measurement)

[0414] C1 to C4 pads (equivalent to pads for the second current supply)

[0415] Pads d1 to d4 (equivalent to pads for second voltage measurement)

[0416] e1, e2 pads

[0417] L1p, L2p primary side coils

[0418] L1s, L2s, L3s, L4s secondary coils

[0419] Resistors R0, R1, R2, R3, R4, R5

[0420] T21, T22, T23, T24, T25, T26 external terminals

[0421] X First Direction

[0422] X21, X22, X23 internal terminals

[0423] Y second direction

[0424] Y21, Y22, Y23 wiring

[0425] Z-normal direction

[0426] Through holes Z21, Z22, and Z23.

Claims

1. A signal transmission device that isolates a primary circuit system from a secondary circuit system and transmits a drive signal for a gate drive transistor between the primary and secondary circuit systems, characterized in that, The signal transmission device has: The first external terminal is configured as a ground terminal connected to the secondary circuit system; The second external terminal is configured such that the terminal voltage varies depending on whether the first external terminal is in an open circuit state; An open-circuit detection circuit monitors the terminal voltage of the second external terminal to perform open-circuit detection of the first external terminal; and The diode has its anode connected to the first external terminal and its cathode connected to the second external terminal.

2. The signal transmission device according to claim 1, characterized in that, The signal transmission device further includes a discharge switch that complements the gate driving transistor in turning on / off the path between the first external terminal and the second external terminal.

3. A signal transmission device that isolates a primary circuit system from a secondary circuit system and transmits a drive signal for a gate drive transistor between the primary and secondary circuit systems, characterized in that, The signal transmission device has: The first external terminal is configured as a ground terminal connected to the secondary circuit system; The second external terminal is configured such that the terminal voltage varies depending on whether the first external terminal is in an open circuit state; An open-circuit detection circuit monitors the terminal voltage of the second external terminal to perform open-circuit detection of the first external terminal; and A discharge switch, which complements the gate drive transistor, turns on / off the path between the first external terminal and the second external terminal.

4. The signal transmission device according to claim 2 or 3, characterized in that, The open circuit detection circuit performs the open circuit detection when the discharge switch is turned off.

5. The signal transmission device according to any one of claims 1 to 3, characterized in that, The open-circuit detection circuit includes a comparator that compares the terminal voltages of the first external terminal and the second external terminal to generate a comparison signal.

6. The signal transmission device according to claim 5, characterized in that, The open-circuit detection circuit further includes a shielding processing unit that performs shielding processing on the comparison signal during shielding.

7. The signal transmission device according to claim 6, characterized in that, The shielding period is shorter than the conduction period of the gate driving transistor.

8. The signal transmission device according to any one of claims 1 to 3, characterized in that, The open-circuit detection circuit performs logical operations on the open-circuit detection result of the first external terminal and other abnormal detection signals, and outputs the result of the logical operations.

9. The signal transmission device according to any one of claims 1 to 3, characterized in that, A first chip integrating circuit elements of the primary circuit system, a second chip integrating circuit elements of the secondary circuit system, and a third chip integrating insulating elements that insulate between the primary circuit system and the secondary circuit system are sealed in a single package.

10. An electronic device, characterized in that, have: Power transistors; as well as A gate driver IC that drives the gate of the power transistor, the gate driver IC being a signal transmission device according to any one of claims 1 to 9.

11. A vehicle, characterized in that, have: The electronic device according to claim 10.

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