A novel precision adjustable temperature sensor circuit

Abstract

The application relates to a novel precision-adjustable temperature sensor circuit, wherein after power-on, a temperature sensing circuit starts to work, generates temperature-related voltages VREF and VT, a follower circuit guarantees that the temperature characteristics of a voltage V1 are consistent with VT, and level shifting is realized; a comparator circuit compares the voltage values of VREF and V2 under clock control, outputs corresponding high and low signals, the signals are locked through a latch, serial signals VA are generated, 10-bit control signals are generated through a serial-parallel conversion circuit, are fed back to a voltage control network to adjust the output value of V2, the adjustment is realized through successive approximation, until VREF and V2 are basically consistent, the system is stable, and finally a temperature value is read out through a digital signal VOUT[9:0]. The architecture has low power consumption, small chip area, omits a conventional ADC circuit, is easy to integrate, has high measurement precision, small chip area and low power consumption, and is very suitable for large-scale mixed integrated circuits for temperature monitoring.

Description

Technical Field

[0001] This invention relates to a novel temperature sensor circuit with adjustable precision, and more particularly to one that omits the conventional ADC circuit, saving chip area and power consumption, and belongs to the field of monitoring circuit design. Background Technology

[0002] In recent years, with the rapid development of integrated circuits, integration density has increased and feature size has decreased, leading to larger and larger chip sizes. For example, the overall power consumption of complex devices such as high-power network switching chips and multi-core processors has become more difficult to manage. Increased power consumption causes chip temperature to rise, and excessively high temperatures can seriously affect chip reliability. Moreover, this damage is irreversible and can lead to system failures. Therefore, temperature monitoring has become one of the issues that must be considered in chip design.

[0003] In addition, traditional temperature monitoring circuits are not only limited by chip area and circuit power consumption, but their temperature measurement errors are also greatly affected by factors such as power supply voltage and nonlinearity. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a novel temperature sensor circuit with adjustable accuracy. This temperature sensor has the advantages of high accuracy, small chip area and low power consumption.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A novel temperature sensor circuit with adjustable precision includes: a temperature sensing circuit, a follower circuit, a comparator circuit, a serial-to-parallel conversion circuit, and a latch;

[0007] The temperature sensing circuit collects the ambient temperature and generates a temperature voltage VT and a reference voltage VREF with different ambient temperature coefficients. The temperature voltage VT is transmitted to the follower circuit, and the reference voltage VREF is transmitted to the comparator circuit.

[0008] The follower circuit obtains the temperature voltage VT and receives the digital signal VOUT[9:0] fed back by the serial-to-parallel conversion circuit. The follower circuit adjusts the digital signal VOUT[9:0] according to the temperature voltage VT to obtain a specific temperature voltage V2 and transmits it to the comparator circuit.

[0009] The comparator circuit compares the specific temperature voltage V2 with the reference voltage VREF and obtains the digital signal V0 corresponding to the comparison result, which is then transmitted to the latch.

[0010] The latch receives multiple digital signals V0 and performs latching processing;

[0011] The serial-to-parallel conversion circuit receives the clock signal, converts the serial signal into a parallel signal, outputs the digital signal VOUT[9:0] and feeds it back to the follower circuit.

[0012] Preferably, the temperature sensing circuit includes: a PNP transistor [8:1], a PNP transistor [0], a PMOS transistor P0, a PMOS transistor P1, an operational amplifier, and a temperature adjustment module;

[0013] The source of PMOS transistor P0, the source of PMOS transistor P1, and the substrate are connected to power supply VDD. The gates of PMOS transistor P0 and PMOS transistor P1 are connected to the output of the operational amplifier. The drain of PMOS transistor P0 is connected to the negative input of the operational amplifier and the emitter of transistor PNP[0]. The drain of PMOS transistor P0 serves as the output of the temperature sensing circuit, outputting a temperature voltage VT to the follower circuit. The drain of PMOS transistor P1 is connected to the positive input of the operational amplifier and the output of the temperature adjustment module. The base and collector of transistors PNP[8:1] and PNP[0] are grounded. The emitter of transistor PNP[8:1] is connected to the input of the temperature control adjustment network. The emitter of transistor PNP[8:1] serves as the output of the temperature sensing circuit, outputting a reference voltage VREF to the comparator circuit.

[0014] Preferably, the operational amplifier includes: NMOS transistor N10, NMOS transistor N11, PMOS transistor P10, and PMOS transistor P11;

[0015] The sources and substrates of NMOS transistors N10 and N11 are grounded to GND. The sources and substrates of PMOS transistors P10 and P11 are connected to the power supply VDD. The gate of PMOS transistor P10 is connected to the gate of PMOS transistor P11, the drain of PMOS transistor P10, and the drain of NMOS transistor N10. The drain of PMOS transistor P11 serves as the output terminal VG of the operational amplifier. The drain of NMOS transistor N10 is connected to the gate of PMOS transistor P11.

[0016] Preferably, the temperature adjustment network includes: a 3 / 8 decoder, NMOS transistors N0, NMOS transistors N1, NMOS transistors N2, NMOS transistors N3, NMOS transistors N4, NMOS transistors N5, NMOS transistors N6, NMOS transistors N7, resistors R0, R1, R2, R3, R4, R5, R6, and R7;

[0017] The 3 / 8 decoder is controlled by the external input signal SEL[2:0]. The output of the 3 / 8 decoder is connected to the gates of NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7, respectively, and the sources of NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7 are also connected. After connection, it is connected to the emitter of the PNP [8:1] transistor; the drains of NMOS transistors N0, NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and NMOS transistor N7 are connected to the series resistors R0, R1, R2, R3, R4, R5, R6, and R7, respectively. The other end of resistor R0 is connected to the positive input of the operational amplifier as the output of the temperature adjustment network.

[0018] Preferably, the follower circuit includes: a PMOS transistor P2, an operational amplifier, and a voltage control network;

[0019] The source and substrate of PMOS transistor P2 are connected to power supply VDD, and the gate of PMOS transistor P2 is connected to the output of the operational amplifier. The drain of PMOS transistor P2 is connected to the negative input of the operational amplifier and the port V1 of the voltage control network.

[0020] Preferably, the comparator circuit includes: NMOS transistor N0, NMOS transistor N1, PMOS transistor P3, PMOS transistor P4 and PMOS transistor P5;

[0021] The sources and substrates of NMOS transistors N0 and N1 are grounded to GND. The gate of NMOS transistor N0 receives the reference voltage VREF. The gate of NMOS transistor N1 is connected to the output of the voltage control network. The drain of NMOS transistor N0 is connected to the drain of PMOS transistor P3. The sources and substrates of PMOS transistors P3 and P4 are connected to the power supply VDD. The gate of PMOS transistor P3 is connected to the gate of PMOS transistor P4, the drain of PMOS transistor P5, the drain of PMOS transistor P3, and the drain of NMOS transistor N0. The substrate of PMOS transistor P5 is connected to the power supply VCC. The gate of PMOS transistor P5 is connected to the serial-to-parallel conversion circuit and receives the clock signal CLK. The drain of NMOS transistor N1 is connected together with the drains of PMOS transistors P4 and P5 as the output of the comparator circuit, which transmits the digital signal V0 to the latch.

[0022] Preferably, the comparator circuit output is controlled by the clock signal CLK. The comparison result is output when the clock signal CLK is low, and the intermediate state is output when the clock signal CLK is high.

[0023] Preferably, when the clock signal CLK is low, the comparator circuit outputs the comparison result between the reference voltage VREF and the specific temperature voltage V2. If the reference voltage VREF is greater than the specific temperature voltage V2, the output is high; otherwise, the output is low-high. When the clock signal CLK is high, the output is in an intermediate state.

[0024] Preferably, the temperature voltage VT is greater than the reference voltage VREF; the ambient temperature coefficient corresponding to the temperature voltage VT is less than the ambient temperature coefficient corresponding to the reference voltage VREF.

[0025] Preferably, the follower circuit adjusts the digital signal VOUT[9:0] according to the temperature voltage VT to obtain a specific temperature voltage V2 and transmits it to the comparator circuit so that the specific temperature voltage V2 approaches the reference voltage VREF.

[0026] Compared with existing temperature sensor circuits, the present invention has the following advantages:

[0027] (1) The present invention adopts a novel serial-to-parallel conversion circuit and does not require an ADC, thus saving chip area and power consumption;

[0028] (2) The present invention uses two PNP transistors VBE with the same linearity but different voltage values ​​to sense the temperature and determine the temperature range, and the output accuracy is adjustable;

[0029] (3) The present invention achieves clock synchronization by controlling the output of the comparator through clock control, thus avoiding subsequent synchronization operations. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the temperature sensor structure.

[0031] Figure 2 This is the circuit diagram of an operational amplifier;

[0032] Figure 3 Circuit diagram for temperature adjustment network;

[0033] Figure 4 This is a circuit diagram of a voltage control network;

[0034] Figure 5 The circuit diagram is for a variable impedance network.

[0035] Figure 6 This is a circuit diagram of a serial-to-parallel conversion circuit. Detailed Implementation

[0036] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0037] This invention relates to a novel temperature sensor circuit with adjustable precision, which includes modules such as a temperature sensing circuit 101, a follower circuit 102, a comparator circuit 103, a serial-to-parallel conversion circuit 104, and a latch 105.

[0038] Temperature sensing circuit 101 collects ambient temperature and generates temperature voltage VT and reference voltage VREF with different ambient temperature coefficients. Temperature voltage VT is transmitted to follower circuit 102; reference voltage VREF is transmitted to comparator circuit 103.

[0039] The follower circuit 102 obtains the temperature voltage VT and receives the digital signal VOUT[9:0] fed back by the serial-to-parallel conversion circuit 104. The follower circuit 102 adjusts the digital signal VOUT[9:0] according to the temperature voltage VT to obtain a specific temperature voltage V2 and transmits it to the comparator circuit 103 to make the specific temperature voltage V2 approach the reference voltage VREF.

[0040] The temperature voltage VT is greater than the reference voltage VREF; the ambient temperature coefficient corresponding to the temperature voltage VT is less than the ambient temperature coefficient corresponding to the reference voltage VREF.

[0041] Comparator circuit 103 compares a specific temperature voltage V2 with a reference voltage VREF and obtains a digital signal V0 corresponding to the comparison result, which is then transmitted to latch 105.

[0042] The latch 105 receives multiple digital signals V0 and performs latching processing;

[0043] The serial-to-parallel conversion circuit 104 receives the clock signal, converts one latch signal output by the latch 105 into ten parallel signals, outputs the digital signal VOUT[9:0] to the outside and feeds it back to the follower circuit 102;

[0044] The temperature sensing circuit 101 outputs two voltage values ​​(VT and VREF) with the same linearity; the follower circuit 102 is used to divide the temperature voltage VT; the comparator circuit 103 is used to compare the magnitudes of the voltage values ​​(V2 and VREF) at both ends; and the serial-to-parallel conversion circuit 104 is used to convert the serial signal into a parallel signal.

[0045] This circuit differs from the conventional voltage-type temperature sensing circuit 101. After power-on, the temperature sensing circuit 101 starts working, generating temperature-related voltages VREF and VT. The follower circuit 102 ensures that the temperature characteristics of voltage V1 are consistent with VT, achieving level shifting. The temperature sensor uses a PNP transistor VBE as the sensing voltage. The temperature sensing circuit 101 outputs two voltage values ​​with the same linearity to divide the temperature range. The follower circuit 102 is used for level shifting; the comparator is used to compare the magnitudes of the voltage values ​​at both ends; the parallel-to-serial conversion module is used to convert the serial signal into a parallel signal. The comparator circuit 103 compares the voltage values ​​of VREF and V2 under clock control and outputs the corresponding high and low signals. After this signal is locked by the latch 105, a serial signal VA is generated. The serial signal VA is converted into a 10-bit control signal by the serial-to-parallel conversion circuit 104 and fed back to the voltage control network 113 to adjust the output value of V2. Through successive approximation adjustments, until VREF and V2 are basically consistent, the system reaches stability. Finally, the temperature value is read out through the digital signal VOUT[9:0]. This architecture features low power consumption, small chip area, and eliminates the need for conventional ADC circuitry, making it easy to integrate. It offers high measurement accuracy while maintaining a small chip area and low power consumption, making it highly suitable for large-scale hybrid integrated circuits for temperature monitoring. The comparator circuit 103's output is clock-controlled; it outputs the comparison result when the clock is low and an intermediate state when the clock is high.

[0046] The main function of the temperature sensing circuit 101 is to generate voltages VREF and VT with different linearity related to temperature, i.e., the ambient temperature coefficients of the temperature voltage VT and the reference voltage VREF are different. Figure 1 As shown, the temperature sensing circuit 101 includes: a PNP transistor [8:1], a PNP transistor [0], a PMOS transistor P0, a PMOS transistor P1, an operational amplifier 110, and a temperature adjustment module 112;

[0047] The source of PMOS transistor P0, the source of PMOS transistor P1, and the substrate are connected to power supply VDD. The gates of PMOS transistor P0 and PMOS transistor P1 are connected to the output of operational amplifier 110. The drain of PMOS transistor P0 is connected to the negative input of operational amplifier 110 and the emitter of transistor PNP[0]. The drain of PMOS transistor P0 serves as the output of temperature sensing circuit 101, outputting temperature voltage VT to follower circuit 102. The drain of PMOS transistor P1 is connected to the positive input of operational amplifier 110 and the output of temperature adjustment module 112. The base and collector of transistors PNP[8:1] and PNP[0] are grounded. The emitter of transistor PNP[8:1] is connected to the input of temperature control adjustment network. The emitter of transistor PNP[8:1] serves as the output of temperature sensing circuit 101, outputting reference voltage VREF to comparator circuit 103.

[0048] The main function of the operational amplifier 110 is to ensure Figure 1 The voltages across VP and VT are the same. P0 and P1 of the same size ensure the same drain current across their terminals. The device temperature is monitored using the VBE temperature characteristics of the PNP[8:0], and the output temperature is calibrated using a temperature adjustment module. The temperature adjustment network 112, controlled by a 3 / 8 decoder, controls the transmission gate switch to adjust the resistance value. For example... Figure 2 As shown, operational amplifier 110 includes: NMOS transistors N10 and N11, PMOS transistors P10 and P11. The sources and substrates of NMOS transistors N10 and N11 are grounded to GND. The sources and substrates of PMOS transistors P10 and P11 are connected to the power supply VDD. The gate of PMOS transistor P10 is connected to the gate of PMOS transistor P11, the drain of PMOS transistor P10, and the drain of NMOS transistor N10. The drain of PMOS transistor P11 serves as the output terminal VG of operational amplifier 110. The drain of NMOS transistor N10 is connected to the gate of PMOS transistor P11.

[0049] The main function of the temperature adjustment network 112 is to overcome the influence of process and nonlinear factors by decoding the adjustment resistor, optimize the voltage difference between VREF and VT, and complete the calibration of the output temperature. Figure 3 As shown, the temperature adjustment network 112 includes: a 3 / 8 decoder, NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7, and resistors R0, R1, R2, R3, R4, R5, R6, and R7. The 3 / 8 decoder is controlled by an external input signal SEL[2:0]. The output of the 3 / 8 decoder is connected to the gates of NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7, respectively. 0. The sources of NMOS transistors N1, N2, N3, N4, N5, N6, and N7 are connected to the emitter of a PNP transistor [8:1]. The drains of NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7 are connected to resistors R0, R1, R2, R3, R4, R5, R6, and R7, which are connected in series. The other end of resistor R0 is connected to the positive input of operational amplifier 110 as the output of temperature adjustment network 112.

[0050] The main function of the follower circuit 102 is to ensure that the temperature characteristics of voltage V1 are consistent with VT, and to output a variable voltage V2. The follower circuit 102 includes a PMOS transistor P2, an operational amplifier 111, and a voltage control network 113; the voltage control network 113 can achieve 2 10 A voltage value is output; the source and substrate of PMOS transistor P2 are connected to power supply VDD, the gate of PMOS transistor P2 is connected to the output terminal of operational amplifier 111; the drain of PMOS transistor P2 is connected to the negative input terminal of operational amplifier 111 and port V1 of voltage control network 113.

[0051] like Figure 4 As shown, the voltage control network 113 includes: an encoding circuit 201, NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7, a variable impedance network 202 (R0…R7), and a resistor R8. The variable impedance network 202 includes resistors R0, R1, R2, R3, R4, R5, R6, and R7. The encoding circuit 201 uses the high three bits of a parallel signal to select the output voltage range, and the low seven bits to fine-tune the output voltage. The outputs of the encoding circuit 201 are connected to the gates of NMOS transistors N0…N7, and the sources of N0…N7 are connected to port V2. The drains of N0…N7 are connected to the series-connected variable impedance network 202 (R0…R7) and resistor R8, with the other end of resistor R8 connected to GND. The input terminal of the encoding circuit 201 is connected to the serial-to-parallel conversion circuit 104 to receive the digital signal VOUT[9:0] fed back by the serial-to-parallel conversion circuit 104. The digital signal VOUT[9:0] includes VOUT[2:0] and VOUT[9:3]. The input of the encoding circuit 201 is controlled by VOUT[2:0]. The truth table is shown in Table 1. The default state of the circuit is 011. Under any state condition, only one of the NMOS transistors N0…N7 is turned on, completing the impedance range selection.

[0052] Table 1 Truth Table of Voltage Control Network 113 Encoding Circuit 201

[0053]

[0054]

[0055] The variable impedance network 202 functions to provide fine-tuning of the resistance, outputting different voltage values ​​so that the output voltage V2 successively approximates the reference voltage VREF. For example... Figure 5As shown, the variable impedance network 202 consists of NMOS transistors N0…N6 and resistors R0…R6. The source and drain of NMOS transistors N0…N6 are cascaded in sequence and then connected to the series-connected R0…R6. Finally, the source terminal of NMOS transistor N0 is connected to the unused terminal of resistor R0, and the drain terminal of NMOS transistor N6 is connected to the unused terminal of resistor R6.

[0056] The main function of the comparator circuit 103 is as follows: when the clock CLK is low, it outputs the comparison result between the reference voltage VREF and V2. If the reference voltage VREF is greater than V2, it outputs a high level; otherwise, it outputs a low level. When the clock is high, the output is in an intermediate state. The comparator circuit 103 includes: NMOS transistors N0 and N1, PMOS transistors P3, P4, and P5. The sources and substrates of NMOS transistors N0 and N1 are grounded to GND. The gate of NMOS transistor N0 receives the reference voltage VREF. The gate of NMOS transistor N1 is connected to the output V2 of voltage control network 113. The drain of NMOS transistor N0 is connected to the drain of PMOS transistor P3. The sources and substrates of PMOS transistors P3 and P4 are connected to power supply VDD. The gate of PMOS transistor P3 is connected to the gate of PMOS transistor P4, the drain of PMOS transistor P5, the drain of PMOS transistor P3, and the drain of NMOS transistor N0. The substrate of PMOS transistor P5 is connected to power supply VCC. The gate of PMOS transistor P5 is connected to serial-to-parallel conversion circuit 104 and receives clock signal CLK. The drain of NMOS transistor N1, the drain of PMOS transistor P4, and the drain of PMOS transistor P5 are connected together as the output of comparator circuit 103, which transmits digital signal V0 to latch 105.

[0057] The main function of the latch 105 is to lock and store the output of the comparator when the clock CLK is low, VA = V0; when the clock is high, the output remains unchanged, VA = VA.

[0058] like Figure 6 As shown, the serial-to-parallel conversion circuit 104 includes three logic units: flip-flops, NAND gates, and inverters. After the single-pulse signal is sampled by the first clock cycle, it is NAND-NOT-ed with the first bit of the serial signal VA. Since the pulse signal is high at this time, the output Q0 is the first bit of the VA data signal. After the first clock edge, the pulse signal remains low, so Q0 remains low until the 10th clock edge, until the next data cycle begins. The pulse signal after being sampled by the previous clock edge is input to the next stage flip-flop to complete the data conversion of the corresponding clock signal. This process is repeated until the serial data VA is converted into 10 bits of parallel data QN. The serial-to-parallel conversion circuit 104 does not require a high-speed clock signal; it can complete the serial-to-parallel conversion using only a low-speed clock.

[0059] The above description is only the best specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

[0060] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A novel temperature sensor circuit with adjustable precision, characterized in that, include: Temperature sensing circuit (101), follower circuit (102), comparator circuit (103), serial-to-parallel conversion circuit (104) and latch (105); The temperature sensing circuit (101) collects the ambient temperature and generates a temperature voltage VT and a reference voltage VREF with different ambient temperature coefficients. The temperature voltage VT is transmitted to the follower circuit (102); the reference voltage VREF is transmitted to the comparator circuit (103). The follower circuit (102) obtains the temperature voltage VT and receives the digital signal VOUT[9:0] fed back by the serial-to-parallel conversion circuit (104). The follower circuit (102) adjusts the digital signal VOUT[9:0] according to the temperature voltage VT to obtain a specific temperature voltage V2 and transmits it to the comparator circuit (103). The comparator circuit (103) compares the specific temperature voltage V2 with the reference voltage VREF and obtains the digital signal V0 corresponding to the comparison result, which is then transmitted to the latch (105). The latch (105) receives multiple digital signals V0 and performs latching processing; The serial-to-parallel conversion circuit (104) receives the clock signal, converts the serial signal into a parallel signal, outputs the digital signal VOUT[9:0] to the outside and feeds it back to the follower circuit (102). The follower circuit (102) includes: PMOS transistor P2, operational amplifier (111) and voltage control network (113); The source and substrate of PMOS transistor P2 are connected to power supply VDD, and the gate of PMOS transistor P2 is connected to the output terminal of operational amplifier (111). The drain of PMOS transistor P2 is connected to the negative input terminal of operational amplifier (111) and the port V1 of voltage control network (113). The voltage control network (113) includes: an encoding circuit (201), a third NMOS transistor N0, a fourth NMOS transistor N1, a fifth NMOS transistor N2, a sixth NMOS transistor N3, a seventh NMOS transistor N4, an eighth NMOS transistor N5, a ninth NMOS transistor N6, a tenth NMOS transistor N7, a variable impedance network (202), and a resistor R8; The output of the encoding circuit (201) is connected to the gates of the third NMOS transistor N0, the fourth NMOS transistor N1, the fifth NMOS transistor N2, the sixth NMOS transistor N3, the seventh NMOS transistor N4, the eighth NMOS transistor N5, the ninth NMOS transistor N6, and the tenth NMOS transistor N7, respectively. The source of the third NMOS transistor N0, the fourth NMOS transistor N1, the fifth NMOS transistor N2, the sixth NMOS transistor N3, the seventh NMOS transistor N4, the eighth NMOS transistor N5, the ninth NMOS transistor N6, and the tenth NMOS transistor N7 is connected to port V2. The drain of the third NMOS transistor N0, the fourth NMOS transistor N1, the fifth NMOS transistor N2, the sixth NMOS transistor N3, the seventh NMOS transistor N4, the eighth NMOS transistor N5, the ninth NMOS transistor N6, and the tenth NMOS transistor N7 is connected to the series-connected variable impedance network (202) and resistor R8, respectively. The other end of resistor R8 is connected to GND. The input of the encoding circuit (201) is connected to the serial-to-parallel conversion circuit (104). The positive input terminal of the operational amplifier (111) receives the temperature voltage VT output by the temperature sensing circuit (101).

2. The novel temperature sensor circuit with adjustable precision according to claim 1, characterized in that, The temperature sensing circuit (101) includes: a PNP transistor [8:1], a PNP transistor [0], a PMOS transistor P0, a PMOS transistor P1, a first operational amplifier (110), and a temperature adjustment network (112); The source of PMOS transistor P0, the source of PMOS transistor P1, and the substrate are connected to power supply VDD. The gates of PMOS transistor P0 and PMOS transistor P1 are connected to the output of the first operational amplifier (110). The drain of PMOS transistor P0 is connected to the negative input of the first operational amplifier (110) and the emitter of transistor PNP[0]. The drain of PMOS transistor P0 serves as the output of the temperature sensing circuit (101), outputting a temperature voltage V to the follower circuit (102). T; The drain of PMOS transistor P1 is connected to the positive input terminal of the first operational amplifier (110) and the output terminal of the temperature adjustment network (112); The base and collector of transistors PNP[8:1] and PNP[0] are grounded, the emitter of transistor PNP[8:1] is connected to the input terminal of the temperature control adjustment network, and the emitter of transistor PNP[8:1] serves as the output terminal of the temperature sensing circuit (101) to output the reference voltage VREF to the comparator circuit (103).

3. The novel temperature sensor circuit with adjustable precision according to claim 2, characterized in that, The first operational amplifier (110) includes: NMOS transistor N10, NMOS transistor N11, PMOS transistor P10 and PMOS transistor P11; The sources and substrates of NMOS transistors N10 and N11 are grounded to GND. The sources and substrates of PMOS transistors P10 and P11 are connected to the power supply VDD. The gate of PMOS transistor P10 is connected to the gate of PMOS transistor P11, the drain of PMOS transistor P10, and the drain of NMOS transistor N10. The drain of PMOS transistor P11 serves as the output terminal VG of the first operational amplifier (110). The drain of NMOS transistor N10 is connected to the gate of PMOS transistor P11.

4. A novel temperature sensor circuit with adjustable precision according to claim 3, characterized in that, The temperature adjustment network (112) includes: a 3 / 8 decoder, NMOS transistors N0, NMOS transistors N1, NMOS transistors N2, NMOS transistors N3, NMOS transistors N4, NMOS transistors N5, NMOS transistors N6, NMOS transistors N7, resistors R0, R1, R2, R3, R4, R5, R6, and R7; The 3 / 8 decoder is controlled by the external input signal SEL[2:0]. The output of the 3 / 8 decoder is connected to the gates of NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7, respectively. The sources of NMOS transistors N0, N1, N2, N3, N4, N5, N6, and N7 are connected to the transistors. The emitter of the PNP transistor [8:1] is connected; the drains of NMOS transistors N0, NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and NMOS transistor N7 are connected to resistors R0, R1, R2, R3, R4, R5, R6, and R7 respectively, which are connected in series. The other end of resistor R0 is connected to the positive input of the first operational amplifier (110) as the output of the temperature adjustment network (112).

5. A novel temperature sensor circuit with adjustable precision according to any one of claims 2 to 4, characterized in that, The comparator circuit (103) includes: a first NMOS transistor N0, a second NMOS transistor N1, a PMOS transistor P3, a PMOS transistor P4, and a PMOS transistor P5; The sources and substrates of the first NMOS transistor N0 and the second NMOS transistor N1 are grounded to GND. The gate of the first NMOS transistor N0 receives the reference voltage VREF. The gate of the second NMOS transistor N1 is connected to the output of the voltage control network (113). The drain of the first NMOS transistor N0 is connected to the drain of the PMOS transistor P3. The sources and substrates of the PMOS transistors P3 and P4 are connected to the power supply VDD. The gate of the PMOS transistor P3 is connected to the gate of the PMOS transistor P4, the drain of the PMOS transistor P5, the drain of the PMOS transistor P3, and the drain of the first NMOS transistor N0. The substrate of the PMOS transistor P5 is connected to the power supply VDD. The gate of the PMOS transistor P5 is connected to the serial-to-parallel conversion circuit (104) and receives the clock signal CLK. The drain of the second NMOS transistor N1 is connected together with the drains of the PMOS transistors P4 and P5 as the output of the comparator circuit (103) to transmit the digital signal V0 to the latch (105).

6. A novel temperature sensor circuit with adjustable precision according to claim 5, characterized in that, The output of the comparator circuit (103) is controlled by the clock signal CLK. When the clock signal CLK is low, the comparison result is output, and when the clock signal CLK is high, the intermediate state is output.

7. A novel temperature sensor circuit with adjustable precision according to claim 5, characterized in that, When the clock signal CLK is low, the comparator circuit (103) outputs the comparison result between the reference voltage VREF and the specific temperature voltage V2. If the reference voltage VREF is greater than the specific temperature voltage V2, the output is high; otherwise, the output is low. When the clock signal CLK is high, the output is in an intermediate state.

8. A novel temperature sensor circuit with adjustable precision according to claim 7, characterized in that, The temperature voltage VT is greater than the reference voltage VREF; the ambient temperature coefficient corresponding to the temperature voltage VT is less than the ambient temperature coefficient corresponding to the reference voltage VREF.

9. A novel temperature sensor circuit with adjustable precision according to claim 8, characterized in that, The follower circuit (102) adjusts the digital signal VOUT[9:0] according to the temperature voltage VT to obtain a specific temperature voltage V2 and transmits it to the comparator circuit (103) so that the specific temperature voltage V2 approaches the reference voltage VREF.

Images