Measurement device for acquiring a time delay of a test signal

Abstract

The application provides a measuring device for obtaining time delay of a test signal, which comprises a clock unit, a signal trigger unit, a phase detector, a clock pulse counting unit and a processing unit; the clock unit comprises a first clock and a second clock, the first clock provides a pulse signal with a first frequency, the second clock provides a pulse signal with a second frequency, a first signal triggers the first clock to start timing, and a second signal triggers the second clock to start timing; the phase detector obtains the timing termination time point of the first clock and the second clock; the clock pulse counting unit records the pulse number of the first clock and the pulse number of the second clock respectively; and the processing unit calculates the time delay result according to the total number of pulses generated by the first clock and the total number of pulses generated by the second clock. The application improves the measurement precision of the clock pulse signal without a clock with a higher frequency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a measuring device for acquiring the delay of test signals. Background Technology

[0002] In the field of Automatic Test Equipment (ATE), high-precision measurement of the signal timing of the chip under test is one of the important test elements for judging chip quality. In addition, in the field of signal measurement of communication equipment, the ability to achieve high-precision measurement of signal timing has always been a guarantee of high product reliability.

[0003] Currently, the pulse accuracy based on clock signal measurements is limited by the clock frequency, for example, such as Figure 1 As shown, the time between time point t1 and time point t2 is measured by counting clock pulses (rising edge) at a frequency of 200MHz. The measurement error is one clock cycle. In this example, the test error obtained is ±5ns. Under this test scheme, if the measurement accuracy is to be further improved, that is, to obtain measurement results on the order of nanoseconds, the clock frequency needs to be increased. That is, the order of magnitude of the measurement result is limited by the clock frequency.

[0004] Increasing the clock frequency can lead to problems such as power consumption, electromagnetic compatibility (EMC), and cost. Furthermore, due to current process and technology limitations, there is an upper limit to the clock frequency used to measure pulse accuracy. Generally, systems can only achieve the GHz level, which limits the accuracy of the measurement error.

[0005] This clock measurement scheme is clearly insufficient for some high-precision testing systems. Therefore, this invention proposes a measurement device for acquiring the time delay of test signals, which improves the measurement accuracy of clock pulse signals without being limited by the specific clock frequency. Summary of the Invention

[0006] This invention provides a measurement device for acquiring the delay of a test signal, which improves the measurement accuracy of clock pulse signals without requiring a higher frequency clock.

[0007] This invention provides a measurement device for acquiring the time delay of a test signal, comprising: a clock unit, a signal triggering unit, a phase detector, a clock pulse counting unit, and a processing unit. The processing unit is electrically connected to the clock unit, the signal triggering unit, the phase detector, and the clock pulse counting unit. The clock unit includes a first clock and a second clock. The first clock provides a pulse signal at a first frequency F1, and the second clock provides a pulse signal at a second frequency F2, wherein the first frequency F1 > the second frequency F2, and (first frequency F1 - second frequency F2) / first frequency F1 ≤ 5%. The signal triggering unit is electrically connected to the first clock and the second clock through the processing unit, and is used to generate a first signal and a second signal at the start point t1 and the end point t2 of the time delay, respectively. The first signal triggers the first clock to start timing, and the second signal triggers the second clock to start timing. The phase detector is electrically connected to the first clock and the second clock, respectively, and is used to record the phase of the first clock and the phase of the second clock in real time during the timing process of the first clock and the second clock. The processing unit obtains the timing termination time point t3 of the first clock and the second clock, where t3 is the moment when the phases of the first clock and the second clock first align. The clock pulse counting unit is electrically connected to the first clock and the second clock respectively, and is used to record the number of pulses of the first clock and the second clock respectively. The processing unit controls the clock pulse counting unit to start recording the number of pulses of the first clock and the second clock at the starting point t1 and the ending point t2 respectively, and triggers the counting termination point t4 of the first clock and the counting termination point t5 of the second clock according to the starting point t1, the ending point t2, and the timing termination time point t3, so as to obtain the total number of pulses n1 generated by the first clock and the total number of pulses n2 generated by the second clock respectively during the counting process of the clock pulse counting unit. The processing unit is also used to calculate the delay result Δ based on the total number of pulses n1 generated by the first clock and the total number of pulses n2 generated by the second clock. t .

[0008] The beneficial effects of the time delay measurement device for acquiring test signals provided by this invention are as follows: By establishing clocks of different frequencies, that is, providing pulse signals of a first frequency F1 and a second frequency F2, and (F1-F2) / F1≤5%, this invention can provide an accurate measurement reference for the subsequent time delay measurement process; through the first signal and the second signal, an independent control process for the first clock and the second clock is realized; and based on the start point t1, the end point t2, and the timing termination point t3, the counting termination point t4 of the first clock and the counting termination point t5 of the second clock are triggered, so as to obtain a more accurate result Δ of the time delay.t Under the premise of achieving the invention objective of not needing a higher frequency clock.

[0009] Optionally, the clock unit further includes: a delay estimation unit and a frequency selection unit; the delay estimation unit is used to obtain an estimated delay T0 based on historical time data of the chip under test, and transmit the estimated delay T0 to the frequency selection unit; the frequency selection unit is used to determine the first frequency F1 based on the estimated delay T0, and determine the second frequency F2 based on (F1-F2) / F1≤5%. Its advantages are: the clock unit provided by this invention selects its frequency based on the order of magnitude of the estimated delay, but through this invention, more accurate delay measurement results can be obtained compared to existing technologies.

[0010] Optionally, the first frequency F1 and the estimated time delay T0 satisfy the following relationship: F1 = 1 / T0.

[0011] Optionally, the counting termination point t4 of the first clock and the counting termination point t5 of the second clock are both the timing termination time point t3.

[0012] Optionally, the result of the time delay Δ t Δ is calculated using the following formula: t = (n1-1) / F1-(n2-1) / F2.

[0013] Optionally, the counting termination point t4 of the first clock is the end point t2 of the delay, and the counting termination point t5 of the second clock is the timing termination point t3.

[0014] Optionally, the result of the time delay Δ t Δ is calculated using the following formula: t = (n1+n2-1) / F1+(n2-1) / F2.

[0015] Optionally, the signal triggering unit includes: a first comparator and a second comparator; both the first input terminal of the first comparator and the first input terminal of the second comparator receive a test signal to obtain the actual value of the test signal; the second input terminal of the first comparator is fixedly connected to the starting target value of the test signal, and the second input terminal of the second comparator is fixedly connected to the ending target value of the test signal; the first comparator generates the first signal according to the actual value of the test signal and the starting target value of the test signal, and transmits the first signal to the processing unit; the time point at which the first signal is generated is the start point t1 of the delay; the processing unit triggers the first clock to start timing based on the first signal at the start point t1 of the delay; the second comparator generates the second signal according to the actual value of the test signal and the ending target value of the test signal, and transmits the second signal to the processing unit; the time point at which the second signal is generated is the end point t2 of the delay; the processing unit triggers the second clock to start timing based on the second signal at the end point t2 of the delay. Its advantages are: the signal triggering unit provided by the present invention can realize independent control of whether the timing of the first clock and the second clock is started, and it is convenient and fast.

[0016] Optionally, the test signal is an electrical signal generated by the automatic test system during the electrical performance test of the chip under test.

[0017] Optionally, the electrical signal includes at least one of a voltage signal, a current signal, and a resistance value. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an embodiment of the prior art used for measuring time error;

[0019] Figure 2 A schematic diagram of an embodiment of a device for measuring the delay of a test signal provided by the present invention;

[0020] Figure 3 A schematic diagram of another embodiment of the device for measuring the delay of acquiring test signals provided by the present invention;

[0021] Figure 4 A schematic diagram illustrating the working principle of an embodiment of a device for measuring the delay of a test signal provided by the present invention;

[0022] Figure 5 This is a schematic diagram illustrating the working principle of another device for measuring the delay of a test signal provided by the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of this application are described below with reference to the accompanying drawings. In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to limit the application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0024] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0025] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0026] In measurement or metrology systems, test accuracy often determines the system's test precision and reliability. This invention provides a measurement device for acquiring the delay of a test signal, improving the measurement accuracy of clock pulse signals without requiring a higher frequency clock. The delay mentioned herein refers to the duration of the test signal within a preset requirement, which can be the time from a certain start time to an end time. For example, it can be the time from the start of the rise of a signal to the end of the fall of a signal, a high-level duration of a signal, a low-level duration of a signal, or a pulse width.

[0027] This invention provides a measurement device for acquiring the time delay of a test signal, such as... Figure 2 As shown, it includes: a clock unit 201, a signal triggering unit 202, a phase detector 203, a clock pulse counting unit 204, and a processing unit 205. The processing unit 205 is electrically connected to the clock unit 201, the signal triggering unit 202, the phase detector 203, and the clock pulse counting unit 204, respectively. The clock unit 201 includes: a first clock 2011 and a second clock 2012. The first clock 2011 provides a pulse signal at a first frequency F1, and the second clock 2012 provides a pulse signal at a second frequency F2. F1 > second frequency F2, and (first frequency F1 - second frequency F2) / first frequency F1 ≤ 5%; the signal triggering unit 202 is electrically connected to the first clock 2011 and the second clock 2012 through the processing unit 205, and is used to generate a first signal and a second signal at the start point t1 and the end point t2 of the time delay, respectively. The first signal triggers the first clock 2011 to start timing, and the second signal triggers the second clock 2012 to start timing; the phase detector 203 is electrically connected to the first clock 2011 and the second clock 2012 respectively. Figure 2(Not shown), used to record the phase of the first clock 2011 and the phase of the second clock 2012 in real time during the timing process of the first clock 2011 and the second clock 2012, and to obtain the timing termination time point t3 of the first clock 2011 and the second clock 2012, wherein the timing termination time point t3 is the moment when the phase of the first clock 2011 and the phase of the second clock 2012 are first aligned; the clock pulse counting unit 204 is electrically connected to the first clock 2011 and the second clock 2012 respectively, and is used to record the number of pulses of the first clock 2011 and the number of pulses of the second clock 2012 respectively; the processing unit 205 controls the starting point t1 and the ending point t2 respectively. The clock pulse counting unit 204 starts recording the number of pulses of the first clock 2011 and the number of pulses of the second clock 2012, and triggers the counting termination point t4 of the first clock 2011 and the counting termination point t5 of the second clock 2012 according to the start point t1, the end point t2, and the timing termination point t3, so as to obtain the total number of pulses n1 generated by the first clock 2011 and the total number of pulses n2 generated by the second clock 2012 respectively during the counting process of the clock pulse counting unit 204; the processing unit 205 is further configured to calculate the delay result Δ based on the total number of pulses n1 generated by the first clock 2011 and the total number of pulses n2 generated by the second clock 2012. t .

[0028] The beneficial effects of the device for measuring the delay of acquiring test signals provided by this invention are as follows: By establishing clocks of different frequencies, that is, providing pulse signals of a first frequency F1 and a second frequency F2, and (F1-F2) / F1≤5%, this invention can provide a precise measurement reference for the subsequent measurement process of the delay of acquiring test signals; through the first signal and the second signal, an independent control process for the first clock and the second clock is realized; and based on the starting point t1, the ending point t2, and the timing termination point t3, the counting termination point t4 of the first clock and the counting termination point t5 of the second clock are triggered, so as to obtain a more accurate result Δ of the delay. t Under these conditions, there is no need to use a higher frequency clock.

[0029] In some embodiments, the clock unit further includes a delay estimation unit and a frequency selection unit; the delay estimation unit is used to obtain an estimated delay T0 based on historical time data of the chip under test, and transmit the estimated delay T0 to the frequency selection unit; the frequency selection unit is used to determine a first frequency F1 based on the estimated delay T0, and to determine a second frequency F2 based on (F1-F2) / F1≤5%. Its advantage is that the frequency of the clock unit provided by this invention can be selected according to the order of magnitude of the estimated delay, so as to obtain a more accurate measurement result of the delay of the acquired test signal. Further, the first frequency F1 and the estimated delay T0 satisfy the following relationship: F1=1 / T0, that is, this invention determines the first frequency F1 based on the reciprocal of the estimated delay T0 being equal to the first frequency F1.

[0030] For example, the first frequency F1 is 200MHz and the second frequency F2 is 199.9MHz. Of course, the specific scope of protection of this invention is not limited to these values. In fact, the specific values ​​of the first frequency F1 and the second frequency F2 can be flexibly selected according to the estimated time delay. Optionally, the first frequency F1 is 10MHz and the second frequency F2 is 9.9MHz; or the first frequency F1 is 1GHz and the second frequency F2 is 0.99GHz. Further, a ratio of the frequency difference between the first frequency F1 and the second frequency F2 to the first frequency F1 within 1% can achieve better measurement results. Of course, the values ​​in this embodiment are only examples and do not limit the actual scope of protection of this invention.

[0031] In some embodiments, the counting termination point t4 of the first clock and the counting termination point t5 of the second clock are both the timing termination time point t3.

[0032] In some embodiments, the result of the delay Δ t Δ is calculated using the following formula: t = (n1-1) / F1-(n2-1) / F2.

[0033] In some embodiments, the counting termination point t4 of the first clock is the end point t2 of the delay, and the counting termination point t5 of the second clock is the timing termination point t3.

[0034] In some embodiments, the result of the delay Δ t Δ is calculated using the following formula: t = (n1+n2-1) / F1+(n2-1) / F2.

[0035] In some embodiments, refer to Figure 3In (b), the signal triggering unit includes: a first comparator and a second comparator; the first input terminal of the first comparator and the first input terminal of the second comparator both receive a test signal to obtain the actual value Vt of the test signal, the second input terminal of the first comparator is fixedly connected to the starting target value VL-REF of the test signal, and the second input terminal of the second comparator is fixedly connected to the ending target value VH-REF of the test signal. The first comparator generates a first signal Trigger1 based on the actual value Vt of the test signal and the starting target value VL-REF of the test signal, and transmits the first signal Trigger1 to the processing unit. The time point at which the first signal Trigger1 is generated is the start point t1 of the delay. The processing unit triggers the first clock to start timing based on the first signal Trigger1 at the start point t1 of the delay. The second comparator generates a second signal Trigger2 based on the actual value Vt of the test signal and the ending target value VH-REF of the test signal, and transmits the second signal Trigger2 to the processing unit. The time point at which the second signal Trigger2 is generated is the end point t2 of the delay. The processing unit triggers the second clock to start timing based on the second signal Trigger2 at the end point t2 of the delay.

[0036] Furthermore, suppose we need to obtain the time delay during the signal rise of the test signal at a certain stage, that is, we need to obtain the time length during which the actual value Vt of the test signal rises from the initial target value VL-REF to the final target value VH-REF. At this time, the final target value VH-REF is greater than the initial target value VL-REF, then referring to... Figure 3 In (a), when the actual value Vt of the test signal reaches the initial target value VL-REF, the first comparator generates the first signal; when the actual value Vt of the test signal reaches the termination target value VH-REF, the second comparator generates the second signal. (Refer to...) Figure 3In example (a), the initial target value VL-REF is set to 10% of the target value of the test signal, and the final target value VH-REF is set to 90% of the target value of the test signal. This example illustrates that the purpose of this example is to obtain the time delay between 10% and 90% of the target value of the test signal. More specifically, taking a voltage as an example, and with a target value of 10V, to obtain the time delay required for the test signal to rise from 1V to 9V, the initial target value VL-REF is 1V, and the final target value VH-REF is 9V. This example is merely illustrative and is not intended to limit the actual scope of protection of the present invention. Furthermore, the relationship between the initial target value VL-REF and the final target value VH-REF is not fixed and can be adjusted according to testing requirements.

[0037] In some embodiments, the test signal is an electrical signal generated by the automated test system during the electrical performance testing of the chip under test. Further, the historical time data mentioned in the above embodiments refers to the relevant time data of the electrical signals generated by the automated test system during the electrical performance testing of the chip under test. The automated test system is prior art and includes an ATE (Automatic Test Equipment).

[0038] In some embodiments, the electrical signal includes at least one of a voltage signal, a current signal, and a resistance value.

[0039] To illustrate in more detail the working principle of the device for measuring the delay of acquiring test signals provided by this invention, a specific example is given below:

[0040] This embodiment provides a measurement device for acquiring the delay of a test signal. The device includes a clock unit, a first comparator, a second comparator, a phase detector, a clock pulse counting unit, and a processing unit. The clock unit includes a first clock and a second clock. The first clock provides a pulse signal with a first frequency F1 of 200MHz, and the second clock provides a pulse signal with a second frequency F2 of 199.9MHz. The phase detector is used to identify the moment when the phases of the pulse signals emitted by the 200MHz clock and the 199.9MHz clock first align, i.e., the pulse point. The first comparator is used to trigger the measurement start and end times of the first clock; the second comparator is used to trigger the measurement start and end times of the second clock. The processing unit controls the clock pulse counting unit to monitor and record the number of pulses of the first clock from the start time of the measurement to the end time of the measurement of the first clock. The processing unit controls the clock pulse counting unit to monitor and record the number of pulses of the second clock from the start time of the measurement to the end time of the measurement of the second clock. In this embodiment, the number of pulses refers to the number of rising edges of the pulses.

[0041] Its working principle is as follows:

[0042] The following is an example of using ATE to measure the rise time of a signal generated by a chip under test. However, the specific scope of protection of this invention is not limited to measuring the rise time of the generated signal. It may also include measuring the fall time of the generated signal, measuring the width of the high or low level of the signal, and the time delay of a certain segment of the signal.

[0043] like Figure 3 As shown in (a), to test whether the rise time of a signal transmitted by a chip under test (DUT) meets the requirements, the ATE needs to obtain the estimated rise time of the transmitted signal in advance based on the historical time data of the DUT. For example, the time between time point t1 and time point t2 measured by existing technology can be directly used as the estimated rise time, i.e., 5ns as the estimated rise time. Assuming that the estimated rise time is the time required for the test signal to rise from the initial target value VL-REF to the final target value VH-REF, and that the initial target value VL-REF is 10% of the target value of the test signal and the final target value VH-REF is 90% of the target value of the test signal, the first frequency F1 provided by the first clock is 200MHz, which is the reciprocal of 5ns, and the second frequency F2 provided by the second clock is 199.9MHz. The second frequency F2 is obtained according to the relationship with the first frequency F1.

[0044] Option 1:

[0045] When the actual value of the test signal reaches the initial target value VL-REF, the signal triggering unit generates a first signal Trigger1 at the starting point t1, starts the first clock to start timing, and starts the clock pulse counting unit to start counting the pulse signal of the first clock.

[0046] When the actual value of the test signal reaches the termination target value VH-REF, the signal triggering unit generates a second signal Trigger2 at the endpoint t2, the first clock continues to count, the second clock starts to count, and the clock pulse counting unit starts to count the pulse signal of the second clock.

[0047] During the timing of the first clock and the second clock, the phase detector monitors the phase of the pulse signals of the two clocks. When the phase detector detects that the pulse signals of the first clock and the second clock are in phase for the first time, that is, when they are in phase for the first time, or when their rising edges are aligned for the first time, the clock pulse counting unit stops counting the pulse signals of the first clock and the pulse signals of the second clock, and simultaneously turns off the first clock and the second clock. This is the timing termination time point t3. The total number of pulses generated by the first clock is n1, and the total number of pulses generated by the second clock is n2.

[0048] like Figure 4 As shown, in this scheme, the counting termination point t4 of the first clock and the counting termination point t5 of the second clock are both the timing termination time point t3. At this time, the rise time Δt is also the time delay, which is the time period between the starting point t1 and the ending point t2, and is equal to the counting time period of the first clock minus the counting time period of the second clock. The pulse period of the first clock is 1 / F1, and the pulse period of the second clock is 1 / F2. Therefore, Δt=(n1-1)×(1 / F1)-(n2-1)×(1 / F2)=(n1-1) / F1-(n2-1) / F2.

[0049] The second option:

[0050] When the actual value of the test signal reaches the initial target value VL-REF, the signal triggering unit generates a first signal Trigger1 at the starting point t1, starts the first clock to start timing, and starts the clock pulse counting unit to start counting the pulse signal of the first clock.

[0051] When the actual value of the test signal reaches the termination target value VH-REF, the signal triggering unit generates a second signal Trigger2 at the endpoint t2, the clock pulse counting unit stops counting the pulse signal of the first clock, and obtains the total count of pulses generated by the first clock as n1. At this time, the second clock starts timing, and the clock pulse counting unit starts counting the pulse signal of the second clock.

[0052] During the timing of the first clock and the second clock, the phase detector monitors the phase of the pulse signals of the two clocks. At the timing termination point t3, when the phase detector detects that the pulse signals of the first clock and the pulse signals of the second clock are in phase for the first time, that is, when the two are in phase for the first time, or when their rising edges are aligned for the first time, the clock pulse counting unit stops counting the pulse signal of the second clock, and the first clock and the second clock are turned off. This is the timing termination point t3. The total number of pulses generated by the second clock is n2.

[0053] like Figure 5 As shown, in this scheme, the counting termination point t4 of the first clock is the end point t2 of the delay, and the counting termination point t5 of the second clock is the timing termination time point t3. Therefore, the delay, i.e., the rise time Δt = t2 - t1, is calculated using the following formula:

[0054] Δt=t2-t1=(n1-1)×1 / F1+[n2×1 / F1-(n2-1)×1 / F2]=(n1+n2-1) / F1+(n2-1) / F2.

[0055] In both of the above schemes, when the clock pulse counting unit counts the pulse signals of the first clock and the second clock, it counts based on the number of rising edges of the pulse signals.

[0056] In the prior art, the measurement error obtained using a single clock with a frequency of 200MHz is 1 / F1 = 5ns. The measurement accuracy obtained by this measurement system is |1 / F1-1 / F2| = |(1 / 200M)-(1 / 199.9M)| = 2.5ps, which is equivalent to the measurement accuracy obtained using a single clock with a frequency of 400GHz. Therefore, the present invention can achieve a measurement accuracy 2000 times that of the prior art without using a higher frequency clock, which is 3-4 orders of magnitude higher.

[0057] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A measuring device for acquiring the time delay of a test signal, characterized in that, include: The system includes a clock unit, a signal triggering unit, a phase detector, a clock pulse counting unit, and a processing unit, wherein the processing unit is electrically connected to the clock unit, the signal triggering unit, the phase detector, and the clock pulse counting unit, respectively. The clock unit includes: a first clock and a second clock, wherein the first clock provides a pulse signal at a first frequency F1 and the second clock provides a pulse signal at a second frequency F2, wherein the first frequency F1 > the second frequency F2 and (first frequency F1 - second frequency F2) / first frequency F1 ≤ 5%. The signal triggering unit is electrically connected to the first clock and the second clock through the processing unit, and is used to generate a first signal and a second signal at the start point t1 and the end point t2 of the time delay, respectively. The first signal triggers the first clock to start timing, and the second signal triggers the second clock to start timing. The phase detector is electrically connected to the first clock and the second clock respectively, and is used to record the phase of the first clock and the phase of the second clock in real time during the timing process of the first clock and the second clock, and to obtain the timing termination time point t3 of the first clock and the second clock. The timing termination time point t3 is the moment when the phase of the first clock and the phase of the second clock are first aligned. The clock pulse counting unit is electrically connected to the first clock and the second clock respectively, and is used to record the number of pulses of the first clock and the number of pulses of the second clock respectively; The processing unit controls the clock pulse counting unit to start recording the number of pulses of the first clock and the number of pulses of the second clock at the starting point t1 and the ending point t2, respectively. Based on the starting point t1, the ending point t2, and the timing termination point t3, the processing unit triggers the counting termination point t4 of the first clock and the counting termination point t5 of the second clock, respectively, during the counting process of the clock pulse counting unit. The processing unit is also used to calculate the delay result Δ based on the total number of pulses n1 and n2 generated by the first clock and the second clock, respectively. t .

2. The device for measuring the time delay of acquiring a test signal according to claim 1, characterized in that, The clock unit further includes: a delay prediction unit and a frequency selection unit; The delay estimation unit is used to obtain the estimated delay T0 based on the historical time data of the chip under test, and transmit the estimated delay T0 to the frequency selection unit. The frequency selection unit is used to determine the first frequency F1 based on the estimated time delay T0, and to determine the second frequency F2 based on (F1-F2) / F1≤5%.

3. The device for measuring the time delay of acquiring a test signal according to claim 2, characterized in that, The first frequency F1 and the estimated time delay T0 satisfy the following relationship: F1 = 1 / T0.

4. The device for measuring the time delay of acquiring a test signal according to claim 1, characterized in that, The counting termination point t4 of the first clock and the counting termination point t5 of the second clock are both the timing termination time point t3.

5. The device for measuring the time delay of acquiring a test signal according to claim 4, characterized in that, The result of the delay Δ t Calculated using the following formula: Δ t =(n1-1) / F1-(n2-1) / F2。 6. The measuring device for acquiring the time delay of a test signal according to claim 1, characterized in that, The counting termination point t4 of the first clock is the end point t2 of the delay, and the counting termination point t5 of the second clock is the timing termination point t3.

7. The device for measuring the time delay of acquiring a test signal according to claim 6, characterized in that, The result of the delay Δ t Calculated using the following formula: Δ t (n1+n2-1) / F1+(n2-1) / F2 8. The measuring device for acquiring the time delay of a test signal according to claim 1, characterized in that, The signal triggering unit includes: a first comparator and a second comparator; Both the first input terminal of the first comparator and the first input terminal of the second comparator receive a test signal to obtain the actual value of the test signal. The second input terminal of the first comparator is fixedly connected to the starting target value of the test signal, and the second input terminal of the second comparator is fixedly connected to the ending target value of the test signal. The first comparator generates the first signal based on the actual value of the test signal and the starting target value of the test signal, and transmits the first signal to the processing unit. The time point at which the first signal is generated is the start point t1 of the time delay. The processing unit triggers the first clock to start timing based on the first signal at the start point t1 of the time delay. The second comparator generates the second signal based on the actual value of the test signal and the target value of the test signal, and transmits the second signal to the processing unit. The time point at which the second signal is generated is the end point t2 of the delay. The processing unit triggers the second clock to start timing based on the second signal at the end point t2 of the delay.

9. The measuring apparatus for acquiring the time delay of a test signal according to any one of claims 1-8, characterized in that, The test signal is an electrical signal generated by the automatic test system during the electrical performance test of the chip under test.

10. The measuring device for acquiring the time delay of a test signal according to claim 9, characterized in that, The electrical signal includes at least one of voltage signal, current signal, and resistance value.

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