A data sorting method and a data sorting circuit thereof
By receiving and comparing data in parallel, obtaining scores and accumulating them, and then reordering them, the method and circuit solve the problem of slow data sorting speed in existing technologies, and achieve real-time performance and cost-effectiveness in high-speed data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DAPUSTOR CORP
- Filing Date
- 2022-12-28
- Publication Date
- 2026-07-21
Smart Images
Figure CN116243882B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data processing technology, and in particular to a data sorting method and its data sorting circuit. Background Technology
[0002] In data and signal processing, one of the most fundamental problems is data sorting. Data sorting involves arranging data in a specific order so that researchers can identify obvious features or trends and find clues to solve problems by browsing the data. In addition, sorting also helps to check and correct errors in the data, and facilitates reclassification or grouping.
[0003] Existing data sorting methods typically employ algorithms such as bubble sort, selection sort, quick sort, and shell sort. However, these methods are relatively slow and struggle to meet real-time requirements in high-speed data transmission scenarios, such as compression and data processing.
[0004] Therefore, it is necessary to provide a data sorting circuit and a data sorting method thereof to solve the above-mentioned problems existing in the prior art. Summary of the Invention
[0005] In view of this, the purpose of this invention is to provide a data sorting method and a data sorting circuit that can meet the requirements of real-time performance.
[0006] The present invention also provides a data sorting method, the data sorting method comprising: receiving at least one set of input data from a plurality of input data in parallel; comparing the plurality of input data to be sorted pairwise and obtaining corresponding comparison values; obtaining a corresponding score value based on the comparison value corresponding to each input data; accumulating the score values corresponding to each input data to obtain a cumulative score value for each input data; and re-sorting the plurality of input data based on the cumulative score value for each input data.
[0007] In one embodiment, the step of receiving at least one set of input data from a plurality of input data in parallel includes: receiving the plurality of input data in parallel.
[0008] In one embodiment, the step of comparing multiple input data to be sorted pairwise and obtaining corresponding comparison values includes: if the number of multiple input data is N, comparing the i-th input data with each of the other input data after the i-th input data to output a comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N}, where i=1,2,…,N-1,j=i+1,i+2,…,N,Data_i n i Data_i represents the i-th input data. j This represents the j-th input data;
[0009]
[0010] In one embodiment, the step of obtaining the corresponding score value based on the comparison value corresponding to each input data includes: if the input data is Data_in L The corresponding score D L ={D L,1 ,…,D L,k ,…,D L,N}, L=1,2,3,…,N, K=1,2,3,…,N, then:
[0011]
[0012] In one embodiment, the step of accumulating the score values corresponding to each input data to obtain a cumulative score value for each input data includes: accumulating the score values corresponding to each input data to obtain a corresponding cumulative score value, wherein if the input data Data_in L The corresponding cumulative score is CNT. L ,but:
[0013]
[0014] In one embodiment, the step of reordering the plurality of input data according to the cumulative score of each input data includes: determining the sorting position of each input data according to the magnitude of the cumulative score of each data, and outputting the plurality of input data as output data in sequence after reordering them;
[0015] Among them, the m-th output data after reordering, Data_out m =Data_in L Where m = CNT L m = 0, 1, 2, ... N-1.
[0016] This invention provides a data sorting circuit, comprising a comparator, a scorer, an accumulator, and a reordering module. The comparator receives multiple input data to be sorted, compares each pair of input data, and outputs corresponding comparison values. The multiple input data are divided into at least one group, with multiple input data in each group input to the comparator in parallel. The scorer is connected to the output of the comparator and obtains a corresponding score value based on the comparison value for each input data. The accumulator is connected to the output of the scorer and accumulates the score values corresponding to each input data to obtain the score value for each input data. Indicates CO k, Invert.
[0017] The cumulative score of the input data. The reordering module is connected to the output of the accumulator and is used to reorder the multiple input data according to the cumulative score of each input data.
[0018] In one embodiment, the plurality of input data are divided into a group of input data and simultaneously input to the comparator in parallel.
[0019] In one embodiment, if the number of the plurality of input data is N, then the comparator includes N-1 sub-comparators, and the i-th sub-comparator includes Ni comparison units. The comparison units in the i-th sub-comparator are used to compare the i-th input data with other input data after the i-th input data to output a comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N}, where i=1,2,…,N-1,j=i+1,i+2,…,N.
[0020] In one embodiment, the scorer includes N sub-scorers, each sub-scorer being used to obtain a score value for a corresponding input data compared with other input data; wherein, if the input data Data_in L The corresponding score D L ={D L,1 ,…,D L,k ,…,D L,N}, L=1,2,3,…,N, K=1,2,3,…,N, then:
[0021] in, Indicates CO k, Invert.
[0022] In one embodiment, the accumulator includes N sub-accumulators, each sub-accumulator being connected to a sub-scorer in a one-to-one correspondence. Each sub-accumulator is used to accumulate the score values in the corresponding sub-scorer to obtain the cumulative score value of the corresponding input data. Wherein, if the input data is Data_in... L The corresponding cumulative score is CNT. L ,but:
[0023]
[0024] In one embodiment, the reordering module determines the sorting position of each input data based on the cumulative score of each data, and arranges the multiple input data in sequence.
[0025] In one embodiment, the plurality of input data is divided into two groups of input data, and the two groups of input data are sequentially input to the comparator.
[0026] In one embodiment, the comparator includes a first half-comparator and a second half-comparator. The first half-comparator is used to compare data in a first set of input data pairwise in a first clock cycle and to compare data in a second set of input data pairwise in a second clock cycle; the second half-comparator is used to compare data between the first set of input data and the second set of input data pairwise in a second clock cycle.
[0027] In one embodiment, if the number of the plurality of input data is N, and N is an even number, and the first group of input data and the second group of input data each include N / 2 input data, then the first half-comparator includes N / 2-1 sub-half-comparators. The nth sub-half-comparator in the first half-comparator includes N / 2-n comparison units, where n = 1, 2, ..., N / 2-1. The comparison unit in the i-th sub-half-comparator of the first half-comparator is used to compare the i-th input data in the first group of input data with the other input data after the i-th input data in the first group of input data within the first clock cycle, so as to output a comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N / 2}, where i = 1, 2, ..., N / 2-1, j = i+1, i+2, ..., N / 2; the second half comparator includes N / 2 sub-half comparators, each of which includes N / 2 comparison units. The comparison units in the second half comparator are used to compare the i-th input data in the first group of input data with each input data in the second group of input data within the second clock cycle, so as to output the comparison value {CO}. i,N / 2+1 ,…,CO i,j ,…,CO i,N}. Where i = 1, 2, ..., N / 2, j = N / 2+1, N / 2+2, ..., N; wherein, the comparison unit in the i-th sub-half comparator of the first half comparator is also used to compare the i-th input data in the second group of input data with the other input data after the i-th input data in the second group of input data in the second clock cycle, so as to output the comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N}, where i=N / 2+1, N / 2+2,…, N-1, j=i+1,i+2,…,N.
[0028] In one embodiment, the scorer includes N / 2 sub-scorers, which are used to acquire the score value of the first set of input data in a third clock cycle and the score value of the second set of input data in a fourth clock cycle.
[0029] In one embodiment, the accumulator includes N / 2 sub-accumulators, which are used to acquire the cumulative score of the first set of input data in the fourth clock cycle and the cumulative score of the second set of input data in the fifth clock cycle. The beneficial effects of the technical solution provided by this embodiment of the invention are:
[0030] The data sorting method and circuit provided by this invention compare multiple parallel input data pairs, output the corresponding comparison values, obtain the corresponding score value based on the comparison value of each input data, and then accumulate the scores of each input data to obtain the cumulative score value of each input data. Finally, the multiple input data are reordered based on the cumulative score value of each input data. Therefore, the data sorting circuit and data sorting method provided by this invention can meet the real-time requirements of data sorting. In one embodiment, the data sorting circuit can simultaneously and in parallel input to the comparator, thereby requiring only 4 clock cycles for sorting. This fewer clock cycles result in faster sorting speed and further improves the real-time performance of data sorting. In another embodiment, all input data can be divided into two groups of input data, with multiple input data in each group being input to the comparator in parallel. The two groups of input data are then input to the comparator sequentially. A scorer with a number of input data items less than, for example, half the number of input data items is used to process the comparison value, and an accumulator with a number of input data items less than, for example, half the number of input data items is used to process the score value. This method requires fewer clock cycles, has a faster sorting speed, and can improve the real-time performance of data sorting while reducing the number of logic elements, thereby reducing costs and simplifying the structure of the data sorting circuit.
[0031] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0032] Figure 1 This is a flowchart illustrating a data sorting method according to an embodiment of the present invention.
[0033] Figure 2 This is a schematic diagram of a data sorting circuit according to an embodiment of the present invention.
[0034] Figure 3 This is a circuit diagram of a data sorting circuit according to an embodiment of the present invention.
[0035] Figure 4As an embodiment of the present invention Figure 3 The timing diagram of the data sorting circuit shown is shown.
[0036] Figure 5 This is a circuit diagram of a data sorting circuit according to another embodiment of the present invention.
[0037] Figure 6 As an embodiment of the present invention Figure 5 The timing diagram of the data sorting circuit shown is shown. Detailed Implementation
[0038] To further illustrate the technical means and effects of the present invention in order to achieve the intended purpose, the following detailed description of the specific implementation methods, steps, structures, features and effects of the sorting circuit proposed according to the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.
[0039] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.
[0040] It should be understood that although the terms first, second, third, etc., may be used in this document to describe various modules or information, these modules or information should not be limited to these terms. These terms are only used to distinguish modules or information of the same type from one another. For example, without departing from the scope of this document, a first module may also be referred to as a second module, and similarly, a second module may also be referred to as a first module.
[0041] Figure 1 This is a flowchart illustrating a data sorting method according to an embodiment of the present invention. Figure 1 As shown, the data sorting method includes the following steps:
[0042] Step S11: Receive at least one set of input data from multiple input data sets in parallel;
[0043] Step S12: Compare each pair of the multiple input data to be sorted and obtain the corresponding comparison values;
[0044] Step S13: Obtain the corresponding score value based on the comparison value corresponding to each input data;
[0045] Step S14: Sum the scores corresponding to each input data to obtain the cumulative score for each input data.
[0046] Step S15: Reorder the multiple input data according to the cumulative score of each input data.
[0047] In one embodiment, step S11: receiving multiple input numbers in parallel includes: receiving the multiple input data in parallel.
[0048] In one embodiment, step S12: comparing each pair of input data to be sorted and obtaining the corresponding comparison value includes: if the number of input data is N, comparing the i-th input data with each of the other input data after the i-th input data to output the comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N}, where i=1,2,…,N-1,j=i+1,i+2,…,N.
[0049] In one implementation, if Data_in i Data_i represents the i-th input data. j Let j be the j-th input data.
[0050]
[0051] In one embodiment, step S13: obtaining the corresponding score value based on the comparison value corresponding to each input data, including: if the input data Data_in L The corresponding score D L ={D L,1 ,…,D L,k ,…,D L,N}, L=1,2,3,…,N, K=1,2,3,…,N, then:
[0052] in, Indicates CO k, Invert.
[0053] In one embodiment, step S14: accumulating the score values corresponding to each input data to obtain a cumulative score value for each input data, includes: accumulating the score values corresponding to each input data to obtain a corresponding cumulative score value, wherein if the input data Data_in L The corresponding cumulative score is CNT. L ,but:
[0054]
[0055] In one embodiment, step S15: reordering the plurality of input data according to the cumulative score of each input data includes: determining the sorting position of each input data according to the magnitude of the cumulative score of each data, and outputting the plurality of input data as output data in sequence after reordering them;
[0056] Among them, the m-th output data after reordering, Data_out m =Data_in L Where m = CNT L m = 0, 1, 2, ... N-1.
[0057] If the actual number of input data is odd, a reference input data can be set to make the number of input data even, thus allowing the input data to be sorted using the method described above. The value of the reference input data can be smaller than any actual input data, and the output data corresponding to the smallest input data after sorting will be used, for example, the (N-1)th output data after reordering, Data_out. N-1 Simply discard it.
[0058] Specifically, in one embodiment, the steps in the data sorting method can be implemented in part or in whole in hardware, or in part or in whole in software code, and the present invention is not limited thereto.
[0059] The present invention also provides a data sorting circuit, such as Figure 2 As shown, the data sorting circuit includes a comparator 10, a scorer 11, an accumulator 12, and a reordering module 13.
[0060] The comparator 10 receives multiple input data to be sorted, compares each pair of input data, and outputs the corresponding comparison value. The multiple input data are divided into at least one group, and the multiple input data in each group are input to the comparator 10 in parallel. In one embodiment, the multiple input data are divided into one group. In other embodiments, the multiple input data can also be divided into multiple groups, which are input to the comparator 10 sequentially. For example, the first group of input data is input to the comparator 10 within one clock cycle, and the second group of input data is input to the comparator 10 within another clock cycle.
[0061] In one embodiment, to compare multiple input data pairs individually using comparison units and avoid redundant comparisons between input data (e.g., avoiding a comparison where, after comparing the first input data with the second input data, the second input data is then compared with the first input data), if the number of multiple input data is N, then comparator 10 may include N-1 sub-comparators. The nth sub-comparator 10 includes Nn comparison units, where n = 1, 2, 3, ..., N-1. Specifically, the first sub-comparator includes N-1 comparison units for comparing the first input data with other input data, the second sub-comparator includes N-2 comparison units for comparing the second input data with subsequent input data, and so on, with the Nth sub-comparator including one comparison unit for comparing the (N-1)th input data with the Nth input data. That is, comparator 10 may include a total of N(N-1) / 2 comparison units. In other embodiments, if the number of multiple input data is N, the comparator 10 may also include more or fewer comparison units than N(N-1) / 2.
[0062] Specifically, in one embodiment, if the number of multiple input data is 8, the comparator may include 28 comparison units, wherein the first and second comparison units are used to compare the first input data Data_in1 and the second input data Data_in2 to output the first and second comparison value C. 1,2 The first and third comparison units are used to compare the first input data Data_in1 with the second input data Data_in3 to output the first and third comparison value C. 1,3 Similarly, the first eight-comparison unit is used to compare the first input data Data_in1 with the eighth input data Data_in8 to output the first eight-comparison value C. 1,8 The second and third comparison units are used to compare the second input data Data_in2 with the third input data Data_in3 to output the second and third comparison values C. 2,3 The second and fourth comparison units are used to compare the second input data Data_in2 with the fourth input data Data_in4 to output the second and fourth comparison value C. 2,4 Similarly, the second octet comparison unit compares the second input data Data_in2 with the eighth input data Data_in8 to output the second octet comparison value C. 2,8 Similarly, the seventh and eighth comparison units are used to compare the seventh input data Data_in7 with the eighth input data Data_in8 to output the seventh and eighth comparison value C. 7,8 .
[0063] The scorer 11 is connected to the output of the comparator 10 and is used to obtain the corresponding score value based on the comparison value corresponding to each input data. In one embodiment, if the number of multiple input data is N, the scorer 11 may include N sub-scorers, each sub-scorer corresponding to one input data. The sub-scorers can specifically be D flip-flops or memory devices such as SM (Smart Media Card). In other embodiments, each sub-scorer can be reused between different clock cycles to correspond to multiple input data. For example, the first sub-scorer obtains the score value corresponding to the first input data in one clock cycle and obtains the score value corresponding to the fifth input data in another clock cycle. Therefore, the scorer 11 may also include fewer than N sub-scorers, such as N / 2 sub-scorers, (N+1) / 2 sub-scorers, N / 3 sub-scorers, etc.
[0064] The accumulator 12 is connected to the output of the scorer 11 and is used to accumulate the score value corresponding to each input data to obtain the cumulative score value of each input data. In one embodiment, if the number of multiple input data is N, the accumulator 12 may include N sub-accumulators, each sub-accumulator corresponding to one input data. In other embodiments, each sub-accumulator may also be reused between different clock cycles to correspond to multiple input data. For example, the first sub-accumulator obtains the accumulated value corresponding to the first input data in one clock cycle and is used to obtain the accumulated value corresponding to the fifth input data in another clock cycle. Therefore, the accumulator 12 may also include fewer than N sub-accumulators, such as N / 2 sub-accumulators, (N+1) / 2 sub-accumulators, N / 3 sub-accumulators, etc.
[0065] The reordering module 13 is connected to the output of the accumulator 12 and is used to reorder multiple input data according to the cumulative score of each input data, and output the reordered input data as output data. In one embodiment, the input data with the largest cumulative score can be placed at the beginning, thereby rearranging the input data in ascending order, or the input data with the smallest cumulative score can be placed at the beginning, thereby rearranging the input data in descending order.
[0066] Figure 3 This is a circuit diagram of a data sorting circuit according to an embodiment of the present invention. Figure 3 As shown, multiple input data Data_in 1,…， Data_i n N The input data is divided into a set and input to comparator 10a in parallel, where N is a positive integer greater than 1.
[0067] In one embodiment, if the number of multiple input data is N, then comparator 10a includes N-1 sub-comparators, and the i-th sub-comparator includes Ni comparison units. The comparison units in the i-th sub-comparator are used to compare the i-th input data with other input data after the i-th input data to output a comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N}, where i=1,2,…,N-1,j=i+1,i+2,…,N.
[0068] Specifically, in one embodiment, if the number of multiple input data is 8, then comparator 10a includes 8 sub-comparators. The first sub-comparator includes 7 comparison units, the second sub-comparator includes 6 comparison units, the third sub-comparator includes 5 comparison units, the fourth sub-comparator includes 4 comparison units, the fifth sub-comparator includes 3 comparison units, the sixth sub-comparator includes 2 comparison units, and the seventh sub-comparator includes 1 comparison unit. The comparison units in the first sub-comparator are used to output the comparison value {CO} between the first input data and the subsequent input data (the second to the eighth input data). 1,2 ,…,CO 1,4 ,…,CO 1,8 The comparison unit in the second sub-comparator is used to output the comparison value {CO} between the second input data and the subsequent input data (the third to the eighth input data). 2,3 ,…,CO 2,4 ,…,CO 2,8}. Similarly, the comparison unit in the seventh sub-comparator is used to output the comparison value {CO} between the seventh input data and the eighth input data. 7,8}
[0069] In one embodiment, the output C of the comparison unit of the sub-comparator in comparator 10a i,j With the i-th input data Data_i n i and the j-th input data Data_i n j The relationship is as follows:
[0070]
[0071] Specifically, in one embodiment, if the number of input data is 8, and the first input data is the smallest among all input data, then the comparison value {CO} of the first input data with the subsequent input data (the second to the eighth input data) is used to determine the smallest input data. 1,2 ,…,CO 1,4 ,…,CO 1,8 All are 1.
[0072] In one embodiment, if the number of input data is N, then the scorer 11a includes N sub-scorers, each sub-scorer being used to obtain a score value for a corresponding input data compared with other input data; wherein, if the input data Data_in L The corresponding score D L ={D L,1 ,…,D L,k ,…,D L,N}, L=1,2,3,…,N, K=1,2,3,…,N, then:
[0073] in, Indicates CO k, Invert.
[0074] Specifically, if L = 2, then the score D2 corresponding to the second input data Data_in2 = {D 2,1 ,…,D 2,4 ,…,D 2,N In one embodiment, as described above, the comparison unit of comparator 10a only outputs the comparison value CO between the first input data and the second input data. 1,2 However, it did not output the comparison value CO between the second input data and the first input data. 2,1 Therefore, the score D obtained by comparing the second input data with the first input data is... 2,1 It is necessary to pass CO 1,2 Obtained by inverting. For example, if the comparison value CO of the first input data and the first input data... 1,2 If the value is 1, then the score D obtained by comparing the second input data with the first input data is... 2,1 For example, if the comparison value CO of the first input data is 0, or if the comparison value of the first input data and the first input data is 0. 1,2 If the value is 0, then the score D obtained by comparing the second input data with the first input data is... 2,1 The value is 1.
[0075] In one embodiment, the accumulator 12a includes N sub-accumulators 12a, each sub-accumulator 12a being connected to a sub-scorer 11a in a one-to-one correspondence. Each sub-accumulator 12a is used to accumulate the score values in the corresponding sub-scorer 11a to obtain the cumulative score value of the corresponding input data. Wherein, if the input data Data_in L The corresponding cumulative score is CNT. L ,but:
[0076]
[0077] If the number of input data is 8, and the first input data is the smallest among all input data, then the comparison value of the first input data with the other input data (the second to the eighth input data) is {CO}. 1,2 ,…,CO 1,4 ,…,CO 1,8 All values are 1. The score D1 corresponding to the first input data is D1 = {D 1,1 ,…,D 1,4 ,…,D 1,8}={CO 1,1 ,…,CO 1,4 ,…,CO 1,8 If}={0,1,1,1,1,1,1,1}, then if the cumulative score corresponding to the first input data Data_in1 is CNT1=0+1+1+1+1+1+1+1=7.
[0078] In one embodiment, the reordering module 13a determines the sorting position of each input data based on the cumulative score of each data and rearranges the multiple input data.
[0079] In one implementation, the input data is Data_in L The corresponding cumulative score CNT L It can also directly represent the sorting position of the Lth input data among the N input data. Where, CNT L The value range is [0, N-1], where L = 1, 2, ..., N. That is, the m-th output data is Data_out. m =Data_in L Where m = CNT L , m = 0, 1, 2, ..., N-1. Specifically, if the cumulative score corresponding to the first input data Data_in1 is CNT1 = 7, then Data_out7 = Data_in1.
[0080] Figure 4 As an embodiment of the present invention Figure 3 The timing diagram of the data sorting circuit is shown below. Please also refer to... Figure 3 and Figure 4In one embodiment, if multiple input data are input to comparator 10a in parallel within the fourth clock cycle, comparator 10a can compare the multiple input data pairwise within the fifth clock cycle to output the corresponding comparison values. Scorer 11a can obtain the corresponding score value based on the comparison value of each input data within the sixth clock cycle. Accumulator 12a can obtain the corresponding cumulative score value based on the score value of each input data within the seventh clock cycle. Reordering module 13a can determine the sorting position of each input data based on the cumulative score value of each input data within the eighth clock cycle and then rearrange and output the multiple input data. Therefore, in one embodiment, the sorting circuit can reorder and output N input data within four clock cycles (i.e., from the fifth to the eighth clock cycle). Furthermore, the number of comparison units in comparator 11a can be set to N(N-1) / 2, and the number of sub-scorers and sub-accumulators can both be set to N. Therefore, the sorting circuit of this embodiment requires fewer clock cycles, has a faster sorting speed, and can improve real-time performance while reducing the use of logic elements.
[0081] Figure 5 This is a circuit diagram of a sorting circuit according to another embodiment of the present invention. Figure 5 As shown, in one embodiment, multiple input data are divided into two groups of input data, and the two groups of input data are sequentially input to comparator 10b. Specifically, for example, the first group of input data is input to comparator 10b in parallel within one clock cycle, and the second group of input data is input to comparator 10b in parallel within another clock cycle. Specifically, if N equals 8, the 8 input data are divided into two groups, the first group of input data includes the first to fourth input data, and the second group of input data includes the fifth to eighth input data.
[0082] In one embodiment, comparator 10b includes a first half-comparator 101b and a second half-comparator 102b. The first half-comparator 101b is used to acquire a comparison value between a first set of input data within a first clock cycle, and also to acquire a comparison value between a second set of input data within a second clock cycle. The second half-comparator 102b is used to acquire a comparison value between the first set of input data and the second set of input data within a second clock cycle.
[0083] In one embodiment, if the number of multiple input data is N, and N is an even number, the first half-comparator 101b includes N / 2-1 sub-half-comparators. The nth sub-half-comparator in the first half-comparator 101b includes N / 2-n comparison units, where n = 1, 2, ..., N / 2-1, that is, the first half-comparator 101b includes N*(N-2) / 8 comparison units. The comparison unit in the i-th sub-half-comparator of the first half-comparator 101b is used to compare the i-th input data in the first group of input data with the other input data after the i-th input data in the first group of input data within the first clock cycle, so as to output a comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N / 2}, where i=1,2,…,N / 2-1,j=i+1,i+2,…,N / 2.
[0084] Specifically, if N equals 8, then the first half comparator 101b includes three sub-half comparators. Each first sub-half comparator in the first half comparator 101b includes three comparison units, and is used to compare the first input data in the first group of input data with the second, third, and fourth input data in the first group of input data respectively within the first clock cycle, to output a comparison value {CO}. 1,2 CO 1,3 CO 1,4 The second sub-half comparator in the first half comparator 101b includes two comparison units, which are used to compare the second input data with the third input data and the fourth input data respectively, so as to output the comparison value {CO}. 2,3 CO 2,4 The third sub-half comparator in the first half comparator 101b includes a comparison unit and is used to compare the third input data with the fourth input data to output a comparison value {CO}. 3,4}
[0085] In one embodiment, the second half comparator 102b includes N / 2 sub-half comparators, and each sub-half comparator in the second half comparator includes N / 2 comparison units, that is, the second half comparator 102b includes N... 2 / 4 comparison units. The comparison units in the second half of the sub-comparator are used to compare the i-th input data in the first group of input data with each input data in the second group of input data within the second clock cycle, to output the comparison value {CO}. i,N / 2+1 ,…,CO i,j ,…,CO i,N}. Among them, i=1,2,…,N / 2,j=N / 2+1,N / 2+2,…,N.
[0086] Specifically, if N equals 8, then the second half comparator 102b includes four sub-half comparators. The first sub-half comparator in the second half comparator 102b includes four comparison units, which are used to compare the first input data in the first group of input data with each input data in the second group of input data (i.e., the fifth to eighth input data) respectively within the second clock cycle, so as to output the comparison value {CO}. 1,5 CO 1,6 CO 1,7 CO 1,8 The second sub-comparator in the second half-comparator 102b includes four comparison units, which are used to compare the second input data with each input data in the second set of input data (i.e., the fifth to eighth input data) to output a comparison value {CO}. 2,5 CO 2,6 CO 2,7 CO 2,8 The third sub-half comparator in the second half comparator 102b includes four comparison units, which are used to compare the third input data with each input data in the second set of input data (i.e., the fifth to eighth input data) to output a comparison value {CO}. 3,5 CO 3,6 CO 3,7 CO 3,8 The fourth sub-half comparator in the second half comparator 102b includes four comparison units, which are used to compare the fourth input data with each input data in the second set of input data (i.e., the fifth to eighth input data) to output a comparison value {CO}. 4,5 CO 4,6 CO 4,7 CO 4,8}
[0087] In one embodiment, the comparison unit in the i-th sub-half comparator of the first half comparator 101b is further configured to compare the i-th input data in the second set of input data with the other input data after the i-th input data in the second set of input data within the second clock cycle, so as to output a comparison value {CO}. i,i+1 ,…,CO i,j ,…,CO i,N}, where i = N / 2+1, N / 2+2, ..., N-1, j = i+1, i+2, ..., N. If N equals 8, then the first sub-half comparator in the first half comparator 101b is also used to compare the fifth input data in the second group of input data with the sixth, seventh, and eighth input data in the second group of input data respectively within the second clock cycle, so as to output the comparison value {CO}. 5,6 CO 5,7 CO5,8 The second sub-comparator in the first half-comparator 101b is also used to compare the sixth input data with the seventh and eighth input data respectively, so as to output the comparison value {CO}. 6,7 CO 6,8 The third sub-half comparator in the first half comparator 101b is also used to compare the seventh input data with the eighth input data to output a comparison value {CO}. 7,8}
[0088] In one embodiment, the scorer 11b includes multiple sub-scorers, which are used to acquire the score value of the first set of input data in the third clock cycle and the score value of the second set of input data in the fourth clock cycle. In one embodiment, the number of input data in the first set of input data and the second set of input data is the same. If the number of input data in both the first set of input data and the second set of input data is N / 2, where N is a multiple of 2, then the scorer 11b includes N / 2 sub-scorers. The scorer 11b is used to acquire the score value of the first N / 2 data (i.e., the first set of input data) in the third clock cycle and the score value of the last N / 2 data (i.e., the second set of input data) in the fourth clock cycle. The working principle of the scorer 11b is as follows: Figure 3 The scoring device 11a shown works on a similar principle, and will not be described in detail here.
[0089] In one embodiment, the accumulator 12b includes multiple sub-accumulators, which are used to acquire the cumulative score of the first group of input data in the fourth clock cycle and the cumulative score of the second group of input data in the fifth clock cycle. In one embodiment, the number of input data in the first group of input data and the second group of input data is the same. If the number of input data in both the first group of input data and the second group of input data is N / 2, where N is a multiple of 2, then the accumulator 12b includes N / 2 sub-accumulators. The accumulator 12b is used to acquire the cumulative score of the first N / 2 data (i.e., the first group of input data) in the fourth clock cycle and the cumulative score of the last N / 2 data (i.e., the second group of input data) in the fifth clock cycle. The working principle of the accumulator 12b is as follows: Figure 3 The accumulator 12a shown works on a similar principle, and will not be described in detail here.
[0090] In one embodiment, the reordering module 13b determines the sorting position of each input data based on the cumulative score of each data and rearranges the multiple input data.
[0091] If the actual number of input data is odd, a reference input data can be set to make the number of input data even, thus allowing the circuit described above to sort the input data. The value of the reference input data can be smaller than any actual input data. In this case, the reordering module 13b will output the smallest input data, for example, the (N-1)th reordered output data, Data_out. N-1 Simply discard it.
[0092] Figure 6 As an embodiment of the present invention Figure 5 The timing diagram of the data sorting circuit is shown below. Please also refer to... Figure 5 and Figure 6 In one embodiment, if the first set of input data from a plurality of input data is input to comparator 10b in parallel within a third clock cycle, and the second set of input data is input to comparator 10b within a fourth clock cycle, then comparator 10b can compare each pair of input data from the first set of input data in the fourth clock cycle to output a comparison value between the first set of input data. Furthermore, comparator 10b also compares each pair of input data from the second set of input data in the fifth clock cycle, and compares each pair of data from the first set of input data with each pair of data from the second set of input data, to output a comparison value between the second set of input data and a comparison value between the two sets of input data. Scorer 11b can acquire a score value corresponding to a portion (e.g., the first N / 2, where N is a multiple of 2) of the input data in the sixth clock cycle, and acquire a score value corresponding to another portion (e.g., the last N / 2) of the input data in the seventh clock cycle. Accumulator 12b can obtain the corresponding cumulative score value based on the score value corresponding to a portion (e.g., the first N / 2) of input data within the seventh clock cycle, and can obtain the corresponding cumulative score value based on the score value corresponding to another portion (e.g., the last N / 2) of input data within the eighth clock cycle. Reordering module 13a can determine the sorting position of each input data based on the cumulative score value corresponding to each input data within the ninth clock cycle, and then rearrange and output the multiple input data. Therefore, in one embodiment, the sorting circuit can reorder and output N input data within four clock cycles (i.e., from the fourth to the ninth clock cycle). Furthermore, the number of comparison units in comparator 10b can be set to N(3N-2) / 8, and the number of sub-scorers in scorer 11b and sub-accumulators in accumulator 12b can both be set to N / 2. Therefore, the sorting circuit of one embodiment of the present invention can improve real-time performance while further reducing the use of logic elements.
[0093] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.
[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the invention without departing from the scope of the invention shall still fall within the scope of the present invention.
Claims
1. A data sorting method, characterized in that, The sorting method includes: At least one set of input data from a plurality of input data is received in parallel, wherein the plurality of input data is divided into two sets of input data, and the two sets of input data are received sequentially. Within the first clock cycle, the data in the first set of input data are compared pairwise, and within the second clock cycle, the data in the second set of input data are compared pairwise. In the second clock cycle, the data between the first set of input data and the second set of input data are also compared pairwise to obtain the corresponding comparison values. The score is obtained based on the comparison value corresponding to each input data point; The scores corresponding to each input data point are summed to obtain the cumulative score for each input data point. Based on the cumulative score of each input data, the sorting position of each input data is determined, and the multiple input data are reordered and then output as multiple output data in sequence. The steps to obtain the corresponding comparison value include: If the number of input data is N, and N is even, the first group of input data and the second group of input data each include N / 2 input data. The comparison unit in the i-th sub-half comparator of the first half comparator compares the i-th input data in the first group of input data with all other input data after the i-th input data within the first clock cycle, and outputs a comparison value {C}. i,i+1 ,…,C i,j ,…,C i,N / 2 },where,i=1,2,…,N / 2-1,j=i+1,i+2,…,N / 2,Data_in i Data_in represents the i-th input data. j Let j represent the j-th input data. The first half comparator includes N / 2-1 sub-half comparators. The n-th sub-half comparator in the first half comparator includes N / 2-n comparison units, where n=1,2,…,N / 2-1. ； The comparison unit in the second half-comparator compares the i-th input data in the first group of input data with each input data in the second group of input data within the second clock cycle to output a comparison value {C}. i,N / 2+1 ,…,C i,j ,…,C i,N }, where i=1,2,…,N / 2,j= N / 2+1, N / 2+2,…,N, the second half comparator includes N / 2 sub-half comparators, and each sub-half comparator in the second half comparator includes N / 2 comparison units; The comparison unit in the i-th sub-half comparator of the first half comparator is still within the second clock cycle, comparing the i-th input data in the second set of input data with the other input data after the i-th input data in the second set of input data, and outputting the comparison value {C}. i,i+1 ,…,C i,j ,…,C i,N }, where i= N / 2+1, N / 2+2,…, N-1, j=i+1,i+2,…, N.
2. The data sorting method as described in claim 1, characterized in that, The steps for obtaining the corresponding score value based on the comparison value for each input data point include: If the input data is Data_in L The corresponding score D L = {D L,1 ,…, D L,k ,…, D L,N }, L=1,2,3,…,N, K=1,2,3,…,N, then: ;in, express Invert.
3. The data sorting method as described in claim 2, characterized in that, The steps of summing the scores for each input data point to obtain the cumulative score for each input data point include: The scores for each input data point are summed to obtain the cumulative score. Where the input data is Data_in L The corresponding cumulative score is CNT. L ,but: 。 4. The data sorting method as described in claim 3, characterized in that, Based on the cumulative score of each input data point, the sorting position of each input data point is determined, and the multiple input data points are reordered before being output sequentially as multiple output data points. include: Among them, the m-th output data after reordering , where m , m=0,1,2,…N-1.
5. A data sorting circuit, characterized in that, The data sorting circuit includes: A comparator is used to receive multiple input data to be sorted, compare the multiple input data pairwise, and output the corresponding comparison value. The multiple input data are divided into at least one group of input data, and multiple input data in each group are input to the comparator in parallel. A scorer, connected to the output of the comparator, is used to obtain the corresponding score value based on the comparison value corresponding to each input data. An accumulator, connected to the output of the scorer, is used to accumulate the score value corresponding to each input data to obtain the cumulative score value of each input data. The reordering module, connected to the output of the accumulator, is used to determine the sorting position of each input data based on the cumulative score of each input data, and to reorder the multiple input data and output them as multiple output data in sequence. The multiple input data are divided into two groups of input data, and the two groups of input data are sequentially input to the comparator; The comparator includes a first half-comparator and a second half-comparator; The first half comparator is used to compare the data in the first set of input data pairwise in the first clock cycle, and to compare the data in the second set of input data pairwise in the second clock cycle; The second half comparator is used to compare the data between the first set of input data and the second set of input data pairwise within the second clock cycle; If the number of input data is N, and N is even, and the first group of input data and the second group of input data each include N / 2 input data, then the first half-comparator includes N / 2-1 sub-half-comparators. The nth sub-half-comparator in the first half-comparator includes N / 2-n comparison units, where n=1,2,…,N / 2-1. The comparison unit in the i-th sub-half-comparator of the first half-comparator is used to compare the i-th input data in the first group of input data with the other input data after the i-th input data in the first group of input data within the first clock cycle, so as to output the comparison value {C}. i,i+1 ,…,C i,j ,…,C i,N / 2 }, where, i=1,2,…,N / 2-1,j=i+1,i+2,…,N / 2; The second half-comparator includes N / 2 sub-half-comparators, each of which includes N / 2 comparison units. These comparison units compare the i-th input data in the first group of input data with each input data in the second group of input data within the second clock cycle, to output a comparison value {C}. i,N / 2+1 ,…,C i,j ,…,C i,N }, where i=1,2,…,N / 2,j= N / 2+1, N / 2+2,…,N; Specifically, the comparison unit in the i-th sub-half comparator of the first half comparator is also used, within the second clock cycle, to compare the i-th input data in the second set of input data with the other input data following the i-th input data in the second set of input data, so as to output a comparison value {C}. i,i+1 ,…,C i,j ,…,C i,N }, where i= N / 2+1, N / 2+2,…, N-1, j=i+1,i+2,…, N.
6. The data sorting circuit as described in claim 5, characterized in that, The scorer is used to obtain the score value of the first set of input data in the third clock cycle and the score value of the second set of input data in the fourth clock cycle.
7. The data sorting circuit as described in claim 6, characterized in that, The accumulator is used to obtain the cumulative score of the first group of input data in the fourth clock cycle and the cumulative score of the second group of input data in the fifth clock cycle.