Operation method and related apparatus

Abstract

The embodiment of the application discloses an operation method and related device, the operation method is applied to a board card including an operation device, the board card includes a storage device, an interface device, a control device and a neural network chip, the neural network chip is connected with the storage device, the interface device and the control device respectively; the storage device is used for storing data; the interface device is used for realizing data transmission between the neural network chip and an external device; the control device is used for monitoring the state of the neural network chip. By adopting the embodiment of the application, the success rate of operation can be improved.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence, and in particular to a computational method and related apparatus. Background Technology

[0002] Operators are the fundamental computational units in deep learning frameworks (such as PyTorch and TensorFlow). Rich operator libraries provide powerful tools for quickly building models within these frameworks. However, existing operator dispatch mechanisms, when running on hardware backends (such as machine learning units (MLUs), require the hardware to pre-register the operator and implement and adapt its specific functionality before operator invocation can occur. If an operator is not registered or registration fails, operator invocation will fail, thus hindering the rapid integration and validation of the entire network. Summary of the Invention

[0003] This application provides a calculation method and related apparatus that can improve the success rate of calculations.

[0004] In a first aspect, embodiments of this application provide a calculation method, the method comprising:

[0005] Obtain a first invocation instruction, which instructs the machine learning processor to invoke a target operator to perform operations on the first data, wherein the first data is data that the machine learning processor can process.

[0006] In response to the failure of the machine learning processor to call the target operator, the first data is converted into second data that can be processed by the target processor;

[0007] A second invocation instruction is sent to the target processor, the second invocation instruction being used to instruct the target processor to invoke the target operator to perform operations on the second data;

[0008] Receive the third data obtained by the target processor;

[0009] The third data is converted into a fourth data that can be processed by the machine learning processor.

[0010] In one possible implementation, the first invocation instruction includes the operator identifier of the target operator, and after obtaining the first invocation instruction, the method further includes:

[0011] Based on the operator identifiers of registered operators in the preset operator library, search for whether there is an operator identifier that is the same as the operator identifier of the target operator;

[0012] If no operator identifier matching the target operator is found, it is determined that the machine learning processor failed to invoke the target operator.

[0013] In one possible implementation, after determining that the machine learning processor has failed to invoke the target operator, the method further includes:

[0014] Determine the importance value and / or computational complexity of the target operator;

[0015] Calculate the registration evaluation value of the target operator based on the importance value and / or computational complexity of the target operator;

[0016] If the registration evaluation value is less than a preset threshold, then the step of converting the first data into second data that can be processed by the target processor is executed; or

[0017] If the registration evaluation value is greater than or equal to a preset threshold, the target operator is registered in the machine learning processor so that the machine learning processor stores the operator identifier and operation logic of the target operator when the target operator is successfully registered.

[0018] In one possible implementation, obtaining the first invocation instruction includes:

[0019] Retrieve computational instructions for the data to be processed;

[0020] Determine the computational logic for the data to be processed;

[0021] The target operator is found based on the aforementioned operational logic;

[0022] Based on the data to be processed, obtain the first data that the machine learning processor can process;

[0023] A first invocation instruction is generated based on the target operator and the first data.

[0024] In one possible implementation, after finding the target operator based on the operational logic, the method further includes:

[0025] Based on the data to be processed, obtain reference data that the target processor can process;

[0026] A third invocation instruction is generated based on the target operator and the reference data;

[0027] The third invocation instruction is sent to the target processor, which instructs the target processor to invoke the target operator to perform operations on the reference data.

[0028] In one possible implementation, prior to converting the first data into second data that can be processed by the target processor, the method further includes:

[0029] Identify the reference processor that has registered the target operator;

[0030] If the number of reference processors is greater than 1, then the operation priority of the reference processors is determined;

[0031] The reference processor corresponding to the maximum value of the operation priority is used as the target processor.

[0032] Secondly, embodiments of this application provide another calculation method, the method comprising:

[0033] Receive a second invocation instruction, which instructs the target processor to invoke the target operator to perform operations on the second data, which is obtained by converting the first data;

[0034] The target operator is invoked to perform operations on the second data to obtain the third data;

[0035] The third data is sent to the machine learning processor.

[0036] In one possible implementation, the second invocation instruction includes target parameters declared by the target operator; the target operator includes at least two functions, each of which declares different parameters;

[0037] The step of calling the target operator to perform operations on the second data to obtain the third data includes:

[0038] The objective function of the objective operator is determined based on the objective parameters;

[0039] The third data is obtained by performing calculations on the second data based on the objective function.

[0040] Thirdly, embodiments of this application provide a computing device that includes units of the method of any one of the first or second aspects of embodiments of this application.

[0041] Fourthly, embodiments of this application provide a machine learning processor, which is used to execute the method described in any one of the first aspects of this application. The machine learning processor includes: a computing unit and a controller unit; the computing unit includes: a main processing circuit and multiple slave processing circuits.

[0042] The controller unit is used to acquire input data and calculation instructions;

[0043] The controller unit is also used to parse the calculation instruction to obtain multiple operation instructions, and send the multiple operation instructions and the input data to the main processing circuit;

[0044] The main processing circuit is used to perform pre-processing on the input data and to transmit data and arithmetic instructions between the multiple slave processing circuits.

[0045] The plurality of slave processing circuits are used to perform intermediate operations in parallel based on the data and operation instructions transmitted from the main processing circuit to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the main processing circuit;

[0046] The main processing circuit is used to perform subsequent processing on the multiple intermediate results to obtain the calculation result of the calculation instruction.

[0047] Fifthly, embodiments of this application provide a neural network chip, which is included in the computing device described in the third aspect of embodiments of this application, or the machine learning processor described in the fourth aspect of embodiments of this application.

[0048] Sixthly, embodiments of this application provide a board, the board including the neural network chip described in the fifth aspect of embodiments of this application.

[0049] In a seventh aspect, embodiments of this application provide an electronic device, which includes the computing device described in the third aspect of embodiments of this application, or the machine learning processor described in the fourth aspect of embodiments of this application, or the neural network chip described in the fifth aspect of embodiments of this application, or the board described in the sixth aspect of embodiments of this application.

[0050] Eighthly, embodiments of this application provide an electronic device including a processor, a memory, and a communication interface, wherein the memory stores a computer program configured to be executed by the processor, and the computer program includes instructions for some or all of the steps described in the first or second aspects of embodiments of this application.

[0051] Ninthly, embodiments of this application provide a computer-readable storage medium storing a computer program that causes a computer to perform some or all of the steps described in the first or second aspects of embodiments of this application.

[0052] Using the aforementioned calculation method and related apparatus, after obtaining the first invocation instruction, if the machine learning processor fails to invoke the target operator, the first data is converted into second data that the target processor can process. Then, a second invocation instruction is sent to the target processor to invoke the target operator and perform calculations on the second data. Next, the third data obtained from the target processor's calculations is received and converted into fourth data that the machine learning processor can process. In this way, when the machine learning processor fails to invoke the target operator, the target processor can be used for calculations, improving the success rate of the calculations. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0054] Figure 1A This is a schematic diagram of the structure of a machine learning processor provided in an embodiment of this application;

[0055] Figure 1B A schematic diagram of the structure of a computing unit of a machine learning processor provided in an embodiment of this application;

[0056] Figure 2 A flowchart illustrating a calculation method provided in an embodiment of this application;

[0057] Figure 3 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0058] Figure 4 This is a schematic diagram of the structure of a circuit board provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0062] In this document, the term "embodiment" means that a particular feature, result, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0063] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0064] First, we introduce the machine learning unit (MLU) used in this application. (See also...) Figure 1A A machine learning processor is provided for performing machine learning calculations. The machine learning processor includes a controller unit 11 and a computation unit 12, wherein the controller unit 11 is connected to the computation unit 12.

[0065] The controller unit 11 is used to acquire input data and calculation instructions. In one possible implementation, the acquisition of input data and calculation instructions can be obtained through a data input / output unit, which can specifically be one or more data I / O interfaces or I / O pins.

[0066] The aforementioned calculation instructions include, but are not limited to, forward operation instructions or backward training instructions, or other neural network operation instructions, such as convolution operation instructions. The specific implementation of this application does not limit the specific form of the aforementioned calculation instructions.

[0067] The controller unit 11 is also used to parse the calculation instruction to obtain multiple operation instructions, and send the multiple operation instructions and the input data to the main processing circuit.

[0068] The main processing circuit 101 is used to perform preprocessing on the input data and to transmit data and arithmetic instructions between the multiple slave processing circuits;

[0069] Multiple slave processing circuits 102 are used to perform intermediate calculations in parallel based on data and calculation instructions transmitted from the main processing circuit to obtain multiple intermediate results, and transmit the multiple intermediate results to the main processing circuit;

[0070] The main processing circuit 101 is used to perform subsequent processing on the multiple intermediate results to obtain the calculation result of the calculation instruction.

[0071] In one possible implementation, the arithmetic unit 12 is as follows: Figure 1B As shown, it may include a branch processing circuit 103; its specific connection structure is as follows: Figure 1B As shown, where:

[0072] The main processing circuit 101 is connected to one or more branch processing circuits 103, and the branch processing circuit 103 is connected to one or more slave processing circuits 102.

[0073] Branch processing circuit 103 is used to forward data or instructions between main processing circuit 101 and slave processing circuit 102.

[0074] The technical solution provided in this application sets the machine learning processor as a master-slave structure. For forward computation instructions, it can split the data according to the forward computation instructions. In this way, multiple slave processing circuits can perform parallel operations on the computationally intensive parts, thereby improving the computing speed, saving computing time, and reducing power consumption.

[0075] Optionally, the aforementioned machine learning computation may specifically include: artificial neural network operations, and the aforementioned input data may specifically include: input neuron data and weight data. The aforementioned computation result may specifically be: the result of the artificial neural network operation, i.e., the output neuron data.

[0076] In neural networks, operations can be performed at the level of a single layer. For multi-layer neural networks, the process is as follows: In forward operation, after the previous layer completes its operation, the next layer's instructions use the output neuron calculated by the computation unit as the input neuron for the next layer's operation (or perform certain operations on the output neuron before using it as the input neuron). Simultaneously, the weights are replaced with those of the next layer. In backward operation, after the previous layer completes its backward operation, the next layer's instructions use the gradient of the input neuron calculated by the computation unit as the gradient of the output neuron for the next layer's operation (or perform certain operations on the input neuron's gradient before using it as the output neuron's gradient), and the weights are replaced with those of the next layer.

[0077] The aforementioned machine learning computations can also include support vector machine (SVM) operations, k-nearest neighbor (k-NN) operations, k-means operations, principal component analysis operations, and so on. For ease of description, the following uses artificial neural network operations as an example to illustrate the specific scheme of machine learning computations.

[0078] For artificial neural network operations, if the artificial neural network has multiple layers, the input and output neurons of these layers do not refer to the neurons in the entire input and output layers of the neural network. Instead, for any two adjacent layers in the network, the neuron in the lower layer of the forward operation is the input neuron, and the neuron in the upper layer of the forward operation is the output neuron. Taking a convolutional neural network as an example, suppose a convolutional neural network has L layers, K = 1, 2, ..., L-1. For the Kth layer and the (K+1)th layer, we call the Kth layer the input layer, and the neurons in it are the input neurons. The (K+1)th layer is called the output layer, and the neurons in it are the output neurons. That is, except for the top layer, each layer can be used as an input layer, and the layer below it is the corresponding output layer.

[0079] Optionally, the aforementioned machine processor may further include: the storage unit 10 and the direct memory access unit 50. The storage unit 10 may include one or any combination of registers and caches. Specifically, the cache is used to store the calculation instructions; the registers are used to store the input data and scalars; and the cache is a high-speed temporary cache. The direct memory access unit 50 is used to read or store data from the storage unit 10.

[0080] Optionally, the controller unit includes: an instruction storage unit 110, an instruction processing unit 111, and a storage queue unit 113;

[0081] The instruction storage unit 110 is used to store the computation instructions associated with the artificial neural network operation;

[0082] The instruction processing unit 111 is used to parse the calculation instruction to obtain multiple operation instructions;

[0083] Storage queue unit 113 is used to store an instruction queue, which includes multiple arithmetic instructions or calculation instructions to be executed in the order of the queue.

[0084] For example, in one possible implementation, the main processing circuit may also include a controller unit, which may include a main instruction processing unit specifically used to decode instructions into microinstructions. In another possible implementation, the slave processing circuit may also include another controller unit, which includes a slave instruction processing unit specifically used to receive and process microinstructions. These microinstructions can be next-level instructions, obtained by splitting or decoding instructions, and can be further decoded into control signals for various components, units, or processing circuits.

[0085] In one possible implementation, the structure of the operation instruction can be as shown in Table 1.

[0086] Table 1

[0087] opcode Register or immediate value Registers / Immediate Values ...

[0088] The ellipsis in the table above indicates that multiple registers or immediate values ​​may be included.

[0089] In another possible implementation, the computation instruction may include one or more operation fields and an opcode. The computation instruction may include neural network computation instructions. Taking neural network computation instructions as an example, as shown in Table 2, register numbers 0, 1, 2, 3, and 4 can be operation fields. Each register number (0, 1, 2, 3, or 4) can be the number of one or more registers.

[0090] Table 2

[0091]

[0092]

[0093] The aforementioned registers can be off-chip memory, but in practical applications, they can also be on-chip memory for storing data. Specifically, the data can be n-dimensional data, where n is an integer greater than or equal to 1. For example, when n=1, it is 1-dimensional data, i.e., a vector; when n=2, it is 2-dimensional data, i.e., a matrix; and when n=3 or more, it is a multi-dimensional tensor.

[0094] Optionally, the controller unit may further include:

[0095] The dependency processing unit 108 is used to determine whether there is an association between the first operation instruction and the zeroth operation instruction preceding the first operation instruction when there are multiple operation instructions. If there is an association between the first operation instruction and the zeroth operation instruction, the first operation instruction is cached in the instruction storage unit. After the zeroth operation instruction is executed, the first operation instruction is retrieved from the instruction storage unit and transmitted to the operation unit.

[0096] Determining whether there is a relationship between the first arithmetic instruction and the zeroth arithmetic instruction preceding the first arithmetic instruction includes:

[0097] The first storage address range of the required data (e.g., a matrix) in the first operation instruction is extracted according to the first operation instruction. The zeroth storage address range of the required matrix in the zeroth operation instruction is extracted according to the zeroth operation instruction. If the first storage address range and the zeroth storage address range have overlapping areas, it is determined that the first operation instruction and the zeroth operation instruction are associated. If the first storage address range and the zeroth storage address range do not have overlapping areas, it is determined that the first operation instruction and the zeroth operation instruction are not associated.

[0098] As can be seen, the machine learning processor provided in this application embodiment can improve operating efficiency and information processing efficiency compared with general-purpose processors, while reducing operating time and power consumption.

[0099] Operators are the fundamental computational units in deep learning frameworks (such as PyTorch and TensorFlow). Rich operator libraries provide powerful tools for quickly building models within these frameworks. However, existing operator dispatch mechanisms, when running on hardware backends (such as machine learning units (MLUs), require the hardware to pre-register the operator and implement and adapt its specific functionality before operator invocation can occur. If an operator is not registered or registration fails, operator invocation will fail, thus hindering the rapid integration and validation of the entire network.

[0100] To address the aforementioned issues, this application provides a computation method that can improve the success rate of computation.

[0101] Please see Figure 2 , Figure 2 This is a flowchart illustrating a calculation method provided in an embodiment of this application. The method may include the following steps S201-S206, wherein:

[0102] Step S201: The machine learning processor obtains the first invocation instruction.

[0103] The first invocation instruction instructs the machine learning processor to invoke the target operator to perform operations on the first data. The first invocation instruction may carry an operator identifier for the target operator. The operator identifier identifies the operator's identity. The operator identifier can be a marker identifying the operator's computational logic or specific function, such as the operator's name. Alternatively, it can be other information that identifies the operator; there are no limitations on this.

[0104] The target operator is used to perform operations on the first data. The target operator can be an addition operator, subtraction operator, convolution operator, pooling operator, activation operator, custom operator, etc., and is not limited here. The target operator can include at least one function, through which the operation logic of the target operator and the declared parameters can be obtained. These parameters can include input parameters or output parameters.

[0105] For example, operator 1 is `at::Tensor add(const at::Tensor&, const at::Tensor&, const at::Scalar&)`. The operator identifier can be either `operator1` or `add`. The input parameters can be `const at::Tensor`, `const at::Tensor`, or `const at::Scalar`. The operation logic can be the addition of the three input parameters `const at::Tensor`, `const at::Tensor`, and `const at::Scalar`.

[0106] The primary data refers to the data that the machine learning processor can process. This primary data can be data obtained by the machine learning processor from external devices, data within the machine learning processor itself, or intermediate data obtained through the machine learning processor's operations.

[0107] In one possible implementation, the machine learning processor acquiring the first invocation instruction may include the following steps:

[0108] Obtain the computation instructions for the data to be processed; determine the computation logic of the data to be processed; find the target operator based on the computation logic; obtain the first data that the machine learning processor can process based on the data to be processed; generate the first calling instruction based on the target operator and the first data.

[0109] In this embodiment, the data to be processed can be one-dimensional or multi-dimensional, without limitation. The operation instruction is used to instruct the machine learning processor to process the data. The operation instruction may include one or more operation fields and an opcode. The opcode can be used to indicate the function of the calculation instruction, which performs different operations through the opcode. The operation field can be used to indicate the data information of the calculation instruction, including the immediate value of the calculation instruction or the register number storing the data block used to execute the calculation instruction. The specific structure of the operation instruction can be found in Tables 1 and 2, and will not be elaborated upon here.

[0110] In one possible implementation, the user can input the computation instructions for the data to be processed through an electronic device. The machine learning processor can obtain the computation instructions for the data to be processed by reading the information of the electronic device, or it can obtain the computation instructions for the data to be processed from the instruction storage unit, etc., without limitation.

[0111] After obtaining the computation instructions for the data to be processed, the instruction processing unit of the machine learning processor can parse the computation instructions to determine the computation logic of the data to be processed. The computation logic can be addition, subtraction, convolution, pooling, activation, etc. Then, a target operator can be found based on this computation logic. For example, if the computation logic is pooling, the target operator is the corresponding pooling operator. If the computation logic is activation, the target operator is the corresponding activation operator, and so on. In this embodiment, the machine learning processor can obtain processable first data from the data to be processed. A first invocation instruction generated based on the target operator and the first data can be used to instruct the machine learning processor to invoke the target operator to perform computation on the first data.

[0112] As can be seen, after obtaining the computational instructions for the data to be processed, the machine learning processor determines the computational logic for the data, and then generates a first invocation instruction based on the target operator found according to the computational logic and the first data obtained from the data to be processed. Here, the first data is the data that the machine learning processor can process. This improves the processing efficiency of the machine learning processor.

[0113] It should be noted that the data to be processed can include data that a machine learning processor can process, or data that a machine learning processor cannot or is not good at processing. If the data to be processed includes data that a machine learning processor cannot or is not good at processing, it needs to be converted into reference data that the target processor can process. In addition, data that a machine learning processor can process can be configured for computation on the target processor, thereby enabling cross-validation and improving the accuracy of the computation.

[0114] In one possible implementation, after the machine learning processor searches for the target operator based on computational logic, it may further include the following steps:

[0115] Based on the data to be processed, obtain reference data that the target processor can process; generate a third invocation instruction based on the target operator and the reference data; send the third invocation instruction to the target processor, which is used to instruct the target processor to invoke the target operator to perform operations on the reference data.

[0116] In this embodiment, the target operator can be pre-registered in the target processor, so the target processor can call the target operator to perform calculations. The target processor can be a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0117] The specific implementation method for converting the data in the data to be processed into reference data that the target processor can process can be found in the method for converting machine learning processor data into central processing unit data below, and will not be repeated here. After the machine learning processor generates a third invocation instruction based on the target operator and the reference data, it sends it to the target processor. After receiving the third invocation instruction, the target processor invokes the target operator to perform operations on the reference data.

[0118] It should be noted that the target operator in the third invocation instruction may be the same as or different from the target operator in the first invocation instruction. The operator invoked by the machine learning processor is an operator already registered by the machine learning processor, and the operator invoked by the target processor is an operator already registered by the target processor. This application does not limit the type of registered operator and can determine it based on the hardware attributes of the electronic device configuration and the type of operator. For example, some operators may not be decisive for the overall network delivery task, so these operators may be considered to have low importance values ​​and may not be registered in the machine learning processor but may be registered in the target processor. Alternatively, operators with high computational complexity may be registered in both the machine learning processor and the target processor.

[0119] It can be seen that after obtaining the operation instructions for the data to be processed, the machine learning processor can also obtain the reference data that the target processor can process based on the data to be processed, and then generate a third calling instruction so that the target processor can call the target operator to perform operations on the reference data, which can improve the processing efficiency of the target processor and is conducive to improving the overall operation efficiency.

[0120] If the target operator is pre-registered in both the machine learning processor and the target processor, both processors will call the target operator for computation. After the computation is complete, cross-validation can be performed by comparing the computation time, computational resources used, or accuracy of the two processors, thereby improving computational efficiency.

[0121] In one possible implementation, the first invocation instruction includes the operator identifier of the target operator, and the machine learning processor may further include the following steps after executing step S201:

[0122] The system searches for an operator identifier that matches the operator identifier of the registered operator in the preset operator library. If no operator identifier matching the operator identifier of the target operator is found, it is determined that the machine learning processor failed to call the target operator.

[0123] In this embodiment, the first invocation instruction may carry the operator identifier of the target operator. The description of the operator identifier is as described above and will not be repeated here. The machine learning processor stores a preset operator library, which stores registered operators that have been registered. Registered operators may carry operator identifiers. Therefore, after obtaining the operator identifier of the target operator, it is possible to search for an operator identifier identical to the target operator's operator identifier based on the operator identifiers of registered operators in the preset operator library. If no operator identifier identical to the target operator's operator identifier is found, it can be determined that the target operator is an operator not registered with the machine learning processor. If the target operator is not registered in the machine learning processor, it cannot run under the machine learning processor, and when the machine learning processor calls an unregistered target operator, the call will fail.

[0124] It can be seen that determining whether a target operator is a registered operator in a machine learning processor based on the operator identifier, and thus determining whether the machine learning processor will fail to be invoked, can improve the efficiency and accuracy of the search.

[0125] In one possible implementation, after determining that the machine learning processor has failed to invoke the target operator, the process may further include the following steps:

[0126] Determine the importance value and / or computational complexity of the target operator; calculate the registration evaluation value of the target operator based on the importance value and / or computational complexity; if the registration evaluation value is less than a preset threshold, execute the step of converting the first data into second data that can be processed by the target processor; or if the registration evaluation value is greater than or equal to the preset threshold, register the target operator in the machine learning processor so that the machine learning processor stores the operator identifier and operation logic of the target operator when the target operator is successfully registered.

[0127] In this embodiment, the importance value of a target operator describes its impact on the computation of the data to be processed. A higher importance value indicates a greater impact on the computation result of the data. The computational load of a target operator refers to the computational resources required to process the first data. The importance value of a target operator can be based on the correlation and computational order of the various target operators corresponding to the data to be processed. The computational load of a target operator can also be based on the specific network delivery task and the computing power of the processor calling the target operator. When executing a network delivery task, a machine learning processor typically needs to call many operators during computation. For example, some operators may affect the computation of other operators, thus playing a decisive role in the entire network delivery task; therefore, these operators have the highest importance values. If some operators undertake most of the computation, it can be determined that these operators have a large computational load. If some operators consume most of the processor's computing resources, it can be determined that the target operator has a large computational load.

[0128] The registration evaluation value can be used to evaluate whether the target operator needs to be registered in the machine learning processor. This application does not limit the calculation method of the registration evaluation value; it can be achieved by weighting the importance value and / or computational load of the target operator through certain computing units of an electronic device, or by calculating the product of the importance value and computational load, or the maximum or minimum value between the importance value and computational load, etc.

[0129] The preset threshold is a pre-defined parameter that can be set based on historical experience. For example, if the preset threshold is 60, and the calculated registration evaluation value is 50, which is less than the preset threshold, the machine learning processor will proceed to step S202 without registering the target operator. If the calculated registration evaluation value is 70, which is greater than the preset threshold, then the target operator needs to be registered in the machine learning processor so that it can support computation under the machine learning processor.

[0130] This application does not limit the specific implementation of registering target operators in the processor. Taking a machine learning processor as an example, one possible implementation may include the following steps: obtaining the registration configuration file of the target operator; generating the class corresponding to the target operator based on the registration configuration file; and adding the class corresponding to the target operator to the registry of the machine learning processor.

[0131] The registration configuration file includes the target operator's operator identifier, computational logic, input parameters, output parameters, and supported processors. The class corresponding to the target operator can be understood as a function that calls the target operator. In this example, the class corresponding to the target operator is generated from the registration configuration file, and then added to the registry to complete the registration, which can improve the registration success rate.

[0132] It can be seen that calculating the registration evaluation value of the target operator by its importance value and / or computational complexity can result in a highly accurate registration evaluation value. Then, based on the registration evaluation value, it is determined whether the machine learning processor needs to register the target operator. If the registration evaluation value is less than a preset threshold, it is determined that the machine learning processor is not suitable for registering the target operator. In this case, the first data is converted into second data that the target processor can process, allowing the target processor to call the target operator to process the second data. If the registration evaluation value is greater than or equal to the preset threshold, it is determined that the machine learning processor is suitable for registering the target operator. In this case, the machine learning processor registers the target operator first. Upon successful registration, the operator identifier and computational logic of the target operator are stored, enabling the machine learning processor to call the target operator for computation, thus improving efficiency.

[0133] Step S202: In response to the failure of the machine learning processor to call the target operator, the machine learning processor converts the first data into second data that can be processed by the target processor.

[0134] In this embodiment, the machine learning processor may fail to call the target operator because the target operator is not registered in the machine learning processor's operator library. The method for determining whether a target operator is registered in the machine learning processor's operator library can be found above and will not be repeated here.

[0135] In the embodiments of this application, the first data is data that can be processed by the machine learning processor. When the machine learning processor calls the target operator for recognition, the first data can be converted into second data that can be processed by the target processor, so that the target processor can call the target operator to perform operations on the second data.

[0136] Taking the target processor as a central processing unit (CPU) as an example, the machine learning processor inputs the first data into a preset first transformation function, and the resulting data is called the second data that the CPU can process. It should be noted that the first data can be a single data point or a data block corresponding to multiple data points. Data transmission is usually carried out in data block format. If the first data is a single data point, it can be stored in data block format first, and then transformed based on the first transformation function. If the first data consists of data blocks corresponding to multiple data points, it can be transformed based on the first transformation function.

[0137] It should be noted that the above conversion method is only one way to convert data that can be processed by a machine learning processor into data that can be processed by a central processing unit. Other conversion methods can also be used, and this application does not limit this.

[0138] In one possible implementation, the machine learning processor may further include the following steps before performing step S202:

[0139] Determine the reference processors of the registered target operators; if the number of reference processors is greater than 1, determine the operation priority of the reference processors; and take the reference processor corresponding to the maximum operation priority as the target processor.

[0140] Because operators have different functional requirements and usage scenarios, the same operator can support computation on different hardware devices, such as simultaneously supporting operations on a central processing unit (CPU) and a graphics processing unit (GPU). In this embodiment, the reference processor supported by the target operator can be determined from the processor information supported by the target operator in the target operator's registration configuration information, thereby identifying the reference processor for the registered target operator. Alternatively, the presence of the target operator's operator identifier in the registry of each processor can be used to determine whether the processor is a reference processor.

[0141] In this embodiment, the computation priority of the reference processor is used to define the computation order of the reference processor; the higher the computation priority, the earlier the computation occurs. The computation priority can be determined based on information such as computation time, computational resources consumed, or computation accuracy. For example, the shorter the computation time of the reference processor, the smaller the computational resources consumed, and the higher the computation accuracy, the higher the computation priority can be considered. The reference processor corresponding to the maximum computation priority is selected as the target processor.

[0142] It can be seen that when the number of reference processors is greater than 1, using the reference processor with the highest computational priority as the target processor helps to reduce computation time and improve computational efficiency.

[0143] Step S203: The machine learning processor sends a second call instruction to the target processor.

[0144] Accordingly, the target processor receives the second invocation instruction. This second invocation instruction instructs the target processor to invoke the target operator to perform operations on the second data.

[0145] Step S204: The target processor calls the target operator to perform operations on the second data to obtain the third data.

[0146] Target operators can be pre-registered operators in the target processor, allowing the target processor to call them for computation. A target operator can include two different functions implementing the same operation, each with different declared parameters. For example, operator 1 is "at::Tensor add(const at::Tensor&,const at::Tensor&,const at::Scalar&)", operator 2 is "at::Tensor& add_(at::Tensor&,const at::Tensor&,const at::Scalar&)", and operator 3 is "at::Tensor& add_out(const at::Tensor&,const at::Tensor&,const at::Scalar&,at::Tensor&)". These three operators all perform the same addition, but their function declarations are different. Operator 1 is the most common operator; all parameters are passed in and cannot be modified. Operator 2 is an in-place operator, whose first parameter is both an input and an output parameter. Operator 3, on the other hand, is an operator with an out parameter, whose last parameter is both an input and an output parameter.

[0147] In one possible implementation, the second invocation instruction includes the target parameters declared by the target operator; the target operator includes at least two functions, each of which declares different parameters; step S204 may include the following steps:

[0148] The objective function of the objective operator is determined based on the objective parameters; the second data is then processed based on the objective function to obtain the third data.

[0149] In this embodiment, when the machine learning processor fails to call the target operator, the machine learning processor calls a default (e.g., fallback) function registered by the machine learning processor, and then transmits the target parameters of the target operator to the target processor through the default function, so that the target processor can function normally. The target parameters are transmitted in the form of a stack, and the target processor needs to parse the target parameters from the stack corresponding to the target operator's target parameters before calling the target operator.

[0150] As mentioned earlier, the target operator can include at least two different functions that perform the same operation, each with different declared parameters. Before calling the target operator, the target function of the target operator is determined based on the declared target parameters, and the second data is then processed based on the target function to obtain the third data. This improves the efficiency and accuracy of the computation.

[0151] Step S205: The target processor sends third data to the machine learning processor.

[0152] The third data is the result obtained by the target processor calling the target operator to operate on the second data. After the target processor obtains the third data, it sends it to the machine learning processor, which in turn receives the third data obtained by the target processor.

[0153] Step S206: The machine learning processor transforms the third data into a fourth data that the machine learning processor can process.

[0154] Since the third data is obtained by the target processor and conforms to the target processor's data format, it can be converted into a fourth data that the machine learning processor can process, making it easier for the machine learning processor to process it further.

[0155] Taking the target processor as a central processing unit (CPU) as an example, the machine learning processor inputs the third data, which can be processed by the CPU, into a preset second transformation function. The resulting data is called the fourth data that the machine learning processor can process. It should be noted that the third data can be a single data point or a data block corresponding to multiple data points. Data transmission is usually carried out in data block format. If the third data is a single data point, it can be stored in data block format first, and then converted based on the second transformation function. If the third data is a data block corresponding to multiple data points, it can be converted based on the second transformation function.

[0156] The second conversion function can be understood as the inverse function of the first conversion function. For example, if the first conversion function is inputElement.cpu(), the second conversion function is inputElement.to("mlu"). Or, for another example, if the first conversion function is args[i].toTensor().cpu(), the second conversion function is args[i].toTensor().to("mlu").

[0157] It should be noted that the above conversion method is only one way to convert data that can be processed by the central processing unit into data that can be processed by the machine learning processor. Other conversion methods can also be used, and this application does not limit this.

[0158] In such Figure 2 As shown in the method, after receiving the first invocation instruction, if the machine learning processor fails to invoke the target operator, it converts the first data into second data that the target processor can process. Then, it sends a second invocation instruction to the target processor, causing it to invoke the target operator to perform calculations on the second data. Next, it receives the third data obtained from the target processor's calculations and converts it into fourth data that the machine learning processor can process. In this way, when the machine learning processor fails to invoke the target operator, it can utilize the target processor for calculations, improving the success rate of the computation.

[0159] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 3 As shown, the computing device 300 includes a processing unit 301 and a communication unit 302.

[0160] When the computing device is a machine learning processor, the detailed descriptions of each unit are as follows:

[0161] Processing unit 301 is configured to acquire a first invocation instruction, which instructs the machine learning processor to invoke a target operator to perform operations on first data, wherein the first data is data that the machine learning processor can process; in response to the machine learning processor failing to invoke the target operator, the first data is converted into second data that the target processor can process; communication unit 302 is configured to send a second invocation instruction to the target processor, which instructs the target processor to invoke the target operator to perform operations on the second data; receive third data obtained by the target processor; processing unit 301 is further configured to convert the third data into fourth data that the machine learning processor can process.

[0162] In one possible implementation, the first invocation instruction includes the operator identifier of the target operator, and the processing unit 301 is further configured to search for whether there is an operator identifier that is the same as the operator identifier of the target operator based on the operator identifier of the registered operators in the preset operator library; if no operator identifier that is the same as the operator identifier of the target operator is found, it is determined that the machine learning processor has failed to invoke the target operator.

[0163] In one possible implementation, the processing unit 301 is further configured to determine the importance value and / or computational complexity of the target operator; calculate the registration evaluation value of the target operator based on the importance value and / or computational complexity of the target operator; if the registration evaluation value is less than a preset threshold, then execute the step of converting the first data into second data that can be processed by the target processor; or if the registration evaluation value is greater than or equal to the preset threshold, then register the target operator in the machine learning processor, so that when the machine learning processor successfully registers the target operator, it stores the operator identifier and computational logic of the target operator.

[0164] In one possible implementation, the processing unit 301 is specifically used to obtain the operation instructions of the data to be processed; determine the operation logic of the data to be processed; find the target operator based on the operation logic; obtain the first data that the machine learning processor can process based on the data to be processed; and generate a first calling instruction based on the target operator and the first data.

[0165] In one possible implementation, the processing unit 301 is further configured to obtain reference data that the target processor can process based on the data to be processed; generate a third invocation instruction based on the target operator and the reference data; and the communication unit 302 is further configured to send the third invocation instruction to the target processor, the third invocation instruction being used to instruct the target processor to invoke the target operator to perform operations on the reference data.

[0166] In one possible implementation, the processing unit 301 is further configured to determine a reference processor that has registered the target operator; if the number of reference processors is greater than 1, then determine the operation priority of the reference processor; and take the reference processor corresponding to the maximum value of the operation priority as the target processor.

[0167] When the computing device is the target processor, the detailed description of each unit is as follows:

[0168] The communication unit 302 is used to receive a second call instruction, which instructs the target processor to call the target operator to perform operations on the second data, which is obtained by converting the first data; the processing unit 301 is used to call the target operator to perform operations on the second data to obtain the third data; the communication unit 302 is also used to send the third data to the machine learning processor.

[0169] In one possible implementation, the second invocation instruction includes target parameters declared by the target operator; the target operator includes at least two functions, each of which declares different parameters; the processing unit 301 is specifically used to determine the target function of the target operator based on the target parameters; and to perform operations on the second data based on the target function to obtain the third data.

[0170] It should be noted that the implementation of each unit can also be referenced accordingly. Figure 2 The corresponding description of the method embodiments shown.

[0171] This application provides a neural network chip, which includes the machine learning processor shown in FIG1 and... Figure 3 The arithmetic unit shown.

[0172] This application provides a circuit board, see below. Figure 4 In addition to the aforementioned neural network chip, the board may also include other supporting components, including but not limited to: storage devices, interface devices, and control devices; the storage devices are connected to the neural network chip via a bus and are used to store data.

[0173] The storage device may include multiple sets of storage cells. Each set of storage cells is connected to the neural network chip via a bus. It is understood that each set of storage cells may be a double data rate synchronous dynamic random access memory (DDR SDRAM).

[0174] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the storage device may include four groups of storage cells. Each group of storage cells may include multiple DDR4 chips (neural network chips). In one possible implementation, the neural network chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification. It is understood that when DDR4-3200 chips are used in each group of storage cells, the theoretical data transmission bandwidth can reach 25600MB / s.

[0175] In one possible implementation, each group of the memory cells includes multiple Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs) arranged in parallel. DDRs can transfer data twice within one clock cycle. A controller for controlling the DDRs is provided in the neural network chip for controlling the data transmission and data storage of each memory cell.

[0176] The interface device is electrically connected to the neural network chip within the neural network chip package structure. The interface device is used to realize data transmission between the neural network chip and external devices (e.g., servers or computers). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the neural network chip via a standard PCIe interface, realizing data transfer. Preferably, when using a PCIe 3.0 x 16 interface, the theoretical bandwidth can reach 16000 MB / s. In another embodiment, the interface device can also be other interfaces; this application does not limit the specific form of the other interfaces mentioned above, as long as the interface unit can realize the switching function. Furthermore, the calculation results of the neural network chip are still transmitted back to the external device (e.g., the server) by the interface device.

[0177] The controller is electrically connected to the neural network chip. The controller monitors the state of the neural network chip. Specifically, the neural network chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller unit (MCU). The neural network chip may include multiple processing neural network chips, multiple processing cores, or multiple processing circuits, capable of driving multiple loads. Therefore, the neural network chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing neural network chips, multiple processing cores, and / or multiple processing circuits within the neural network chip.

[0178] This application provides an electronic device, which includes the aforementioned machine learning processor, computing device, neural network chip, or circuit board.

[0179] See Figure 5 This application provides a schematic diagram of the structure of an electronic device. Figure 5As shown, the electronic device 500 includes a processor 501, a memory 502, and a communication interface 503. The processor 501, memory 502, and communication interface 503 are connected via a bus 505. The memory 502 stores a computer program 504, which is configured to be executed by the processor 501. The computer program 504 includes instructions for some or all of the steps described in any of the methods described in the above method embodiments.

[0180] Electronic devices include data processing devices, robots, computers, printers, scanners, tablets, smart terminals, mobile phones, dashcams, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and / or medical devices.

[0181] The means of transportation include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical equipment includes MRI scanners, ultrasound scanners and / or electrocardiographs.

[0182] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0183] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0184] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0185] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0186] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0187] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0188] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0189] This application also provides a computer storage medium storing a computer program that is executed by a processor to implement some or all of the steps of any of the computational methods described in the above method embodiments.

[0190] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the operation methods described in the above method embodiments.

[0191] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A calculation method, characterized in that, include: Obtain a first invocation instruction, which instructs the machine learning processor to invoke a target operator to perform operations on the first data, wherein the first data is data that the machine learning processor can process. In response to the failure of the machine learning processor to call the target operator, the first data is converted into second data that can be processed by the target processor; A second invocation instruction is sent to the target processor, the second invocation instruction being used to instruct the target processor to invoke the target operator to perform operations on the second data; Receive the third data obtained by the target processor; The third data is converted into a fourth data that can be processed by the machine learning processor; The step of obtaining the first invocation instruction includes: Retrieve computation instructions for the data to be processed; Determine the computational logic of the data to be processed; The target operator is found based on the aforementioned operational logic; Based on the data to be processed, obtain the first data that the machine learning processor can process; A first invocation instruction is generated based on the target operator and the first data.

2. The method according to claim 1, characterized in that, The first invocation instruction includes the operator identifier of the target operator. After obtaining the first invocation instruction, the method further includes: Based on the operator identifiers of registered operators in the preset operator library, search for whether there is an operator identifier that is the same as the operator identifier of the target operator; If no operator identifier matching the target operator is found, it is determined that the machine learning processor failed to invoke the target operator.

3. The method according to claim 2, characterized in that, After determining that the machine learning processor failed to invoke the target operator, the method further includes: Determine the importance value and / or computational complexity of the target operator; Calculate the registration evaluation value of the target operator based on the importance value and / or computational complexity of the target operator; If the registration evaluation value is less than a preset threshold, then the step of converting the first data into second data that can be processed by the target processor is executed; or If the registration evaluation value is greater than or equal to a preset threshold, the target operator is registered in the machine learning processor so that the machine learning processor stores the operator identifier and operation logic of the target operator when the target operator is successfully registered.

4. The method according to claim 1, characterized in that, After finding the target operator based on the operational logic, the method further includes: Based on the data to be processed, obtain reference data that the target processor can process; A third invocation instruction is generated based on the target operator and the reference data; The third invocation instruction is sent to the target processor, which instructs the target processor to invoke the target operator to perform operations on the reference data.

5. The method according to any one of claims 1-3, characterized in that, Before converting the first data into second data that can be processed by the target processor, the method further includes: Identify the reference processor that has registered the target operator; If the number of reference processors is greater than 1, then the operation priority of the reference processors is determined; The reference processor corresponding to the maximum value of the operation priority is used as the target processor.

6. A calculation method, characterized in that, The method is applied to the target processor according to any one of claims 1-5, and the method includes: Receive a second invocation instruction, which instructs the target processor to invoke the target operator to perform operations on the second data, which is obtained by converting the first data; The target operator is invoked to perform operations on the second data to obtain the third data; The third data is sent to the machine learning processor.

7. The method according to claim 6, characterized in that, The second invocation instruction includes the target parameters declared by the target operator; the target operator includes at least two functions, each of which declares different parameters; The step of calling the target operator to perform operations on the second data to obtain the third data includes: The objective function of the objective operator is determined based on the objective parameters; The third data is obtained by performing calculations on the second data based on the objective function.

8. A computing device, characterized in that, Units including those of the method as claimed in any one of claims 1-5 or 6-7.

9. A machine learning processor, characterized in that, The machine learning processor is used to execute the method of any one of claims 1-5, the machine learning processor comprising: a computing unit and a controller unit; the computing unit comprising: a main processing circuit and a plurality of slave processing circuits; The controller unit is used to acquire input data and calculation instructions; The controller unit is also used to parse the calculation instruction to obtain multiple operation instructions, and send the multiple operation instructions and the input data to the main processing circuit; The main processing circuit is used to perform pre-processing on the input data and to transmit data and arithmetic instructions between the multiple slave processing circuits. The plurality of slave processing circuits are used to perform intermediate operations in parallel based on the data and operation instructions transmitted from the main processing circuit to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the main processing circuit; The main processing circuit is used to perform subsequent processing on the multiple intermediate results to obtain the calculation result of the calculation instruction.

10. A neural network chip, characterized in that, The neural network chip includes the computing device as described in claim 8 or the machine learning processor as described in claim 9.

11. A circuit board, characterized in that, The board includes a storage device, an interface device, a control device, and a neural network chip as described in claim 10, wherein: The neural network chip is connected to the storage device, the interface device, and the control device, respectively. The storage device is used to store data; The interface device is used to realize data transmission between the neural network chip and external devices; The control device is used to monitor the state of the neural network chip.

12. An electronic device, characterized in that, The electronic device includes the computing device as described in claim 8, or the machine learning processor as described in claim 9, or the neural network chip as described in claim 10, or the board as described in claim 11.

13. An electronic device, characterized in that, The method includes a processor, a memory, and a communication interface, wherein the memory stores a computer program configured to be executed by the processor, the computer program including instructions for performing the steps of the method of any one of claims 1-5 or 6-7.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that causes a computer to perform the method according to any one of claims 1-5 or 6-7.

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