A port enabling method and apparatus
By introducing processors and chips into ultra-low latency switches, the processing and forwarding of control streams are realized, solving the applicability problem of ultra-low latency switches under network structure limitations and ensuring normal communication under unidirectional and bidirectional connections.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEW H3C TECH CO LTD
- Filing Date
- 2022-09-09
- Publication Date
- 2026-07-21
AI Technical Summary
The existing networking structure of ultra-low latency switches limits their applicability, especially when the source device is a distributed node and the destination device is a central server. It is impossible to enable bidirectional connection of the ports of the energy-end device, which makes the applicability of ultra-low latency switches relatively low.
By introducing an inbound chip with bitstream processing capabilities into an ultra-low latency switch, and configuring the port correspondence through a processor, the control bitstream of the source device can be processed and returned to the source device in unidirectional or bidirectional connection, thereby enabling its ports.
This improves the applicability of ultra-low latency switches in both unidirectional and bidirectional connection scenarios, ensuring that source devices can send and receive bitstreams normally, thus expanding their application scope.
Smart Images
Figure CN116244239B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a port enabling method and apparatus. Background Technology
[0002] In some application scenarios, there are high requirements for the efficiency of switch forwarding of bitstreams, such as in the financial industry, where low latency is required. For these applications, related technologies use switches with only simple forwarding functions to forward bitstreams. Since these switches simply forward the bitstream received at the source port through the corresponding destination port without processing the bitstream, the forwarding latency is low. In this paper, these switches are referred to as ultra-low latency switches.
[0003] Network devices connected to an ultra-low latency switch (hereinafter referred to as source devices) send control streams (i.e., MAC streams) to the ultra-low latency switch. The source device only enables its own port and sends data streams normally upon receiving a returned control stream. However, ultra-low latency switches do not have stream processing capabilities. Therefore, the ultra-low latency switch cannot return control streams to the source device. Another device (hereinafter referred to as the destination device) needs to be connected to the ultra-low latency switch, and the control stream sent by the source device is sent to the destination device so that the destination device can return control streams to the source device.
[0004] To ensure that the control stream sent by the source device can be transmitted to the destination device, and that the destination device can return a control stream to the source device, the source device needs to be connected to both the source and destination ports on the ultra-low latency switch, and the destination device needs to be connected to both the source and destination ports on the ultra-low latency switch, thus forming a configuration as follows: Figure 1 The network structure shown establishes a bidirectional connection between the source device and the destination device, as well as between the destination device and the source device.
[0005] However, this method has limitations on network topology, resulting in limited applicability of ultra-low latency switches. For example, in scenarios where the source device is a distributed node and the destination device is a central server, only a one-way connection from the source device to the destination device needs to be established; there is no need to establish a connection like... Figure 1 The bidirectional connection shown cannot be used to connect the ports of the energy-side devices in this application scenario. Summary of the Invention
[0006] The purpose of this invention is to provide a port enabling method and apparatus to improve the applicability of ultra-low latency switches. The specific technical solution is as follows:
[0007] In a first aspect of the present invention, a port enabling method is provided, the method comprising:
[0008] The processor obtains the first control stream sent by the source device through the second port; and sends the first control stream to the first port according to the first correspondence between the first port and the second port in a pre-configured manner.
[0009] The chip acquires the first control stream through the first port; processes the first control stream to obtain the second control stream; and sends the second control stream to the first port.
[0010] The processor obtains the second control stream through the first port; and sends the second control stream to the second port according to the first correspondence, so that the source device obtains the second control stream and enables the port of the source device in response to the second control stream.
[0011] In one possible embodiment, the target device accesses the ultra-low latency switch through a third port of the plurality of ports, and the method further includes:
[0012] The processor acquires the data stream sent by the source device through the second port; and sends the data stream to the third port according to the pre-configured second correspondence between the first port and the third port, so that the destination device can acquire the data stream.
[0013] In one possible embodiment, the first correspondence is pre-configured in the following ways:
[0014] The processor configures the second port as the destination port corresponding to the source port being the first port, and configures the first port as the destination port corresponding to the source port being the second port.
[0015] In one possible embodiment, the processor sends the first control stream to the first port according to a pre-configured first correspondence between the first port and the second port, including:
[0016] If the source device and the ultra-low latency switch are connected in a one-way manner, the processor sends the first control stream to the first port according to the first correspondence between the first port and the second port as pre-configured.
[0017] In one possible embodiment, the source device further connects to the ultra-low latency switch via a fourth port of the plurality of ports, and the network device connects to the ultra-low latency switch via a fifth and a sixth port of the plurality of ports. The method further includes:
[0018] If the source device and the ultra-low latency switch are bidirectionally connected, the processor sends the first control stream to the fifth port according to the pre-configured third correspondence between the second port and the fifth port, so that the network device can obtain and process the first control stream to obtain the third control stream.
[0019] The processor obtains the third control stream sent by the network device through the sixth port; and sends the third control stream to the fourth port according to the pre-configured fourth correspondence between the sixth port and the fourth port, so that the source device obtains the third control stream and enables the port of the source device in response to the third control stream.
[0020] In a second aspect of the present invention, a port enabling device is provided, the device being applied to an ultra-low latency switch, the ultra-low latency switch including a processor, an ingress chip, and multiple ports, the ingress chip being electrically connected to a first port among the multiple ports, and a source device being connected to the ultra-low latency switch through a second port among the multiple ports, the device comprising:
[0021] The first stream routing module is used to drive the processor to obtain the first control stream sent by the source device through the second port; and to send the first control stream to the first port according to the first correspondence between the first port and the second port in a pre-configured manner.
[0022] The processing module is configured to drive the input chip to acquire the first control stream through the first port; process the first control stream to obtain a second control stream; and send the second control stream to the first port.
[0023] The second flow-guiding module is used to drive the processor to obtain the second control stream through the first port; and to send the second control stream to the second port according to the first correspondence, so that the source device obtains the second control stream and enables the port of the source device in response to the second control stream.
[0024] In one possible embodiment, the target device accesses the ultra-low latency switch through a third port of the plurality of ports, and the apparatus further includes:
[0025] The data stream forwarding module is used to drive the processor to obtain the data stream sent by the source device through the second port; and to send the data stream to the third port according to the second correspondence between the first port and the third port in a pre-configured manner, so that the destination device can obtain the data stream.
[0026] In one possible embodiment, the first correspondence is pre-configured in the following manner:
[0027] The processor configures the second port as the destination port corresponding to the source port being the first port, and configures the first port as the destination port corresponding to the source port being the second port.
[0028] In one possible embodiment, the first flow-directing module drives the processor to send the first control stream to the first port according to a pre-configured first correspondence between the first port and the second port, including:
[0029] If the source device and the ultra-low latency switch are connected in a one-way manner, the processor is driven to send the first control stream to the first port according to the first correspondence between the first port and the second port as pre-configured.
[0030] In one possible embodiment, the source device further connects to the ultra-low latency switch via a fourth port of the plurality of ports, and the network device connects to the ultra-low latency switch via a fifth and a sixth port of the plurality of ports. The apparatus further includes:
[0031] A bidirectional connection module is used to drive the processor to send the first control stream to the fifth port according to the pre-configured third correspondence between the second port and the fifth port if there is a bidirectional connection between the source device and the ultra-low latency switch, so that the network device can obtain and process the first control stream to obtain the third control stream.
[0032] The processor is driven to acquire the third control stream sent by the network device through the sixth port; and according to the pre-configured fourth correspondence between the sixth port and the fourth port, the third control stream is sent to the fourth port, so that the source device acquires the third control stream and enables the port of the source device in response to the third control stream.
[0033] In a third aspect of the present invention, an ultra-low latency switch is also provided, comprising:
[0034] Processor, integrated chip, and multiple ports;
[0035] The first port of the plurality of ports is electrically connected to the introduced chip, and the second port of the plurality of ports is communicatively connected to the source device.
[0036] The processor is configured to acquire a first control stream sent by the source device through the second port; and send the first control stream to the first port according to a pre-configured first correspondence between the first port and the second port.
[0037] The introduced chip is used to acquire the first control stream through the first port; process the first control stream to obtain a second control stream; and send the second control stream to the first port.
[0038] The processor is further configured to acquire the second control stream through the first port; and send the second control stream to the second port according to the first correspondence, so that the source device acquires the second control stream and enables the port of the source device in response to the second control stream.
[0039] In a fourth aspect of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, it implements the steps of any of the methods described in the first aspect above.
[0040] Beneficial effects of the embodiments of the present invention:
[0041] The port enabling method and apparatus provided in this invention, since the source device connects to the ultra-low latency switch through a second port, allows the processor to forward the second control stream through the second port, i.e., send the second control stream to the source device. For the source device, the second control stream can be considered as a control stream returned in response to the first control stream; therefore, the source device can enable its own port, i.e., enable the port on the source device that connects to the ultra-low latency switch. Corresponding to the port on the source device enabling itself, the port on the ultra-low latency switch that connects to the source device, i.e., the second port, will also be enabled.
[0042] Of course, implementing any product or method of the present invention does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description
[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings.
[0044] Figure 1 This is a schematic diagram illustrating an application scenario of the ultra-low latency switch provided in an embodiment of the present invention.
[0045] Figure 2This is a schematic diagram of the structure of an ultra-low latency switch provided in an embodiment of the present invention;
[0046] Figure 3 A schematic flowchart of a port enabling method provided in an embodiment of the present invention;
[0047] Figure 4 This is a schematic diagram illustrating another application scenario of the ultra-low latency switch provided in this embodiment of the invention.
[0048] Figure 5 A schematic diagram of a data stream forwarding process after port enabling is provided in an embodiment of the present invention;
[0049] Figure 6 This is a schematic diagram of the forwarding routes for the control stream and data stream in an ultra-low latency switch provided in an embodiment of the present invention;
[0050] Figure 7 This is a schematic diagram illustrating another application scenario of the ultra-low latency switch provided in this embodiment of the invention.
[0051] Figure 8 Another flowchart illustrating the port enabling method provided in an embodiment of the present invention;
[0052] Figure 9 This is a schematic diagram of a port enabling device provided in an embodiment of the present invention. Detailed Implementation
[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of the present invention.
[0054] This invention provides a port enabling method for enabling ports of power-end devices. This method is applied to ultra-low latency switches. To more clearly explain the port enabling method provided by this invention, the structure of an ultra-low latency switch will be described below, such as... Figure 2 As shown, the ultra-low latency switch includes a processor 210, a PIPE chip 220, and multiple ports 230. Among the multiple ports 230, there is a first port 231 and a second port 232. The first port 231 is electrically connected to the PIPE chip 220, and the second port 232 is communicatively connected to the source device. That is, the source device accesses the ultra-low latency switch through the second port 232.
[0055] Data interaction between the first port 231 and the input chip 220 is achieved through the internal circuitry of an ultra-low latency switch. For example, the first port 231 and the input chip 220 are connected via a PCIe (Peripheral Component Interconnect Express, a computer expansion bus standard) bus, and data interaction is achieved through the PCIe bus. The input chip in this invention can be any chip with bitstream processing capabilities.
[0056] The processor 210 is used to implement the forwarding function of the ultra-low latency switch, that is, according to the pre-configured correspondence between the source port and the destination port, it forwards the bit stream obtained from the source port through the destination port. In this embodiment of the invention, the first port 231 is pre-configured as the destination port when the source port is the second port 232, and the second port 232 is configured as the destination port when the source port is the first port 231. Therefore, the processor 210 forwards the bit stream obtained from the first port 231 through the second port 232, and forwards the bit stream obtained from the second port 232 through the first port 231.
[0057] See Figure 3 , Figure 3 The diagram shown is a flowchart of a port enabling method provided in an embodiment of the present invention, including:
[0058] S301, the processor obtains the first control stream sent by the source device through the second port.
[0059] After the source device connects to the ultra-low latency switch, it will send the first control stream to the ultra-low latency switch through the second port. The processor in the ultra-low latency switch responsible for stream forwarding will obtain the first control stream through the second port.
[0060] S302, the processor sends the control code stream to the first port according to the pre-configured first correspondence between the first port and the second port.
[0061] As described above regarding ultra-low latency switches, the processor will forward the first control stream obtained from the second port through the first port.
[0062] The S303 introduces a chip that obtains the first control stream through the first port.
[0063] The chip is electrically connected to the first port, so after the processor forwards the first control stream to the first port, the chip can obtain the first control stream from the first port.
[0064] S304 introduces a chip to process the first control code stream and obtain the second control code stream.
[0065] Because the introduced chip has the capability to process bitstreams, it can process the first control bitstream to obtain the second control bitstream.
[0066] The S305 chip sends the second control stream to the first port.
[0067] S306, the processor obtains the second control stream through the first port.
[0068] S307, the processor sends the second control code stream to the second port according to the first correspondence.
[0069] As described above regarding ultra-low latency switches, the processor will forward the second control stream obtained from the first port through the second port.
[0070] S308, the source device acquires the second control stream and responds to the second control stream by enabling the port of the energy device.
[0071] Since the source device connects to the ultra-low latency switch via the second port, the processor forwards the second control stream through the second port, sending the second control stream to the source device. For the source device, the second control stream can be considered a response to the control stream returned by the first control stream; therefore, the source device can enable its own port, that is, enable the port on the source device that connects to the ultra-low latency switch. Corresponding to the source device enabling its own port, the port on the ultra-low latency switch that connects to the source device, i.e., the second port, will also be enabled.
[0072] By employing this embodiment, an ingress chip with bitstream processing capabilities can be incorporated into the ultra-low latency switch. The bitstream forwarding function of the ultra-low latency switch's processor forwards the first control bitstream sent by the source device to a first port electrically connected to the ingress chip. This allows the ingress chip to acquire and process the first control bitstream to obtain a second control bitstream. The processor's bitstream forwarding function then re-forwards the second control bitstream to the source device, enabling the source device to receive the returned control bitstream and thus enable its own port. Since this method can be implemented even when the source device connects to the ultra-low latency switch through a single port, it is suitable for unidirectional connections, effectively improving the applicability of the ultra-low latency switch.
[0073] Understandably, after the source device enables its own port, it can send data streams through the enabled port. The following example illustrates the data stream forwarding process of an ultra-low latency switch, using the scenario of the source device sending a data stream to the destination device as an example. The network structure in this example is as follows: Figure 4As shown, among the multiple ports 230, there is also a third port 233. The third port 233 is connected to the destination device for communication, that is, the destination device accesses the ultra-low latency switch through the third port 233.
[0074] The data stream forwarding process is as follows: Figure 5 As shown, it includes:
[0075] S501: The processor obtains the data stream sent by the source device through the second port.
[0076] S502, the processor sends the data stream to the third port according to the pre-configured second correspondence between the first port and the third port.
[0077] In this example, the third port will also be configured as the destination port when the source port is the second port. Therefore, the processor will forward the data stream obtained from the second port through the third port, i.e., send it to the destination device. It is understandable that, since the processor also obtains the aforementioned first control stream through the second port, in this example, the processor will also send the first control stream to the destination device through the third port. However, in this example, the destination device is connected to the ultra-low latency switch via the third port as the destination port; therefore, in this example, the destination device will not respond to the first control stream by returning a control stream to the source device.
[0078] S503, the destination device acquires the data stream.
[0079] To more clearly illustrate the differences in the forwarding methods of control streams and data streams, please refer to [link / reference]. Figure 6 , Figure 6 The route indicated by the solid arrow is the control stream, namely the route of the first and second control streams mentioned above. Figure 6 The route indicated by the dashed arrow is the route of the data stream. This can be understood as... Figure 6 The network structure shown only illustrates one destination device. In other possible embodiments, the number of destination devices accessing the ultra-low latency switch can also be multiple. In the case of multiple destination devices, the principle of the ultra-low latency switch forwarding control code stream and data code stream is the same as in the case of one destination device, so it will not be described again here.
[0080] In some application scenarios, users need to establish a one-way connection, for example... Figure 2 , Figure 4 , Figure 6 In the example shown, in other application scenarios, users may need to establish a bidirectional connection. For example, a bidirectional connection could be established as follows: Figure 7As shown in the example, the multiple ports 230 also include a fourth port 234, a fifth port 235, and a sixth port 236. In this example, the source device is connected to the ultra-low latency switch through the second port 232 and the fourth port 234, and there is another network device (hereinafter referred to as the network device) connected to the ultra-low latency switch through the fifth port 235 and the sixth port 236.
[0081] In this example, the second port 232 and the sixth port 236 are configured as source ports, while the fourth port 234 and the fifth port 235 are configured as destination ports. That is, the ultra-low latency switch obtains the bit streams sent by the source device and the network device through the second port 232 and the sixth port 236, respectively, and sends the bit streams to the source device and the network device through the fourth port 234 and the fifth port 235, respectively.
[0082] As mentioned above Figure 2 , Figure 3 According to the relevant instructions, the second control stream sent by the chip 220 will be sent by the processor 210 to the second port 232. However, in this example, the ultra-low latency switch is configured to send the stream to the source device through the fourth port 234 instead of the second port 232. Therefore, the second control stream sent to the second port 232 cannot be obtained by the source device. That is, in this example, the source device cannot obtain the second control stream sent by the chip 220.
[0083] As can be seen, for the case of bidirectional connection, the aforementioned Figure 3 The method shown cannot enable the source device's own ports. Therefore, in one possible implementation, the ultra-low latency switch only enables the port according to the specified method when there is a unidirectional connection between the source device and the ultra-low latency switch. Figure 3 Port enabling is performed as shown. That is, the aforementioned S302 includes:
[0084] If the source device and the ultra-low latency switch are connected in a one-way manner, the processor will send the first control stream to the first port according to the first correspondence between the first port and the second port as pre-configured.
[0085] By using this embodiment, the processor can send the first control stream to the introduced chip only when it can successfully access the port of the energy-side device, effectively avoiding the waste of resources of the introduced chip.
[0086] However, for the case where the connection between the source device and the ultra-low latency switch is not unidirectional, but bidirectional, then... Figure 7 Taking the network topology shown as an example, the forwarding process of the control stream is as follows: Figure 8 As shown, it includes:
[0087] S801, the processor obtains the first control stream sent by the source device through the second port.
[0088] S802, the processor sends the first control stream to the fifth port according to the pre-configured third correspondence between the second port and the fifth port.
[0089] In this embodiment of the invention, the processor executes S702 only when there is a bidirectional connection between the source device and the ultra-low latency switch. In this example, the fifth port is pre-configured as the destination port when the source port is the second port. Therefore, for the first control stream obtained from the second port, the processor will forward it through the fifth port, that is, send it to the network device.
[0090] S803: The network device acquires and processes the first control stream to obtain the third control stream.
[0091] As mentioned above Figure 7 As explained, the ultra-low latency switch obtains the packets sent by the network device through port 6. Therefore, the third control stream obtained by the network device will be sent to the ultra-low latency switch through port 6.
[0092] The S804 processor obtains the third control stream sent by the network device through port 6.
[0093] S805, the processor sends the third control stream to the fourth port.
[0094] In this example, the fourth port is pre-configured as the destination port when the source port is the sixth port. Therefore, for the third control stream obtained from the sixth port, the processor will forward it through the fourth port, that is, send it to the source device.
[0095] S806, the source device acquires the third control stream and responds to the third control stream to enable the port of the energy device.
[0096] By using this embodiment, the source device can still enable its own ports normally even in bidirectional connection, thus enabling the use of ultra-low latency switches in both unidirectional and bidirectional connection scenarios, further improving the applicability of ultra-low latency switches.
[0097] Corresponding to the aforementioned port enabling method, this embodiment of the invention also provides a port enabling device applied to an ultra-low latency switch. The ultra-low latency switch includes a processor, an ingress chip, and multiple ports. The ingress chip is electrically connected to a first port among the multiple ports. A source device connects to the ultra-low latency switch through a second port among the multiple ports. The device is as follows: Figure 9 As shown, it includes:
[0098] The first flow-guiding module 901 is used to drive the processor to obtain the first control code stream sent by the source device through the second port; and to send the first control code stream to the first port according to the first correspondence between the first port and the second port in a pre-configured manner.
[0099] Processing module 902 is used to drive the input chip to acquire the first control code stream through the first port; process the first control code stream to obtain a second control code stream; and send the second control code stream to the first port.
[0100] The second flow-guiding module 903 is used to drive the processor to obtain the second control code stream through the first port; and send the second control code stream to the second port according to the first correspondence, so that the source device obtains the second control code stream and enables the port of the source device in response to the second control code stream.
[0101] In one possible embodiment, the target device accesses the ultra-low latency switch through a third port of the plurality of ports, and the apparatus further includes:
[0102] The data stream forwarding module is used to drive the processor to obtain the data stream sent by the source device through the second port; and to send the data stream to the third port according to the second correspondence between the first port and the third port in a pre-configured manner, so that the destination device can obtain the data stream.
[0103] In one possible embodiment, the first correspondence is pre-configured in the following manner:
[0104] The processor configures the second port as the destination port corresponding to the source port being the first port, and configures the first port as the destination port corresponding to the source port being the second port.
[0105] In one possible embodiment, the first flow-directing module drives the processor to send the first control stream to the first port according to a pre-configured first correspondence between the first port and the second port, including:
[0106] If the source device and the ultra-low latency switch are connected in a one-way manner, the processor is driven to send the first control stream to the first port according to the first correspondence between the first port and the second port as pre-configured.
[0107] In one possible embodiment, the source device further connects to the ultra-low latency switch via a fourth port of the plurality of ports, and the network device connects to the ultra-low latency switch via a fifth and a sixth port of the plurality of ports. The apparatus further includes:
[0108] A bidirectional connection module is used to drive the processor to send the first control stream to the fifth port according to the pre-configured third correspondence between the second port and the fifth port if there is a bidirectional connection between the source device and the ultra-low latency switch, so that the network device can obtain and process the first control stream to obtain the third control stream.
[0109] The processor is driven to acquire the third control stream sent by the network device through the sixth port; and according to the pre-configured fourth correspondence between the sixth port and the fourth port, the third control stream is sent to the fourth port, so that the source device acquires the third control stream and enables the port of the source device in response to the third control stream.
[0110] This invention also provides an ultra-low latency switch, comprising:
[0111] Processor, integrated chip, and multiple ports;
[0112] The first port of the plurality of ports is electrically connected to the introduced chip, and the second port of the plurality of ports is communicatively connected to the source device.
[0113] The processor is configured to acquire a first control stream sent by the source device through the second port; and send the first control stream to the first port according to a pre-configured first correspondence between the first port and the second port.
[0114] The introduced chip is used to acquire the first control stream through the first port; process the first control stream to obtain a second control stream; and send the second control stream to the first port.
[0115] The processor is further configured to acquire the second control stream through the first port; and send the second control stream to the second port according to the first correspondence, so that the source device acquires the second control stream and enables the port of the source device in response to the second control stream.
[0116] For information on the structure of ultra-low latency switches, please refer to the aforementioned text. Figure 2 , Figure 4 , Figure 6 As shown in the example, it will not be elaborated upon here.
[0117] In another embodiment of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, the computer program implements the steps of any of the above-described port enabling methods.
[0118] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the port enabling methods described in the above embodiments.
[0119] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).
[0120] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0121] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, embodiments of apparatus, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0122] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A port enabling method, characterized in that, An application is made in an ultra-low latency switch, the ultra-low latency switch including a processor, an ingress chip, and multiple ports, the ingress chip being electrically connected to a first port among the multiple ports, and a source device connecting to the ultra-low latency switch through a second port among the multiple ports, the method comprising: The processor obtains the first control stream sent by the source device through the second port; and sends the first control stream to the first port according to the first correspondence between the first port and the second port in a pre-configured manner. The chip acquires the first control stream through the first port; processes the first control stream to obtain a second control stream; and sends the second control stream to the first port. The processor obtains the second control stream through the first port; and sends the second control stream to the second port according to the first correspondence, so that the source device obtains the second control stream and enables the port of the source device in response to the second control stream, wherein, for the source device, the second control stream is regarded as the control stream returned in response to the first control stream.
2. The method according to claim 1, characterized in that, The target device connects to the ultra-low latency switch through a third port among the plurality of ports, and the method further includes: The processor acquires the data stream sent by the source device through the second port; and sends the data stream to the third port according to the pre-configured second correspondence between the first port and the third port, so that the destination device can acquire the data stream.
3. The method according to claim 1, characterized in that, The first correspondence is pre-configured in the following ways: The processor configures the second port as the destination port corresponding to the source port being the first port, and configures the first port as the destination port corresponding to the source port being the second port.
4. The method according to claim 1, characterized in that, The processor sends the first control stream to the first port according to a pre-configured first correspondence between the first port and the second port, including: If the source device and the ultra-low latency switch are connected in a one-way manner, the processor sends the first control stream to the first port according to the first correspondence between the first port and the second port as pre-configured.
5. The method according to claim 4, characterized in that, The source device is also connected to the ultra-low latency switch via the fourth port of the plurality of ports, and the network device is connected to the ultra-low latency switch via the fifth and sixth ports of the plurality of ports. The method further includes: If the source device and the ultra-low latency switch are bidirectionally connected, the processor sends the first control stream to the fifth port according to the pre-configured third correspondence between the second port and the fifth port, so that the network device can obtain and process the first control stream to obtain the third control stream. The processor obtains the third control stream sent by the network device through the sixth port; and sends the third control stream to the fourth port according to the pre-configured fourth correspondence between the sixth port and the fourth port, so that the source device obtains the third control stream and enables the port of the source device in response to the third control stream.
6. A port enabling device, characterized in that, The device is applied to an ultra-low latency switch, which includes a processor, an ingress chip, and multiple ports. The ingress chip is electrically connected to a first port among the multiple ports. A source device is connected to the ultra-low latency switch through a second port among the multiple ports. The device includes: The first stream routing module is used to drive the processor to obtain the first control stream sent by the source device through the second port; and to send the first control stream to the first port according to the first correspondence between the first port and the second port in a pre-configured manner. The processing module is configured to drive the input chip to acquire the first control stream through the first port; process the first control stream to obtain a second control stream; and send the second control stream to the first port. The second flow-guiding module is used to drive the processor to obtain the second control code stream through the first port; and send the second control code stream to the second port according to the first correspondence, so that the source device obtains the second control code stream and enables the port of the source device in response to the second control code stream, wherein, for the source device, the second control code stream is regarded as the control code stream returned in response to the first control code stream.
7. The apparatus according to claim 6, characterized in that, The target device connects to the ultra-low latency switch through a third port among the plurality of ports, and the device further includes: The data stream forwarding module is used to drive the processor to obtain the data stream sent by the source device through the second port; and to send the data stream to the third port according to the second correspondence between the first port and the third port in a pre-configured manner, so that the destination device can obtain the data stream.
8. The apparatus according to claim 6, characterized in that, The first correspondence is pre-configured in the following ways: The processor configures the second port as the destination port corresponding to the source port being the first port, and configures the first port as the destination port corresponding to the source port being the second port.
9. The apparatus according to claim 6, characterized in that, The first traffic redirection module drives the processor to send the first control stream to the first port according to a pre-configured first correspondence between the first port and the second port, including: If the source device and the ultra-low latency switch are connected in a one-way manner, the processor is driven to send the first control stream to the first port according to the first correspondence between the first port and the second port as pre-configured.
10. The apparatus according to claim 9, characterized in that, The source device is also connected to the ultra-low latency switch via the fourth port of the plurality of ports, and the network device is connected to the ultra-low latency switch via the fifth and sixth ports of the plurality of ports. The device further includes: A bidirectional connection module is used to drive the processor to send the first control stream to the fifth port according to the pre-configured third correspondence between the second port and the fifth port if there is a bidirectional connection between the source device and the ultra-low latency switch, so that the network device can obtain and process the first control stream to obtain the third control stream. The processor is driven to acquire the third control stream sent by the network device through the sixth port; and according to the pre-configured fourth correspondence between the sixth port and the fourth port, the third control stream is sent to the fourth port, so that the source device acquires the third control stream and enables the port of the source device in response to the third control stream.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-5.