Data processing method, system, electronic device and computer readable storage medium

Abstract

The application discloses a data processing method and system, electronic equipment and a computer readable storage medium. The method comprises the following steps: receiving data acquisition instructions sent by a plurality of predetermined processors respectively; in response to the data acquisition instructions sent by the plurality of predetermined processors respectively, acquiring initial output data corresponding to the plurality of predetermined processors respectively; comparing the initial output data corresponding to the plurality of predetermined processors respectively to obtain a target comparison result; and in the case that the target comparison result is that the initial output data corresponding to the plurality of predetermined processors respectively are all the same, performing a target operation according to target information, a target address and an operation type in the target output data. The application solves the technical problem of high cost in the data processing process caused by the fact that, in the related art, when a processor performs safety detection on input data, the input data needs to be compared by customized hardware to realize safety detection on the input data.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically, to a data processing method, system, electronic device, and computer-readable storage medium. Background Technology

[0002] Currently, computer systems have increasingly higher requirements for data reliability. In the information age, to defend against various external cyberattacks, many computer systems have begun to use homogeneous or heterogeneous redundant processors to process the same information, and then obtain more reliable and secure information by adjudicating the outputs of each redundant processor. How to conveniently and quickly process this redundant information is a key technology of redundant systems. In related technologies, when the processor performs security checks on the input data, it needs to compare the input data through customized hardware to achieve security checks, resulting in excessively high costs in the data processing process.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This invention provides a data processing method, system, electronic device, and computer-readable storage medium to at least solve the technical problem in related technologies where processors need to compare input data with customized hardware to achieve security detection of input data, resulting in excessively high costs during data processing.

[0005] According to one aspect of the present invention, a data processing method is provided, comprising: receiving data acquisition instructions sent by a plurality of predetermined processors respectively; in response to the data acquisition instructions sent by the plurality of predetermined processors respectively, acquiring initial output data corresponding to the plurality of predetermined processors respectively, wherein the initial output data is data obtained by the plurality of predetermined processors respectively executing a target task, and the initial output data includes target information, a target address, and an operation type; comparing the initial output data corresponding to the plurality of predetermined processors respectively to obtain a target comparison result; and, if the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors respectively, performing a target operation according to the target information, the target address, and the operation type in the target output data, wherein the target output data is any one of the initial output data corresponding to the plurality of predetermined processors respectively.

[0006] Optionally, when the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors, performing a target operation based on the target information, the target address, and the operation type in the target output data includes: when the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, performing an operation based on the offset storage address, the current address, and the read operation to retrieve the target read data from the current address and store the target read data to the plurality of target storage addresses respectively, wherein the plurality of target storage addresses are determined based on the offset storage address, and the target read data is data read by the target processor from the target address.

[0007] Optionally, before performing the operation of retrieving the target read data from the current address and storing the target read data to multiple target storage addresses based on the offset storage address, the current address, and the read operation when the target comparison result is the same as the initial output data corresponding to the multiple predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, the method further includes: determining the base address corresponding to the multiple predetermined processors when the target comparison result is the same as the initial output data corresponding to the multiple predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation; and determining the target storage address corresponding to the multiple predetermined memories based on the offset storage address and the base address corresponding to the multiple predetermined processors.

[0008] Optionally, when the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors respectively, performing the target operation based on the target information, the target address, and the operation type in the target output data includes: when the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors respectively, the target information is target write data, the target address is the storage address of the target write data, and the operation type is a write operation, performing the operation of storing the target write data to the target address based on the target write data, the storage address, and the write operation, wherein the target write data is data read by the target processor from the target information in the target output data.

[0009] Optionally, in response to data acquisition instructions sent by the plurality of predetermined processors respectively, acquiring initial output data corresponding to the plurality of predetermined processors respectively includes: in response to the data acquisition instructions sent by the plurality of predetermined processors respectively, sending a data copy instruction to a direct memory access device (DMA), wherein the data copy instruction is used to cause the DMA to copy the initial output data corresponding to the plurality of predetermined processors respectively to the DMA, and send the initial output data corresponding to the plurality of predetermined processors respectively to the target processor; and receiving the initial output data corresponding to the plurality of predetermined processors sent by the DMA.

[0010] Optionally, after comparing the initial output data corresponding to the plurality of predetermined processors to obtain the target comparison result, the method further includes: if the target comparison result is different from the initial output data corresponding to the plurality of predetermined processors, sending operation failure information to the plurality of predetermined processors respectively.

[0011] Optionally, after receiving data acquisition instructions sent by multiple predetermined processors, the method further includes: determining a first number of predetermined processors executing the target task, and determining a second number of received data acquisition instructions; if the first number is greater than the second number, determining a standby processor, wherein the standby processor is a processor among the predetermined processors that has not sent a data acquisition instruction; and sending a fault determination instruction to the standby processor, wherein the fault determination instruction is used to determine whether the standby processor is faulty.

[0012] According to one aspect of the present invention, a data processing system is provided, comprising: a target processor, configured to receive data acquisition instructions sent by a plurality of predetermined processors respectively; in response to the data acquisition instructions sent by the plurality of predetermined processors respectively, acquire initial output data corresponding to the plurality of predetermined processors respectively, wherein the initial output data is data obtained by the plurality of predetermined processors respectively executing a target task, and the initial output data includes target information, a target address, and an operation type; compare the initial output data corresponding to the plurality of predetermined processors respectively to obtain a target comparison result; and, if the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors respectively, execute a target operation according to the target information, the target address, and the operation type in the target output data, wherein the target output data is any one of the initial output data corresponding to the plurality of predetermined processors respectively; and a plurality of predetermined processors, configured to execute the target task respectively to obtain corresponding initial output data, and respectively send the data acquisition instructions to the target processor.

[0013] According to one aspect of the present invention, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the data processing method described in any of the preceding embodiments.

[0014] According to one aspect of the present invention, a computer-readable storage medium is provided, wherein when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform any of the data processing methods described above.

[0015] In this embodiment of the invention, data acquisition instructions sent by multiple predetermined processors are received first, and then, in response to these instructions, initial output data corresponding to each predetermined processor is acquired. This initial output data is then compared with the initial output data corresponding to each predetermined processor to obtain a target comparison result. If the target comparison result is identical to the initial output data corresponding to each predetermined processor, a target operation is executed based on the target information, target address, and operation type in the target output data. The initial output data consists of data obtained by the multiple predetermined processors executing the target task, including target information, target address, and operation type. The target output data is any one of the initial output data corresponding to each predetermined processor. Because the initial output data is compared using software, a target comparison result can be obtained without custom hardware comparison of the initial input data, reducing the cost of data processing. Since the target operation can be executed based on the target information, target address, and operation type in the target output data when the target comparison result is identical to the initial output data corresponding to each predetermined processor, the target operation can be executed accurately based on the target output data. This technology reduces the cost of data processing, thereby solving the problem of high costs in data processing caused by the need for customized hardware to compare input data when the processor performs security checks on the input data. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0017] Figure 1 This is a flowchart of a data processing method according to an embodiment of the present invention;

[0018] Figure 2 This is a hardware block diagram of a data processing system provided by an optional embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the structure of a memory provided in an optional embodiment of the present invention;

[0020] Figure 4 This is a flowchart of a method provided by an optional embodiment of the present invention;

[0021] Figure 5 This is a structural block diagram of a data processing system according to an embodiment of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] Example 1

[0025] According to an embodiment of the present invention, an embodiment of a data processing method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0026] Figure 1 This is a flowchart of a data processing method according to an embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0027] Step S102: Receive data acquisition instructions sent by multiple predetermined processors respectively;

[0028] In the technical solution provided by step S102 of the present invention, when multiple predetermined processors execute the target task respectively, the target task can trigger an interrupt request to ensure that the target processor can quickly receive the data acquisition instructions sent by the multiple predetermined processors respectively.

[0029] Step S104: In response to the data acquisition instructions sent by the multiple predetermined processors respectively, acquire the initial output data corresponding to the multiple predetermined processors respectively. The initial output data is the data obtained by the multiple predetermined processors executing the target task respectively. The initial output data includes target information, target address and operation type.

[0030] In the technical solution provided by step S104 of the present invention, by responding to the data acquisition instructions sent by multiple predetermined processors respectively, the initial output data corresponding to the multiple predetermined processors can be acquired quickly and accurately.

[0031] Step S106: Compare the initial output data with the initial output data corresponding to the multiple predetermined processors respectively to obtain the target comparison result;

[0032] In the technical solution provided by step S106 of the present invention, since the initial output data corresponding to multiple predetermined processors is compared by software, the target comparison result can be obtained without comparing the initial input data by customized hardware, thereby reducing the cost in the data processing process.

[0033] Step S108: If the target comparison result is the same as the initial output data corresponding to the multiple predetermined processors, the target operation is performed according to the target information, target address and operation type in the target output data, wherein the target output data is any one of the initial output data corresponding to the multiple predetermined processors.

[0034] In the technical solution provided by step S108 of the present invention, when the target comparison result is the same as the initial output data corresponding to the multiple predetermined processors respectively, that is, when the initial output data passes the security detection, the target operation can be executed quickly and accurately based on the target information, target address and operation type in the target output data.

[0035] Through steps S102 to S108, the process involves first receiving data acquisition instructions from multiple predetermined processors, then responding to these instructions to acquire initial output data corresponding to each predetermined processor. This initial output data is then compared to the initial output data from each predetermined processor to obtain a target comparison result. If the target comparison result is identical to the initial output data from each predetermined processor, a target operation is executed based on the target information, target address, and operation type within the target output data. The initial output data consists of data obtained by the multiple predetermined processors executing the target task, including target information, target address, and operation type. The target output data is any one of the initial output data corresponding to each predetermined processor. Because the initial output data is compared using software, a target comparison result can be obtained without custom hardware comparison of the initial input data, reducing data processing costs. Since the target operation can be executed accurately based on the target information, target address, and operation type within the target output data when the target comparison result is identical to the initial output data from each predetermined processor, the target operation can be executed precisely based on the target output data. This technology reduces the cost of data processing, thereby solving the problem of high costs in data processing caused by the need for customized hardware to compare input data when the processor performs security checks on the input data.

[0036] As an optional embodiment, when the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, a target operation is performed based on the target information, target address, and operation type in the target output data. This includes: when the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, the target read data is retrieved from the current address and stored in multiple target storage addresses according to the offset storage address, the current address, and the read operation. The multiple target storage addresses are determined based on the offset storage address, and the target read data is the data read by the target processor from the target address.

[0037] In this embodiment, when the target comparison result is identical to the initial output data corresponding to multiple predetermined processors (i.e., the initial output data corresponding to multiple predetermined processors passes security detection), the target information is the offset storage address of the target read data, the target address is the current address of the target read data (i.e., the current address of the target read data in the peripheral device), and the operation type is a read operation, based on the current address and the read operation, the operation of retrieving the target read data from the address currently located in the peripheral device can be accurately executed. In this case, the target read data is the data read by the target processor from the target address and sent by the target processor to the corresponding target memory among the multiple predetermined processors. That is, the target read data can also be understood as the data that the multiple predetermined processors want to obtain from the target address after executing the target task; it is the data that wants to be read from the target address. This ensures that the read operation is executed smoothly in this case. Based on the offset storage address, the operation of storing the target read data to multiple target storage addresses can be accurately executed, where the multiple target storage addresses are determined based on the offset storage address.

[0038] It should be noted that when the target comparison result is identical to the initial output data corresponding to multiple predetermined processors, and the operation type is a read operation, the target information is the offset storage address of the target read data, and the target address is the current address of the target read data. Multiple target storage addresses are the addresses where the target read data should be stored in multiple predetermined memories. Each predetermined memory corresponds one-to-one with a predetermined processor. Multiple target storage addresses are multiple base addresses of multiple predetermined memories plus their offset storage addresses. Each base address is the first address of a multiple predetermined memory, and the target processor can obtain multiple base addresses.

[0039] As an optional embodiment, when the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, before performing the operation of retrieving the target read data from the current address and storing the target read data to multiple target storage addresses based on the offset storage address, the current address, and the read operation, the method further includes: when the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, determining the base address corresponding to each of the multiple predetermined processors; and determining the target storage address corresponding to each of the multiple predetermined memories based on the offset storage address and the base address corresponding to each of the multiple predetermined processors.

[0040] In this embodiment, when the target comparison result is that the initial output data corresponding to the multiple predetermined processors are all the same, that is, the initial output data corresponding to the multiple predetermined processors have passed the security detection, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, that is, the address of the target read data in the peripheral device, and the operation type is a read operation, the base address corresponding to the multiple predetermined processors is determined, that is, the first address of the multiple predetermined memories that correspond one-to-one with the multiple predetermined processors. Based on the offset storage address and the base address corresponding to the multiple predetermined processors, the target storage address corresponding to the multiple predetermined memories can be accurately determined.

[0041] As an optional embodiment, when the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, a target operation is performed based on the target information, target address, and operation type in the target output data. This includes: when the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, the target information is target write data, the target address is the storage address of the target write data, and the operation type is a write operation, an operation is performed to store the target write data to the target address based on the target write data, the storage address, and the write operation. The target write data is the data read by the target processor from the target information in the target output data.

[0042] In this embodiment, when the target comparison result is identical to the initial output data corresponding to multiple predetermined processors (i.e., the initial output data corresponding to multiple predetermined processors passes security detection), the target information is target write data, the target address is the storage address of the target write data (i.e., the address where the target write data should be stored in the peripheral device), and the operation type is a write operation, the operation of storing the target write data in the target address of the peripheral device can be executed accurately and quickly based on the target write data, storage address, and write operation. In this case, the target write data is the data read by the target processor from the target information in the target output data and sent by the target processor to the target address. That is, the target write data can also be understood as the data to be stored at the target address after the multiple predetermined processors have completed their target tasks, i.e., the data written to the target address. This ensures that the write operation is executed smoothly in this situation.

[0043] It should be noted that when the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, and the operation type is a write operation, the target information is the target write data, and the target address is the storage address of the target write data.

[0044] As an optional embodiment, in response to data acquisition instructions sent by a plurality of predetermined processors respectively, initial output data corresponding to the plurality of predetermined processors is acquired, including: in response to data acquisition instructions sent by a plurality of predetermined processors respectively, sending a data copy instruction to a direct memory access device (DMA), wherein the data copy instruction is used to cause the DMA to copy the initial output data corresponding to the plurality of predetermined processors to the DMA, and send the initial output data corresponding to the plurality of predetermined processors to the target processor; and receiving the initial output data corresponding to the plurality of predetermined processors sent by the DMA.

[0045] In this embodiment, in response to data acquisition instructions sent by multiple predetermined processors, a data copy instruction can be quickly and promptly sent to the Direct Memory Access (DMA) device. This causes the DMA to copy the initial output data corresponding to each of the multiple predetermined processors to the DMA, and then send the initial output data corresponding to each of the multiple predetermined processors to the target processor. The initial output data corresponding to each of the multiple predetermined processors sent by the DMA can be received quickly.

[0046] As an optional embodiment, after comparing the initial output data corresponding to the multiple predetermined processors to obtain the target comparison result, the method further includes: if the target comparison result is different from the initial output data corresponding to the multiple predetermined processors, sending operation failure information to the multiple predetermined processors respectively.

[0047] In this embodiment, when the target comparison result is different from the initial output data corresponding to the multiple predetermined processors respectively, that is, when the initial output data corresponding to the multiple predetermined processors respectively fails the security check, operation failure information is sent to the multiple predetermined processors respectively. This can ensure that the multiple predetermined processors receive the operation failure information in a timely manner and know that the operation has failed.

[0048] It should be noted that after multiple pre-defined processors receive operation failure information, the target task can be executed again to ensure that the target task is executed successfully.

[0049] As an optional embodiment, after receiving data acquisition instructions sent by a plurality of predetermined processors respectively, the method further includes: determining a first number of predetermined processors executing the target task, and determining a second number of received data acquisition instructions; if the first number is greater than the second number, determining a standby processor, wherein the standby processor is a processor among the predetermined processors that has not sent a data acquisition instruction; and sending a fault determination instruction to the standby processor, wherein the fault determination instruction is used to determine whether the standby processor is faulty.

[0050] In this embodiment, if the first number is greater than the second number, that is, if the number of predetermined processors executing the target task is greater than the number of received data acquisition instructions, it indicates that there are predetermined processors that have not sent data acquisition instructions. In this case, a standby processor is identified, that is, a processor among the predetermined processors that has not sent a data acquisition instruction. Sending a fault determination instruction to the standby processor can determine whether the standby processor is faulty in a timely and accurate manner.

[0051] It should be noted that in the event of a standby processor failure, a request can be made to address the faulty standby processor to ensure that all scheduled processors can function properly.

[0052] Based on the above embodiments and optional embodiments, an optional implementation method is provided, which is described in detail below.

[0053] In related technologies, when a processor performs security checks on input data, it needs to compare the input data through customized hardware in order to achieve security checks on the input data, which leads to a technical problem of excessively high costs in the data processing process.

[0054] In view of this, an optional embodiment of the present invention provides a data processing method that can perform security detection of input data by comparing input data through software, without the need for customized hardware to compare input data, thereby reducing the cost in the data processing process.

[0055] Figure 2 This is a hardware block diagram of a data processing system provided in an optional embodiment of the present invention. Figure 2In this diagram, CPU 1, CPU 2, and CPU 3 correspond to the multiple pre-defined processors mentioned above, CPU 0 corresponds to the target processor mentioned above, CPU1Memory, CPU 2Memory, and CPU 3Memory correspond to the multiple pre-defined memories mentioned above, and CPU 1Memory, CPU 2Memory, and CPU 3Memory correspond one-to-one with CPU 1, CPU 2, and CPU 3 respectively. CPU 0Memory is the target memory corresponding to CPU 0. Bus Matrix is ​​the bus, and CPU 0 can obtain the base addresses of CPU1Memory, CPU 2Memory, and CPU 3Memory through Bus Matrix. Feedback INT Registers are the feedback interrupt registers corresponding to CPU1Memory, CPU 2Memory, and CPU 3Memory respectively, and CMP INT Registers are the compare interrupt registers corresponding to CPU1Memory, CPU 2Memory, and CPU 3Memory respectively. Peripheral 0, Peripheral 1, and Peripheral 2 correspond to the peripherals mentioned above. Figure 2As shown, a custom software multitasking scheduling system runs on three redundant processors, CPU 1, CPU 2, and CPU 3. Each target task created by the user is assigned a task ID. The initial output data obtained by executing the target task on CPU 1, CPU 2, and CPU 3 are stored in CPU1 Memory, CPU 2 Memory, and CPU 3 Memory, respectively. Each target task triggers a compare interrupt request to CPU 0 to read the initial output data of the target task (equivalent to receiving data acquisition instructions sent by multiple predetermined processors as mentioned above). Since CPU 1, CPU 2, and CPU 3 are running the same target task, under normal circumstances, the arbitration processor CPU 0 will receive the compare interrupt requests sent by CPU 1, CPU 2, and CPU 3 through the CMP INT Register at almost the same time. CPU 0 will also receive the data acquisition instructions sent by CPU 1, CPU 2, and CPU 3 through the compare interrupt requests. The DMA is responsible for copying the initial output data from CPU 1 Memory, CPU 2 Memory, and CPU 3 Memory to CPU 0 Memory (equivalent to sending a data copy instruction to the DMA in response to data fetch instructions from multiple predetermined processors, and receiving the initial output data corresponding to each predetermined processor from the DMA). After processing the arbitration data, CPU 0 triggers a feedback interrupt request via the Feedback INT Register to notify CPU 1, CPU 2, and CPU 3 that the target operation failed (equivalent to sending operation failure information to multiple predetermined processors when the target comparison result is different from the initial output data corresponding to each predetermined processor). It should be noted that if the target comparison result is the same as the initial output data corresponding to multiple predetermined processors, after executing the target operation based on the target information, target address, and operation type in the target output data, CPU 0 also needs to trigger a feedback interrupt request via the Feedback INT Register to notify CPU 1, CPU 2, and CPU 3 that the target operation succeeded.

[0056] The CMP INT Register is triggered by CPU 1, CPU 2, and CPU 3 to CPU 0, indicating that task data needs to be compared. The Feedback INT Register is triggered by CPU 0 to CPU 1, CPU 2, and CPU 3, informing them of the execution result of the target operation. The structures of the two sets of interrupt registers, CMP INT Register and Feedback INT Register, are as follows: Figure 2 As shown, there are three main fields, and the meaning of each field is shown in Table 1. Explanation of each field in the interrupt register.

[0057] Table 1

[0058]

[0059] As shown in Table 1, CPU 1, CPU 2, and CPU 3 can each trigger an interrupt by writing to the CMP INT Register. The interrupt enable flag en is set to 1 when the interrupt is triggered, requesting CPU 0 to read the initial output data. There are two types of interrupt triggering logic: one is that the output id is less than or equal to 31, which means that CPU 0 is requested to read the initial output data corresponding to the output id of the target task; the other is that the output id is greater than 31, which means that CPU 0 is requested to read all the initial output data that has not yet been read during the execution of the target task.

[0060] The `struct task_output` data structure of the initial output data obtained by CPU 1, CPU 2, and CPU 3 executing the target task is as follows:

[0061]

[0062]

[0063] In the data structure, `addr` is equivalent to the target address mentioned above, where `uint32_t addr` occupies 32 bits. `w_en` is equivalent to the operation type mentioned above, where `uint8_t w_en` occupies 8 bits. `data_with` represents the data width, where `uint8_t data_with` occupies 8 bits. `data` is equivalent to the target information mentioned above, where `uint32_t data` occupies 32 bits. `flag` indicates whether the initial output data has been read by CPU 0, where `uint8_t flag` occupies 8 bits. `result` represents the execution result of the target operation, where `uint8_t result` occupies 8 bits. It should be noted that `w_en` of 1 indicates a write operation, `w_en` of 0 indicates a read operation, `flag` of 0 indicates that the initial output data has been read by CPU 0, `flag` of 1 indicates that the initial output data has not been read by CPU 0, `result` of 1 indicates that the target operation was successful, and `result` of 0 indicates that the target operation failed.

[0064] Figure 3 This is a schematic diagram of the structure of a memory provided in an optional embodiment of the present invention, such as... Figure 3 As shown, the hardware structure of CPU1Memory, CPU2Memory, and CPU3Memory for storing initial output data corresponds one-to-one with the data structure of the initial output data. Task 0 indicates that the task ID is 0, Task 1 indicates that the task ID is 1, and Task n indicates that the task ID is n. The numbers 0-31 on the left are the output IDs. That is, each of the CPU1Memory, CPU2Memory, and CPU3Memory can store the initial output data obtained from n target tasks, and each target task supports a maximum of 32 initial output data.

[0065] It should be noted that each of the CPU 1 Memory, CPU 2 Memory, and CPU 3 Memory allocates a fixed amount of space to store data for each target task. The output data of task 0 is stored from the beginning of the memory, and each task's data is stored sequentially. CPU 0 calculates the offset storage address of the output data based on the task ID, output ID, and the size of the data structure in the interrupt register. The target storage address is obtained by adding the offset storage address to the base address corresponding to the CPU 1 Memory, CPU 2 Memory, and CPU 3 Memory, respectively.

[0066] Figure 4 This is a flowchart of a method provided by an optional embodiment of the present invention, such as... Figure 4 As shown,

[0067] S1, CPU 1, CPU 2 and CPU 3 respectively run tasks (equivalent to executing the target task in the above text);

[0068] S2, CPU 1, CPU 2 and CPU 3 respectively trigger output compare interrupts (equivalent to multiple predetermined processors sending data fetch instructions to the target processor respectively as mentioned above);

[0069] S3, CPU 0 enables DMA (equivalent to the data copy instruction to DMA mentioned above) to move the task data of CPU1, CPU2 and CPU3 (equivalent to the initial output data mentioned above) to local memory (equivalent to CPU0Memory mentioned above);

[0070] S4, CPU 0 updates the flag field of the task data structure struct task_output (equivalent to the data structure mentioned above) of each redundant CPU (equivalent to CPU 1, CPU 2 and CPU 3 in the above text) to 0, and compares the task data of each CPU moved to local memory (equivalent to comparing the initial output data corresponding to multiple predetermined processors in the above text).

[0071] S5, whether they are consistent (equivalent to obtaining the target comparison result in the above text);

[0072] S5.1, If ​​consistent (equivalent to the case where the target comparison result is the same as the initial output data corresponding to multiple predetermined processors as described above): CPU 0 updates the result field of each redundant CPU memory (equivalent to CPU1Memory, CPU2Memory, and CPU3Memory as described above) to 1, and then executes the target operation. If it is a write operation, CPU 0 writes the data field of the struct task_output structure to the peripheral address specified by the addr field; if it is a read operation, CPU 0 writes the data read from the peripheral address specified by the addr field of the struct task_output structure back to the memory address space of each redundant CPU specified by the data field. After completing these operations, CPU 0 triggers an interrupt to notify each redundant CPU that the peripheral access is complete.

[0073] S5.2, If inconsistent (where the target comparison result differs from the initial output data corresponding to multiple predetermined processors): CPU 0 updates the result field in the memory of each redundant CPU to 0. After completing these operations, CPU 0 triggers an interrupt to notify each redundant CPU peripheral access is complete.

[0074] It should be noted that after receiving an interrupt request from CPU 1, CPU 0 calculates the address of the initial output data (the structure of the struct task_output data structure) based on the task id and output id. It then moves the corresponding task data from CPU 1 Memory to CPU 0 Memory via DMA. Similarly, after receiving interrupt requests from CPU 2 and CPU 3, CPU 0 moves the task output data of CPU 2 and CPU 3 to CPU 0 Memory in sequence, updates the flag field in each CPU struct task_output structure to 1, and then CPU 0 compares the three sets of task data.

[0075] The above optional implementation methods can achieve at least the following beneficial effects:

[0076] (1) By comparing input data with software, security detection of input data can be achieved without the need for customized hardware to compare input data, thereby reducing the cost of data processing.

[0077] (2) By comparing input data with software, security detection of input data can be achieved without customizing hardware, thus avoiding the disadvantage of long hardware development cycle;

[0078] (3) The target tasks executed by multiple pre-defined processors adopt a task-based scheduling operation mode, which reduces the coupling between multiple target tasks compared to single-threaded sequential execution without scheduling.

[0079] (4) The data processing method in this application has a wide range of applications in the field of redundant arbitration, and is flexible and efficient.

[0080] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present invention.

[0082] Example 2

[0083] According to embodiments of the present invention, a system for implementing the above-described data processing method is also provided. Figure 5 This is a structural block diagram of a data processing system according to an embodiment of the present invention, such as... Figure 5 As shown, the system includes a target processor 502 and a plurality of predetermined processors 504. The system is described in detail below.

[0084] The target processor 502 is configured to receive data acquisition instructions sent by a plurality of predetermined processors 504 respectively; in response to the data acquisition instructions sent by the plurality of predetermined processors 504 respectively, acquire initial output data corresponding to the plurality of predetermined processors 504 respectively, wherein the initial output data is data obtained by the plurality of predetermined processors 504 respectively executing the target task, and the initial output data includes target information, target address, and operation type; compare the target output data with the initial output data corresponding to the plurality of predetermined processors 504 respectively to obtain a target comparison result; if the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors 504 respectively, execute the target operation according to the target information, target address, and operation type in the target output data, wherein the target output data is any one of the initial output data corresponding to the plurality of predetermined processors 504 respectively;

[0085] Multiple predetermined processors 504 are connected to the target processor 502, and are used to execute the target task respectively to obtain the corresponding initial output data, and send data acquisition instructions to the target processor 502 respectively.

[0086] It should be noted that the target processor 502 and the plurality of predetermined processors 504 are used to implement steps S102 to S108 in the data processing method. The multiple modules and the corresponding steps are the same in terms of implementation instances and application scenarios, but are not limited to the content disclosed in the above embodiment 1.

[0087] Example 3

[0088] According to another aspect of the present invention, an electronic device is also provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein the processor is configured to execute instructions to implement the data processing method described above.

[0089] Example 4

[0090] According to another aspect of the present invention, a computer-readable storage medium is also provided, which, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform any of the above-described data processing methods.

[0091] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0092] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0093] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The system embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection of units or modules may be electrical or other forms.

[0094] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0095] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0096] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0097] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A data processing method, characterized in that, Applied to target processors, including: Receive data acquisition instructions sent by multiple pre-defined processors; In response to data acquisition instructions sent by the plurality of predetermined processors respectively, initial output data corresponding to the plurality of predetermined processors is acquired. The initial output data is the data obtained by the plurality of predetermined processors executing the target task respectively. The initial output data includes target information, target address and operation type. The operation type is used to identify whether a read operation or a write operation is performed on the target address. The target address is the current address of the target read data or the storage address of the target write data. The target information is the offset storage address of the target read data or the target write data. By comparing the initial output data corresponding to the plurality of predetermined processors respectively, a target comparison result is obtained; If the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors, a target operation is performed based on the target information, the target address, and the operation type in the target output data. The target output data is any one of the initial output data corresponding to the plurality of predetermined processors. The target operation includes: when the operation type is a write operation, writing the target information according to the target address; or when the operation type is a read operation, reading data according to the target address and distributing it to the plurality of predetermined processors.

2. The method according to claim 1, characterized in that, When the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors, the target operation is performed based on the target information, the target address, and the operation type in the target output data, including: When the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, based on the offset storage address, the current address, and the read operation, the operation of retrieving the target read data from the current address and storing the target read data to the plurality of target storage addresses is performed, wherein the plurality of target storage addresses are determined based on the offset storage address, and the target read data is the data read by the target processor from the target address.

3. The method according to claim 2, characterized in that, Before the step of retrieving the target read data from the current address and storing the target read data to multiple target storage addresses based on the offset storage address, the current address, and the read operation, in the case where the target comparison result is the same as the initial output data corresponding to the multiple predetermined processors, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, the step further includes: When the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors respectively, the target information is the offset storage address of the target read data, the target address is the current address of the target read data, and the operation type is a read operation, the base address corresponding to the plurality of predetermined processors is determined. Based on the offset storage address and the base address corresponding to each of the plurality of predetermined processors, the target storage address corresponding to each of the plurality of predetermined processors is determined.

4. The method according to claim 1, characterized in that, When the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors, the target operation is performed based on the target information, the target address, and the operation type in the target output data, including: When the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors respectively, the target information is target write data, the target address is the storage address of the target write data, and the operation type is a write operation, the operation of storing the target write data to the target address is performed based on the target write data, the storage address, and the write operation, wherein the target write data is the data read by the target processor from the target information in the target output data.

5. The method according to claim 1, characterized in that, In response to data acquisition instructions sent by the plurality of predetermined processors respectively, initial output data corresponding to the plurality of predetermined processors is acquired, including: In response to the data acquisition instructions sent by the plurality of predetermined processors respectively, a data copy instruction is sent to the direct memory access device (DMA), wherein the data copy instruction is used to cause the DMA to copy the initial output data corresponding to the plurality of predetermined processors to the DMA, and to send the initial output data corresponding to the plurality of predetermined processors to the target processor. Receive the initial output data sent by the DMA, which corresponds to the plurality of predetermined processors respectively.

6. The method according to claim 1, characterized in that, After comparing the initial output data corresponding to the plurality of predetermined processors to obtain the target comparison result, the method further includes: If the target comparison result is different from the initial output data corresponding to the plurality of predetermined processors, operation failure information is sent to the plurality of predetermined processors respectively.

7. The method according to any one of claims 1 to 6, characterized in that, After receiving data acquisition instructions sent by multiple predetermined processors, the method further includes: Determine a first number of predetermined processors to execute the target task, and determine a second number of received data acquisition instructions; If the first quantity is greater than the second quantity, a standby processor is determined, wherein the standby processor is the processor among the predetermined processors that has not sent a data acquisition instruction; A fault determination command is sent to the standby processor, wherein the fault determination command is used to determine whether the standby processor is faulty.

8. A data processing system, characterized in that, include: A target processor is configured to receive data acquisition instructions sent by a plurality of predetermined processors respectively; in response to the data acquisition instructions sent by the plurality of predetermined processors respectively, acquire initial output data corresponding to the plurality of predetermined processors respectively, wherein the initial output data is data obtained by the plurality of predetermined processors respectively executing target tasks, the initial output data includes target information, target address, and operation type, wherein the operation type is used to identify whether a read operation or a write operation is performed on the target address, the target address is the current address of the target read data or the storage address of the target write data, and the target information is the offset storage address of the target read data or the target write data; compare the initial output data corresponding to the plurality of predetermined processors respectively to obtain a target comparison result; if the target comparison result is the same as the initial output data corresponding to the plurality of predetermined processors respectively, perform a target operation according to the target information, the target address, and the operation type in the target output data, wherein the target output data is any one of the initial output data corresponding to the plurality of predetermined processors respectively, and the target operation includes: when the operation type is a write operation, writing the target information according to the target address; or when the operation type is a read operation, reading data according to the target address and distributing it to the plurality of predetermined processors; Multiple predetermined processors are configured to execute the target task respectively to obtain corresponding initial output data, and to send the data acquisition instructions to the target processor respectively.

9. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the data processing method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the data processing method as described in any one of claims 1 to 7.

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