Pixel circuits and their driving methods, display panels and display devices

Abstract

This disclosure provides a pixel circuit and its driving method. The pixel circuit includes: a first reset module coupled to a reset signal terminal, a first initial signal terminal, and a first node; a write data module coupled to a first scan signal terminal, a second scan signal terminal, a data signal terminal, a second node, a third node, and the first node; a first switch module coupled to a first control signal terminal, a first power supply terminal, and a second node; a second reset module coupled to a second control signal terminal, a second initial signal terminal, and a fourth node, wherein the second control signal terminal and the reset signal terminal are different signal terminals; a driving module coupled to the first node, the second node, and the third node; and a second switch module coupled to a third control signal terminal, the third node, and the fourth node, wherein the third control signal terminal and the first control signal terminal are different signal terminals. The technical solution of this disclosure can prevent users from perceiving flickering, thus improving the visual experience.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit and its driving method, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a display and lighting technology that has gradually developed in recent years. Especially in the display industry, OLED displays are considered to have broad application prospects due to their advantages such as high response, high contrast and flexibility.

[0003] In existing technologies, OLED display products suffer from flickering issues, which reduces the visual experience. Summary of the Invention

[0004] This disclosure provides a pixel circuit and its driving method, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the present disclosure, the present disclosure provides a pixel circuit, including:

[0006] The first reset module, coupled to the reset signal terminal, the first initial signal terminal and the first node, is configured to provide the signal of the first initial signal terminal to the first node under the signal control of the reset signal terminal;

[0007] The write data module is coupled to the first scan signal terminal, the second scan signal terminal, the data signal terminal, the second node, the third node, and the first node. It is configured to provide signals from the data signal terminal to the first node through the second node and the third node under the signal control of the first scan signal terminal and the second scan signal terminal.

[0008] The storage module is coupled to a first power supply terminal and a first node at its two ends, respectively, and is configured to store the signals of the first node.

[0009] The first switch module is coupled to the first control signal terminal, the first power supply terminal, and the second node, and is configured to provide the signal from the first power supply terminal to the second node under the signal control of the first control signal terminal.

[0010] The second reset module is coupled to the second control signal terminal, the second initial signal terminal and the fourth node, and is configured to provide the signal of the second initial signal terminal to the fourth node under the signal control of the second control signal terminal. The second control signal terminal and the reset signal terminal are different signal terminals.

[0011] The drive module, coupled to the first node, the second node and the third node, is configured to provide drive electrical signals to the third node based on the signals of the second node under the signal control of the first node;

[0012] The second switch module is coupled to the third control signal terminal, the third node, and the fourth node. It is configured to provide the third node with a driving electrical signal to the fourth node under the signal control of the third control signal terminal to drive the light-emitting module to emit light. The third control signal terminal is a different signal terminal from the first control signal terminal.

[0013] In one embodiment, a third switch module is further included. The third switch module is coupled to a fourth control signal terminal, a first power supply terminal, and a third node, and is configured to provide a signal from the first power supply terminal to the third node under the signal control of the fourth control signal terminal.

[0014] In one embodiment, the third switching module includes an eighth transistor, the gate of which is coupled to a fourth control signal terminal, and the first and second terminals of the eighth transistor are coupled to a first power supply terminal and a third node, respectively.

[0015] In one embodiment, the signals of the second control signal terminal and the fourth control signal terminal are the same.

[0016] In one embodiment, the pixel circuit satisfies at least one of the following:

[0017] The first reset module includes a first transistor, the gate of the first transistor is coupled to a reset signal terminal, and the first terminal and the second terminal of the first transistor are coupled to a first initial signal terminal and a first node, respectively.

[0018] The data writing module includes a second transistor and a fourth transistor. The gate of the second transistor is coupled to the second scan signal terminal, and the first and second terminals of the second transistor are coupled to the third node and the first node, respectively. The gate of the fourth transistor is coupled to the first scan signal terminal, and the first and second terminals of the fourth transistor are coupled to the data signal terminal and the second node, respectively.

[0019] The first switching module includes a fifth transistor, the gate of which is coupled to a first control signal terminal, and the first and second terminals of the fifth transistor are coupled to a first power supply terminal and a second node, respectively.

[0020] The second reset module includes a seventh transistor, the gate of which is coupled to a second control signal terminal, and the first and second terminals of the seventh transistor are coupled to a second initial signal terminal and a fourth node, respectively.

[0021] The driving module includes a third transistor, the gate of which is coupled to the first node, and the first and second terminals of the third transistor are coupled to the second and third nodes, respectively.

[0022] The second switching module includes a sixth transistor, the gate of which is coupled to a third control signal terminal, and the first and second terminals of the sixth transistor are coupled to a third node and a fourth node, respectively.

[0023] In one embodiment, the active layer of the first transistor is made of oxide semiconductor; and / or, the active layer of the second transistor is made of oxide semiconductor.

[0024] As a second aspect of the present disclosure, the present disclosure provides a driving method for a pixel circuit, applied to the pixel circuit in any embodiment of the present disclosure. The working stages of the pixel circuit include a refresh frame stage and a hold frame stage. The refresh frame stage includes a first conduction bias sub-stage and a first light-emitting sub-stage. The hold frame stage includes a second conduction bias sub-stage and a second light-emitting sub-stage. The driving method includes:

[0025] During the first conduction bias sub-stage and the second conduction bias sub-stage, an effective level signal is provided to the first control signal terminal to provide the first power supply terminal signal to the second node;

[0026] In the first and second photonic stages, an effective level signal is provided to the first control signal terminal and an effective level signal is provided to the third control signal terminal, so that under the control of the first node, a driving electrical signal is provided to the fourth node based on the signal of the first power supply terminal.

[0027] In one embodiment, the pixel circuit further includes a third switching module.

[0028] During the first and second conduction bias stages, an effective level signal is provided to the fourth control signal terminal, so that the third switch module provides the first power supply signal to the third node in the pixel circuit under the signal control of the fourth control signal terminal.

[0029] In one embodiment, the refresh frame phase further includes a third conduction bias sub-phase, a reset sub-phase, and a write data sub-phase, wherein the first conduction bias sub-phase is located after the write data sub-phase, and the method further includes:

[0030] In the third conduction bias sub-stage, an effective level signal is provided to the first control signal terminal and an effective level signal is provided to the fourth control signal terminal to provide the first power supply terminal signal to the second node and the first power supply terminal signal to the third node;

[0031] During the reset sub-phase, an effective level signal is provided to the reset signal terminal to provide the signal of the first initial signal terminal to the first node;

[0032] During the data writing sub-stage, a valid level signal is provided to the first scan signal terminal and a valid level signal is provided to the second scan signal terminal, so as to provide the data signal terminal signal to the first node through the second node and the third node;

[0033] During the third conduction bias sub-stage, the reset sub-stage, or the first conduction bias sub-stage, an effective level signal is provided to the second control signal terminal to provide the signal of the second initial signal terminal to the fourth node.

[0034] In one embodiment, the signals of the second control signal terminal and the fourth control signal terminal are the same. During the third conduction bias sub-stage and the first conduction bias sub-stage, an effective level signal is provided to the second control signal terminal to provide the signal of the second initial signal terminal to the fourth node.

[0035] As a third aspect of the present disclosure, the present disclosure provides a display panel including the pixel circuitry in any embodiment of the present disclosure.

[0036] As a fourth aspect of the present disclosure, the present disclosure provides a display device, including the display panel described in the present disclosure.

[0037] The pixel circuit and driving method of the present disclosure embodiment sets a first conduction bias sub-stage before the first light-emitting sub-stage and a second conduction bias sub-stage before the second light-emitting sub-stage. In the first and second conduction bias sub-stages, an effective level signal is provided to the first control signal terminal to provide a signal from the first power supply terminal to the second node. This realizes the reset of the potential of the second node to the signal from the first power supply terminal before the first and second light-emitting sub-stages, so that the potential of the second node is the same at the beginning of the first and second light-emitting sub-stages. This reduces the difference between the brightness waveform of the light-emitting module in the second and first light-emitting sub-stages and the brightness waveform in the first light-emitting sub-stage, making the brightness waveform of the light-emitting module in the second and first light-emitting sub-stages similar to that in the first light-emitting sub-stage, avoiding the user's perception of flicker and improving the visual experience.

[0038] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0039] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0040] Figure 1 This is a schematic diagram of a pixel circuit in one embodiment of the present disclosure;

[0041] Figure 2 This is a schematic diagram of a 7T1C pixel circuit in related technologies;

[0042] Figure 3 This is a schematic diagram of a pixel circuit in another embodiment of the present disclosure;

[0043] Figure 4 This is a schematic diagram of a pixel circuit in another embodiment of the present disclosure;

[0044] Figure 5 for Figure 4 The driving timing diagram of the pixel circuit is shown. Detailed Implementation

[0045] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0046] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in these embodiments are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In these embodiments, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the gate (also called the gate electrode), the signal input terminal as the source, and the signal output terminal as the drain. The switching transistors used in these embodiments can be P-type or N-type switching transistors. P-type switching transistors conduct when the gate is low and are cut off when the gate is high; N-type transistors conduct when the gate is high and are cut off when the gate is low. Furthermore, multiple signals in each embodiment of this invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal and do not imply that the first potential or the second potential has a specific numerical value throughout the text. In this embodiment of the invention, the first potential is used as an example for illustration.

[0047] The coupling can include direct physical contact between the two ends or indirect connection between the two ends (such as establishing a connection between the two ends through a signal line). This embodiment of the invention does not limit the coupling method between the two ends.

[0048] Figure 1 This is a schematic diagram of a pixel circuit according to one embodiment of the present disclosure. In one embodiment, such as Figure 1 As shown, the pixel circuit includes a first reset module 10, a write data module 20, a storage module 30, a first switch module 40, a second reset module 50, a drive module 60, and a second switch module 70.

[0049] The first reset module 10 is coupled to the reset signal terminal Reset, the first initial signal terminal Init1, and the first node N1, and is configured to provide the first initial signal terminal Init1 to the first node N1 under the signal control of the reset signal terminal Reset.

[0050] The write data module 20 is coupled to the first scan signal terminal Scan1, the second scan signal terminal Scan2, the data signal terminal Data, the second node N2, the third node N3, and the first node N1. It is configured to provide the data signal terminal Data to the first node N1 through the second node N2 and the third node N3 under the signal control of the first scan signal terminal Scan1 and the second scan signal terminal Scan2.

[0051] The two ends of the storage module 30 are coupled to the first power supply terminal VDD and the first node N1, respectively, and are configured to store the signals of the first node N1.

[0052] The first switch module 40 is coupled to the first control signal terminal EM1, the first power supply terminal VDD, and the second node N2, and is configured to provide the first power supply terminal VDD signal to the second node N2 under the signal control of the first control signal terminal EM1.

[0053] The second reset module 50 is coupled to the second control signal terminal EM2, the first initial signal terminal Init2, and the fourth node N4. It is configured to provide the signal from the first initial signal terminal Init2 to the fourth node N4 under the control of the signal from the second control signal terminal EM2. The second control signal terminal EM2 and the reset signal terminal Reset are different signal terminals. The signals provided by the second control signal terminal EM2 and the reset signal terminal Reset can be the same or different.

[0054] The drive module 60 is coupled to the first node N1, the second node N2 and the third node N3, and is configured to provide drive electrical signals to the third node N3 based on the signals of the second node N2 under the signal control of the first node N1.

[0055] The second switching module 70 is coupled to the third control signal terminal EM3, the third node N3, and the fourth node N4, and is configured to provide the driving electrical signal of the third node N3 to the fourth node N4 under the signal control of the third control signal terminal EM3 to drive the light-emitting module DL to emit light. The third control signal terminal EM3 is a different signal terminal from the first control signal terminal EM1. The signals provided by the third control signal terminal EM3 and the first control signal terminal EM1 may be different. One end of the light-emitting module DL (e.g., the anode) is coupled to the fourth node N4, and the other end of the light-emitting module DL (e.g., the cathode) is coupled to the second power supply terminal VSS.

[0056] Exemplarily, the light-emitting module DL includes at least one light-emitting device. In embodiments of the present invention, the light-emitting device may be a MicroLED or a MiniLED, but this application is not limited to these. The light-emitting device may also be other light-emitting devices whose display brightness is affected by both current and time, such as OLED and QLED. The light-emitting module DL may include multiple light-emitting devices connected in series, multiple light-emitting devices connected in parallel, or multiple light-emitting devices combined in series and parallel.

[0057] Figure 2 This is a schematic diagram of a 7T1C pixel circuit in related technologies. (For example...) Figure 2 In the pixel circuit of the 7T1C shown, the fifth transistor T5 and the sixth transistor T6 are coupled to the same control signal terminal EM0, and the fifth transistor T5 and the sixth transistor T6 operate in the same state. To ensure the operation of the pixel circuit, the fifth transistor T5 and the sixth transistor T6 are only turned on during the light-emitting sub-stage of the pixel circuit. For example, the pixel circuit includes a refresh frame stage and a hold frame stage. The refresh frame stage may include a reset sub-stage, a write data sub-stage, and a first light-emitting sub-stage, and the hold frame stage includes a second light-emitting sub-stage. During the first light-emitting sub-stage of the refresh frame stage, the fifth transistor T5 and the sixth transistor T6 are turned on simultaneously, driving the light-emitting module DL to emit light. During the second light-emitting sub-stage of the hold frame stage, the fifth transistor T5 and the sixth transistor T6 are turned on simultaneously, driving the light-emitting module DL to emit light. Since there is no reset or write data process during the hold frame stage, Figure 2 Before the second photoluminescent phase begins, the pixel circuit shown has residual grayscale voltages from the first photoluminescent phase at nodes N2, N3, and N4. This means that the potentials of nodes N2, N3, and N4 are different at the beginning of the first and second photoluminescent phases. Consequently, the brightness waveform of the light-emitting module DL in the second photoluminescent phase differs significantly from that in the first photoluminescent phase, causing flickering to be perceived by the user and reducing the visual experience.

[0058] In the pixel circuit of this embodiment, the second control signal terminal EM2 and the reset signal terminal Reset are different signal terminals, and the third control signal terminal EM3 and the first control signal terminal EM1 are different signal terminals. Therefore, the operating states of the second reset module 50 and the first reset module 10 can be controlled respectively, and the operating states of the first switch module 40 and the second switch module 70 can be controlled respectively. Thus, before the first light-emitting stage and before the second light-emitting stage, the first switch module 40 can be controlled to be turned on while the second switch module 70 is turned off, and the second reset module 50 can be controlled to be turned on while the first reset module 10 is turned off. This achieves the reset of the second node N2 and the fourth node N4 before the first light-emitting stage and before the second light-emitting stage, respectively. This ensures that the potential of the second node N2 and the fourth node N4 are the same at the beginning of the first and second light-emitting stages, thereby reducing the difference between the brightness waveform of the light-emitting module DL in the second light-emitting stage and the brightness waveform in the first light-emitting stage. This makes the brightness waveform of the light-emitting module DL in the second light-emitting stage similar to that in the first light-emitting stage, preventing users from perceiving flicker and improving the visual experience.

[0059] In one embodiment, the pixel circuit includes a refresh frame stage and a hold frame stage. The refresh frame stage includes a first light-emitting sub-stage, and the hold frame stage includes a second light-emitting sub-stage. A first switching module 40 is configured to provide a first power supply terminal VDD signal to a second node N2 under the signal control of a first control signal terminal EM1 before the first and second light-emitting sub-stages, thereby resetting the second node N2. A second reset module 50 is configured to provide a second initial signal terminal Init2 signal to a fourth node N4 under the signal control of the second control signal terminal EM2 before the first and second light-emitting sub-stages, thereby resetting the fourth node N4. This ensures that the potential of the second node N2 and the fourth node N4 are the same at the beginning of the first and second light-emitting sub-stages, making the brightness waveform of the light-emitting module DL in the second light-emitting sub-stage similar to that in the first light-emitting sub-stage, preventing users from perceiving flicker and improving the visual experience.

[0060] Figure 3 This is a schematic diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, as shown... Figure 3 As shown, the pixel circuit may further include a third switch module 80, which is coupled to the fourth control signal terminal EM4, the first power supply terminal VDD and the third node N3, and is configured to provide the first power supply terminal VDD signal to the third node N3 under the signal control of the fourth control signal terminal EM4.

[0061] By setting the third switch module 80, the third switch module 80 can be turned on before the first light-emitting sub-stage and before the second light-emitting sub-stage, thereby resetting the third node N3. This ensures that the potential of the third node N3 is the same when the light-emitting module DL starts at the beginning of the first light-emitting sub-stage and the beginning of the second light-emitting sub-stage. This further reduces the difference between the brightness waveform of the light-emitting module DL in the second light-emitting sub-stage and the brightness waveform in the first light-emitting sub-stage, making the brightness waveform of the light-emitting module DL in the second light-emitting sub-stage more similar to the brightness waveform in the first light-emitting sub-stage. Users will not perceive flickering, thus improving the visual experience.

[0062] For example, the third switch module 80 is configured to provide a signal of the first power supply terminal VDD to the third node N3 under the signal control of the fourth control signal terminal EM4 before the first light-emitting stage and before the second light-emitting stage, thereby resetting the third node N3.

[0063] In one embodiment, the signals of the second control signal terminal EM2 and the fourth control signal terminal EM4 are the same. This allows a single signal line to simultaneously provide the same signal to both the second control signal terminal EM2 and the fourth control signal terminal EM4, reducing the number of signal lines and facilitating wiring.

[0064] Figure 4 This is a schematic diagram of a pixel circuit according to another embodiment of this disclosure. Figure 4 As shown, the third switch module 80 may include an eighth transistor T8, the gate of the eighth transistor T8 is coupled to the fourth control signal terminal EM4, and the first and second terminals of the eighth transistor T8 are coupled to the first power supply terminal VDD and the third node N3, respectively.

[0065] The first reset module 10 includes a first transistor T1, the gate of the first transistor T1 is coupled to the reset signal terminal Reset, and the first terminal and the second terminal of the first transistor T1 are coupled to the first initial signal terminal Init1 and the first node N1, respectively.

[0066] The data writing module 20 includes a second transistor T2 and a fourth transistor T4. The gate of the second transistor T2 is coupled to the second scan signal terminal Scan2, and the first and second terminals of the second transistor T2 are coupled to the third node N3 and the first node N1, respectively. The gate of the fourth transistor T4 is coupled to the first scan signal terminal Scan1, and the first and second terminals of the fourth transistor T4 are coupled to the data signal terminal Data and the second node N2, respectively.

[0067] The first switching module 40 includes a fifth transistor T5. The gate of the fifth transistor T5 is coupled to the first control signal terminal EM1. The first terminal and the second terminal of the fifth transistor T5 are coupled to the first power supply terminal VDD and the second node N2, respectively.

[0068] The second reset module 50 includes a seventh transistor T7, the gate of which is coupled to the second control signal terminal EM2, and the first and second terminals of the seventh transistor T7 are coupled to the first initial signal terminal Init2 and the fourth node N4, respectively.

[0069] The driving module 60 includes a third transistor T3, the gate of which is coupled to the first node N1, and the first and second terminals of which are coupled to the second node N2 and the third node N3, respectively.

[0070] The second switching module 70 includes a sixth transistor T6, the gate of which is coupled to the third control signal terminal EM3, and the first and second terminals of the sixth transistor T6 are coupled to the third node N3 and the fourth node N4, respectively.

[0071] The storage module 30 may include a storage capacitor, one end of which is coupled to the first power supply terminal VDD and the other end of which is coupled to the first node N1.

[0072] For example, the first transistor T1 can be an N-type transistor. The active layer of the first transistor T1 can be made of oxide semiconductor. The second transistor T2 can be an N-type transistor. The active layer of the second transistor T2 can be made of oxide semiconductor.

[0073] from Figure 4 As can be seen, both the first transistor T1 and the second transistor T2 are coupled to the storage capacitor. The active layer of the first transistor T1 can be made of oxide semiconductor, and the active layer of the second transistor T2 can also be made of oxide semiconductor. This results in smaller leakage current for the first transistor T1 and the second transistor T2, which allows the charge of the storage capacitor to be retained for a longer time (about one second). This is beneficial for realizing low-frequency driving of the pixel circuit (e.g., 1Hz driving) and greatly reduces the driving power of the pixel circuit.

[0074] For example, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be P-type transistors. The active layer of the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be made of low-temperature polycrystalline silicon (LTPS).

[0075] This pixel circuit uses LTPO (Low Temperature Polycrystalline Oxide) technology, which makes the leakage current of the pixel circuit smaller and enables low-frequency driving of the pixel circuit (e.g., 1Hz driving), greatly reducing the driving power of the pixel circuit.

[0076] It should be noted that, Figure 4The diagram illustrates exemplary structures of the first reset module 10, the write data module 20, the storage module 30, the first switch module 40, the second reset module 50, the drive module 60, the second switch module 70, and the third switch module 80. Those skilled in the art will understand that these modules are not limited to... Figure 4 The structure shown is acceptable as long as it can fulfill its function.

[0077] It should be noted that, Figure 4 The diagram shows the types of transistors, and those skilled in the art will understand that the transistors are not limited to those shown. Figure 4 The types shown can be either P-type or N-type transistors, as long as their gate signals match their types to achieve the function of the corresponding module.

[0078] This disclosure also provides a driving method for a pixel circuit, applicable to the pixel circuit in any embodiment of this disclosure. The operating phases of the pixel circuit may include a refresh frame phase and a skip frame phase.

[0079] The refresh frame phase includes a first conduction bias sub-phase and a first light-emitting sub-phase, while the hold frame phase includes a second conduction bias sub-phase and a second light-emitting sub-phase.

[0080] During the first conduction bias sub-stage and the second conduction bias sub-stage, an effective level signal is provided to the first control signal terminal EM1 to provide the first power supply terminal VDD signal to the second node N2.

[0081] In the first and second light-emitting phases, an effective level signal is provided to the first control signal terminal EM1 and an effective level signal is provided to the third control signal terminal EM3, so that under the control of the first node N1, a driving electrical signal is provided to the fourth node N4 based on the signal of the first power supply terminal VDD to drive the light-emitting module DL to emit light.

[0082] For example, the first conduction bias sub-stage is located before the first photoluminescence stage, and the second conduction bias sub-stage is located before the second photoluminescence stage.

[0083] The pixel circuit driving method of this disclosure sets a first conduction bias sub-stage before the first light-emitting sub-stage and a second conduction bias sub-stage before the second light-emitting sub-stage. During both the first and second conduction bias sub-stages, an effective level signal is provided to the first control signal terminal EM1 to provide the first power supply terminal VDD signal to the second node N2. This resets the potential of the second node N2 to the first power supply terminal VDD signal before the first and second light-emitting sub-stages, ensuring that the potential of the second node N2 is the same at the beginning of the first and second light-emitting sub-stages. This reduces the difference between the brightness waveform of the light-emitting module DL in the second and first light-emitting sub-stages and makes the brightness waveform of the light-emitting module DL in the second and first light-emitting sub-stages similar, preventing users from perceiving flicker and improving the visual experience.

[0084] In one embodiment, the pixel circuit further includes a third switching module 80. During the first and second conduction bias sub-stages, a valid level signal is provided to the fourth control signal terminal EM4, causing the third switching module 80 to provide the first power supply terminal VDD signal to the third node N3 in the pixel circuit under the signal control of the fourth control signal terminal EM4. This method resets the potential of the third node N3 to the first power supply terminal VDD signal before the first and second light-emitting sub-stages, ensuring that the potential of the third node N3 is the same at the beginning of the first and second light-emitting sub-stages. This further reduces the difference between the brightness waveform of the light-emitting module DL in the second and first light-emitting sub-stages, making the brightness waveform of the light-emitting module DL in the second and first light-emitting sub-stages more similar, preventing users from perceiving flicker and improving the visual experience.

[0085] In one embodiment, the refresh frame phase further includes a third conduction bias sub-phase, a reset sub-phase, and a write data sub-phase, with the first conduction bias sub-phase following the write data sub-phase. Therefore, the refresh frame phase includes a third conduction bias sub-phase, a reset sub-phase, a write data sub-phase, a first conduction bias sub-phase, and a first light-emitting sub-phase.

[0086] During the third conduction bias sub-stage, an effective level signal is provided to the first control signal terminal EM1 and the fourth control signal terminal EM4 to provide the first power supply terminal VDD signal to the second node N2 and the third node N3.

[0087] During the reset phase, a valid level signal is provided to the Reset signal terminal to provide the first initial signal terminal Init1 to the first node N1.

[0088] During the data writing sub-stage, a valid level signal is provided to the first scan signal terminal Scan1 and the second scan signal terminal Scan2, so that the data signal terminal Data is provided to the first node N1 through the second node N2 and the third node N3. For example, the duration of providing a valid level signal to the second scan signal terminal Scan2 can be longer than the duration of providing a valid level signal to the first scan signal terminal Scan1, which is beneficial for the data signal to be fully written from the third node to the first node.

[0089] During the third conduction bias sub-stage, the reset sub-stage, or the first conduction bias sub-stage, an effective level signal is provided to the second control signal terminal EM2 to provide the first initial signal terminal Init2 signal to the fourth node N4.

[0090] In the pixel circuits of related technologies, such as Figure 2 As shown, before writing data to the first node, the second node N2 and the third node N3 retain the grayscale voltage from the previous frame, causing a data writing delay. In this embodiment, a third conduction bias sub-stage is set before the data writing sub-stage to provide the first power supply terminal VDD signal to the second node N2 and the third node N3. This ensures that the second node N2 and the third node N3 are reset to the first power supply terminal VDD signal before writing data to the first node N1, avoiding the data writing delay caused by the residual grayscale voltage of the second node N2 and the third node N3, and ensuring that the data signal is successfully written to the first node N1.

[0091] It should be noted that the third conduction bias sub-stage can be located before the reset sub-stage or between the reset sub-stage and the write data sub-stage, as long as the third conduction bias sub-stage is located before the write data sub-stage.

[0092] In one embodiment, the signals of the second control signal terminal EM2 and the fourth control signal terminal EM4 are identical. During the third conduction bias sub-stage and the first conduction bias sub-stage, a valid level signal is provided to the second control signal terminal EM2 to provide the first initial signal terminal Init2 signal to the fourth node N4. This not only achieves the reset of the fourth node N4 before the light-emitting module DL is lit, but also allows a single signal line to simultaneously provide signals to the second control signal terminal EM2 and the fourth control signal terminal EM4, reducing the number of signal lines.

[0093] Figure 5 for Figure 4 The driving timing diagram of the pixel circuit is shown below. (Followed by...) Figure 4 and Figure 5The working principle of the pixel circuit according to the embodiments of this disclosure is explained in detail. The driving method of the pixel circuit according to the embodiments of this disclosure can achieve a driving frequency of 1Hz.

[0094] like Figure 5 As shown, the pixel circuit's operating stages include a refresh frame stage and a skip frame stage. The refresh frame stage includes a third biased conduction sub-stage (On biased 3) S1, a reset sub-stage (Reset) S2, a data writing sub-stage (Compensation) S3, a first biased conduction sub-stage (On biased 1) S4, and a first emission sub-stage (Emission 1) S5. The skip frame stage includes a second biased conduction sub-stage (On biased 2) S7 and a second emission sub-stage (Emission 2) S8. The skip frame stage may also include a fourth biased conduction sub-stage (On biased 4) S6. Table 1 shows the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 in each sub-stage of the refresh frame stage, and Table 2 shows the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 in each sub-stage of the skip frame stage.

[0095] Table 1 shows the potential status of each node during the refresh frame phase.

[0096] node On biased 3 Reset Compensation On biased 1 Emission 1 N1 <![CDATA[V data +V th ]]> <![CDATA[V init1 ]]> <![CDATA[V data +V th ]]> <![CDATA[V data +V th ]]> <![CDATA[V data +V th <!-- 8 --> ]]> N2 <![CDATA[V dd ]]> floating <![CDATA[V data ]]> <![CDATA[V dd ]]> <![CDATA[V dd ]]> N3 <![CDATA[V dd ]]> floating <![CDATA[V data +V th ]]> <![CDATA[V dd ]]> Anode N4 <![CDATA[V init2 ]]> floating floating <![CDATA[V init2 ]]> Anode

[0097] Table 2 shows the potential states of each node during the frame-holding phase.

[0098] node On biased 4 On biased 2 Emission 2 N1 <![CDATA[V data +V th ]]> <![CDATA[V data +V th ]]> <![CDATA[V data +V th ]]> N2 <![CDATA[V dd ]]> <![CDATA[V dd ]]> <![CDATA[V dd ]]> N3 <![CDATA[V dd ]]> <![CDATA[V dd ]]> Anode N4 <![CDATA[V init2 ]]> <![CDATA[V init2 ]]> Anode

[0099] In the third conduction bias sub-stage S1, an effective level signal is provided to the first control signal terminal EM1, the fourth control signal terminal EM4, and the second control signal terminal EM2. Under the control of the effective level signal of the first control signal terminal EM1, the fifth transistor T5 provides the signal V of the first power supply terminal VDD to the second node N2. dd This resets the second node N2, and the signal for the second node N2 is V. dd Under the control of the effective level signal of the fourth control signal terminal EM4, the eighth transistor T8 provides the signal VDD of the first power supply terminal to the third node N3. dd To reset the third node N3, the signal of the third node N3 is V. dd The seventh transistor T7, under the control of the effective level signal of the second control signal terminal EM2, provides the signal V of the first initial signal terminal Init2 to the fourth node N4. init2This resets the fourth node N4, whose signal is V. init2 The potential of the first node N1 remains the same as the voltage V of the previous photon phase. data +V th .

[0100] During the reset sub-stage S2, a valid level signal is provided to the reset signal terminal Reset. Under the control of the valid level signal at the reset signal terminal Reset, the first transistor T1 provides the first initial signal V at the first initial signal terminal Init1 to the first node N1. init1 This achieves the reset of the first node N1.

[0101] During the data writing sub-stage S3, a valid level signal is provided to the first scan signal terminal Scan1 and the second scan signal terminal Scan2. Under the control of the valid level signal at the first scan signal terminal Scan1, the fourth transistor T4 provides the data signal V at the data signal terminal Data to the second node N2. data The third transistor T3 receives the first initial signal V at the first node N1. init1 Under the control of the third node N3, the data signal V of the second node N2 is provided to the third node N3. data The second transistor T2, under the control of the effective level signal of the second scan signal terminal Scan2, provides the data signal V of the third node N3 to the first node N1. data , will the data signal V data Write to the first node N1 so that the voltage of the first node N1 is V. data +V th .

[0102] In the first conduction bias sub-stage S4, an effective level signal is provided to the first control signal terminal EM1, the second control signal terminal EM2, and the fourth signal control terminal. Under the control of the effective level signal of the first control signal terminal EM1, the fifth transistor T5 provides the signal V of the first power supply terminal VDD to the second node N2. dd This resets the second node N2, and the signal for the second node N2 is V. dd Under the control of the effective level signal of the fourth control signal terminal EM4, the eighth transistor T8 provides the signal VDD of the first power supply terminal to the third node N3. dd To reset the third node N3, the signal of the third node N3 is V. dd The seventh transistor T7, under the control of the effective level signal of the second control signal terminal EM2, provides the signal V of the first initial signal terminal Init2 to the fourth node N4. init2 This resets the fourth node N4, whose signal is V. init2The potential of the first node N1 remains the same as the voltage V of the previous photon phase. data +V th .

[0103] In the first photonic stage S5, an effective level signal is provided to the first control signal terminal EM1 and the third control signal terminal EM3. Under the control of the effective level signal of the first control signal terminal EM1, the fifth transistor T5 provides the signal VDD of the first power supply terminal to the second node N2. dd The third transistor T3 receives the data signal V at the first node N1. data +V th Under control, a driving electrical signal is provided to the third node N3; the sixth transistor T6 is turned on under the control of the effective level signal of the third control signal terminal EM3, so that the third node N3 is coupled to the anode of the light-emitting module DL to drive the light-emitting module DL to emit light.

[0104] During the fourth conduction bias sub-stage S6 and the second conduction bias sub-stage S7, an effective level signal is provided to the first control signal terminal EM1, an effective level signal is provided to the second control signal terminal EM2, and an effective level signal is provided to the fourth signal control terminal. Under the control of the effective level signal of the first control signal terminal EM1, the fifth transistor T5 provides the signal VDD of the first power supply terminal to the second node N2. dd This resets the second node N2, and the signal for the second node N2 is V. dd Under the control of the effective level signal of the fourth control signal terminal EM4, the eighth transistor T8 provides the signal VDD of the first power supply terminal to the third node N3. dd To reset the third node N3, the signal of the third node N3 is V. dd The seventh transistor T7, under the control of the effective level signal of the second control signal terminal EM2, provides the signal V of the first initial signal terminal Init2 to the fourth node N4. init2 This resets the fourth node N4, whose signal is V. init2 The potential of the first node N1 remains the same as the voltage V of the previous photon phase. data +V th .

[0105] In the second photonic stage S8, an effective level signal is provided to the first control signal terminal EM1 and the third control signal terminal EM3. Under the control of the effective level signal of the first control signal terminal EM1, the fifth transistor T5 provides the signal VDD of the first power supply terminal to the second node N2. dd The third transistor T3 receives the data signal V at the first node N1. data +V thUnder control, a driving electrical signal is provided to the third node N3; the sixth transistor T6 is turned on under the control of the effective level signal of the third control signal terminal EM3, so that the third node N3 is coupled to the anode of the light-emitting module DL to drive the light-emitting module DL to emit light.

[0106] The pixel circuit and driving method of this disclosure reset the second node N2 and the third node N3 before writing data signals to the first node N1. This avoids data writing lag caused by residual grayscale voltage in the second node N2 and the third node N3, ensuring that data signals are smoothly written to the first node N1. Before the first light-emitting sub-stage and before the second light-emitting sub-stage, the second node N2, the third node N3, and the fourth node N4 are reset. This ensures that the signals of the second node N2, the third node N3, and the fourth node N4 are the same at the beginning of the first and second light-emitting sub-stages. This reduces the difference between the brightness waveform of the light-emitting module DL in the second light-emitting sub-stage and the brightness waveform in the first light-emitting sub-stage, making the brightness waveform of the light-emitting module DL in the second light-emitting sub-stage similar to that in the first light-emitting sub-stage. This prevents users from perceiving flicker and improves the visual experience.

[0107] This disclosure also provides a display panel, including the pixel circuitry found in any embodiment of this disclosure.

[0108] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display device, which includes the display panel of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0109] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0110] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0111] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0112] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0113] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0114] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized in that, include: A first reset module, coupled to a reset signal terminal, a first initial signal terminal, and a first node, is configured to provide the signal from the first initial signal terminal to the first node under the signal control of the reset signal terminal. The write data module is coupled to the first scan signal terminal, the second scan signal terminal, the data signal terminal, the second node, the third node, and the first node, and is configured to provide the data signal terminal to the first node through the second node and the third node under the signal control of the first scan signal terminal and the second scan signal terminal. A storage module, the two ends of which are coupled to a first power supply and the first node respectively, and is configured to store the signal of the first node; A first switching module, coupled to a first control signal terminal, a first power supply terminal, and a second node, is configured to provide the signal from the first power supply terminal to the second node under the signal control of the first control signal terminal. The second reset module is coupled to the second control signal terminal, the second initial signal terminal and the fourth node, and is configured to provide the signal of the second initial signal terminal to the fourth node under the signal control of the second control signal terminal. The second control signal terminal and the reset signal terminal are different signal terminals. A drive module, coupled to the first node, the second node and the third node, is configured to provide a drive electrical signal to the third node based on the signal of the second node under the signal control of the first node; The second switch module is coupled to the third control signal terminal, the third node, and the fourth node. It is configured to provide the driving electrical signal of the third node to the fourth node under the signal control of the third control signal terminal to drive the light-emitting module to emit light. The third control signal terminal is a different signal terminal from the first control signal terminal. The operation phase of the pixel circuit includes a refresh frame phase and a hold frame phase. The refresh frame phase includes a first conduction bias sub-phase and a first light-emitting sub-phase. The hold frame phase includes a second conduction bias sub-phase and a second light-emitting sub-phase. The first switching module is further configured to: in the first conduction bias sub-stage and the second conduction bias sub-stage, in response to the effective level signal provided by the first control signal terminal, provide the first power supply terminal signal to the second node, so that the potential of the second node is substantially the same at the beginning of the first light-emitting sub-stage and at the beginning of the second light-emitting sub-stage.

2. The pixel circuit according to claim 1, characterized in that, It also includes a third switch module, which is coupled to a fourth control signal terminal, a first power supply terminal and a third node, and is configured to provide the first power supply terminal signal to the third node under the signal control of the fourth control signal terminal.

3. The pixel circuit according to claim 2, characterized in that, The third switching module includes an eighth transistor, the gate of which is coupled to the fourth control signal terminal, and the first and second terminals of the eighth transistor are coupled to the first power supply terminal and the third node, respectively.

4. The pixel circuit according to claim 2, characterized in that, The second control signal terminal has the same signal as the fourth control signal terminal.

5. The pixel circuit according to claim 1, characterized in that, Meet at least one of the following: The first reset module includes a first transistor, the gate of the first transistor is coupled to the reset signal terminal, and the first terminal and the second terminal of the first transistor are coupled to the first initial signal terminal and the first node, respectively. The write data module includes a second transistor and a fourth transistor. The gate of the second transistor is coupled to the second scan signal terminal. The first and second terminals of the second transistor are coupled to the third node and the first node, respectively. The gate of the fourth transistor is coupled to the first scan signal terminal. The first and second terminals of the fourth transistor are coupled to the data signal terminal and the second node, respectively. The first switching module includes a fifth transistor, the gate of which is coupled to the first control signal terminal, and the first and second terminals of which are coupled to the first power supply terminal and the second node, respectively. The second reset module includes a seventh transistor, the gate of which is coupled to the second control signal terminal, and the first and second terminals of which are coupled to the second initial signal terminal and the fourth node, respectively. The driving module includes a third transistor, the gate of which is coupled to the first node, and the first and second terminals of which are coupled to the second node and the third node, respectively. The second switching module includes a sixth transistor, the gate of which is coupled to the third control signal terminal, and the first and second terminals of which are coupled to the third node and the fourth node, respectively.

6. The pixel circuit according to claim 5, characterized in that, The active layer of the first transistor is made of oxide semiconductor; and / or, the active layer of the second transistor is made of oxide semiconductor.

7. A driving method for a pixel circuit, characterized in that, A pixel circuit applied to any one of claims 1-6, wherein the operating phase of the pixel circuit includes a refresh frame phase and a hold frame phase, the refresh frame phase includes a first conduction bias sub-phase and a first light-emitting sub-phase, the hold frame phase includes a second conduction bias sub-phase and a second light-emitting sub-phase, and the driving method includes: During the first conduction bias sub-stage and the second conduction bias sub-stage, an effective level signal is provided to the first control signal terminal to provide the first power supply terminal signal to the second node; During the first and second light-emitting phases, an effective level signal is provided to the first control signal terminal and an effective level signal is provided to the third control signal terminal, so that under the control of the first node, a driving electrical signal is provided to the fourth node based on the signal from the first power supply terminal.

8. The method according to claim 7, characterized in that, The pixel circuit also includes a third switching module. During the first conduction bias sub-stage and the second conduction bias sub-stage, an effective level signal is provided to the fourth control signal terminal, so that the third switch module provides the signal from the first power supply terminal to the third node in the pixel circuit under the signal control of the fourth control signal terminal.

9. The method according to claim 8, characterized in that, The refresh frame stage further includes a third conduction bias sub-stage, a reset sub-stage, and a write data sub-stage, wherein the first conduction bias sub-stage is located after the write data sub-stage, and the method further includes: In the third conduction bias sub-stage, an effective level signal is provided to the first control signal terminal and an effective level signal is provided to the fourth control signal terminal to provide the signal from the first power supply terminal to the second node and the signal from the first power supply terminal to the third node; During the reset sub-phase, a valid level signal is provided to the reset signal terminal to provide the signal from the first initial signal terminal to the first node; During the data writing sub-stage, a valid level signal is provided to the first scan signal terminal and a valid level signal is provided to the second scan signal terminal, so as to provide the signal of the data signal terminal to the first node through the second node and the third node; During the third conduction bias sub-stage, the reset sub-stage, or the first conduction bias sub-stage, a valid level signal is provided to the second control signal terminal to provide the signal of the second initial signal terminal to the fourth node.

10. The method according to claim 9, characterized in that, The second control signal terminal and the fourth control signal terminal have the same signal. During the third conduction bias sub-stage and the first conduction bias sub-stage, an effective level signal is provided to the second control signal terminal to provide the signal of the second initial signal terminal to the fourth node.

11. A display panel, characterized in that, Includes the pixel circuit according to any one of claims 1-6.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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