Self-aligned patterning method for two-dimensional semiconductor transistors and two-dimensional semiconductor transistors

Abstract

This invention provides a self-aligned patterning method for two-dimensional semiconductor transistors and a two-dimensional semiconductor transistor. The method includes the following steps: providing a substrate; forming a semiconductor material layer on the substrate; forming a gate structure on the semiconductor material layer; forming pseudo-gate sidewalls surrounding the sidewalls of the gate structure; performing surface modification treatment on the surface of the two-dimensional semiconductor material layer to form a solid active source metal layer on the surface of the two-dimensional semiconductor material; forming a conventional metal layer on the solid active source metal layer and performing annealing treatment to obtain a two-dimensional half-metal / metal material layer; photolithographically lithographically forming the solid active source metal layer and the conventional metal layer, and self-aligning to form source / drain contact regions, the source / drain contact regions including the solid active source metal layer, the conventional metal layer, and the two-dimensional half-metal / metal material layer. This method can reduce contact resistance, reduce device area, improve integration and performance, and realize source / drain self-alignment process for two-dimensional semiconductor material devices.

Description

Technical Field

[0001] This invention specifically relates to a self-aligned patterning method for two-dimensional semiconductor transistors and a two-dimensional semiconductor transistor, belonging to the field of two-dimensional semiconductor technology. Background Technology

[0002] Silicon-based technology is nearing the physical limits of Moore's Law. The rate at which integrated circuit transistors shrink proportionally continues to decline, and its gains are increasingly limited by process costs and yield rates. Furthermore, the increased integration density and current density of silicon-based integrated circuits lead to a rapid increase in power consumption per unit area, exacerbating the "power wall" problem caused by scattering. These issues are becoming increasingly acute at sub-10nm advanced nodes. Two-dimensional semiconductor materials, due to their atomically thin profile, can extend Moore's Law and are expected to break the "power wall," further improving performance and reducing power consumption. Since stacked transistors in 3D integrated chips can alleviate memory bandwidth issues or the "memory wall," the industry believes that the future of half-Moore's Law will be driven by 3D integrated chips, which may also fundamentally change design and wiring methods. Two-dimensional semiconductors may be a key solution for creating such 3D integrated chips because they can be easily grown at low temperatures while maintaining intact electrical properties; however, high-resistance contacts have always been an obstacle to the adoption of two-dimensional semiconductors.

[0003] Due to the Fermi pinning effect, metal-semiconductor interfaces often exhibit high Schottky barrier heights, resulting in excessively high contact resistance and significantly impacting the performance of advanced small-channel node devices. Silicon-based devices typically employ source / drain doping to create metal silicides to reduce contact resistance. However, for two-dimensional semiconductors, there is currently no strategy compatible with semiconductor fabrication processes to achieve controllable source / drain doping, making contact issues a core challenge in the field.

[0004] Doping in two-dimensional semiconductor materials is often introduced during the growth process, making it impossible to control the doped region. Methods such as sampling solutions or molecular interface adsorption of dopants are prone to desorption and instability. Currently, there is a lack of doping contact processes compatible with integrated circuit fabrication for two-dimensional semiconductor materials. The source-drain metal silicide processes used in silicon-based CMOS technology have not yet been widely adopted for two-dimensional semiconductor materials. Current fabrication processes for two-dimensional semiconductors are based on metal lift-off processes, which are unsuitable for large-scale digital integrated circuit processes. To reduce device area and improve integration density and performance, it is necessary to develop source-drain self-alignment processes for two-dimensional semiconductor devices.

[0005] Therefore, reducing contact resistance and realizing source-drain self-alignment technology for two-dimensional semiconductor devices are technical problems that urgently need to be solved. Summary of the Invention

[0006] The purpose of this invention is to reduce the contact resistance of the source and drain regions of two-dimensional semiconductor transistors and realize the source and drain self-alignment process of two-dimensional semiconductor transistors, so as to broaden the application of two-dimensional semiconductor transistors and improve integration and performance.

[0007] To achieve the above objectives, the present invention adopts the following technical solution.

[0008] A self-aligned patterning method for a two-dimensional semiconductor transistor includes the following steps: providing a substrate; forming a semiconductor material layer on the substrate; forming a gate structure on the semiconductor material layer; forming pseudo-gate sidewalls surrounding the sidewalls of the gate structure; fabricating a two-dimensional semiconductor material layer on the substrate; performing surface modification treatment on the surface of the two-dimensional semiconductor material layer not covered by the gate structure and sidewalls; depositing a solid active source metal layer on the surface of the two-dimensional semiconductor material layer away from the substrate; depositing a conventional metal layer on the solid active source metal layer; annealing the solid active source metal layer and the conventional metal layer to obtain a two-dimensional half-metal / metal material layer; photolithographically forming the solid active source metal layer and the conventional metal layer to self-align and form a source / drain contact region, wherein the source / drain contact region includes the solid active source metal layer, the conventional metal layer, and the two-dimensional half-metal / metal material layer.

[0009] The surface modification process includes bombarding the surface of the two-dimensional semiconductor material layer that is not covered by the gate structure and sidewalls with ultra-low power soft plasma.

[0010] The annealing process employs a rapid annealing method, annealing at 250°C to 600°C for 2-60 seconds.

[0011] The process of photolithography of the solid-state active source metal layer and the conventional metal layer includes using photoresist as a mask and opening windows to define the overall size of the source / drain contact area and the gate structure.

[0012] The two-dimensional semiconductor material layer includes any one or a combination of indium selenide (InSe), molybdenum disulfide (MoS2), indium diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum telluride (MoTe2), black phosphorus (BP), silene, germanene, tellurene, and ionic layered semiconductor materials (Bi2O2X, X = S or Se).

[0013] The solid active source metal layer includes any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), and rhenium (Re).

[0014] The present invention also provides a two-dimensional semiconductor transistor, comprising: a substrate; a two-dimensional semiconductor material layer disposed on the substrate; a two-dimensional semi-metal / metal material layer disposed on a surface of the two-dimensional semiconductor material layer away from the substrate; a solid-state source active metal layer disposed on a surface of the two-dimensional semi-metal material layer away from the two-dimensional semiconductor material layer; a conventional metal layer disposed on a surface of the solid-state source active metal layer away from the two-dimensional semi-metal / metal material layer; a gate structure penetrating the solid-state source metal layer and the conventional metal layer, disposed on a surface of the two-dimensional semiconductor material layer away from the substrate; and a source / drain contact region including the two-dimensional semi-metal / metal material layer, the solid-state source active metal layer, and the conventional metal layer, wherein the source / drain contact region contacts the gate structure.

[0015] The two-dimensional semi-metal / metal material layer is obtained by the phase transition of the two-dimensional semiconductor material layer induced by the metal atoms in the solid-state source active metal layer.

[0016] The gate structure includes: a gate dielectric layer, a gate layer disposed on the gate dielectric layer, and a sidewall covering the gate dielectric layer and the sidewall of the gate layer.

[0017] The solid active source metal layer includes any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), and rhenium (Re).

[0018] The advantages and technical effects of this invention are as follows:

[0019] The self-aligned patterning method for two-dimensional semiconductor transistors employed in this invention is based on solid-state source doping-induced phase transition technology for two-dimensional semiconductors. This method induces the two-dimensional semiconductor material in the contact region to transform into a two-dimensional semi-metallic material or a two-dimensional metallic material. The induced two-dimensional semi-metallic material or two-dimensional metallic material is then used to directly contact the two-dimensional semiconductor material, avoiding the Fermi pinning effect caused by conventional direct metal deposition. This allows for the formation of ohmic contacts, solving the problem of high-resistance contacts at a lower cost. Furthermore, an automated alignment process is used to form the source and drain contact regions of the two-dimensional semiconductor transistor, reducing the device area, improving integration density and performance, and realizing a self-aligned source and drain process for two-dimensional semiconductor material devices. Attached Figure Description

[0020] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0021] Figures 1-11 This is a schematic diagram of the structure obtained in each step of the fabrication process of a two-dimensional semiconductor transistor using the self-aligned patterning method provided by the present invention.

[0022] Figure 12 This is a schematic diagram of the structure of a two-dimensional semiconductor transistor provided according to the present invention. Detailed Implementation

[0023] To make the objectives, content, and advantages of this invention clearer, the specific embodiments of this invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solutions of this invention and should not be construed as limiting the scope of protection of this invention.

[0024] Example 1

[0025] This embodiment specifically describes a self-aligned patterning method for a two-dimensional semiconductor transistor provided by the present invention, comprising the following steps: providing a substrate; forming a semiconductor material layer on the substrate; forming a gate structure on the semiconductor material layer; forming pseudo-gate sidewalls to surround the sidewalls of the gate structure; fabricating a two-dimensional semiconductor material layer on the substrate; performing surface modification treatment on the surface of the two-dimensional semiconductor material layer not covered by the gate structure and sidewalls; depositing a solid active source metal layer on the surface of the two-dimensional semiconductor material layer away from the substrate; depositing a conventional metal layer on the solid active source metal layer; annealing the solid active source metal layer and the conventional metal layer to obtain a two-dimensional half-metal / metal material layer; photolithographically forming the solid active source metal layer and the conventional metal layer to form a source / drain contact region by self-alignment, wherein the source / drain contact region includes the solid active source metal layer, the conventional metal layer, and the two-dimensional half-metal / metal material layer.

[0026] The following is combined with Figures 1-11 A detailed description of a self-aligned patterning method for two-dimensional semiconductor transistors is provided, comprising the following steps:

[0027] S1 provides a substrate 100, the substrate material of which includes insulating materials such as silicon, silicon oxide, sapphire, and mica;

[0028] S2, a two-dimensional semiconductor material layer 101 is prepared on the substrate 101, resulting in the structure shown below. Figure 1As shown, the two-dimensional semiconductor material layer includes any one or a combination of indium selenide (InSe), molybdenum disulfide (MoS2), indium diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum telluride (MoTe2), black phosphorus (BP), silene, germanene, tellurene, and ionic layered semiconductor materials (Bi2O2X, X=S or Se), but the present invention is not limited thereto;

[0029] S3, forming a gate structure on the semiconductor material layer, including forming a gate dielectric layer 102 on the semiconductor material layer 101 and forming a gate layer 103 on the gate dielectric layer, resulting in the structure shown below. Figure 2 As shown, the gate layer 103 can be a polycrystalline silicon or amorphous silicon dummy gate, or a metal gate;

[0030] S4, a dielectric layer 104 is deposited to cover the semiconductor material layer 101 and the gate structure using PECVD (plasma-enhanced chemical vapor deposition), resulting in the structure shown below. Figure 3 As shown, the dielectric layer 104 can be made of insulating materials such as silicon nitride; then, the dielectric layer 104 is etched back to form a pseudo-gate sidewall 105, surrounding the sidewall of the gate structure, resulting in the structure shown below. Figure 4 As shown;

[0031] S5, such as Figure 5 As shown, the surface of the two-dimensional semiconductor material layer 101 is bombarded with soft plasma to modify the surface of the two-dimensional semiconductor material layer 101 that is not covered by the gate structure and sidewall 105. Specifically, the two-dimensional semiconductor is bombarded with ultra-low power soft plasma (such as nitrogen, argon, hydrogen, etc.) of 1-100W for 5-300 seconds, which causes lattice defects and distortions on the uncovered surface of the two-dimensional semiconductor material layer 101, making it easier to implant active metal atoms in the future.

[0032] S6, evaporating a solid active source metal layer 106 and a conventional metal layer 107, the resulting structure is as follows: Figure 6 As shown, the thickness of the solid active source metal layer is 0.5-5 nm. The metal in the solid active source metal layer is a metal that readily reacts with two-dimensional semiconductor materials. Its categories can include any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re), etc. The thickness of the conventional metal layer is more than 5 nm. The metal in the conventional metal layer is often an inert metal, such as any one or a combination of gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), palladium (Pd), silver (Ag), and titanium nitride (TiNx). Its function is passivation to prevent oxidation of the active metal layer.

[0033] S7, undergo annealing treatment to obtain the structure as shown. Figure 7 As shown, metal atoms in the solid active source metal layer 106 are injected into the two-dimensional semiconductor material layer 101, resulting in substitutional doping. The two-dimensional semiconductor material layer after substitutional doping is induced to undergo a phase transition and transform into a two-dimensional half-metal / metal material layer 108. The annealing process can be a rapid annealing method from 250°C to 600°C for 2-60 seconds, or a conventional annealing method from 150°C to 250°C under high vacuum for 15 minutes to 4 hours. The annealing time and temperature determine the atomic concentration of substitutional doping. A longer annealing time and higher temperature result in a higher doping concentration, and the semiconductor material layer transforms into a two-dimensional metal material layer with a lower doping concentration.

[0034] S8, SOD dielectric layer 109 is prepared by sampling spin coating method, or dielectric layer 109 is grown by PECVD, and the structure obtained is as follows. Figure 8 As shown, the material of the dielectric layer can be silicon nitride or silicon oxide, etc.

[0035] S9, using the conventional metal layer 107 on the conventional gate structure as the stop layer, the dielectric layer 109 is planarized using CMP (chemical mechanical polishing), resulting in the structure shown below. Figure 9 As shown;

[0036] S10, etching back the dielectric layer 109 achieves thinning of the insulating dielectric until it reaches above the conventional metal layer 107 in the contact area. A dielectric layer 10-20 nanometers thick is retained above the contact area. The outer wall of the gate sidewall and the metal layer at the top of the gate outside the contact area are exposed. Part of the dielectric layer 109 is retained, resulting in the structure shown below. Figure 10 As shown;

[0037] S11, the transistor dimensions are defined using photolithography. A photoresist mask is used, and windows are created to define the overall dimensions of the source / drain regions and the gate pattern. The remaining unmasked dielectric layer is then etched away, leaving a self-aligned source / drain contact region. The resulting structure is shown below. Figure 11 As shown;

[0038] S12 employs a wet etching process, where a metal etching solution is used to selectively etch away the metal layer in other areas without a mask (the dielectric layer 109 is not etched away by the metal etching solution). Therefore, only the source and drain metal below the contact area 109 remains, resulting in a two-dimensional semiconductor transistor, as shown in the schematic diagram below. Figure 12 As shown.

[0039] The self-aligned patterning method for two-dimensional semiconductor transistors provided in this embodiment induces the two-dimensional semiconductor material in the contact area to transform into a two-dimensional semi-metallic material or a two-dimensional metallic material. The induced two-dimensional semi-metallic material or two-dimensional metallic material is used to directly contact the two-dimensional semiconductor material, avoiding the Fermi pinning effect caused by conventional direct metal evaporation. This can form ohmic contacts, solving the problem of high-resistance contacts at a lower cost. Furthermore, the automatic alignment process is used to form the source and drain contact areas of the two-dimensional semiconductor transistor, reducing the device area, improving integration and performance, and realizing the source and drain self-alignment process for two-dimensional semiconductor material devices.

[0040] This embodiment also provides a two-dimensional semiconductor transistor, such as Figure 12 As shown, the two-dimensional semiconductor transistor includes: a substrate 100; a two-dimensional semiconductor material layer 101 disposed on the substrate 100; a two-dimensional semi-metal / metal material layer 108 disposed on the surface of the two-dimensional semiconductor material layer away from the substrate; a solid-state source active metal layer 106 disposed on the surface of the two-dimensional semi-metal / metal material layer 108 away from the two-dimensional semiconductor material layer; a conventional metal layer 107 disposed on the surface of the solid-state source active metal layer away from the two-dimensional semi-metal / metal material layer; a gate structure penetrating the solid-state source metal layer and the conventional metal layer, disposed on the surface of the two-dimensional semiconductor material layer away from the substrate; and a source / drain contact region including the two-dimensional semi-metal / metal material layer 108, the solid-state source active metal layer 107, and the conventional metal layer 106, wherein the source / drain contact region contacts the gate structure.

[0041] Because two-dimensional semiconductor materials are layered van der Waals stacked materials, they can be divided into the following two cases: (1) Single-layer two-dimensional semiconductor materials, that is, two-dimensional semiconductor materials with only one layer, which is also the most common single-layer two-dimensional semiconductor materials. In this case, all the two-dimensional semiconductor materials in the lower part of the contact area are transformed into two-dimensional metal and half-metal materials; (2) Multi-layer two-dimensional semiconductor materials, in this case, only the uppermost two-dimensional semiconductor material is transformed into two-dimensional metal and half-metal materials. In this case, there are still two-dimensional semiconductor materials remaining in the lower part of the contact area. However, since the upper layer is a two-dimensional half-metal and metal material, the contact area as a whole exhibits half-metal and metallic properties. For clarity, the accompanying drawings of the preparation process described above show the second case, but the present invention is not limited to this.

[0042] As described above, the two-dimensional semi-metal / metal material layer in the contact region is obtained by inducing a phase transition in the two-dimensional semiconductor material layer by metal atoms in the solid-state source active metal layer. Using this induced two-dimensional semi-metal / metal material layer in direct contact with the two-dimensional semiconductor material 101 avoids the Fermi pinning effect caused by conventional direct metal deposition, enabling the formation of an ohmic contact with a contact resistance below 200 Ω·μm. The Schottky barrier height is close to the physical limit of 0 meV, and the two-dimensional ballistic transistor exhibits an on-state current greater than 1 mA / μm, significantly improving the contact resistance of the two-dimensional semiconductor material.

[0043] The gate structure of the two-dimensional semiconductor transistor includes: a gate dielectric layer 102, a gate layer 103 disposed on the gate dielectric layer, and a sidewall 105 covering the gate dielectric layer 102 and the sidewall of the gate layer.

[0044] The two-dimensional semiconductor transistor provided in this embodiment reduces contact resistance and device area, and can meet the requirements of semiconductor technology roadmap at advanced nodes.

[0045] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are preferred embodiments. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and they should not be construed as limiting the scope of protection of the present invention. All equivalent transformations or modifications made according to the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A self-aligned patterning method for two-dimensional semiconductor transistors, characterized in that, Includes the following steps: Provide a base; A two-dimensional semiconductor material layer is formed on the substrate; A gate structure is formed on the two-dimensional semiconductor material layer; A pseudo-gate sidewall is formed to surround the sidewall of the gate structure; The surface of the two-dimensional semiconductor material layer not covered by the gate structure and sidewalls is subjected to surface modification treatment by bombarding with ultra-low power soft plasma. A solid active source metal layer is formed on the surface of the two-dimensional semiconductor material away from the substrate; A conventional metal layer is formed on the solid active source metal layer; Annealing is performed on the solid active source metal layer and the conventional metal layer to induce a phase transition in the two-dimensional semiconductor material layer by metal atoms in the solid active source metal layer, resulting in a two-dimensional half-metal / metal material layer. Photolithography is used to form the solid-state active source metal layer and the conventional metal layer, and self-alignment is performed to form the source / drain contact region, which includes the solid-state active source metal layer, the conventional metal layer and the two-dimensional half-metal / metal material layer.

2. The self-aligned patterning method for two-dimensional semiconductor transistors according to claim 1, characterized in that, The annealing process employs a rapid annealing method, annealing at 250°C to 600°C for 2-60 seconds.

3. The self-aligned patterning method for two-dimensional semiconductor transistors according to claim 1 or 2, characterized in that, The process of photolithography of the solid-state active source metal layer and the conventional metal layer includes using photoresist as a mask and opening windows to define the overall size of the source / drain contact region and the gate structure.

4. The self-aligned patterning method for two-dimensional semiconductor transistors according to claim 1 or 2, characterized in that, The two-dimensional semiconductor material layer includes any one or a combination of indium selenide (InSe), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum telluride (MoTe2), black phosphorus (BP), silicene, Germanene, tellurene, and ionic layered semiconductor materials (Bi2O2X, X=S or Se).

5. The self-aligned patterning method for two-dimensional semiconductor transistors according to claim 1 or 2, characterized in that, The solid active source metal layer includes any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), and rhenium (Re).

6. A two-dimensional semiconductor transistor, characterized in that, include: Base; A two-dimensional semiconductor material layer is disposed on the substrate; A two-dimensional semi-metal / metal material layer is disposed on the surface of the two-dimensional semiconductor material layer away from the substrate; A solid-state active source metal layer is disposed on the surface of the two-dimensional semi-metal / metal material layer away from the two-dimensional semiconductor material layer; A conventional metal layer is disposed on the surface of the solid-state active source metal layer away from the two-dimensional half-metal / metal material layer; A gate structure, penetrating the solid-state active source metal layer and the conventional metal layer, is disposed on the surface of the two-dimensional semiconductor material layer away from the substrate; The source / drain contact region includes the two-dimensional half-metal / metal material layer, the solid-state active source metal layer, and the conventional metal layer, and the source / drain contact region is in contact with the gate structure.

7. The two-dimensional semiconductor transistor according to claim 6, characterized in that, The two-dimensional semi-metal / metal material layer is obtained by the metal atoms in the solid active source metal layer inducing a phase transition in the two-dimensional semiconductor material layer.

8. The two-dimensional semiconductor transistor according to claim 6 or 7, characterized in that, The gate structure includes: a gate dielectric layer, a gate layer disposed on the gate dielectric layer, and a sidewall covering the gate dielectric layer and the sidewall of the gate layer.

9. The two-dimensional semiconductor transistor according to claim 6 or 7, characterized in that, The solid active source metal layer includes any one or a combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), and rhenium (Re).

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