Electronic device package with electrical isolation

Abstract

This application relates to electronic device packages with electrical isolation. In one general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface, and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads other than the subset of the first plurality of signal leads can be spaced apart from the dielectric substrate. Signal leads of the second plurality of signal leads other than the subset of the second plurality of signal leads can be spaced apart from the dielectric substrate. The assembly can further include first and second semiconductor dies electrically coupled with the substrate and the leadframe portions.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on August 23, 2018, with application number 201810967435.1 and invention title "Electrically Isolated Electronic Device Package". Technical Field

[0003] This description relates to packaged circuitry and associated manufacturing methods for electronic device assemblies that include electrical isolation (e.g., capacitive isolation) between semiconductor dies contained within such assemblies. Background Technology

[0004] The transmission of data, such as control, feedback, and status information, in automotive and industrial applications or electrical systems may involve data transfer between different power domains, where such power domains may have a significant voltage difference (e.g., tens of thousands of volts in some embodiments). For example, a first data communication circuit in a first power domain can transmit data to a second data communication circuit in a second power domain. In such applications, to prevent (block, etc.) stray currents, such as currents at ground potential differences and / or currents from alternating current (AC) sources, from flowing between the first and second data communication circuits (e.g., between different power domains), the first and second data communication circuits may be electrically (e.g., capacitively isolated). Summary of the Invention

[0005] In a general aspect, an electronic device assembly may include a dielectric substrate having a first surface and a second surface opposite to the first surface. The dielectric substrate may include: a first unidirectional isolation channel defined thereon, the first unidirectional isolation channel having an input terminal and an output terminal; and a second unidirectional isolation channel defined thereon, the second unidirectional isolation channel having an input terminal and an output terminal. The assembly may further include a lead frame having a first lead frame portion and a second lead frame portion. The first lead frame portion may include a first plurality of signal leads. A first corner of the first surface of the dielectric substrate may be coupled to a first signal lead of the first plurality of signal leads. A second corner of the first surface of the dielectric substrate may be coupled to a second signal lead of the first plurality of signal leads. The second lead frame portion may include a second plurality of signal leads. A third corner of the first surface of the dielectric substrate may be coupled to a first signal lead of the second plurality of signal leads. A fourth corner of the first surface of the dielectric substrate may be coupled to a second signal lead of the second plurality of signal leads. The assembly may further include a first semiconductor die, which is electrically coupled to at least one signal lead of the first plurality of signal leads, an input terminal of the first unidirectional isolation channel, and an output terminal of the second unidirectional isolation channel using corresponding wire connections. The assembly may further include a second semiconductor die, which is electrically coupled to at least one signal lead of the second plurality of signal leads, an output terminal of the first unidirectional isolation channel, and an input terminal of the second unidirectional isolation channel using corresponding wire connections. Attached Figure Description

[0006] Figure 1 and 2 It is a block diagram schematically illustrating a data communication device assembly.

[0007] Figure 3 , 4 Figures 5 and 6 are plan views of an electronic device assembly.

[0008] Figure 6A , 6B 6C is a diagram illustrating an electronic device assembly.

[0009] Figure 7A , 7B 7C is a diagram illustrating another electronic device assembly.

[0010] Figure 8A , 8B 8C is a diagram illustrating another electronic device assembly.

[0011] Figure 9A , 9B 9C is a diagram illustrating another electronic device assembly.

[0012] Figure 10A , 10B 10C is a diagram illustrating another electronic device assembly.

[0013] Figure 11 This is a diagram illustrating another electronic device assembly.

[0014] Figure 12 This is an exploded view of the electronic device assembly in Figure 10.

[0015] Figure 13 It is a diagram illustrating lead frame strips and single lead frames of strips.

[0016] Figure 14 , 15 Figures 16 and 17 are diagrams illustrating the manufacturing process flow for producing electronic device assemblies. Detailed Implementation

[0017] This disclosure relates to electronic device assemblies (assemblies) and methods for producing such assemblies. The example assemblies described herein can be used to implement electronic devices that bidirectionally transmit data (e.g., for multiple data channels) using unidirectional electrically isolated channels (e.g., two unidirectional differential isolation channels per bidirectional channel). For example, the assemblies described herein can be used, for instance, in industrial and / or automotive applications involving power conversion, gate drivers, motor control, etc., to transmit data between different power domains. For example, data can be transmitted using a first unidirectional isolation channel from a first circuit (e.g., a first integrated circuit (IC) in a first power domain) to a second circuit (e.g., a second integrated circuit (IC) in a second power domain), while data from the second circuit to the first circuit can be transmitted using a second unidirectional isolation channel.

[0018] In the methods described herein, electrical isolation between data communication circuits (and associated power domains) can be achieved using multiple capacitors defined on a common dielectric substrate (substrate), such as a printed circuit substrate (e.g., ceramic, FR4, etc.). For example, in some embodiments, capacitors may be defined on the substrate for each of two unidirectional differential isolation channels (e.g., a total of four capacitors, including one for each of the positive differential signals and one for each of the negative differential signals). In some embodiments, additional circuitry (integrated circuits) and isolation channels may be included. High insulation penetration distances are achieved using the methods described herein, attributable to the thickness of the substrate used to implement the isolation capacitors. Such isolation channels can be formed using printed circuit traces and vias (through the substrate) to form and interconnect capacitor electrodes.

[0019] Figure 1 This is a block diagram illustrating the electronic device assembly (assembly) 100. For example... Figure 1 As shown, assembly 100 includes a substrate 110, a primary circuit 130, and a secondary circuit 140. The substrate 110 can be a printed circuit substrate, such as a ceramic substrate, an FR4 substrate, or any suitable substrate material having dielectric (electrically insulating) properties. Circuit 130 and secondary circuit 140 can be implemented on corresponding integrated circuits (ICs). The primary circuit 130 (e.g., a first IC) and secondary circuit 140 (e.g., a second IC), such as... Figure 1 As shown, it can be mounted on substrate 110 (coupled to it, physically coupled to it, etc.). Furthermore, primary circuitry 130 and secondary circuitry 140 can be electrically coupled to capacitors contained on substrate 110 using wire bonds, circuit traces, and / or conductive vias included on substrate 110. In some embodiments, other electrical connections, such as solder connections, can be used between the respective IC and substrate 110.

[0020] like Figure 1 As shown, capacitor pairs for two unidirectional isolation channels may be defined (formed, implemented, etc.) on substrate 110. For example, in device 100, a first capacitor pair may include capacitors 112 and 114, and a second capacitor pair may include capacitors 116 and 118. Capacitors 112-118 may be formed using corresponding capacitor electrodes (e.g., printed circuit traces) disposed on opposite sides of substrate 110. In device 100, a first unidirectional isolation channel may include a first capacitor pair (including capacitors 112 and 114), while a second unidirectional isolation channel may include a second capacitor pair (including capacitors 116 and 118). The first and second unidirectional isolation channels may be used for bidirectional data communication (e.g., between two different power domains).

[0021] like Figure 1 As shown, in this example, primary circuit 130 includes a transmitter (TX) 132 and a receiver (RX) 134, while secondary circuitry includes TX 142 and RX 144. In device 100, capacitors 112 and 114 provide differential series coupling between TX 132 of primary circuit 130 and RX 144 of secondary circuit 140. Capacitors 116 and 118 provide differential series coupling between TX 142 of secondary data circuit 140 and RX 134 of primary circuit 130.

[0022] In device 100, TX 132, capacitors 112 and 114, and RX 144 may be referred to as being contained in a first (unidirectional) isolation channel, while TX 142, capacitors 116 and 118, and RX 134 may be referred to as being in a second (unidirectional) isolation channel. In some embodiments (e.g., device 100), data may be transmitted in a similar or identical manner in the first and second isolation channels, respectively. The specific method for data communication between primary circuit 130 and secondary circuit 140 will depend on the specific embodiment.

[0023] Figure 2 This is a block diagram illustrating another electronic device assembly (assembly) 200. For example... Figure 2 As shown, assembly 200 includes substrate 210, primary circuitry 230, and secondary circuitry 240. Like substrate 110, substrate 210 can be a printed circuit substrate, such as a ceramic substrate, FR4 substrate, or any suitable substrate material with dielectric (electrically insulating) properties.

[0024] Similar to data communication device 100, primary circuit 230 and secondary circuit 240 can be implemented on corresponding integrated circuits (ICs). Compared to circuits 130 and 140 of device 100, primary circuit 230 (e.g., a first IC) and secondary circuit 240 (e.g., a second IC), such as... Figure 2 As shown, it is not placed on substrate 110 (coupled to it, physically coupled to it, etc.). In some embodiments, such as those described herein, the circuitry (ICs) 230 and 240 of device 200 may be disposed on a lead frame. Furthermore, primary circuitry 230 and secondary circuitry 240 may be electrically coupled to capacitors contained in substrate 230 using wire connections, circuit traces, and / or conductive vias contained on substrate 110.

[0025] like Figure 2 As shown, capacitor pairs for two unidirectional isolation channels of device 200 may be defined (formed, implemented, etc.) on substrate 210. In device 200, a first capacitor pair may include capacitors 212 and 214, and a second capacitor pair may include capacitors 216 and 218. Capacitors 212-218 may be formed using corresponding capacitor electrodes disposed on opposite sides of substrate 210, the corresponding capacitor electrodes being interconnected with vias and / or circuit traces formed on substrate 210. In device 200, a first unidirectional isolation channel may include a first capacitor pair including capacitors 212 and 214, while a second unidirectional isolation channel may include a second capacitor pair including capacitors 216 and 218. The first and second unidirectional isolation channels of device 200 may be used for bidirectional data communication (e.g., between two different power domains).

[0026] like Figure 2As shown, primary circuit 230 includes TX 232 and RX 234, while secondary circuit includes TX 242 and RX 244. In device 200, capacitors 212 and 214 provide differential series coupling between TX 232 of primary circuit 230 and RX 244 of secondary circuit 240. Similarly, in device 200, capacitors 216 and 218 provide differential series coupling between TX 242 of secondary circuit 240 and RX 234 of primary circuit 230. In device 200, TX 232, capacitors 212 and 214, and RX 244 may be referred to as being included in a first (unidirectional) isolation channel, while TX 242, capacitors 216 and 218, and RX 234 may be referred to as being in a second (unidirectional) isolation channel. Similar to that described above with respect to device 100, in device 200, data can be transmitted (unidirectional transmission) in a first isolation channel (from TX 232 to RX 244) and a second isolation channel (from TX 242 to RX 234) to implement bidirectional data communication.

[0027] Figure 3 , 4 Figures 300, 400, and 500 are plan views of electronic device assemblies (assemblies) 300, 400, and 500, respectively. Figures 6A-6C Figures 300-700, 700-700, 800-800, 900-900, 1000, and 1100 are schematic illustrations of electronic device assemblies 600, 700, 800, 900, 1000, and 1100, respectively. In some embodiments, assemblies 300, 600, and 700 may be used to implement... Figure 1 Assembly 100. In some embodiments, assemblies 400 and 500, 800, 900, 1000 and 1100 may be used. Figure 2 Assembly 200. In Figure 3-11 In this illustration, for purposes of illustration, the assembly is shown using a shading (e.g., X-ray) view, such that internal features of the assembly that would be invisible to the molded compound in the actual device are shown.

[0028] exist Figure 3 and 4 In the diagram, the plan view of assemblies 300 and 400 is shown as a bottom-side (dead insect, lead wire facing upwards) view of the assemblies, while Figure 5 The plan view of assembly 500 is shown as a top-side (live, lead wire facing down) view of the assembly. Figure 3 Assembly 300 and Figures 6A-6C The 600 assembly corresponds to this. Figure 4 Assembly 400 and Figures 8A-8C The assembly part 800 corresponds to, and Figure 5 Assembly 500 and Figures 9A-9C The assembly corresponds to component 900. Figure 3-11 The assemblies are shown by way of example and for illustrative purposes. In some embodiments, features of one assembly may be implemented in another assembly (e.g., as a supplement to or replacement of existing features).

[0029] like Figure 3 As shown, assembly 300 may include a dielectric substrate 310, a first lead frame portion 320a, a second lead frame portion 320b, a first semiconductor die 330, a second semiconductor die 340, a wire bond 350, and a molding compound 360. The substrate 310 may have a first surface ( Figure 3 (Middle facing upward) and the second surface opposite to the first surface ( Figure 3 (Middle facing down). For example Figure 3 As shown, substrate 310 may have printed circuit features 312 defined thereon, which may include copper traces (e.g., forming capacitor electrodes and / or attachment pads for coupling substrate 310 to leadframe portions 320a and 320b) and vias through substrate 310. Printed circuit features 312 may define first unidirectional isolated channel input and output terminals on substrate 310, for example, as described above relative to… Figure 1 and 2 As discussed above. Printed circuit feature 312 may also define a second unidirectional isolated channel input terminal and output terminal on substrate 310.

[0030] like Figure 3 As shown, the first lead frame portion 320a may include a plurality of signal leads arranged linearly along a first edge 321 of the assembly 300, while the second lead frame portion 320b includes a second plurality of signal leads arranged linearly along a second edge 323 of the assembly 300. Figure 3 As shown, signal leads 322, 324, 326, and 328, located at the ends of edges 321 and 323 (e.g., at corners of assembly 300), extend into the molding compound 360 and are coupled to the first (upward) surface of substrate 310, for example, at a corresponding corner of the first surface of substrate 310. Similarly, as... Figure 3 As shown, the other signal leads of lead frame portions 320a and 320b, excluding signal leads 322, 324, 326 and 328, extend into the molding compound 360, but are pulled back from the substrate 310 (spaced apart from it, laterally spaced from it, not in physical contact with it, etc.).

[0031] like Figure 3 As shown, the first semiconductor die 330 and the second semiconductor die 340 are also disposed on the first surface of the substrate 310 in the assembly 300. Wire bonding 350 electrically couples the first and second semiconductor dies to the substrate 310 (e.g., to the input and output terminals of the isolation channel) and to the signal leads of the lead frame portions 320a and 320b.

[0032] like Figure 4 As shown, assembly 400 may include a dielectric substrate 410, a first lead frame portion 420a, a second lead frame portion 420b, a first semiconductor die 430, a second semiconductor die 440, a wire bond 450, and a molding compound 460. The substrate 410 may have a first surface ( Figure 4 (Middle facing upward) and the second surface opposite to the first surface ( Figure 4 (Middle facing down). For example Figure 4 As shown, substrate 410 may have printed circuit features 412 defined thereon, which may include copper traces (e.g., forming capacitor electrodes and / or attachment pads for coupling substrate 410 to leadframe portions 420a and 420b) and vias through substrate 410. Printed circuit features 412 may define first unidirectional isolated channel input and output terminals on substrate 410, for example, as described above relative to… Figure 1 and 2 As discussed. Printed circuit feature 412 may also define a second unidirectional isolated channel input terminal and output terminal on substrate 410.

[0033] like Figure 4 As shown, the first lead frame portion 420a may include a plurality of signal leads arranged linearly along a first edge 421 of the assembly 400, while the second lead frame portion 420b includes a second plurality of signal leads arranged linearly along a second edge 423 of the assembly 400. Figure 4 As shown, signal leads 422, 424, 426, and 428, located at the ends of edges 421 and 423 (e.g., at corners of assembly 400), extend into the molding compound 460 and are coupled to the first (upward) surface of substrate 410, for example, at a corresponding corner of the first surface of substrate 410. Similarly, as... Figure 4 As shown, the other signal leads of lead frame portions 420a and 420b, excluding signal leads 422, 424, 426 and 428, extend into the molding compound 460, but are pulled back from the substrate 410 (spaced apart from it, laterally spaced from it, not in physical contact with it, etc.).

[0034] like Figure 4 As shown, a first semiconductor die 430 and a second semiconductor die 440 are disposed on signal leads 422, 424, 426, and 428 (e.g., on a surface opposite to the surface coupled to the substrate 410). Wire bonding 450 electrically couples the first and second semiconductor dies to the substrate 410 (e.g., to the input and output terminals of the isolation channel) and to the signal leads of lead frame portions 420a and 420b.

[0035] like Figure 5As shown, assembly 500 may include a dielectric substrate 510, a first lead frame portion 520a, a second lead frame portion 520b, a first semiconductor die 530, a second semiconductor die 540, a wire bond 550, and a molding compound 560. Substrate 510 may have a first surface ( Figure 5 (Middle facing down) and the second surface opposite to the first surface ( Figure 5 (Middle of the road, facing upwards). For example... Figure 5 As shown, substrate 510 may have printed circuit features 512 defined thereon, which may include copper traces (e.g., forming capacitor electrodes and / or attachment pads for coupling substrate 510 to leadframe portions 520a and 520b) and vias through substrate 510. Printed circuit features 512 may define first unidirectional isolated channel input and output terminals on substrate 510, for example, as described above relative to… Figure 1 and 2 As discussed above. Printed circuit feature 512 may also define a second unidirectional isolated channel input terminal and output terminal on substrate 510.

[0036] like Figure 5 As shown, the first lead frame portion 520a may include a plurality of signal leads arranged linearly along a first edge 521 of the assembly 500, while the second lead frame portion 520b includes a second plurality of signal leads arranged linearly along a second edge 523 of the assembly 500. Figure 5 As shown, signal leads 522, 524, 526, and 528, located at the ends of edges 521 and 523 (e.g., at corners of assembly 500), extend into the molding compound 560 and are coupled to the first (downward) surface of substrate 510, for example, at corresponding corners of the first surface of substrate 410. Similarly, as... Figure 5 As shown, the other signal leads of lead frame portions 520a and 520b, excluding signal leads 522, 524, 526 and 528, extend into the molding compound 560, but are pulled back from the substrate 510 (spaced apart from it, laterally spaced from it, not in physical contact with it, etc.).

[0037] like Figure 5 As shown, a first semiconductor die 530 and a second semiconductor die 540 are disposed on signal leads 522, 524, 526, and 528 (e.g., on the same surface coupled to the substrate 510). A wire bond 550 electrically couples the first and second semiconductor dies to the substrate 510 (e.g., to the input and output terminals of the isolation channel) and to the signal leads of lead frame portions 520a and 520b.

[0038] As noted above, assembly 300 and Figures 6A-6C Assembly 600 corresponds to, and assembly 400 is... Figures 8A-8C The assembly part 800 corresponds to, and Figure 5 Assembly 500 and Figures 9A-9C The assembly part 900 corresponds to this. In addition, respectively... Figures 7A-7C The assemblies 700, 1000, and 1100 of 10A-10C and 11 are variations of assemblies 300, 400, and 500. Accordingly, for the sake of brevity, the details of each of these assemblies are not described in detail in the discussion below.

[0039] Figure 6A , 6B And 6C is an explanation of... Figure 3 The diagram of the electronic device assembly 600 corresponding to the assembly 300. Figure 6A This is an isometric view of the top side (live insect). Figure 6B It is an isometric view of the bottom side (dead insect), and Figure 6C This is a side view of assembly 600. Assembly 600 includes a substrate 610 (having printed circuit features 612), a first lead frame portion 620a, a second lead frame portion 620b, a first semiconductor die 630, a second semiconductor die 640, a wire bond 650, and a molding compound 660.

[0040] like Figures 6A-6C As shown, signal leads 622, 624, 626, and 628 extend into the molding compound 660 and are coupled to corresponding corners of the substrate 610 on the first surface of the substrate 610. Similarly, as... Figures 6A-6C As shown, the first and second semiconductor dies 630 and 640 are also disposed on the first surface of the substrate 610, for example, between signal leads 622 and 624 and between signal leads 626 and 628, respectively.

[0041] Figure 7A , 7B 7C is a diagram illustrating an electronic device assembly 700 that can be a variation of assembly 600. Figure 7A This is an isometric view of the top side (live insect). Figure 7B It is an isometric view of the bottom side (dead insect), and Figure 7C This is a side view of assembly 700. Assembly 700 includes a substrate 710 (with printed circuit features 712), a first lead frame portion 720a, a second lead frame portion 720b, a first semiconductor die 730, a second semiconductor die 740, a wire bond 750, and a molding compound 760.

[0042] exist Figures 7A-7C In the diagram, signal leads 722 and 726 are shown for use with Figures 7A-7C Orientation reference between views. (See figure.) Figures 7A-7CAs shown, compared to assembly 600, first and second semiconductor dies 730 and 740 are disposed on a second surface of substrate 710 opposite to a first surface of substrate 710 (e.g., the surface coupled to signal leads of first leadframe portion 720a and second leadframe portion 720b). Similarly, compared to assembly 600, the substrate 710 of assembly 700 is coupled to signal leads centrally positioned (rather than end (corner) signal leads) in a linear arrangement of signal leads in the first and second leadframe portions 720a and 720b. In some embodiments, leadframe portions 620a and 620b may be implemented in assembly 700, for example, replacing leadframe portions 720a and 720b.

[0043] Figure 8A , 8B 8C and 8C are diagrams illustrating the electronic device assembly 800 corresponding to assembly 400. Figure 8A This is an isometric view of the top side (live insect). Figure 8B It is an isometric view of the bottom side (dead insect), and Figure 8C This is a side view of assembly 800. Assembly 800 includes a substrate 810 (with printed circuit features 812), a first lead frame portion 820a, a second lead frame portion 820b, a first semiconductor die 830, a second semiconductor die 840, a wire bond 850, and a molding compound 860.

[0044] like Figures 8A-8C As shown, signal leads 822, 824, 826, and 828 extend into the molding compound 860 and are coupled to corresponding corners of the substrate 810 on the first surface of the substrate 810. Similarly, as... Figures 8A-8C As shown, a first semiconductor die 830 is disposed on the surface of signal leads 822 and 824 opposite to the surface coupled to the substrate 810. Furthermore, in the assembly 800, a second semiconductor die 840 is disposed on signal leads 826 and 828, on the surface of signal leads 822 and 828 opposite to the surface coupled to the substrate 810.

[0045] Figure 9A , 9B 9C and 9C are diagrams illustrating the electronic device assembly 900 corresponding to assembly 500. Figure 9A This is an isometric view of the top side (live insect). Figure 9B It is an isometric view of the bottom side (dead insect), and Figure 9C This is a side view of assembly 900. Assembly 900 includes a substrate 910 (having printed circuit features 912), a first lead frame portion 920a, a second lead frame portion 920b, a first semiconductor die 930, a second semiconductor die 940, a wire bond 950, and a molding compound 960.

[0046] like Figures 9A-9C As shown, signal leads 922, 924, 926, and 928 extend into the molding compound 960 and are coupled to corresponding corners of the substrate 910 on a first surface of the substrate 910. Signal leads 922 and 924 also define die attachment paddles for a first semiconductor die 930, while signal leads 926 and 928 define die attachment paddles for a second semiconductor die 940. Figure 9A and 9C As shown, a first semiconductor die 930 is disposed on a die attachment paddle defined by signal leads 922 and 924, on the same surface as the signal leads 922 and 924 coupled to the substrate 910. Furthermore, in the assembly 900, a second semiconductor die 940 is disposed on a die attachment paddle defined by signal leads 926 and 928, on the same surface as the signal leads 926 and 928 coupled to the substrate 910.

[0047] Figure 10A , 10B 10C is a diagram illustrating electronic device assembly 1000. Figure 10A This is an isometric view of the top side (live insect). Figure 10B It is an isometric view of the bottom side (dead insect), and Figure 10C This is a side view of assembly 1000. Assembly 1000 includes a substrate 1010 (having printed circuit features 1012), a first lead frame portion 1020a, a second lead frame portion 1020b, a first semiconductor die 1030, a second semiconductor die 1040, a wire bond 1050, and a molding compound 1060.

[0048] like Figures 10A-10B As shown, signal leads 1022, 1024, 1025, and 1028 extend into the molding compound 1060 and are coupled to corresponding corners of the substrate 1010 on a first surface of the substrate 1010. Signal leads 1022 and 1024 are adjacent to each other and centrally located among the linearly arranged signal leads in the lead frame portion 1020a. Similarly, signal leads 1024 and 1026 are adjacent to each other and centrally located among the linearly arranged signal leads in the lead frame portion 1020b.

[0049] Signal leads 1022 and 1024 further define die attachment paddles for the first semiconductor die 1030, while signal leads 1026 and 1028 define die attachment paddles for the second semiconductor die 1040. For example... Figure 10AAs shown, a first semiconductor die 1030 is disposed on a die attachment paddle defined by signal leads 1022 and 1024 on the same surface as the signal leads 1022 and 1024 coupled to the substrate 1010. Furthermore, in the assembly 1000, a second semiconductor die 1040 is disposed on a die attachment paddle defined by signal leads 1026 and 1028 on the same surface as the signal leads 1022 and 1028 coupled to the substrate 1010.

[0050] Figure 11 This is a schematic top view (or isometric view) of an electronic device assembly 1100, similar to assembly 1100. Assembly 1100 includes a substrate 1110 (with printed circuit features 1112), a first lead frame portion 1120a, a second lead frame portion 1120b, a first semiconductor die 1030, a second semiconductor die 1140a, a third semiconductor die 1140b, a wire bond 1150, and a molding compound 1160. (As shown...) Figure 11 As shown, signal leads 1122, 1124, 1126, and 1128 extend into the molding compound and are coupled to corresponding corners of the substrate 1110 on a first surface of the substrate 1110. Signal leads 1122 and 1124 are adjacent to each other and centrally positioned within the linearly arranged signal leads of the lead frame portion 1120a. Similarly, signal leads 1124 and 1126 are adjacent to each other and centrally positioned within the linearly arranged signal leads of the lead frame portion 1120b.

[0051] Signal leads 1122 and 1124 also define a die attachment paddle for the first semiconductor die 1030, while signal lead 1126 defines a die attachment paddle for the second semiconductor die 1140a, and signal lead 1128 defines a die attachment paddle for the third semiconductor die 1140b. Figure 11 As shown, a first semiconductor die 1030 is disposed on a die attachment paddle defined by signal leads 1122 and 1124, on the same surface as the signal leads 1122 and 1124 coupled to the substrate 1110. Furthermore, in assembly 1000, a second semiconductor die 1140a is disposed on a die attachment paddle defined by signal lead 1126, on the same surface as the signal lead 1126 coupled to the substrate 1110. Similarly, in assembly 1100, a third semiconductor die 1140b is disposed on a die attachment paddle defined by signal lead 1128, on the same surface as the signal lead 1128 coupled to the substrate 1110.

[0052] Figure 12 This is an exploded view of the electronic device assembly 1000 of the 10A-10C series. Figure 12 The exploded view illustrates the various components of assembly 1000. For example... Figure 12As shown, assembly 1000 includes a substrate 1010, lead frame portions 1020a and 1020b, a semiconductor die 1030, a semiconductor die 1040, a wire bond 1050, and a molding compound 1060. Figure 12 As shown, assembly 1000 may also include adhesive 1015, which may be solder or other suitable adhesive, said adhesive being used, for example, in... Figures 10A-10C In the arrangement shown, substrate 1010 is coupled to lead frame portions 1020a and 1020b. As discussed herein, substrate 1010 may have printed circuit traces (e.g., Cu traces) for coupling (soldering, etc.) substrate 1010 to lead frame portions 1020a and 1020b.

[0053] like Figure 12 The diagram further shows that assembly 1000 may also include die attachment materials 1032 and 1042, which may be solder, epoxy resin, die attachment film (DAF), etc. Depending on the specific embodiment, die attachment materials 1032 and 1042 may be conductive or non-conductive. For example, the use of conductive or non-conductive die attachment materials may depend on the specific circuit implemented in the positively attached semiconductor die. In assembly 1000, die attachment material 1032 may be used, for example, in... Figures 10A-10C In the arrangement shown, the semiconductor die 1030 is coupled to the lead frame portion 1020a. Furthermore, in the assembly 1000, the die attachment material 1042 can be used, for example, in… Figures 10A-10C The arrangement shown in the figure couples the semiconductor die 1040 to the lead frame portion 1020b.

[0054] The wire connection 1050 of device 1000 can be used, for example, in... Figures 10A-10C The arrangement shown in the diagram electrically couples semiconductor dies 1030 and 1040 to substrate 1010 and to signal leads to lead frame portions 1020a and 1020b. Figure 12 In the exploded view of assembly 1000, molding compound 1060 is shown separately. However, in device assembly 1000 (e.g., as... Figures 10A-10C In the diagram, molding compound 1060 (e.g., in an initial liquid form which subsequently solidifies into a solid form) can be used to encapsulate substrate 1010, semiconductor dies 1030 and 1040, wire bond 1050, adhesive 1015, die attachment materials 1032 and 1042, and portions of leadframe portions 1020a and 1020b.

[0055] Figure 13 This is a diagram illustrating a lead frame strip 1310 containing multiple individual lead frames 1320. A single lead frame 1320 (in...) Figure 13 (shown on the right) Figure 13The single lead frame 1320 is indicated by a dashed line 1315 within the lead frame strip 1310. It is also shown rotated 180 degrees in the horizontal plane from its orientation within the lead frame strip 1310. In some embodiments, the lead frame 1320 may be used, for example, to implement... Figure 1 Assembly 100 Figure 3 Assembly 300 Figures 6A-6C Assembly 600, and / or other electronic device assemblies.

[0056] like Figure 13 As shown, leadframe 1320 may include a first leadframe portion 1320a and a second leadframe portion 1320b, such as the leadframe portions described herein. In some embodiments, leadframe strips 1310 may be included in a leadframe matrix containing a plurality of leadframe strips. Leadframe strips 1310 (or a matrix of leadframe strips) can be used to produce a plurality of assemblies (e.g., using, for example, those described below). Figure 13-17 The manufacturing process described herein (manufacturing process, etc.). As part of this manufacturing process, individual assemblies may be separated from the lead frame strip 1310, for example, by separating each individual lead frame 1320 from the lead frame strip 1310 (separation, etc.).

[0057] Figure 14 , 15 Figures 1400, 1500, 1600, and 1700 are schematic diagrams illustrating manufacturing process flows 1400, 1500, 1600, and 1700, respectively, for producing electronic device assemblies such as those described herein. Figure 14-17 The diagrams illustrate examples of various process operations. The components and / or illustrations of the example electronic device assembly are used with the aid of these examples. Figure 14-17 The process operation. Although it does not include specific procedures. Figure 14-17 The process flow includes specific reference numerals for assemblies and assembly elements, but it should be noted that these process flows or similar process flows can be used to produce the assemblies described herein.

[0058] In some implementations, process flows 1400-1700 or similar process flows can be used to produce other electronic device assemblies. That is, while a specific instance of an assembly is referenced relative to process flow 1400-1700, other electronic device assemblies can be produced using process flow 1400-1700 or similar process flows. Accordingly, process flows 1400-1700 are given by way of example. Furthermore, in Figure 14-17 The process flow 1400-1700 is described for a single electronic device assembly, but the process can be used to produce multiple assemblies in parallel (e.g., in a lead frame strip), and the process is then divided (single-divided) into individual assemblies as part of the manufacturing process flow.

[0059] See Figure 14 The process flow is described in section 1400. In some implementation schemes, Figure 14 Process flow 1400 can be used to produce, for example, assemblies 100, 300, and 600 as described above. In process flow 1400, at process operation (operation) 1405, solder printing can be performed on a lead frame, where solder from the solder printing will be used to attach a substrate to the lead frame. At operation 1410, a ceramic substrate (or other dielectric substrate) can be flipped onto the solder printed from operation 1405 (attached to the solder, placed on the solder, etc.). At operation 1415, a solder reflow process can be performed to reflow the solder from solder printing operation 1405, for example, to securely couple the substrate to the lead frame. Flux removal can be performed at operation 1420 to remove residual flux from solder reflow operation 1415.

[0060] At operation 1425, a non-conductive epoxy resin may be applied to the substrate, wherein the non-conductive epoxy resin will be used to couple (attach, etc.) the semiconductor die to the substrate. In some embodiments, a conductive adhesive (epoxy resin, solder, etc.) may be used. In some embodiments, a die attachment film (conductive or non-conductive) may be used, and operation 1425 may be omitted. At operation 1430, in this example, a first semiconductor die may be attached to the substrate (coupled to the substrate, disposed on the substrate, etc.) using the non-conductive epoxy resin of operation 1425. At operation 1435, in this example, a second semiconductor die may be attached to the substrate (coupled to the substrate, disposed on the substrate, etc.) using the non-conductive epoxy resin of operation 1425. At operation 1440, die attachment curing (e.g., baking) may be performed to cure the non-conductive epoxy resin of operation 1425 and to fix the first and second semiconductor dies to the substrate (attach, etc.).

[0061] At operation 1445, thermo-ultrasonic wire bonding can be performed to electrically couple the first and second semiconductor dies to the substrate (e.g., to an isolation channel formed on the substrate) and to the signal leads of the leadframe. At operation 1450, a plasma cleaning process can be performed prior to transfer molding and post-mold curing processes. The molding process of operation 1450 can encapsulate the assembly (excluding the exposed portions of the leadframe) in a molding compound such as an epoxy molding compound. At operation 1455, a deflashing process can be performed to prepare the exposed portions of the leadframe for plating (e.g., to remove burrs, etc.). Also at operation 1455, the exposed portions of the leadframe can be plated (e.g., solder plating), and stress-relief baking can be performed.

[0062] At operation 1460, degate-deflash-dejunk (DDD), signal lead trimming and forming, and individual assembly separation, such as from leadframe strips, can be performed. At operation 1465, functional and electrical tests (e.g., high voltage and DC tests) can be performed on the assemblies, and the assemblies can be marked (e.g., with part numbers, etc.). At operation 1470, finishing processes can be performed, including packaging the produced assemblies for shipment (e.g., using tape and reels).

[0063] See Figure 15 The process flow is described in section 1500. In some implementation schemes, Figure 15 Process flow 1500 can be used to produce assemblies 200 and 1000 as described above. In process flow 1500, at process operation (operation) 1505, solder printing (or other adhesive printing) can be performed on the lead frame, where solder or adhesive will be used to attach the substrate to the lead frame. At operation 1510, a ceramic substrate (or other dielectric substrate) can be attached to (or disposed thereon) the solder or adhesive from operation 1505. At operation 1515, a solder reflow or adhesive curing process can be performed to reflow the solder from operation 1505 or cure the adhesive from operation 1505, for example, to securely couple the substrate to the lead frame. Flux removal can be performed at operation 1520 to remove residual flux from solder reflow operation 1515. In some embodiments, such as those using adhesives other than solder, operation 1520 can be omitted.

[0064] At operation 1525, the first semiconductor die may be attached to the lead frame (coupled to the lead frame, disposed on the lead frame, etc.) using a (conductive or non-conductive) die attachment film. At operation 1530, in this example, the second semiconductor die may be attached to the lead frame (coupled to the lead frame, disposed on the lead frame, etc.) using a (conductive or non-conductive) die attachment film. At operation 1535, die attachment curing (e.g., baking) may be performed to cure the die attachment film (of operations 1525 and 1530) and fix the first and second semiconductor dies to the lead frame (attached, etc.).

[0065] At operation 1540, thermo-ultrasonic wire bonding can be performed to electrically couple the first and second semiconductor dies to the substrate (e.g., to an isolation channel formed on the substrate) and to the signal leads of the leadframe. At operation 1545, a plasma cleaning process can be performed prior to transfer molding and post-molding curing processes. The molding process of operation 1545 can encapsulate the assembly (excluding the exposed portion of the leadframe) in a molding compound such as an epoxy molding compound.

[0066] At operation 1550, a deburring process can be performed to prepare the exposed portions of the leadframe for plating (e.g., to remove burrs, etc.). Also at operation 1550, the exposed portions of the leadframe can be plated (e.g., solder plating), and stress-relief baking can be performed. At operation 1555, DDD, signal lead trimming and forming, and individual assembly separation, such as from leadframe strips, can be performed. At operation 1560, functional and electrical tests (e.g., high voltage and DC tests) can be performed on the assemblies, and the assemblies can be marked (e.g., with part numbers, etc.). At operation 1565, a finishing process can be performed, including packaging the produced assemblies for shipment (e.g., using tape and reels).

[0067] See Figure 16 The process flow is described in section 1600. In some implementation schemes, Figure 16 The process flow 1600 can be used to produce, for example, assemblies 200 and 1100 as described above. Figure 16 The present invention illustrates, by way of example, an embodiment of a power converter electronic device assembly (having a control IC, a low-side metal-oxide-semiconductor field-effect transistor (MOSFET) IC, and a high-side MOSFET IC). In some embodiments, process flow 1600 can be used to produce other electronic device assemblies.

[0068] In process flow 1600, at process operation (operation) 1605, solder printing can be performed on the leadframe, wherein the solder will be used to couple (attach, etc.) the substrate to the leadframe, and to couple (attach, etc.) the low-side MOSFET IC and the high-side MOSFET IC to the leadframe. At operation 1610, a ceramic substrate (or other dielectric substrate) can be attached to the solder from operation 1605 (placed on said solder, etc.). At operation 1615, the low-side MOSFET IC (or, high-side MOSFET IC) can be attached to the solder from operation 1605 (placed on said solder, etc.). At operation 1620, the high-side MOSFET IC (or, low-side MOSFET IC) can be attached to the solder from operation 1605 (placed on said solder, etc.). At operation 1625, a solder reflow process can be performed to reflow the solder from operation 1605, for example, to permanently couple the substrate, the high-side MOSFET IC, and the low-side MOSFET IC to the leadframe. Flux removal can be performed at operation 1630 to remove residual flux from solder reflow operation 1625.

[0069] At operation 1635, the control IC may be coupled to the lead frame (attached to the lead frame, placed on the lead frame, etc.) using, for example, a (conductive or non-conductive) die attachment film or adhesive. At operation 1640, die attachment curing (e.g., baking) may be performed to cure the die attachment film or adhesive of operation 1635 and fix the control IC to the lead frame (attached, etc.).

[0070] At operation 1645, thermo-ultrasonic wire bonding can be performed to electrically couple the low-side MOSFET, high-side MOSFET, and control IC to the substrate (e.g., to an isolation channel formed on the substrate) and to the signal leads of the leadframe. At operation 1650, a plasma cleaning process can be performed prior to transfer molding and post-mold curing processes. The molding process of operation 1650 can encapsulate the assembly (excluding the exposed portion of the leadframe) in a molding compound such as an epoxy molding compound.

[0071] At operation 1655, a deburring process can be performed to prepare the exposed portions of the leadframe for plating (e.g., to remove burrs, etc.). Also at operation 1655, the exposed portions of the leadframe can be plated (e.g., solder plating), and stress-relief baking can be performed. At operation 1660, DDD, signal lead trimming and forming, and individual assembly separation, such as from leadframe strips, can be performed. At operation 1665, functional and electrical tests (e.g., high voltage and DC tests) can be performed on the assemblies, and the assemblies can be marked (e.g., with part numbers, etc.). At operation 1670, a finishing process can be performed, including packaging the produced assemblies for shipment (e.g., using tape and reels).

[0072] See Figure 17 This describes process flow 1700. Similar to process flow 1600, in some implementation schemes, Figure 17 The process flow 1700 can be used to produce, for example, assemblies 200 and 1100 as described above. As... Figure 16 In Figure 17 The present invention illustrates, by way of example, an embodiment of a power converter electronic device assembly (having a control IC, a low-side MOSFET IC, and a high-side MOSFET IC). In some embodiments, process flow 1700 can be used to produce other electronic device assemblies.

[0073] In process flow 1700, at operation 1705, solder printing (or other adhesive printing) may be performed on the leadframe, wherein solder or adhesive will be used to attach the substrate to the leadframe. At operation 1710, a ceramic substrate (or other dielectric substrate) may be attached to (or disposed thereon) the solder or adhesive from operation 1705. At operation 1715, a solder reflow or adhesive curing process may be performed to reflow the solder from operation 1705 or cure the adhesive from operation 1705, for example, to securely couple the substrate to the leadframe. Flux removal may be performed at operation 1720 to remove residual flux from solder reflow operation 1715. In some embodiments, such as those using adhesives other than solder, operation 1720 may be omitted.

[0074] At operation 1725, the control IC may be coupled to the leadframe using a (conductive or non-conductive) die attachment film (attached to the leadframe, mounted on the leadframe, etc.). At operation 1730, in this example, the low-side MOSFET IC may be attached to the leadframe using, for example, a (conductive or non-conductive) die attachment film or other die attachment adhesive (coupled to the leadframe, mounted on the leadframe, etc.). At operation 1735, in this example, the high-side MOSFET IC may be attached to the leadframe using, for example, a (conductive or non-conductive) die attachment film or other die attachment adhesive (coupled to the leadframe, mounted on the leadframe, etc.). In some embodiments, the order in which the IC is coupled to the leadframe may vary. At operation 1740, die attachment curing (e.g., baking) can be performed to cure (operations 1725, 1730 and 1735) the die attachment film and / or other die attachment adhesive, and to securely couple (attach, etc.) the control IC, low-side MOSFET IC and high-side MOSFET IC to the lead frame.

[0075] At operation 1745, thermo-ultrasonic wire bonding can be performed to electrically couple the low-side MOSFET, high-side MOSFET, and control IC to the substrate (e.g., to an isolation channel formed on the substrate) and to the signal leads of the leadframe. At operation 1750, a plasma cleaning process can be performed prior to the transfer molding and post-curing processes. The molding process of operation 1750 can encapsulate the assembly (excluding the exposed portion of the leadframe) in a molding compound such as an epoxy molding compound.

[0076] At operation 1755, a deburring process can be performed to prepare the exposed portions of the leadframe for plating (e.g., to remove burrs, etc.). Also at operation 1755, the exposed portions of the leadframe can be plated (e.g., solder plating), and stress-relief baking can be performed. At operation 1760, DDD, signal lead trimming and forming, and individual assembly separation, such as from leadframe strips, can be performed. At operation 1765, functional and electrical tests (e.g., high voltage and DC tests) can be performed on the assemblies, and the assemblies can be marked (e.g., with part numbers, etc.). At operation 1770, a finishing process can be performed, including packaging the produced assemblies for shipment (e.g., using tape and reels).

[0077] In some embodiments, a first semiconductor die may be disposed on a first signal lead and a second signal lead of a first plurality of signal leads, on corresponding identical surfaces of the first signal leads and the second signal leads of the first plurality of signal leads coupled to a dielectric substrate. A second semiconductor die may be disposed on a first signal lead and a second signal lead of a second plurality of signal leads, on corresponding identical surfaces of the first signal leads and the second signal leads of the second plurality of signal leads coupled to a dielectric substrate.

[0078] In some embodiments, a first semiconductor die may be disposed on a first signal lead and a second signal lead of a first plurality of signal leads, wherein a corresponding first surface of the first signal lead and the second signal lead of the first plurality of signal leads is opposite to a corresponding second surface of the first signal lead and the second signal lead of the first plurality of signal leads coupled to a dielectric substrate. A second semiconductor die may be disposed on a first signal lead and a second signal lead of a second plurality of signal leads, wherein a corresponding first surface of the first signal lead and the second signal lead of the second plurality of signal leads is opposite to a corresponding second surface of the first signal lead and the second signal lead of the second plurality of signal leads coupled to a dielectric substrate.

[0079] In some embodiments, the electronic device assembly may include a non-conductive adhesive that couples a first semiconductor die to a first signal lead and a second signal lead of a first plurality of signal leads, and couples a second semiconductor die to a first signal lead and a second signal lead of a second plurality of signal leads.

[0080] The various devices and techniques described herein can be implemented using a variety of semiconductor processing and / or packaging techniques. Some embodiments may be implemented using different types of semiconductor processing techniques associated with semiconductor substrates, which include (but are not limited to) silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like.

[0081] It will also be understood that when a component, such as a layer, region, or substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another component, it may be directly on, directly connected to, or directly coupled to the other component, or there may be one or more intermediate components. In contrast, when a component is referred to as being directly on, directly connected to, or directly coupled to another component or layer, there are no intermediate components or layers.

[0082] Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used extensively in the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to may be referred to as such. The claims of this application may be amended to describe the exemplary relationships described in the specification or shown in the figures.

[0083] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. Spatial relation terms (e.g., above, over, upper, below, under, lower, etc.) are intended to cover different orientations of the device in use or operation other than those depicted in the figures. In some embodiments, the relation terms above and below may respectively include vertical above and vertical below. In some embodiments, the term proximity may include lateral proximity or horizontal proximity.

[0084] While certain features of the described embodiments have been illustrated herein, those skilled in the art will now appreciate many modifications, substitutions, alterations, and equivalents. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations as fall within the scope of the embodiments. It should be understood that they have been presented by way of example only and not as limitation, and various changes in form and detail may be made. Any part of the apparatus and / or method described herein can be combined in any combination, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. An electronic device assembly comprising: A dielectric substrate having a first surface and a second surface opposite to the first surface, the dielectric substrate comprising: A first unidirectional isolation channel is defined thereon, the first unidirectional isolation channel having an input terminal and an output terminal; as well as A second unidirectional isolation channel defined thereon, the second unidirectional isolation channel having an input terminal and an output terminal, wherein the first unidirectional isolation channel and the second unidirectional isolation channel are configured to perform bidirectional data communication; The lead frame includes: A first lead frame portion comprising a plurality of signal leads, wherein a first corner of the first surface of the dielectric substrate is coupled to a first signal lead of the plurality of signal leads, and a second corner of the first surface of the dielectric substrate is coupled to a second signal lead of the plurality of signal leads; as well as A second lead frame portion including a second plurality of signal leads, wherein a third corner of the first surface of the dielectric substrate is coupled to a first signal lead of the second plurality of signal leads, and a fourth corner of the first surface of the dielectric substrate is coupled to a second signal lead of the second plurality of signal leads; and Semiconductor dies disposed on at least one of the following: The first signal lead of the first plurality of signal leads; or The second signal lead of the first plurality of signal leads, The semiconductor die is electrically coupled to at least one signal lead of the first plurality of signal leads, the input terminal of the first unidirectional isolation channel, and the output terminal of the second unidirectional isolation channel using corresponding wire connections.

2. The electronic device assembly of claim 1, wherein the semiconductor die is a first semiconductor die, and the electronic device assembly further comprises: A second semiconductor die disposed on at least one of the following: The first signal lead of the second plurality of signal leads; or The second signal lead of the second plurality of signal leads, The second semiconductor die is electrically coupled to at least one signal lead of the second plurality of signal leads, the output terminal of the first unidirectional isolation channel, and the input terminal of the second unidirectional isolation channel using corresponding wire connections. The first semiconductor die is disposed on the first signal lead and the second signal lead of the first plurality of signal leads, on the corresponding identical surfaces of the first signal lead and the second signal lead of the first plurality of signal leads coupled to the dielectric substrate. The second semiconductor die is disposed on the first signal lead and the second signal lead of the second plurality of signal leads, on the same surface of the first signal lead and the second signal lead of the second plurality of signal leads coupled to the dielectric substrate.

3. The electronic device assembly of claim 1, wherein the semiconductor die is a first semiconductor die, and the electronic device assembly further comprises: A second semiconductor die disposed on at least one of the following: The first signal lead of the second plurality of signal leads; or The second signal lead of the second plurality of signal leads, The second semiconductor die is electrically coupled to at least one signal lead of the second plurality of signal leads, the output terminal of the first unidirectional isolation channel, and the input terminal of the second unidirectional isolation channel using corresponding wire connections. The first semiconductor die is disposed on a corresponding first surface of the first signal lead and the second signal lead of the first plurality of signal leads, the corresponding first surface being opposite to a corresponding second surface of the first signal lead and the second signal lead of the first plurality of signal leads coupled to the dielectric substrate. The second semiconductor die is disposed on a corresponding third surface of the first signal lead and the second signal lead of the second plurality of signal leads, the corresponding third surface being opposite to a corresponding fourth surface of the first signal lead and the second signal lead of the second plurality of signal leads coupled to the dielectric substrate.

4. The electronic device assembly of claim 1, wherein the semiconductor die is a first semiconductor die, and the electronic device assembly further comprises: A second semiconductor die disposed on at least one of the following: The first signal lead of the second plurality of signal leads; or The second signal lead of the second plurality of signal leads; and A non-conductive adhesive couples the first semiconductor die to at least one of the first signal leads or the second signal leads of the first plurality of signal leads, and couples the second semiconductor die to at least one of the first signal leads or the second signal leads of the second plurality of signal leads. The second semiconductor die is electrically coupled to at least one signal lead of the second plurality of signal leads, the output terminal of the first unidirectional isolation channel, and the input terminal of the second unidirectional isolation channel using corresponding wire connections.

5. The electronic device assembly of claim 1, wherein the first plurality of signal leads are arranged linearly along a first edge of the electronic device assembly, and the second plurality of signal leads are arranged linearly along a second edge of the electronic device assembly. The first signal lead of the first plurality of signal leads is disposed at the first end of the first plurality of signal leads on the first edge of the electronic device assembly. The second signal lead of the first plurality of signal leads is disposed at the second end of the first plurality of signal leads on the first edge of the electronic device assembly. The first signal lead of the second plurality of signal leads is disposed at the first end of the second plurality of signal leads on the second edge of the electronic device assembly, and The second signal lead of the second plurality of signal leads is disposed at the second end of the second plurality of signal leads on the second edge of the electronic device assembly.

6. The electronic device assembly of claim 1, wherein the first plurality of signal leads are arranged linearly along a first edge of the electronic device assembly, and the second plurality of signal leads are arranged linearly along a second edge of the electronic device assembly. The first signal lead and the second signal lead of the first plurality of signal leads are adjacent to each other and centrally located within the first plurality of signal leads on the first edge of the electronic device assembly. The first signal lead of the second plurality of signal leads and the second signal lead of the second plurality of signal leads are adjacent to each other and are centrally located in the second plurality of signal leads on the second edge of the electronic device assembly.

7. The electronic device assembly according to claim 1, wherein: The signal leads of the first plurality of signal leads, excluding the first signal lead and the second signal lead of the first plurality of signal leads, are spaced apart from the dielectric substrate; and The signal leads of the second plurality of signal leads, excluding the first signal lead and the second signal lead of the second plurality of signal leads, are spaced apart from the dielectric substrate.

8. An electronic device assembly comprising: A dielectric substrate having a first surface and a second surface opposite to the first surface, the dielectric substrate comprising: The first unidirectional isolation channel limited thereto, and A second unidirectional isolation channel defined thereon, wherein the first unidirectional isolation channel and the second unidirectional isolation channel are configured to perform bidirectional data communication; The lead frame includes: A first lead frame portion includes a first plurality of signal leads arranged linearly along a first edge of the electronic device assembly. A first corner of the first surface of the dielectric substrate is disposed at and coupled to a first signal lead of the first plurality of signal leads. The first signal lead of the first plurality of signal leads is disposed at a first end of the first plurality of signal leads on the first edge of the electronic device assembly. A second corner of the first surface of the dielectric substrate is disposed at and coupled to a second signal lead of the first plurality of signal leads. The second signal lead of the first plurality of signal leads is disposed at a second end of the first plurality of signal leads on the first edge of the electronic device assembly. Other signal leads of the first plurality of signal leads are spaced apart from the dielectric substrate. as well as The second lead frame portion includes a second plurality of signal leads arranged linearly along a second edge of the electronic device assembly. A third corner of the first surface of the dielectric substrate is disposed at and coupled to a first signal lead of the second plurality of signal leads. The first signal lead of the second plurality of signal leads is disposed at a first end of the second plurality of signal leads on the second edge of the electronic device assembly. A fourth corner of the first surface of the dielectric substrate is disposed at and coupled to a second signal lead of the second plurality of signal leads. The second signal lead of the second plurality of signal leads is disposed at a second end of the second plurality of signal leads on the second edge of the electronic device assembly. Other signal leads of the second plurality of signal leads are spaced apart from the dielectric substrate. as well as Semiconductor dies, which are placed in: On the first signal lead of the first plurality of signal leads; and On the second signal lead of the first plurality of signal leads, The semiconductor die is electrically coupled to at least one signal lead of the first plurality of signal leads and to the first and second unidirectional isolation channels on the dielectric substrate using corresponding wire bonding.

9. The electronic device assembly of claim 8, wherein the semiconductor die is a first semiconductor die, and the electronic device assembly further comprises: The second semiconductor die is disposed at: On the first signal lead of the second plurality of signal leads; as well as On the second signal lead of the second plurality of signal leads, The second semiconductor die is electrically coupled to at least one signal lead of the second plurality of signal leads and the dielectric substrate using corresponding wire bonding.

10. The electronic device assembly of claim 9, further comprising a non-conductive adhesive that couples the first semiconductor die to the first signal leads and the second signal leads of the first plurality of signal leads, and couples the second semiconductor die to the first signal leads and the second signal leads of the second plurality of signal leads. The dielectric substrate is coupled to the first signal lead of the first plurality of signal leads, the second signal lead of the first plurality of signal leads, the first signal lead of the second plurality of signal leads, and the second signal lead of the second plurality of signal leads via corresponding electrically isolated copper traces disposed on the first surface of the dielectric substrate.

11. An electronic device assembly, comprising: A dielectric substrate having a first surface and a second surface opposite to the first surface, the dielectric substrate comprising: The first unidirectional isolation channel limited thereto, and A second unidirectional isolation channel defined thereon, wherein the first unidirectional isolation channel and the second unidirectional isolation channel are configured to perform bidirectional data communication; The lead frame includes: The first lead frame portion includes a first plurality of signal leads; and The second lead frame portion contains a second plurality of signal leads. The dielectric substrate is coupled to a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. The signal leads of the first plurality of signal leads, excluding the subset thereof, are spaced apart from the dielectric substrate. The signal leads of the second plurality of signal leads, excluding the subset thereof, are spaced apart from the dielectric substrate. A first semiconductor die is disposed on the subset of the first plurality of signal leads, the first semiconductor die being electrically coupled to at least one signal lead of the first plurality of signal leads and to the first unidirectional isolation channel and the second unidirectional isolation channel on the dielectric substrate using corresponding wire bonding; as well as A second semiconductor die is disposed on the subset of the second plurality of signal leads, the second semiconductor die being electrically coupled to at least one signal lead of the second plurality of signal leads and to the first unidirectional isolation channel and the second unidirectional isolation channel on the dielectric substrate using corresponding wire bonding.

12. The electronic device assembly of claim 11, further comprising: A molding compound that encapsulates the first semiconductor die, the second semiconductor die, the corresponding wire bond, at least a portion of the first lead frame portion, and at least a portion of the second lead frame portion; as well as A non-conductive adhesive couples the first semiconductor die to the subset of the first plurality of signal leads, and couples the second semiconductor die to the subset of the second plurality of signal leads. The first semiconductor die is disposed on the subset of the first plurality of signal leads, and The second semiconductor die is disposed on the subset of the second plurality of signal leads.

13. The electronic device assembly of claim 11, further comprising a third semiconductor die, the third semiconductor die being electrically coupled to at least one signal lead of the second plurality of signal leads and electrically coupled to the dielectric substrate using corresponding wire bonding. The third semiconductor die is disposed on one of the following: The subset of the first plurality of signal leads; or The subset of the second plurality of signal leads.

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