Three-dimensional memory central bit line architecture, three-dimensional memory, and methods of making the same

Abstract

The disclosure provides a three-dimensional memory central bit line architecture, a three-dimensional memory and a preparation method thereof, and relates to the technical field of three-dimensional memories. The central bit line architecture comprises: oppositely arranged first and second common sources; a plurality of layers of word lines stacked between the first and second common sources along a first direction; a plurality of channel holes penetrating through the plurality of layers of word lines and connecting the first and second common sources, each channel hole forming a byte string; and a plurality of central bit lines arranged at the middle part of the channel holes and spaced apart along a second direction intersecting the first direction; wherein a volume formed by the plurality of layers of word lines and the plurality of byte strings forms a total block, and the plurality of central bit lines divide the total block into a first sub-block located at an upper part and a second sub-block located at a lower part to drive the byte strings in the first sub-block and the second sub-block, respectively. The disclosure reduces the block capacity and the channel length (i.e. channel resistance), and conforms to the development trend of future three-dimensional memories.

Description

Technical Field

[0001] This disclosure relates to the field of three-dimensional memory technology, and in particular to a central bitline architecture for a three-dimensional memory, a three-dimensional memory, and a method for fabricating the same. Background Technology

[0002] As the number of word lines in 3D NAND flash memory continues to increase—for example, from 128 layers to 240 layers to over 300 layers—while the page size remains constant (16K bytes), the block size of NAND flash memory is constantly increasing, from 45 Mbit to 80 Mbit to over 140 Mbit. This continuous increase in block size presents increasingly greater technical challenges for improving system performance and also makes improving product yield more difficult. Reducing block size is a major future technical requirement and challenge.

[0003] As the number of word line layers in 3D memory continues to increase, the channel length also lengthens, from 5-6 micrometers in 128-layer memory to 14-18 micrometers in the subsequent 300 layers. Simultaneously, to reduce various noise interferences, the channel thickness decreases from 6-7 nanometers to 5-6 nanometers. Consequently, the channel resistance increases dramatically, and the channel current decreases rapidly. It is anticipated that after 500 layers, traditional polysilicon channel materials will no longer be able to provide sufficient current to support signal reading.

[0004] Electrical half-block erase can partially reduce block size. However, due to significant erase interference, its cycling endurance is insufficient for practical applications. Furthermore, half-block erase cannot overcome the physical bottleneck of reducing channel current. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a central bit line architecture for a three-dimensional memory.

[0006] The first aspect of this disclosure provides a three-dimensional memory central bit line architecture, including: a first common source and a second common source disposed opposite to each other; multiple word lines stacked between the first common source and the second common source along a first direction; a plurality of channel holes penetrating the multiple word lines and connecting the first common source and the second common source, each channel hole forming a byte string; a plurality of central bit lines located in the middle of the channel holes and spaced apart along a second direction intersecting the first direction; wherein the body formed by the multiple word lines and the plurality of byte strings forms a total block, and the plurality of central bit lines divide the total block into a first sub-block located at the upper part and a second sub-block located at the lower part, so as to drive the byte strings inside the first sub-block and the second sub-block respectively.

[0007] Furthermore, the multi-layer word lines are separated, with an insulating layer between adjacent word lines.

[0008] Furthermore, the word line closest to the first common source in the first sub-block and the word line closest to the second common source in the second sub-block are both set as bottom select lines; the word line closest to the center bit line in the first sub-block and the word line closest to the center bit line in the second sub-block are both set as serial select lines.

[0009] Furthermore, the channel holes in the first sub-block and the second sub-block are connected by a plurality of central bit line connection holes disposed in the middle, and the central bit line connection holes intersect the plurality of central bit lines.

[0010] Furthermore, each of the central bit line connection holes is eccentrically positioned with respect to the connected byte string.

[0011] Furthermore, there are multiple string selection lines, each of which intersects and cuts along the arrangement direction of multiple byte strings to form a zigzag cutting path.

[0012] A second aspect of this disclosure provides a three-dimensional memory including the aforementioned three-dimensional memory central bitline architecture.

[0013] A third aspect of this disclosure provides a method for fabricating a three-dimensional memory, comprising: step S1, depositing a multilayer stacked structure on a substrate, each layer of the stacked structure including a sacrificial layer and an insulating layer; step S2, simultaneously etching multiple vias and word line scribes on the multilayer stacked structure; step S3, simultaneously filling gate stacks within the multiple vias and word line scribes, followed by filling a core insulating layer; step S4, wet etching the gate stacks and core insulating layers within the word line scribes; step S5, removing the sacrificial layer within the multilayer stacked structure, replacing it with a word line layer, and after planarization, forming a second sub-block located at the bottom; step S6. Step S7: Sequentially deposit an insulating layer, a serial select line dicing, and an insulating layer on the second sub-block; Step S8: Etch multiple central bit line connection holes, and sequentially deposit an insulating layer and a core metal layer in each central bit line connection hole; Step S9: Etch the serial select line dicing, fill the serial select line dicing with an insulating layer, and after planarization, form the lower serial select line; Step S10: Form multiple central bit lines on the serial select line; Step S11: Repeat steps S3 to S5 to form the upper serial select line; Step S2: Repeat steps S3 to S5 to form the upper first sub-block.

[0014] Further, in step S1, the substrate includes a silicon wafer substrate, the sacrificial layer material is silicon nitride or doped silicon nitride, and the insulating layer material is silicon oxide or a low dielectric constant material.

[0015] Furthermore, in step S2, the width of the character line cutting channel is greater than twice the diameter of the channel hole, and the character line cutting channel is opened on both sides of the plurality of channel holes.

[0016] Further, in step S3, the gate stack includes a TANOS structure, and the core insulating layer material includes silicon oxide.

[0017] Furthermore, in step S5, the word line layer material includes tungsten or molybdenum.

[0018] Further, in step S6, the string selection line is made of a metallic material, including tungsten or polycrystalline silicon.

[0019] Further, in step S7, the plurality of central bit line connection holes are arranged at intervals and are eccentrically arranged with the connected byte string, and the core metal layer includes tungsten.

[0020] Furthermore, in step S8, the string selection line cutting path is zigzag, and the cutting depth is not deeper than the top of the byte string of the second sub-block.

[0021] Further, in step S9, the multiple central bit lines intersect the direction of the word line layer, and the central bit line connecting holes are arranged at intervals. After planarization, multiple central bit lines are formed.

[0022] Compared with the prior art, the three-dimensional memory central bit line architecture, three-dimensional memory and its fabrication method provided in this disclosure have at least the following beneficial effects:

[0023] (1) This disclosure combines a three-dimensional semiconductor memory structure and integration technology with a central bit line to place the central bit line inside the memory array and drive the byte string in two directions.

[0024] (2) According to the number of embedded word lines set in the array, the block capacity can be reduced to 1 / 2, 1 / 3 or even 1 / n, which reduces both the block capacity and the channel length (i.e., channel resistance), which is in line with the future development trend of three-dimensional memory.

[0025] (3) The preparation method disclosed herein has high process feasibility and strong practical prospects. Attached Figure Description

[0026] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0027] Figure 1 The diagram schematically illustrates a cross-sectional view of the basic architecture of a traditional three-dimensional memory.

[0028] Figure 2 A schematic cross-sectional view of a three-dimensional memory central bitline architecture according to an embodiment of the present disclosure is shown.

[0029] Figure 3 The diagram schematically illustrates a cross-sectional view and top sectional views of part A and part B of a three-dimensional memory central bitline architecture according to an embodiment of the present disclosure, wherein part A in the left diagram is a top sectional view, part B in the left diagram is a top sectional view, and the right diagram is a cross-sectional view.

[0030] Figure 4 A flowchart illustrating a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure is shown schematically;

[0031] Figure 5A The diagram schematically illustrates a cross-sectional and partial top view of a channel hole and word line cut track etched simultaneously according to another embodiment of the present disclosure, wherein the left view is a top cross-sectional view and the right view is a cross-sectional view;

[0032] Figure 5B The diagram schematically illustrates a cross-sectional view and a partial top view of a second sub-block located at the lower part according to another embodiment of the present disclosure, wherein the left view is a top view and the right view is a cross-sectional view;

[0033] Figure 5C The diagram schematically illustrates a cross-sectional view and a partial top view of the lower string selection line according to another embodiment of the present disclosure, wherein the left view is a top view and the right view is a cross-sectional view;

[0034] Figure 5D The diagram schematically shows a cross-section and a partial top view of the central alignment line according to another embodiment of the present disclosure, wherein part A in the upper left corner is a top view and the right view is a cross-sectional view;

[0035] Figure 5E A partial cross-sectional view of the upper string selection line is schematically shown according to another embodiment of the present disclosure;

[0036] Figure 5F A cross-sectional view of the upper first sub-block is schematically shown according to another embodiment of the present disclosure.

[0037] [Explanation of Labels in the Attached Image]

[0038] ACS1 - First common source; ACS2 - Second common source; bottom select line; stringselect line; WL - Word line; CBL - Center bit line; CBL plug - Center bit line connector; SSL cut - String select line cut track; string - Byte string; channel - Channel hole; 10 - Silicon wafer substrate; 201 - Insulating layer; 202 - Sacrificial layer; 30 - Word line cut track. Detailed Implementation

[0039] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0040] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0041] In describing the embodiments of this disclosure in detail, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0042] Figure 1 The diagram schematically illustrates a cross-sectional view of the basic architecture of a conventional three-dimensional memory.

[0043] like Figure 1As shown, the basic architecture of a traditional three-dimensional memory places the common source (ACS) at the bottom of the array and the bit line (BL) at the top. Each word line (WL) constitutes a page. Channels pass through all word lines, connecting the ACS and bit lines to form a string. The volume formed by all the string strings and word lines constitutes a block. Typically, the word line closest to the ACS in a multi-layered word line array is the bottom select line, while the word line closest to the bit line is the string select line.

[0044] However, the above-mentioned basic architecture of traditional three-dimensional memory has the problems of excessively large block capacity and excessively high channel resistance.

[0045] In view of this, this disclosure combines a three-dimensional semiconductor memory structure with a central bit line and integration technology to provide a novel three-dimensional memory central bit line architecture. This disclosure also provides a three-dimensional memory using this central bit line architecture, and a method for fabricating the three-dimensional memory.

[0046] The technical solution of this disclosure will be described in detail below with reference to the structure of the central bit line architecture of the three-dimensional memory in a specific embodiment of this disclosure. It should be understood that the following... Figures 2-3 The material layers, shapes, and structures of the various parts of the three-dimensional memory central bit line architecture shown are merely exemplary to help those skilled in the art understand the technical solutions of this disclosure, and are not intended to limit the scope of protection of this disclosure.

[0047] In a first exemplary embodiment of this disclosure, a three-dimensional memory central bitline architecture is provided.

[0048] Figure 2 A cross-sectional view of a central bitline architecture of a three-dimensional memory according to an embodiment of the present disclosure is shown schematically.

[0049] like Figure 2 As shown, the three-dimensional memory central bit line architecture according to this embodiment includes: a first common source (ACS1) and a second common source (ACS2) disposed opposite to each other; a multi-layer word line (WL) stacked between the first common source and the second common source along a first direction; a plurality of channel holes passing through the multi-layer word lines and connecting the first common source and the second common source, each channel hole forming a byte string; and a plurality of center bit lines (CBLs) located in the middle of the channel holes and arranged at intervals along a second direction intersecting the first direction.

[0050] The body, consisting of multiple word lines and multiple byte strings, forms a total block. Multiple central bit lines divide the total block into a first sub-block at the top and a second sub-block at the bottom, respectively driving the byte strings within the first and second sub-blocks.

[0051] In this embodiment, multiple layers of character lines are separated, with an insulating layer between adjacent layers. For details, please refer to [link to specific examples]. Figure 2 Between the first common source and the second common source, an insulating layer is stacked on each word line, and thus word lines and insulating layers are stacked in sequence to ensure that the structures closest to the first common source and the second common source are all insulating layers, so as to separate each common source and the word line closest to the common source.

[0052] In this embodiment, the word line closest to the first common source in the first sub-block and the word line closest to the second common source in the second sub-block are both set as bottom select lines. The word line closest to the center bit line in the first sub-block and the word line closest to the center bit line in the second sub-block are both set as string select lines.

[0053] Figure 3 The diagram schematically illustrates a cross-sectional view and top sectional views of part A and part B of a three-dimensional memory central bitline architecture according to an embodiment of the present disclosure, wherein part A in the left diagram is a top sectional view, part B in the left diagram is a top sectional view, and the right diagram is a cross-sectional view.

[0054] like Figure 3 As shown, part A is to show the positional relationship between the central bit line and the central bit line connecting hole, and part B is to show the positional relationship between the central bit line connecting hole and the connected byte string.

[0055] like Figure 3 As shown in the top view of section A, in this embodiment, the channel holes in the first sub-block and the second sub-block are connected by multiple center bit-line connectors (CBL plugs) located in the middle. These CBL plugs intersect and pass through multiple center bit-lines (CBLs). As can be seen from the figure, in the top view, the CBL plugs pass through each center bit-line and intersect, resulting in a staggered arrangement of all CBL plugs, achieving inter-position connection.

[0056] like Figure 3As shown in the top view of section B, in this embodiment, each central bit line connector (CBL plug) is offset from the connected string. For example, as can be seen from the figure, in the top view, some central bit line connectors are offset to the left of the connected string, while others are offset to the right.

[0057] For further information, please refer to [link / reference]. Figure 3 In the top-view cross-section of section B, there are multiple string select lines. Each string select line intersects and cuts along the arrangement direction of multiple byte strings to form a zigzag cut (SSL cut). Specifically, as shown in the figure, along the first direction (i.e., the stacking direction of multiple word lines), the string select lines are respectively set above and below the center bit-line (CBL). Along the second direction (i.e., the parallel arrangement direction of multiple center bit lines), each string select line intersects and cuts along the arrangement direction of multiple byte strings to form a zigzag cut. For example, in the top-view cross-section, that is, at the same height in the first direction, three zigzag cuts (SSL cuts) can be set to keep the number of multiple byte strings balanced in the second direction.

[0058] Through the above embodiments, the three-dimensional memory central bit-line architecture provided in this disclosure places the central bit-line inside the memory array, driving byte strings in two directions. A common source (ACS) is provided at the top and bottom of the channel via, and the central bit-line (CBL) divides the block into two sub-blocks, facilitating system application. Using the central bit-line architecture, the block volume is halved, and the channel length is also halved, thus simultaneously achieving the technical effects of halving both block capacity and channel resistance.

[0059] Similarly, based on the central bit line architecture of the three-dimensional memory provided in this disclosure, the block capacity can be reduced to 1 / 2, 1 / 3 or even 1 / n depending on the number of embedded word lines set inside the array. This solves the problems of excessively large block capacity and excessively large channel resistance, reducing both the block capacity and the channel length (i.e., channel resistance), which is in line with the future development trend of three-dimensional memory.

[0060] It should be noted that, Figure 2 and Figure 3This is only a partial structural diagram of the central bit line architecture of a three-dimensional memory provided in a specific embodiment of this disclosure. It does not represent a limitation on the number of layers of embedded central bit lines in the array of the central bit line architecture of the three-dimensional memory provided in this disclosure. The number of layers, the number of channel layer arrays, the number of word line layers and the number of central bit line layers of the three-dimensional memory provided in this disclosure can all be set according to the actual application. The embodiments of this disclosure do not limit this.

[0061] In a second exemplary embodiment of this disclosure, a three-dimensional memory is provided, comprising any of the three-dimensional memory central bitline architectures mentioned in the first exemplary embodiment of this disclosure.

[0062] The three-dimensional memory provided in this embodiment can reduce the block capacity to 1 / 2, 1 / 3 or even 1 / n depending on the number of embedded word lines set inside the array. This reduces both the block capacity and the channel length (i.e., channel resistance), which is in line with the future development trend of three-dimensional memory.

[0063] In a third exemplary embodiment of this disclosure, a method for fabricating the above-described three-dimensional memory is provided.

[0064] Figure 4 A flowchart illustrating a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure is shown.

[0065] like Figure 4 As shown, the method for fabricating a three-dimensional memory according to this embodiment includes steps S1 to S11.

[0066] Step S1: Deposit a multilayer stacked structure on the substrate, each stacked structure including a sacrificial layer and an insulating layer.

[0067] For example, the substrate includes a silicon wafer substrate 10, the sacrificial layer 202 material can be silicon nitride or silicon nitride doped with other components (such as carbon), and the insulating layer 201 material can be silicon oxide or a low dielectric constant (10w-k) material.

[0068] Step S2: Simultaneously etch multiple channel holes and word line cutting paths on the multi-layer stacked structure.

[0069] Figure 5A The illustration schematically shows cross-sectional and partial top sectional views of synchronously etched channel holes and word line cut paths according to another embodiment of the present disclosure, wherein the left image is a top sectional view and the right image is a cross-sectional view. Specifically, as Figure 5A As shown, the channel and word line cutting 30 are etched and formed simultaneously. The width of the word line cutting 30 is more than twice the diameter of the channel, and the word line cutting 30 is opened on both sides of multiple channel holes.

[0070] Step S3: Simultaneously fill the grid stack in multiple channel holes and word line cutting channels, and then fill the core insulation layer.

[0071] Within multiple vias and word line cuts, the gate stack of the memory cells is first filled synchronously; this gate stack can be, for example, a TANOS structure. Then, a core insulating layer is filled; this core insulating layer material can be, for example, silicon oxide.

[0072] Because the width of the letter line cutting track is more than twice the diameter of the channel hole, the letter line cutting track remains open even after the channel hole is filled.

[0073] Step S4: Wet etching of the gate stack and core insulation layer within the letter line cutting channel.

[0074] Wet etching was used to etch the gate stack and core insulating layer within the word line cut channels. Since the vias were filled, only a small amount of etching was required.

[0075] Step S5: Remove the sacrificial layer in the multi-layer stacked structure and replace it with a word line layer. After planarization, a second sub-block is formed at the bottom.

[0076] After the lower sacrificial layer material is removed, it is replaced with a word line layer, which is a metallic word line, such as tungsten or molybdenum.

[0077] Figure 5B The diagram schematically illustrates a cross-sectional and partial top-view cross-sectional view of a lower second sub-block according to another embodiment of the present disclosure, wherein the left view is a top-view cross-sectional view and the right view is a cross-sectional view. Figure 5B As shown, after steps S3 to S5 until the overall flattening process, a lower structure, namely the second sub-block located at the bottom, can be formed. This second sub-block includes the second common source pole (ACS2), the bottom select line, the word line (WL), and multiple byte strings that run through the bottom select line and the word line and are distributed in an interleaved manner.

[0078] Step S6: Sequentially deposit an insulating layer, a selected wire cut track, and an insulating layer on the second sub-block.

[0079] In this embodiment, the string selection line can be made of a metallic material, such as tungsten or polycrystalline silicon.

[0080] Step S7: Etch multiple central bit line connection holes, and sequentially deposit an insulating layer and a core metal layer in each central bit line connection hole.

[0081] First, an insulating layer is deposited on the inner wall of each central bit line connection hole, and then a core metal layer is deposited on the core of each central bit line connection hole.

[0082] In this embodiment, multiple central bit line connection holes are arranged at intervals and are eccentrically positioned with respect to the connected byte string, and the core metal layer includes tungsten.

[0083] Step S8: Etch the string selection line cut track, fill the string selection line cut track with an insulating layer, and after planarization, form the lower string selection line.

[0084] In this embodiment, the string select line cutting path is zigzag, and the cutting depth is no deeper than the top of the byte string of the lower second sub-block. Therefore, controlling the cutting depth of the string select line ensures that a gap remains between the bottom of the string select line and the top of the byte string of the second sub-block, within which an insulating layer is deposited.

[0085] Figure 5C The diagram schematically illustrates a cross-sectional view and a partial top view of the lower string selection line according to another embodiment of the present disclosure, wherein the left view is a top cross-sectional view and the right view is a cross-sectional view. Figure 5C As shown, after steps S6 to S8 until the overall flattening process, the lower string selection lines can be formed. As can be seen from the figure, along the second direction (i.e., the direction of the parallel arrangement of multiple central bit lines), each string selection line intersects and cuts along the arrangement direction of multiple byte strings, forming a zigzag cutting path. For example, in the top view section, that is, at the same height in the first direction, three zigzag cutting paths (SSL cuts) can be set to keep the quantity distribution of multiple byte strings balanced in the second direction.

[0086] Step S9: Form multiple center bit lines on the string selection line.

[0087] Figure 5D The diagram schematically illustrates a cross-section and a partial top view of the central ridge according to another embodiment of the present disclosure, wherein part A in the upper left corner is a top view and the right view is a cross-sectional view.

[0088] like Figure 5D As shown, in this embodiment, multiple central bit lines intersect with the direction of the word line layer, and the connecting holes of the central bit lines are arranged at intervals. After overall planarization, multiple central bit lines are formed. As can be seen from part A, in the top view section, the connecting holes of the central bit lines pass through each central bit line and interweave, so that all the connecting holes of the central bit lines are arranged in an alternating manner to achieve interleaved connection.

[0089] Step S10: Repeat steps S6 to S8 above to form the upper string selection line.

[0090] Figure 5E A partial cross-sectional view of the upper string selection line is shown schematically according to another embodiment of the present disclosure.

[0091] like Figure 5E As shown, the lower string selection line preparation process in steps S6 to S8 above is repeated to form the upper string selection line.

[0092] Step S11: Repeat steps S3 to S5 above to form the first sub-block located at the top.

[0093] Figure 5F A cross-sectional view of the upper first sub-block is schematically shown according to another embodiment of the present disclosure.

[0094] like Figure 5F As shown, the preparation process of the second sub-block located at the bottom in steps S3 to S5 is repeated to form the first sub-block located at the top.

[0095] Through the above embodiments, the method for fabricating a three-dimensional memory provided in this disclosure has high process feasibility and strong practical prospects.

[0096] It should be noted that the above... Figure 4 , Figures 5A to 5F The embodiments of each step shown are merely examples illustrating how to fabricate the memory cells of this disclosure on existing conventional device structures. Any fabrication process capable of forming the various structural components and their relative positions of the above-described three-dimensional memory is within the scope of this disclosure.

[0097] Furthermore, the preparation process methods adopted in the embodiments of this disclosure are not limited to those shown in the above embodiments. They can be replaced by other mature process methods in the prior art, and do not constitute a limitation of the embodiments of this disclosure.

[0098] As can be seen from the above description, the embodiments of this disclosure achieve at least the following technical effects:

[0099] (1) This disclosure combines a three-dimensional semiconductor memory structure and integration technology with a central bit line to place the central bit line inside the memory array and drive the byte string in two directions.

[0100] (2) According to the number of embedded word lines set in the array, the block capacity can be reduced to 1 / 2, 1 / 3 or even 1 / n, which reduces both the block capacity and the channel length (i.e., channel resistance), which is in line with the future development trend of three-dimensional memory.

[0101] (3) The preparation method disclosed herein has high process feasibility and strong practical prospects.

[0102] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0103] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A central bit line architecture for a three-dimensional memory, characterized in that, include: The first and second common source electrodes are set relative to each other; Multi-layer word lines are stacked along the first direction between the first common source electrode and the second common source electrode; Multiple vias pass through the multilayer word lines and connect the first common source and the second common source, with each via forming a byte string; Multiple central positioning lines are placed in the middle of the channel hole and are spaced apart along a second direction that intersects the first direction; The body formed by the multi-layer word lines and the multiple byte strings forms a total block, and the multiple central bit lines divide the total block into a first sub-block located at the top and a second sub-block located at the bottom, so as to drive the byte strings inside the first sub-block and the second sub-block respectively. The channel holes in the first sub-block and the second sub-block are connected by a plurality of central bit line connection holes set in the middle. The central bit line connection holes intersect the plurality of central bit lines, so that all the central bit line connection holes are arranged in an interlaced manner to achieve inter-position connection. Each of the central bit line connection holes is eccentrically set with respect to the connected byte string; Among them, three zigzag cutting paths are provided at the same height in the stacking direction of the multi-layer word lines, so that the quantity distribution of the multiple byte strings in the parallel arrangement direction of the multiple central bit lines remains balanced.

2. The three-dimensional memory central bit line architecture according to claim 1, characterized in that, The multi-layered character lines are separated, with an insulating layer between adjacent layers.

3. The three-dimensional memory central bit line architecture according to claim 1, characterized in that, The word line closest to the first common source in the first sub-block and the word line closest to the second common source in the second sub-block are both set as the lower selection line; The word line closest to the central bit line in the first sub-block and the word line closest to the central bit line in the second sub-block are both set as serial select lines.

4. The three-dimensional memory central bit line architecture according to claim 3, characterized in that, The string selection lines are multiple, and each string selection line intersects and cuts along the arrangement direction of multiple byte strings to form a tortuous cutting path.

5. A three-dimensional memory, characterized in that, include: The central bitline architecture of the three-dimensional memory as described in any one of claims 1-4.

6. A method for fabricating a three-dimensional memory as described in claim 5, characterized in that, include: Step S1: Deposit a multilayer stacked structure on a substrate, each of the stacked structures including a sacrificial layer and an insulating layer; Step S2: Simultaneously etch multiple channel holes and word line cutting paths on the multi-layer stacked structure; Step S3: Simultaneously fill the gate stack in the multiple channel holes and word line cutting channels, and then fill the core insulation layer; Step S4: Wet etching of the gate stack and core insulating layer within the word line cutting channel; Step S5: Remove the sacrificial layer in the multi-layer stacked structure and replace it with a word line layer. After planarization, a second sub-block is formed at the bottom. Step S6: Sequentially deposit an insulating layer, a selected wire cut track, and an insulating layer on the second sub-block; Step S7: Etch multiple central bit line connection holes, and sequentially deposit an insulating layer and a core metal layer in each central bit line connection hole; Step S8: Etch the string select line cut track, fill the string select line cut track with an insulating layer, and after planarization, form the lower string select line. Step S9: Form a plurality of central bit lines on the string selection line; Step S10: Repeat steps S6 to S8 above to form the upper string selection line; Step S11: Repeat steps S3 to S5 above to form the first sub-block located at the top.

7. The preparation method according to claim 6, characterized in that, In step S1, the substrate includes a silicon wafer substrate, the sacrificial layer material is silicon nitride or doped silicon nitride, and the insulating layer material is silicon oxide or a low dielectric constant material.

8. The preparation method according to claim 6, characterized in that, In step S2, the width of the character line cutting channel is greater than twice the diameter of the channel hole, and the character line cutting channel is opened on both sides of the plurality of channel holes.

9. The preparation method according to claim 6, characterized in that, In step S3, the gate stack includes a TANOS structure, and the core insulating layer material includes silicon oxide.

10. The preparation method according to claim 6, characterized in that, In step S5, the word line layer material includes tungsten or molybdenum.

11. The preparation method according to claim 6, characterized in that, In step S6, the string selection line is made of a metallic material, including tungsten.

12. The preparation method according to claim 6, characterized in that, In step S7, the plurality of central bit line connection holes are arranged at intervals and are eccentrically arranged with the connected byte string, and the core metal layer includes tungsten.

13. The preparation method according to claim 6, characterized in that, In step S8, the string selection line cutting path is zigzag, and the cutting depth is not deeper than the top of the byte string of the second sub-block.

14. The preparation method according to claim 6, characterized in that, In step S9, the multiple central bit lines intersect the direction of the word line layer, and the connecting holes of the central bit lines are arranged at intervals. After planarization, multiple central bit lines are formed.

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