Monolithically integrated reverse conducting gallium nitride vertical power device and method of fabrication
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-03-08
- Publication Date
- 2026-06-02
Smart Images
Figure CN116247054B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a monolithically integrated reverse-conducting gallium nitride vertical power device, which can be used as a basic component of power electronic systems. Technical Background
[0002] GaN wide-bandgap semiconductor materials, especially junction-type vertical field-effect transistors, have significant advantages in realizing high-performance, low-loss power switching power supplies due to their high breakdown voltage, low on-resistance, and excellent high-temperature characteristics. They also have very broad and unique application prospects in the national economy and military fields.
[0003] A traditional junction vertical field-effect transistor (JFET) is based on a homoepitaxial structure, comprising: a substrate layer 1, a drift layer 2, an N-type GaN channel layer 3, a P-type GaN layer 4, a source 5, a drain 6, and a gate 7. The drift layer 2 is deposited on the substrate layer 1. An N-type GaN channel layer 3 is disposed in the upper middle portion of the drift layer 2. P-type GaN layers 4 are deposited on the left and right sides of the N-type GaN channel layer 3 above the drift layer 2. A source 5 is deposited on the N-type GaN channel layer 3. Gates 7 are deposited on the upper portions of the left and right P-type GaN layers 4. A drain 6 is deposited at the bottom of the substrate layer 1. Figure 1 As shown.
[0004] In most current power switching power supplies, power semiconductor devices are required to achieve bidirectional conduction characteristics, including both forward and reverse conduction. However, in traditional junction field-effect transistors (JFETs), the devices can only achieve good forward conduction characteristics. That is, when the bias voltage applied between the gate and source is greater than the threshold voltage, a voltage is applied between the drain and source, and current flows from the drain to the source. When the bias voltage applied between the gate and source is zero volts or less than the threshold voltage, the device is in the off state. Because the device channel is off, to make the source and drain conduct, i.e., for current to flow from the source to the drain, a large turn-on voltage drop needs to be overcome, which degrades the reverse conduction characteristics and leads to greater power loss. Therefore, to meet the practical needs of power switching power supplies, a freewheeling diode with a small turn-off voltage drop is usually connected in parallel with the external circuit of a conventional junction vertical field-effect transistor (JFET) to achieve reverse conduction characteristics. (See SiC vertical JFET pure diode-less inverter leg, 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 512-517, 2013). However, this introduces large parasitic inductance and capacitance, leading to low power efficiency in the power switching power supply. Alternatively, a freewheeling diode with a small turn-off voltage drop can be fabricated next to the conventional JFET, such as... Figure 2 As shown in the reference "A novel GaN vertical junction field-effect transistor with intrinsic reverseconduction capability and kilo-volt breakdown voltage," IOP, 2022, this scheme still exhibits significant parasitic inductance and capacitance, resulting in substantial power loss. Furthermore, this scheme suffers from high leakage current and poor voltage withstand capability. Therefore, the development of reverse-conducting gallium nitride vertical power devices with excellent bidirectional conduction and blocking characteristics is urgently needed for current high-performance power electronic systems. Summary of the Invention
[0005] The purpose of this invention is to address the shortcomings of the prior art by providing a monolithically integrated reverse-conducting gallium nitride vertical power device and its fabrication method, thereby reducing the device's on-resistance and conduction loss, lowering the reverse conduction voltage drop and off-state leakage current, increasing the device's breakdown voltage, and thus improving the power efficiency of the power electronic system.
[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows:
[0007] 1. A monolithically integrated reverse-conductive gallium nitride vertical power device, comprising, from bottom to top: a drain 10, a substrate layer 1, and a drift layer 2, wherein a channel layer 3 is disposed on the drift layer 2, a source 11 is disposed above the channel layer 3, and P-type GaN layers 6 are disposed on both sides; a first N-type GaN layer 8, a second N-type GaN layer 9, and a gate 12 are sequentially disposed on the P-type GaN layer 6, characterized in that:
[0008] The drift layer 2 is provided with n P-type modulation islands 7 at equal intervals above the center, and the width of each P-type modulation island 7 is equal to the spacing, so as to expose the drift layer 2, improve the withstand voltage of the device under blocking conditions, and reduce leakage current, where n is an integer greater than 1.
[0009] The P-type modulation island 7 and the drift layer 2 are provided with a modulation island 13, which forms a Schottky contact with the drift layer 2. In the off state, a reverse current flows from the modulation island 13 to the drain 10 by applying a bias voltage greater than that of the drain 10 through the modulation island 13, thereby realizing the reverse conduction characteristic.
[0010] Inside the drift layer 2 below the P-type GaN layer 6 and the P-type modulation island 7, there is a first gradient P-type GaN layer 4 and a second gradient P-type GaN layer 5 with m layers. These two gradient P-type GaN layers 4 and 5 form PN junctions with the drift layer 2 to expand the depletion region, suppress leakage current, and improve the withstand voltage, where m is an integer greater than or equal to 1.
[0011] Furthermore, the substrate layer is made of any one of gallium nitride, silicon, diamond, or silicon carbide.
[0012] Furthermore, the channel layer 3 has a thickness of 5nm to 3μm and a width of 5nm to 3μm; the P-type GaN layer 6 has a thickness of 5nm to 3μm and a width of 10nm to 50μm; each P-type modulation island 7 has a thickness of 5nm to 3μm, a length of 10nm to 50μm, and a width of 5nm to 10μm; the spacing between adjacent islands is the same as the width d, and the distance c from the adjacent P-type GaN layer 6 is greater than 0μm.
[0013] Furthermore, the thickness of the first N-type GaN layer 8 is 5 nm to 1 μm, and the doping concentration is 1 × 10⁻⁶. 15 ~5×10 17 cm -3 The second N-type GaN layer 9 has a thickness of 5 nm to 1 μm and a doping concentration of 1 × 10⁻⁶. 18 ~1×10 21 cm -3 .
[0014] Furthermore, the width l1 of the first layer of the first gradient P-type GaN layer 4 is smaller than the width b of the P-type GaN layer 6, and the width l of its m-th layer is... m Width l of less than the (m-1)th layer m-1 And the doping concentration of each layer is 1×10 17 ~1×10 20 cm -3 The width w1 of the first layer of the second gradient P-type GaN layer 5 is smaller than the width d of the P-type modulation island 7, and the width w of its m-th layer is... m Width less than the (m-1)th layer m-1 And the doping concentration of each layer is 1×10 17 ~1×10 20 cm -3 .
[0015] Furthermore, the modulation island 13 is electrically connected to the source 11.
[0016] Furthermore, the modulation island structure, composed of the second gradient P-type GaN layer 5, the P-type modulation island 7, and the modulation island electrode 13, is alternately and repeatedly arranged with the junction field-effect transistor structure, composed of the channel layer 3, the first gradient P-type GaN layer 4, the P-type GaN layer 6, the first N-type GaN layer 8, the second N-type GaN layer 9, the source electrode 11, and the gate electrode 12.
[0017] 2. A method for fabricating a monolithically integrated inverse-conducting gallium nitride vertical power device, characterized by comprising the following:
[0018] A) Epitaxially grow a GaN-based wide-bandgap semiconductor material on substrate 1 to form a drift layer 2;
[0019] B) A mask is first fabricated on the drift layer 2, and the drift layer 2 is etched using the mask to form a channel layer 3 with a width of a;
[0020] C) Create multiple layers of grooves on the drift layer 2;
[0021] C1) A mask is fabricated a second time on the drift layer 2, and the drift layer 2 is etched using the mask to form a first groove with a width of w1 and a depth of h1.
[0022] C2) A mask is fabricated for the third time on the drift layer 2, and the drift layer 2 is etched using the mask to form a second groove with a width of w2 and a depth of h2 in the first groove.
[0023] C3) Repeat the etching process until the (m+1)th mask is fabricated on the drift layer 2. Use this mask to etch the drift layer 2, forming a groove with a width of w in the (m-1)th layer. m Depth is h m The m-th layer of grooves;
[0024] D) Perform selective extension to form;
[0025] D1) In the groove within the drift layer 2, a P-type GaN-based wide bandgap semiconductor material is epitaxially grown using a selective epitaxial process to form a first gradient P-type GaN layer 4 and a second gradient P-type GaN layer 5 in the groove, both of which are flush with the upper surface of the drift layer 2.
[0026] D2) On the drift layer 2, a P-type GaN-based wide bandgap semiconductor material is epitaxially grown using a selective epitaxial process to form a P-type GaN layer 6 on the first gradient P-type GaN layer 4 and the second gradient P-type GaN layer 5, and the P-type GaN layer 6 is made flush with the upper surface of the channel layer 3.
[0027] E) Epitaxially grow a GaN-based wide-bandgap semiconductor material on the channel layer 3 and the P-type GaN layer 6 to form the first N-type GaN layer 8;
[0028] F) Using an epitaxial process, a GaN-based wide-bandgap semiconductor material is epitaxially grown on the first N-type GaN layer 8 to form a second N-type GaN layer 9;
[0029] G) A mask is fabricated on the second N-type GaN layer 9 for the (m+2)th time. The mask is used to etch the second N-type GaN layer (9) and the first N-type GaN layer 8 in sequence until the channel layer 3 and the P-type GaN layer 6 are exposed.
[0030] H) A mask is fabricated for the (m+3)th time on the channel layer 3, the P-type GaN layer 6, and the second N-type GaN layer 9. The mask is used to etch part of the P-type GaN layer 6 until the drift layer 2 is exposed, forming n equally spaced and parallel P-type modulation islands 7 on the second gradient P-type GaN layer 5.
[0031] I) A mask is fabricated for the (m+4)th time on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7 and second N-type GaN layer 9. Metal is deposited on channel layer 3 using the mask and then subjected to rapid thermal annealing to form a good ohmic contact, thus completing the fabrication of source electrode 11.
[0032] J) Deposit metal at the bottom of substrate 1 and perform rapid thermal annealing to form good ohmic contact and complete the fabrication of drain (10);
[0033] K) A mask is fabricated for the (m+5)th time on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7 and second N-type GaN layer 9. Metal is deposited on the second N-type GaN layer 9 using the mask and then thermally annealed to complete the fabrication of gate 12.
[0034] L) A mask is fabricated for the (m+6)th time on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9. Metal is deposited on drift layer 2 and P-type modulation island 7 using this mask, and rapid thermal annealing is performed to form a good Schottky contact between the metal and drift layer 2, thus completing the fabrication of modulation island 13 and the entire device.
[0035] Compared with traditional junction-type vertical field-effect transistors, the device of this invention has the following advantages:
[0036] First, it has high integration and good reverse conduction characteristics.
[0037] Since the modulation island 13 is electrically connected to the source 11, when a voltage higher than that of the drain 10 is applied to the modulation island 13, the Schottky junction formed by the contact between the modulation island 13 and the drift layer 2 is turned on, forming a current flowing from the Schottky metal, i.e., the modulation island 13, to the drain 10, i.e., the device is reverse-conducting. At the same time, since the metal-semiconductor contact between the modulation island 13 and the drift layer 2 is a Schottky contact, its barrier height is modulated by the work function of the modulation island 13. The turn-on voltage drop of the Schottky junction is very low, so that the junction turns on first when the device is reverse-conducting, thereby achieving a low turn-on voltage drop during reverse conduction. Furthermore, the reverse conduction current can be increased by increasing the area of the Schottky junction.
[0038] Second, it has low leakage current in the off-state and strong blocking capability.
[0039] Because a first graded P-type GaN layer 4 is provided inside the drift layer 2 under the P-type GaN layer 6, a P-type modulation island 7 is provided in the center of the upper part of the drift layer 2, and a second graded P-type GaN layer 5 is provided inside the drift layer 2 below it, when the device is in the off state and a voltage higher than that applied to the drain 10 is applied to the modulation island 13, the modulation island 13 and the drift layer 2 form a reverse-biased Schottky junction. At the same time, the drift layer 2 forms a reverse-biased PN junction with the P-type modulation island 7 and the second graded P-type GaN layer 5 respectively. The depletion region of the PN junction broadens rapidly, so that the depletion region of the PN junction connects with the depletion region of the Schottky junction, thereby enabling the PN junction and the Schottky junction to participate in the withstand voltage at the same time, reducing the reverse-biased leakage current of the Schottky junction, and achieving high withstand voltage in the off state. At the same time, the reverse-biased PN junction formed by the first graded P-type GaN layer 4 and the drift layer 2 further pinches off the current channel in the channel layer 3, enhancing the device's blocking capability and reliability.
[0040] Third, the device of the present invention is implemented in a monolithic integrated manner, which improves the reverse conduction characteristics and is compatible with traditional transistor manufacturing processes, making the process simple. Attached Figure Description
[0041] Figure 1This is a diagram of a traditional junction-type vertical field-effect transistor (JFET).
[0042] Figure 2 This is a schematic diagram of an existing junction vertical field-effect transistor with a freewheeling diode.
[0043] Figure 3 This is a top view of the monolithically integrated reverse-conducting gallium nitride vertical power device of the present invention;
[0044] Figure 4 yes Figure 3 Cross-sectional view along the AB direction;
[0045] Figure 5 yes Figure 3 Cross-sectional view along the CD direction;
[0046] Figure 6 yes Figure 3 Cross-sectional view along the EF direction;
[0047] Figure 7 This is a cross-sectional view of the first graded p-type GaN layer 4 along the CD direction;
[0048] Figure 8 This is a cross-sectional view of the second graded p-type GaN layer 5 along the AB direction;
[0049] Figure 9 This is a flowchart illustrating the implementation of the monolithically integrated reverse-conducting gallium nitride vertical power device of this invention. Detailed Implementation
[0050] The embodiments and effects of the present invention will be further described in detail below with reference to the accompanying drawings.
[0051] Reference Figure 3 , Figure 4 , Figure 5 and Figure 6 The monolithically integrated reverse-conducting gallium nitride vertical power device in this example includes: a substrate layer 1, a drift layer 2, a channel layer 3, a first graded P-type GaN layer 4, a second graded P-type GaN layer 5, a P-type GaN layer 6, a P-type modulation island 7, a first N-type GaN layer 8, a second N-type GaN layer 9, a drain 10, a source 11, a gate 12, and a modulation island 13, wherein:
[0052] The substrate layer 1 is made of any one of gallium nitride, silicon, diamond, and silicon carbide.
[0053] The drift layer 2 is located on top of the substrate layer 1, and it is composed of a doping concentration of 1×10⁻⁶. 15 ~5×10 17 cm -3 It is composed of N-type GaN-based wide bandgap semiconductor material with a thickness a of 1μm to 20μm;
[0054] The channel layer 3 is located above the drift layer 2. It is made of the same N-type GaN-based wide bandgap semiconductor material as the drift layer 2, with a thickness of 5 nm to 3 μm and a width a of 5 nm to 3 μm.
[0055] The p-type GaN layer 6 is located on the left and right sides of the channel layer 3, with a first graded p-type GaN layer 4 below it. The p-type GaN layer 6 has a thickness of 5 nm to 3 μm, a width b of 10 nm to 50 μm, and a doping concentration of 1 × 10⁻⁶. 17 ~1×10 20 cm -3 ;
[0056] The first gradient P-type GaN layer 4 is located inside the drift layer 2, and consists of m layers. The width l1 of its first layer is smaller than the width b of the P-type GaN layer 6, and the width l of the m-th layer is... m Width l of less than the (m-1)th layer m-1 The doping concentration of each layer is 1×10 17 ~1×10 20 cm -3 , where m is an integer greater than or equal to 1;
[0057] The second gradient P-type GaN layer 5 is located inside the drift layer 2, and consists of m layers. The width w1 of its first layer is smaller than the width d of the P-type modulation island 7, and the width w of the m-th layer is... m Width less than the (m-1)th layer m-1 And the doping concentration of each layer is 1×10 17 ~1×10 20 cm -3 , where m is an integer greater than or equal to 1;
[0058] The first graded p-type GaN layer 4 and the second graded p-type GaN layer 5, the height of the m-th layer is h. m The size ranges from 5 nm to 10 μm.
[0059] The n P-type modulation islands 7 are uniformly distributed above the center of the drift layer 2. Each P-type modulation island 7 has a thickness of 5nm to 3μm, a length b of 10nm to 50μm, and a width d of 5nm to 10μm. The spacing between adjacent islands is the same as the width d, and the distance c from the adjacent P-type GaN layer 6 is >0μm. The doping concentration is 1×10⁻⁶. 17 ~1×10 20 cm -3 , where n is an integer greater than 1;
[0060] The first N-type GaN layer 8 is located above the P-type GaN layer 6, and has a thickness of 5 nm to 1 μm and a doping concentration of 1 × 10⁻⁶. 15~5×10 17 cm -3 ;
[0061] The second N-type GaN layer 9 is located above the first N-type GaN layer 8, and has a thickness of 5 nm to 1 μm and a doping concentration of 1 × 10⁻⁶. 18 ~1×10 21 cm -3 ;
[0062] The drain 10 is located at the bottom of the substrate 1, forming a good ohmic contact;
[0063] The source electrode 11 is located above the channel layer 3, forming a good ohmic contact, and is separated from the P-type GaN layer 6 by the channel layer 3.
[0064] The gate 12 is located above the second N-type GaN layer 9;
[0065] The modulation island 13 is located on the surface of the drift layer 2 and the P-type modulation island 7. The modulation island 13 forms a good Schottky contact with the drift layer 2 and is electrically connected to the source 11.
[0066] The modulation island structure, consisting of the second gradient P-type GaN layer 5, the P-type modulation island 7, and the modulation island electrode 13, is alternately and repeatedly arranged with the junction field-effect transistor structure consisting of the channel layer 3, the first gradient P-type GaN layer 4, the P-type GaN layer 6, the first N-type GaN layer 8, the second N-type GaN layer 9, the source electrode 11, and the gate electrode 12.
[0067] The monolithically integrated reverse-conducting gallium nitride vertical power device fabricated by this invention is given in the following three embodiments.
[0068] Example 1: A monolithically integrated reverse-conducting gallium nitride vertical power device with 3 graded P-type GaN layers and 5 P-type modulation islands was fabricated using a gallium nitride substrate.
[0069] Step 1. Epitaxially fabricate drift layer 2 on substrate layer 1 using N-type GaN material.
[0070] Using metal-organic chemical vapor deposition (MOCVD), under the following conditions: temperature 500℃, pressure 46 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 20 μmol / min, a 1 μm thick GaN material was epitaxially deposited on substrate 1, forming a doping concentration of 1×10⁻⁶. 15 cm -3 The N-type GaN semiconductor material is used to form a drift layer 2.
[0071] Step 2. Etch the drift layer 2 to form the channel layer 3.
[0072] A mask was first fabricated on the drift layer 2 using SiO2 material. Reactive ion etching was then used to etch an N-type GaN cuboid with a width of 5 nm and a height of 5 nm on the drift layer 2 under the process conditions of 150 W power, 15 sccm Cl2 flow rate and 10 mTorr pressure, forming the channel layer 3.
[0073] Step 3. Create multiple layers of grooves on drift layer 2.
[0074] 3.1) The first groove layer is etched on the drift layer 2:
[0075] A second mask was fabricated on the drift layer 2. Reactive ion etching was used to etch the drift layer 2 under the process conditions of 100W power, 15sccm Cl2 flow rate and 10mTorr pressure, forming a first layer groove with a width of 9nm and a height of 5nm.
[0076] 3.2) A second layer of grooves is formed by etching on the drift layer 2:
[0077] A third mask was fabricated on the drift layer 2. Reactive ion etching was used to etch the drift layer 2 under the process conditions of 100W power, 15sccm Cl2 flow rate and 10mTorr pressure. A second trench with a width of 8nm and a height of 5nm was formed in the first trench.
[0078] 3.3) A third groove is etched into the drift layer 2:
[0079] A fourth mask was fabricated on the drift layer 2. Reactive ion etching was used under the process conditions of 100W power, 15sccm Cl2 flow rate and 10mTorr pressure. The mask was used to etch the drift layer 2 to form a third groove with a width of 6nm and a height of 5nm in the second groove.
[0080] Step 4. Perform selective epitaxy to form a first graded P-type GaN layer 4, a second graded P-type GaN layer 5, and a P-type GaN layer 6.
[0081] 4.1) Using metal-organic chemical vapor deposition (MOCVD), selective epitaxy was performed in a trench under the following process conditions: temperature 500℃, pressure 43 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 25 μmol / min, to form a doped layer with a doping concentration of 1×10⁻⁶. 17 cm -3 The first gradient P-type GaN layer 4 and the second gradient P-type GaN layer 5 are flush with the upper surface of the drift layer 2.
[0082] 4.2) Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 500℃, pressure 43 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 25 μmol / min, selective epitaxy was performed on both sides of the drift layer 2 and the channel layer 3 to form a doping concentration of 1×10⁻⁶. 17 cm -3 The P-type GaN semiconductor material P-type GaN layer 6 is made flush with the upper surface of the channel layer 3.
[0083] Step 5. Fabricate two N-type GaN layers.
[0084] 5.1) On the channel layer 3 and the p-type GaN layer 6, metal-organic chemical vapor deposition (MOCVD) was used at a temperature of 500℃, a pressure of 46 Torr, a hydrogen flow rate of 4300 sccm, an ammonia flow rate of 4300 sccm, and a gallium source flow rate of 20 μmol / min to epitaxially form a layer with a thickness of 5 nm and a doping concentration of 1 × 10⁻⁶. 15 cm -3 The first N-type GaN layer 8;
[0085] 5.2) Metal-organic chemical vapor deposition (MOCVD) was used on the first N-type GaN layer 8 at a temperature of 550℃, a pressure of 46 Torr, a hydrogen flow rate of 4300 sccm, an ammonia flow rate of 4300 sccm, and a gallium source flow rate of 20 μmol / min to epitaxially form a layer with a thickness of 5 nm and a doping concentration of 1 × 10⁻⁶. 18 cm -3 The second N-type GaN layer 9.
[0086] Step 6. Etch the second N-type GaN layer 9 to expose the channel layer 3 and the P-type GaN layer 6.
[0087] A mask was fabricated for the fifth time on the surface of the second N-type GaN layer 9. Reactive ion etching was used under process conditions of 150W power, 15sccm Cl2 flow rate and 10mTorr pressure. The mask was used to sequentially perform deep trench etching on the second N-type GaN layer 9 and the first N-type GaN layer 8 until the top surface of the channel layer 3 and the P-type GaN layer 6 was reached.
[0088] Step 7. Etch five P-type modulation islands 7 on the P-type GaN layer 6.
[0089] A sixth mask was fabricated on the surfaces of the channel layer 3, the P-type GaN layer 6, and the second N-type GaN layer 9. Reactive ion etching was used to perform deep trench etching on the P-type GaN layer 6 under the following process conditions: power of 150W, Cl2 flow rate of 15sccm, and pressure of 15mTorr. The etching continued until the upper surface of the drift layer 2, forming five equally spaced and parallel P-type modulation islands 7. The width and spacing of each P-type modulation island 7 were 5nm, and the distance between each P-type modulation island 7 and the adjacent P-type GaN layer 6 was 5nm. In the AB direction cross-section, the length of the P-type modulation island 7 and the width b of the P-type GaN layer 6 were 10nm.
[0090] Step 8. Fabricate source electrode 11 on the surface of channel layer 3.
[0091] A seventh mask was fabricated on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9. Electron beam evaporation was used to achieve this effect at a vacuum level of less than 1.8 × 10⁻⁶. -3 Pa, voltage 750W, evaporation rate less than Under the specified process conditions, a multilayer metal Ti / Al / Ni / Au was deposited on the surface of the channel layer 3 using a mask. The metal in contact with the channel layer 3 was Ti, with thicknesses of 0.02μm / 0.15μm / 0.05μm / 0.04μm, respectively. Rapid thermal annealing was then performed at a temperature of 860℃ in a N2 atmosphere to form good ohmic contact, thus completing the fabrication of the source electrode 11.
[0092] Step 9. Fabricate drain 10 at the bottom of substrate 1.
[0093] Electron beam evaporation technology was used in an environment with a vacuum level of less than 1.8 × 10⁻⁶. -3 Pa, voltage 500W, evaporation rate less than Under the specified process conditions, a multilayer metal Ti / Al is deposited at the bottom of substrate 1. The metal in contact with substrate 1 is Ti, with thicknesses of 0.06 μm and 0.12 μm, respectively. Rapid thermal annealing is performed at a temperature of 860 °C under N2 atmosphere to form an ohmic contact, thus completing the fabrication of drain 10.
[0094] Step 10. Fabricate gate 12 on the surface of the second N-type GaN layer 9.
[0095] An eighth mask was fabricated on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9. Electron beam evaporation was used to achieve this effect at a vacuum level of less than 1.8 × 10⁻⁶. -3 Pa, voltage 750W, evaporation rate less than Under the specified process conditions, a multilayer metal Ni / Au layer, i.e., a lower Ni layer and an upper Au layer, with thicknesses of 20nm / 20nm respectively, was deposited on the second N-type GaN layer 9 using a mask. The gate 12 was then fabricated by rapid thermal annealing at a temperature of 860℃ and under an N2 atmosphere.
[0096] Step 11. Fabricate modulation island poles 13 on the surface of drift layer 2 and P-type modulation island 7.
[0097] A ninth mask was fabricated on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and the second N-type GaN layer 9. Electron beam evaporation was used to achieve this effect at a vacuum level of less than 1.8 × 10⁻⁶. -3 Pa, voltage 800W, evaporation rate less than Under the specified process conditions, a multilayer metal Ni / Au layer is deposited on the surface of the drift layer 2 and the P-type modulation island 7 using a mask. The thickness of the lower Ni layer is 0.05 μm and the thickness of the upper Au layer is 0.05 μm. Rapid thermal annealing is then performed under process conditions of 200℃ and N2 atmosphere to form a good Schottky contact, which is electrically connected to the source electrode 11. This completes the fabrication of the modulation island 13 and the device fabrication.
[0098] Example 2: A monolithically integrated reverse-conductive gallium nitride vertical power device with a diamond substrate, consisting of a gradient P-type GaN layer and three P-type modulation islands.
[0099] Step A. Epitaxially fabricate a drift layer 2 on substrate 1 using N-type GaN material.
[0100] Set the pressure to 1.0 × 10⁻⁶. -10 The process conditions included mbar, RF power of 700W, N2 as the reactant, and a high-purity Ga source. Molecular beam epitaxy was used to epitaxially grow a 20μm thick GaN material on substrate 1 with a doping concentration of 5×10⁻⁶. 17 cm -3 The N-type GaN semiconductor material is used to form a drift layer 2.
[0101] Step B. Etch the drift layer 2 to form the channel layer 3.
[0102] A mask was first fabricated on the drift layer 2 using SiO2 material. The process conditions were set as follows: power 100W, Cl2 flow rate 10sccm, and pressure 15mTorr. Reactive ion etching technology was used to etch an N-type GaN cuboid with a width of 3μm and a height of 3μm onto the drift layer 2 using the mask, forming the channel layer 3.
[0103] Step C involves creating multiple layers of grooves on the drift layer 2.
[0104] C.1) The first groove layer is etched on the drift layer 2:
[0105] A second mask was fabricated on the drift layer 2. The process conditions were set as follows: power 100W, Cl2 flow rate 10sccm, and pressure 12mTorr. Reactive ion etching was used to etch the drift layer 2 using the mask to form a first layer groove with a width of 49μm and a height of 10μm.
[0106] Step D. Perform selective epitaxy to form a first graded P-type GaN layer 4, a second graded P-type GaN layer 5, and a P-type GaN layer 6.
[0107] D1) Set the process conditions to 500℃, 46 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 15 μmol / min. Use metal-organic chemical vapor deposition (MOCVD) to selectively epitaxially grow in the groove to form a doping concentration of 1×10⁻⁶. 20 cm -3 The first gradient P-type GaN layer 4 and the second gradient P-type GaN layer 5 are flush with the upper surface of the drift layer 2.
[0108] D2) Under the following process conditions: temperature 500℃, pressure 46 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 15 μmol / min, selective epitaxy is performed on both sides of the channel layer 3 on the drift layer 2 using metal-organic chemical vapor deposition (MOCVD). The epitaxial layer has a doping concentration of 1×10⁻⁶. 20 cm -3 A P-type GaN layer (6) is formed and the P-type GaN layer (6) is flush with the upper surface of the channel layer (3).
[0109] Step E involves fabricating two N-type GaN layers.
[0110] E1) Set the pressure to 1.0 × 10⁻⁶. -10 The process involves mbar, RF power of 550W, and the use of N2 and high-purity Ga source as reactants. Molecular beam epitaxy (MBE) is employed to epitaxially form a 1μm thick layer with a doping concentration of 5×10⁻⁶ on channel layer 3 and p-type GaN layer 6. 17 cm -3 The first N-type GaN layer 8;
[0111] E2) Set the pressure to 1.0 × 10 -10 The process involves mbar epitaxy, RF power of 550W, and the use of N2 and high-purity Ga as reactants. Molecular beam epitaxy (MBE) is employed to epitaxially form a 1μm thick, 1×10⁻⁶ doping layer on the first N-type GaN layer 8. 21 cm-3 The second N-type GaN layer 9.
[0112] Step F. Etch on the second N-type GaN layer 9 to expose the channel layer 3 and the P-type GaN layer 6.
[0113] A third mask was fabricated on the surface of the second N-type GaN layer 9. The process conditions were set as follows: SF6 flow rate of 5 sccm, O2 flow rate of 2 sccm, pressure of 10 mTorr, and bias voltage of 150 V. Inductively coupled plasma etching was used to perform deep trench etching on the second N-type GaN layer 9 and the first N-type GaN layer 8 in sequence using the mask, until the trench layer 3 and the upper surface of the P-type GaN layer 6 were reached.
[0114] Step G. Etch five P-type modulation islands 7 on the P-type GaN layer 6.
[0115] A fourth mask was fabricated on the surfaces of the channel layer 3, the P-type GaN layer 6, and the second N-type GaN layer 9. The process conditions were set as follows: SF6 flow rate of 5 sccm, O2 flow rate of 2 sccm, pressure of 10 mTorr, and bias voltage of 150 V. Inductively coupled plasma etching was used to perform deep trench etching on the P-type GaN layer 6 using the mask, etching up to the upper surface of the drift layer 2, forming five equally spaced and parallel P-type modulation islands 7. The width and spacing of each P-type modulation island 7 were 10 μm, and the distance between each P-type modulation island 7 and the adjacent P-type GaN layer 6 was 1 μm. In the AB direction cross-section, the length of the P-type modulation island 7 and the width b of the P-type GaN layer 6 were 50 μm.
[0116] Step H. Fabricate source electrode 11 on the surface of channel layer 3.
[0117] A fifth mask was fabricated on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9, with a vacuum level set to less than 1.8 × 10⁻⁶. -3 Pa, voltage 900W, evaporation rate less than Under the specified process conditions, electron beam evaporation technology was used to deposit multiple layers of metal Ti / Al / Ti / Au on the surface of the channel layer 3 using a mask. The metal in contact with the channel layer 3 was Ti, with thicknesses of 0.05μm / 0.15μm / 0.05μm / 0.15μm, respectively. Rapid thermal annealing was then performed under process conditions of 850℃ and N2 atmosphere to form good ohmic contact, thus completing the fabrication of source electrode 11.
[0118] Step I. Fabricate drain 10 at the bottom of substrate 1.
[0119] Set the vacuum level to less than 1.8 × 10⁻⁶. -3 Pa, voltage 500W, evaporation rate less than Under the specified process conditions, electron beam evaporation technology was used to deposit multiple layers of metal Ti / Al at the bottom of substrate 1. The metal in contact with substrate 1 was Ti, with thicknesses of 0.05 μm and 0.15 μm, respectively. Rapid thermal annealing was performed at a temperature of 850 °C under N2 atmosphere to form ohmic contacts, thus completing the fabrication of drain 10.
[0120] Step J. Fabricate gate 12 on the surface of the second N-type GaN layer 9.
[0121] A sixth mask was fabricated on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and the second N-type GaN layer 9, with a vacuum level of less than 1.8 × 10⁻⁶. -3 Pa, voltage 800W, evaporation rate less than Under the specified process conditions, electron beam evaporation technology was used to deposit multiple layers of metal Ni / Au on the second N-type GaN layer 9 using a mask, namely a lower Ni layer and an upper Au layer, with thicknesses of 0.05μm and 0.25μm respectively. Rapid thermal annealing was then performed at a temperature of 850℃ under N2 atmosphere to complete the fabrication of the gate 12.
[0122] Step K. Fabricate modulation island poles 13 on the surface of drift layer 2 and P-type modulation island 7.
[0123] A seventh mask was fabricated on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9, with a vacuum level of less than 1.8 × 10⁻⁶. -3 Pa, voltage 700W, evaporation rate less than Under the specified process conditions, electron beam evaporation technology was used to deposit multiple layers of metal Ni / Au on the surfaces of drift layer 2 and P-type modulation island 7 using a mask. The layers consist of a lower Ni layer and an upper Au layer with thicknesses of 0.01 μm and 0.05 μm, respectively. Rapid thermal annealing was then performed under process conditions of 400 °C and N2 atmosphere to form a good Schottky contact, which is electrically connected to the source electrode 11. This completed the fabrication of modulation island 13 and the device fabrication.
[0124] Example 3: A monolithically integrated reverse-conductive gallium nitride vertical power device with a 4-layer gradient P-type GaN layer and 8 P-type modulation islands was fabricated using a silicon carbide substrate.
[0125] Step 1. Epitaxially fabricate a drift layer 2 on substrate 1 using N-type GaN material from bottom to top.
[0126] Using metal-organic chemical vapor deposition (MOCVD), a 10 μm thick GaN material was epitaxially deposited on substrate 1 to form a doping concentration of 3 × 10⁻⁶. 16 cm -3 N-type GaN semiconductor material is used to form a drift layer 2;
[0127] The process conditions for metal-organic chemical vapor deposition are: temperature 550℃, pressure 41 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 15 μmol / min.
[0128] Step 2. Etch the drift layer 2 to form the channel layer 3.
[0129] A mask was first fabricated on the drift layer 2 using SiO2 material. Reactive ion etching technology was used to etch an N-type GaN cuboid with a width of 1.2 μm and a height of 2 μm onto the drift layer 2 using the mask, forming the channel layer 3.
[0130] The process conditions for reactive ion etching are: power of 150W, Cl2 flow rate of 10sccm, and pressure of 12mTorr.
[0131] Step 3: Create multiple layers of grooves on drift layer 2.
[0132] 3a) The first groove layer is etched on the drift layer 2:
[0133] A second mask was fabricated on the drift layer 2, and reactive ion etching was used to etch the drift layer 2 using the mask to form a first layer groove with a width of 5μm and a height of 1.5μm.
[0134] The process conditions for reactive ion etching are: power of 150W, Cl2 flow rate of 10sccm, and pressure of 10mTorr.
[0135] 3b) A second layer of grooves is etched on the drift layer 2:
[0136] A third mask is fabricated on the drift layer 2. Reactive ion etching technology is used to etch the drift layer 2 using the mask, forming a second groove with a width of 4μm and a height of 1μm in the first groove.
[0137] The process conditions for reactive ion etching are: power of 150W, Cl2 flow rate of 10sccm, and pressure of 10mTorr.
[0138] 3c) A third groove is formed by etching on the drift layer 2:
[0139] A fourth mask was fabricated on the drift layer 2, and reactive ion etching technology was used to etch the drift layer 2 using the mask, forming a third groove with a width of 3μm and a height of 0.5μm in the second groove.
[0140] The process conditions for reactive ion etching are: power of 150W, Cl2 flow rate of 10sccm, and pressure of 10mTorr.
[0141] 3d) A fourth groove is etched on the drift layer 2:
[0142] A fifth mask was fabricated on the drift layer 2, and reactive ion etching was used to etch the drift layer 2 using the mask, forming a fourth groove with a width of 1.5 μm and a height of 0.2 μm in the second groove.
[0143] The process conditions for reactive ion etching are: power of 150W, Cl2 flow rate of 10sccm, and pressure of 10mTorr.
[0144] Step 4. Perform selective epitaxy to form a first graded P-type GaN layer 4, a second graded P-type GaN layer 5, and a P-type GaN layer 6.
[0145] 4a) Selective epitaxy is performed in the groove to form a first gradient P-type GaN layer 4 and a second gradient P-type GaN layer 5.
[0146] Molecular beam epitaxy (MBE) was used to selectively epitaxially grow in the groove to form a doping concentration of 5 × 10⁻⁶. 19 cm -3 The first gradient P-type GaN layer 4 and the second gradient P-type GaN layer 5 are flush with the upper surface of the drift layer 2.
[0147] The process conditions for molecular beam epitaxy are: pressure of 1.0 × 10⁻⁶. -10 mbar, RF power of 440W, reactant uses N2 and high-purity Ga source;
[0148] 4b) Selective epitaxy is performed on the drift layer 2 to form a P-type GaN layer 6;
[0149] Using molecular beam epitaxy, selective epitaxy was performed on both sides of the channel layer 3 on the drift layer 2 to form a doping concentration of 5×10⁻⁶. 19 cm -3 A P-type GaN layer 6 is formed, and the P-type GaN layer 6 is made flush with the upper surface of the channel layer 3.
[0150] The process conditions for molecular beam epitaxy are: pressure of 1.0 × 10⁻⁶. -10 mbar, RF power of 440W, and N2 and high-purity Ga source are used as reactants.
[0151] Step 5: Fabricate two N-type GaN layers.
[0152] 5a) Using metal-organic chemical vapor deposition (MOCVD), epitaxial growth was performed on the channel layer 3 and the p-type GaN layer 6 to form a layer with a thickness of 0.5 μm and a doping concentration of 5 × 10⁻⁶. 16 cm -3 The first N-type GaN layer 8;
[0153] The process conditions for metal-organic chemical vapor deposition are: temperature 550℃, pressure 43 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 20 μmol / min.
[0154] 5b) Using metal-organic chemical vapor deposition (MOCVD), an epitaxial layer of 0.5 μm thickness and a doping concentration of 5 × 10⁻⁶ was formed on the first N-type GaN layer 8. 19 cm -3 The second N-type GaN layer 9;
[0155] The process conditions for metal-organic chemical vapor deposition are: temperature 550℃, pressure 46 Torr, hydrogen flow rate 4300 sccm, ammonia flow rate 4300 sccm, and gallium source flow rate 25 μmol / min.
[0156] Step 6. Etch on the second N-type GaN layer 9 to expose the channel layer 3 and the P-type GaN layer 6.
[0157] A sixth mask was fabricated on the surface of the second N-type GaN layer 9. Reactive ion etching was used to sequentially perform deep trench etching on the second N-type GaN layer 9 and the first N-type GaN layer 8 using the mask, until the trench layer 3 and the upper surface of the P-type GaN layer 6 were etched.
[0158] The process conditions for reactive ion etching are: power of 150W, Cl2 flow rate of 10sccm, and pressure of 12mTorr.
[0159] Step 7. Etch eight P-type modulation islands 7 on the P-type GaN layer 6.
[0160] A seventh mask was fabricated on the surfaces of the channel layer 3, the P-type GaN layer 6, and the second N-type GaN layer 9. Reactive ion etching was used to perform deep trench etching on the P-type GaN layer 6 using the mask, etching down to the upper surface of the drift layer 2, forming eight equally spaced and parallel P-type modulation islands 7. The width and spacing of each P-type modulation island 7 are 5 μm, and the distance between each P-type modulation island 7 and the adjacent P-type GaN layer 6 is 0.5 μm. In the AB direction cross-section, the length of the P-type modulation island 7 and the width b of the P-type GaN layer 6 are 6 μm.
[0161] The process conditions for reactive ion etching are: power of 150W, Cl2 flow rate of 10sccm, and pressure of 12mTorr.
[0162] Step 8. Fabricate source electrode 11 on the surface of channel layer 3.
[0163] A mask was fabricated for the eighth time on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9. Using a sputtering process, multiple layers of metal Ti / Al / Ni / Au were deposited on the surface of channel layer 3 using the mask. The metal in contact with channel layer 3 was Ti, with thicknesses of 0.02μm / 0.15μm / 0.05μm / 0.04μm, respectively. Rapid thermal annealing was then performed to form good ohmic contact, thus completing the fabrication of source electrode 11.
[0164] The process conditions for rapid thermal annealing are: temperature 860℃, N2 atmosphere;
[0165] The sputtering process conditions are as follows: the sputtering gas pressure is maintained at about 0.1 Pa, the Ar flow rate is 9 sccm, and the substrate temperature is fixed at 250℃.
[0166] Step 9. Fabricate drain 10 at the bottom of substrate 1.
[0167] Using a sputtering process, multiple layers of metal Ti / Al are deposited at the bottom of substrate 1. The metal in contact with substrate 1 is Ti, with thicknesses of 0.06 μm and 0.12 μm, respectively. Rapid thermal annealing is then performed to form an ohmic contact, thus completing the fabrication of drain 10.
[0168] The process conditions for rapid thermal annealing are: temperature 860℃, N2 atmosphere;
[0169] The sputtering process conditions are as follows: the sputtering gas pressure is maintained at about 0.1 Pa, the Ar flow rate is 8 sccm, and the substrate temperature is fixed at 200℃.
[0170] Step 10. Fabricate gate 12 on the surface of the second N-type GaN layer 9.
[0171] A mask is fabricated for the ninth time on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9. Using sputtering, multiple layers of metal Ni / Au are deposited on the second N-type GaN layer 9 using the mask, i.e., a lower Ni layer and an upper Au layer, with thicknesses of 0.05μm and 0.15μm, respectively. Then, thermal annealing is performed to complete the fabrication of gate 12.
[0172] The process conditions for rapid thermal annealing are: temperature 860℃, N2 atmosphere;
[0173] The sputtering process conditions were as follows: sputtering pressure was maintained at 0.1 Pa, Ar flow rate was 9 sccm, and substrate temperature was fixed at 350℃.
[0174] Step 11. Fabricate modulation island poles 13 on the surface of drift layer 2 and P-type modulation island 7.
[0175] A tenth mask was fabricated on the surfaces of drift layer 2, channel layer 3, P-type GaN layer 6, P-type modulation island 7, and second N-type GaN layer 9. Using a sputtering process, multiple layers of metal Ni / Au were deposited on the surfaces of drift layer 2 and P-type modulation island 7, i.e., a lower Ni layer and an upper Au layer, with thicknesses of 0.05 μm and 0.05 μm, respectively. Rapid thermal annealing was then performed to form a good Schottky contact, which was electrically connected to the source electrode 11. The modulation island electrode 13 was then fabricated, and the device fabrication was completed.
[0176] The process conditions for rapid thermal annealing are: temperature 300℃, N2 atmosphere;
[0177] The sputtering process conditions were as follows: the sputtering gas pressure was maintained at approximately 0.05 Pa, the Ar flow rate was 11 sccm, and the substrate temperature was fixed at 300℃.
[0178] The above description is merely a specific embodiment of the present invention and does not constitute a limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principle of the present invention, can make various modifications and changes in form and detail according to the method of the present invention without departing from the principle and scope of the present invention. For example, in addition to gallium nitride, diamond, and silicon carbide, silicon can also be used as the substrate; in addition to metal-organic chemical vapor deposition and molecular beam epitaxy, hydride vapor phase epitaxy can also be used as the epitaxial technology; in addition to using 1, 3, and 4, the number of layers m in the graded P-type GaN layer can also be any integer greater than or equal to 1; in addition to using 3, 5, and 8, the number of blocks n of the P-type modulation island can also be any integer greater than 1. However, these modifications and changes based on the present invention are still within the protection scope of the claims of the present invention.
Claims
1. A monolithically integrated reverse-conducting gallium nitride vertical power device, comprising, from bottom to top: The structure comprises a drain (10), a substrate (1), and a drift layer (2). A channel layer (3) is provided on the drift layer (2), and a source (11) is provided above the channel layer (3). P-type GaN layers (6) are provided on both sides of the channel layer (3). A first N-type GaN layer (8), a second N-type GaN layer (9), and a gate (12) are sequentially provided on the upper surface of the P-type GaN layer (6) from bottom to top. The structure is characterized by: The drift layer (2) is provided with n P-type modulation islands (7) at equal intervals above the center, and the width of each P-type modulation island (7) is equal to the spacing between each P-type modulation island (7) to expose the drift layer (2), improve the withstand voltage of the device under blocking conditions, and reduce leakage current, where n is an integer greater than 1; The P-type modulation island (7) and the drift layer (2) are provided with modulation island poles (13), and they form a Schottky contact with the drift layer (2) so that in the off state, a bias voltage greater than that of the drain (10) is applied through the modulation island pole (13) to generate a reverse current flowing from the modulation island pole (13) to the drain (10), thereby realizing reverse conduction characteristics. Inside the drift layer (2) below the P-type GaN layer (6) and the P-type modulation island (7), there are a first gradient P-type GaN layer (4) and a second gradient P-type GaN layer (5) with m layers. These two gradient P-type GaN layers (4, 5) form PN junctions with the drift layer (2) to expand the depletion region, suppress leakage current, and improve withstand voltage, where m is an integer greater than or equal to 1.
2. The device according to claim 1, characterized in that, The substrate layer (1) is made of any one of gallium nitride, silicon, diamond or silicon carbide.
3. The device according to claim 1, characterized in that: The channel layer (3) has a thickness of 5 nm ~ 3 μm and a width a of 5 nm ~ 3 μm; The thickness of the P-type GaN layer (6) is 5 nm ~ 3 μm, and the width b is 10 nm ~ 50 μm; Each P-type modulation island (7) has a thickness of 5 nm ~ 3 μm, a length b of 10 nm ~ 50 μm, and a width d of 5 nm ~ 10 μm; the spacing between adjacent islands is the same as the width d, and the distance c from the adjacent P-type GaN layer (6) is > 0 μm.
4. The device according to claim 1, characterized in that: The thickness of the first N-type GaN layer (8) is 5 nm ~ 1 μm, and the doping concentration is 1 × 10⁻⁶. 15 ~5×10 17 cm -3 ; The second N-type GaN layer (9) has a thickness of 5 nm ~ 1 μm and a doping concentration of 1 × 10⁻⁶. 18 ~1×10 21 cm -3 .
5. The device according to claim 1, characterized in that: The width l1 of the first layer of the first gradient P-type GaN layer (4) is smaller than the width b of the P-type GaN layer (6), and the width l of its m-th layer is... m Width l of less than the (m-1)th layer m-1 The doping concentration of each layer is 1×10 17 ~1×10 20 cm -3 .
6. The device according to claim 1, characterized in that: The width w1 of the first layer of the second gradient P-type GaN layer (5) is smaller than the width d of the P-type modulation island (7), and the width w of its m-th layer is... m Width less than the (m-1)th layer m-1 And the doping concentration of each layer is 1×10 17 ~1×10 20 cm -3 .
7. The device according to claim 1, characterized in that: The modulation island (13) is electrically connected to the source (11).
8. The device according to claim 1, characterized in that: The modulation island structure, consisting of the second gradient P-type GaN layer (5), the P-type modulation island (7), and the modulation island electrode (13), is alternately and repeatedly arranged with the junction field-effect transistor structure consisting of the channel layer (3), the first gradient P-type GaN layer (4), the P-type GaN layer (6), the first N-type GaN layer (8), the second N-type GaN layer (9), the source electrode (11), and the gate electrode (12).
9. A method for fabricating a monolithically integrated inverse-conducting gallium nitride vertical power device, characterized in that, Including the following: A) Epitaxially grow a GaN-based wide bandgap semiconductor material on a substrate (1) to form a drift layer (2). B) A mask is first made on the drift layer (2), and the drift layer (2) is etched using the mask to form a channel layer (3) with a width of a. C) Create multiple grooves on the drift layer (2); C1) A mask is made on the drift layer (2) for the second time, and the drift layer (2) is etched using the mask to form a first groove with a width of w1 and a depth of h1. C2) A mask is fabricated for the third time on the drift layer (2), and the drift layer (2) is etched using the mask to form a second groove with a width of w2 and a depth of h2 in the first groove. C3) Repeat the etching process until the (m+1)th mask is fabricated on the drift layer (2). Use this mask to etch the drift layer (2) to form a groove with a width of w in the (m-1)th layer. m Depth is h m The m-th layer of grooves; D) Perform selective epitaxy to form a first graded P-type GaN layer (4), a second graded P-type GaN layer (5), and a P-type GaN layer (6); D1) In the groove within the drift layer (2), a P-type GaN-based wide bandgap semiconductor material is epitaxially grown using a selective epitaxial process to form a first gradient P-type GaN layer (4) and a second gradient P-type GaN layer (5) in the groove, both of which are flush with the upper surface of the drift layer (2). D2) On the drift layer (2), a P-type GaN-based wide bandgap semiconductor material is epitaxially grown using a selective epitaxial process to form a P-type GaN layer (6) on the first gradient P-type GaN layer (4) and the second gradient P-type GaN layer (5), and the P-type GaN layer (6) is flush with the upper surface of the channel layer (3). E) Epitaxially grow a GaN-based wide bandgap semiconductor material on the channel layer (3) and the P-type GaN layer (6) to form a first N-type GaN layer (8). F) Using an epitaxial process, a GaN-based wide bandgap semiconductor material is epitaxially grown on the first N-type GaN layer (8) to form a second N-type GaN layer (9). G) A mask is fabricated on the second N-type GaN layer (9) for the (m+2)th time. The mask is used to etch the second N-type GaN layer (9) and the first N-type GaN layer (8) in sequence until the channel layer (3) and the P-type GaN layer (6) are exposed. H) A mask is fabricated for the m+3th time on the channel layer (3), the P-type GaN layer (6) and the second N-type GaN layer (9). The mask is used to etch part of the P-type GaN layer (6) until the drift layer (2) is exposed, forming n equally spaced and parallel P-type modulation islands (7) on the second gradient P-type GaN layer (5). I) A mask is fabricated for the m+4th time on the surfaces of the drift layer (2), the channel layer (3), the P-type GaN layer (6), the P-type modulation island (7), and the second N-type GaN layer (9). Metal is deposited on the channel layer (3) using the mask and then subjected to rapid thermal annealing to form a good ohmic contact, thus completing the fabrication of the source electrode (11). J) Deposit metal at the bottom of the substrate layer (1) and perform rapid thermal annealing to form a good ohmic contact and complete the fabrication of the drain (10); K) A mask is fabricated for the m+5th time on the surfaces of the drift layer (2), the channel layer (3), the P-type GaN layer (6), the P-type modulation island (7), and the second N-type GaN layer (9). Metal is deposited on the second N-type GaN layer (9) using the mask and then thermally annealed to complete the fabrication of the gate (12). L) A mask is fabricated for the m+6th time on the surfaces of the drift layer (2), the channel layer (3), the P-type GaN layer (6), the P-type modulation island (7), and the second N-type GaN layer (9). Metal is deposited on the drift layer (2) and the P-type modulation island (7) using the mask, and rapid thermal annealing is performed to make the metal form a good Schottky contact with the drift layer (2), thus completing the fabrication of the modulation island (13) and the fabrication of the entire device.
10. The method according to claim 9, characterized in that, The epitaxial technologies mentioned include: metal-organic chemical vapor deposition, hydride vapor phase epitaxy, and molecular beam epitaxy.