Semiconductor device and method of forming the same

Abstract

A semiconductor device and method of forming the same. In one embodiment, the device includes a source / drain region adjacent to a channel region; an interlayer dielectric on the source / drain region; a source / drain contact extending through the interlayer dielectric and into the source / drain region; a metal-semiconductor alloy region between the source / drain contact and the source / drain region, the metal-semiconductor alloy region disposed below an upper surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer surrounding the source / drain contact, the contact spacer including the first dopant and an amorphizing impurity.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The manufacture of semiconductor devices generally involves depositing insulating or dielectric layers, conductive layers, and semiconductor layers sequentially on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and elements on top of them.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated within a given area. Summary of the Invention

[0004] One embodiment disclosed herein provides a semiconductor device comprising a source / drain region, an interlayer dielectric, a source / drain contact, a metal-semiconductor alloy region, and contact spacers. The source / drain region is adjacent to a channel region. The interlayer dielectric is located on the source / drain region. The source / drain contact extends through the interlayer dielectric and into the source / drain region. The metal-semiconductor alloy region is located between the source / drain contact and the source / drain region, and is disposed below the upper surface of the channel region. The metal-semiconductor alloy region includes a first dopant. The contact spacers surround the source / drain contact and include the first dopant and amorphous impurities.

[0005] Another aspect of this disclosure provides a semiconductor device including a source / drain region, an interlayer dielectric, a source / drain contact, and a metal-semiconductor alloy region. The source / drain region is adjacent to a channel region and includes a first dopant. The interlayer dielectric is located on the source / drain region. The source / drain contact extends through the interlayer dielectric and into the source / drain region, extending below the upper surface of the channel region. The metal-semiconductor alloy region is located between the source / drain contact and the source / drain region. The metal-semiconductor alloy region includes the first dopant. The lower portion of the metal-semiconductor alloy region has a higher concentration of the first dopant than the source / drain region, and the upper portion of the metal-semiconductor alloy region has a lower concentration of the first dopant than the source / drain region.

[0006] Another aspect of this disclosure is a method for forming a semiconductor device, comprising: depositing a first dopant in a first portion of an epitaxial source / drain region to form a first highly doped region in the epitaxial source / drain region; etching a recess in the epitaxial source / drain region, the recess extending through the first highly doped region; depositing an amorphous impurity in a second portion of the epitaxial source / drain region to form an amorphous region in the epitaxial source / drain region, the second portion of the epitaxial source / drain region being disposed at the bottom of the recess; depositing a first dopant in the amorphous region to form a second highly doped region in the epitaxial source / drain region; and annealing the epitaxial source / drain region to crystallize the amorphous region. Attached Figure Description

[0007] The features disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, many features are not drawn to scale. In fact, for clarity of explanation, the dimensions of each feature may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a fin field-effect transistor according to some embodiments is illustrated;

[0009] Figures 2 to 25C This is a view of an intermediate stage in the fabrication of a fin field-effect transistor according to some embodiments;

[0010] Figures 26A to 26C This is a view of a fin field-effect transistor according to some embodiments;

[0011] Figure 27 It is a spectrum showing the concentration of each element in the example apparatus.

[0012] [Symbol Explanation]

[0013] 50: Substrate

[0014] 50N: n-type region

[0015] 50P:p-type area

[0016] 50R: Area

[0017] 52: Fins

[0018] 54: Insulating materials

[0019] 56: Shallow trench isolation area

[0020] 58: Passage Area

[0021] 62: Dummy Dielectric Layer

[0022] 64: Dummy gate layer

[0023] 66: Masking layer

[0024] 72: Dummy Dielectric

[0025] 74: Dummy gate

[0026] 76: Mask

[0027] 82: Gate spacer

[0028] 84: Fin spacers

[0029] 88: Epitaxial source / drain region

[0030] 88D1: First highly doped region

[0031] 88D2: Second Highly Doped Region

[0032] 88U: Upper part

[0033] 88M: Middle Section

[0034] 88L: Lower part

[0035] 92: Contact Etching Stop Layer

[0036] 94: First interlayer dielectric

[0037] 96: Depression

[0038] 112: Gate Dielectric

[0039] 114: Gate electrode

[0040] 116: Gate mask

[0041] 120: Mask

[0042] 122: Opening

[0043] 124: Contact opening

[0044] 130: Source / Drain Contact

[0045] 132: Contact spacer

[0046] 134: Contact spacer

[0047] 136: Metal-semiconductor alloy region

[0048] 142: Spacer layer

[0049] 144: Depression

[0050] 146: Spare layer

[0051] 148: Amorphous region

[0052] 152: Etching Stop Layer

[0053] 154: Second interlayer dielectric

[0054] 162: Gate contact

[0055] 164: Source / Drain Through-Hole Device

[0056] D1: Distance

[0057] D2: Distance

[0058] D3: Distance

[0059] D4: Distance

[0060] D5: Distance

[0061] I1: First Interface

[0062] I2: Second Interface Detailed Implementation

[0063] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0064] In addition, for ease of description, this document uses spatially relative terms (such as “below,” “under,” “lower,” “above,” “upper,” and the like) to describe the relationship between one element or feature shown in the figures and another. Besides the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatially relative descriptive terms used herein can be interpreted in the same way.

[0065] According to various embodiments, the recess, serving as a contact, extends into the epitaxial source / drain region. Extending the recess into the epitaxial source / drain region increases the contact area with the epitaxial source / drain region. After forming the recess in the epitaxial source / drain region, a placement process is performed, thus increasing the doping concentration in the portion of the epitaxial source / drain region at the bottom of the recess. The metal-semiconductor alloy region can therefore be formed in the recess with a high doping concentration, which further reduces the contact resistance to the epitaxial source / drain region.

[0066] Figure 1 An example of a fin field-effect transistor according to some embodiments is illustrated. Figure 1 This is a three-dimensional view; for clarity, some features of the fin field-effect transistor are omitted. The fin field-effect transistor includes fins 52 extending from a substrate 50 (e.g., a semiconductor substrate), the fins 52 operating identically to the channel region 58 of the fin field-effect transistor. Isolation regions, such as shallow trench isolation (STI) regions 56, are disposed between adjacent fins 52, the fins 52 protruding above and from adjacent shallow trench isolation regions 56. Although the shallow trench isolation region 56 is used herein as described / illustrated as being separated from the substrate 50, the term "substrate" may refer only to the semiconductor substrate or the bonding and isolation region of the semiconductor substrate. Furthermore, although the bottom portion of the fins 52 and the substrate 50 are shown as a single, continuous material, the bottom portion of the fins 52 and / or the substrate 50 may comprise a single material or multiple materials.

[0067] Gate dielectric 112 is located along the sidewalls of fin 52 and above the upper surface of fin 52. Gate electrode 114 is located above gate dielectric 112. Epitaxial source / drain regions 88 are disposed on opposite sides of fin 52 relative to gate dielectric 112 and gate electrode 114. Gate spacers 82 separate epitaxial source / drain regions 88 from gate dielectric 112 and gate electrode 114. First interlayer dielectric (ILD) 94 is formed above epitaxial source / drain regions 88. Contacts to epitaxial source / drain regions 88 (described later) are formed through the first interlayer dielectric 94. Epitaxial source / drain regions 88 can be shared between individual fins 52. For example, adjacent epitaxial source / drain regions 88 can be electrically connected, for instance, by epitaxial growth merging epitaxial source / drain regions 88, or by coupling epitaxial source / drain regions 88 using the same source / drain contacts. In this document, the term "source / drain region" of a transistor refers to a semiconductor region that serves as the source or drain region of a transistor.

[0068] Figure 1Further reference cross-sections, which will be used in the following figures, are illustrated. Cross-section A-A' is along the longitudinal axis of the gate electrode 114. Cross-section B-B' is parallel to cross-section A-A' and extends through the epitaxial source / drain region 88 of the fin field-effect transistor. Cross-section C-C' is along the longitudinal axis of the fin 52 and the direction of current between, for example, the epitaxial source / drain regions 88 of the fin field-effect transistor. For clarity, these reference cross-sections will be referenced in subsequent figures.

[0069] Some embodiments discussed herein are set in the context of fin field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Some embodiments are also contemplated for use in planar devices, such as planar transistors, nanostructure field-effect transistors (NSFETs) (e.g., nanosheets, nanowires, fully wound gates, or the like), or the like.

[0070] Figures 2 to 25C This is a view of an intermediate stage in the manufacturing of a fin field-effect transistor according to some embodiments. Figure 2 , Figure 3 , Figure 4 and Figure 5 It is a 3D view display and Figure 1 A similar 3D view. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 24A ,and Figure 25A Is along such Figure 1 A cross-sectional view drawn from a similar section to the reference section A-A' in the diagram. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 24B ,and Figure 25B Is along such Figure 1 A cross-sectional view drawn from a similar section to the reference section B-B' in the diagram. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24C ,and Figure 25C Is along such Figure 1 A cross-sectional view drawn from a similar section to the reference section C-C' in the diagram.

[0071] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. A semiconductor-on-insulator substrate is typically a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; synthetic semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or combinations thereof.

[0072] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type fin field-effect transistor. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type fin field-effect transistor. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0073] Fin 52 is formed in substrate 50. Fin 52 is a semiconductor strip and may also be referred to as a semiconductor fin. Fin 52 is formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar methods, or combinations thereof. Etching can be anisotropic.

[0074] Fin 52 can be patterned by any suitable method. For example, fin 52 can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes to allow for the generation of patterns with, for example, a pattern spacing smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fin 52. In some embodiments, a mask (or other layer) may be retained on fin 52.

[0075] Insulating material 54 is formed over substrate 50 and between adjacent fins 52. Insulating material 54 can be an oxide, such as silicon oxide, a nitride, a similar material, or a combination thereof, and can be formed by chemical vapor deposition processes, such as high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., in a remote plasma system, chemical vapor deposition-based material deposition and post-curing to transform into other materials, such as oxides), similar methods, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, insulating material 54 is silicon oxide formed by a flowable chemical vapor deposition process. Once insulating material 54 is formed, an annealing process can be performed. Although insulating material 54 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may be formed first along the surfaces of substrate 50 and fins 52. A filler material, such as that discussed previously, may then be formed over the liner.

[0076] In one embodiment, an insulating material 54 is formed such that excess insulating material 54 covers the fin 52. A removal process is applied to the insulating material 54 to remove the excess insulating material 54 above the fin 52. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, or the like, may be utilized. The planarization process exposes the fin 52 such that the upper surface of the fin 52 and the insulating material 54 are substantially coplanar after the planarization process is completed (within process variations). In embodiments where a mask remains above the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the mask or the upper surface of the fin 52 is substantially coplanar with the insulating material 54, respectively (within process variations).

[0077] The previously described process is merely one example of how the fins 52 and insulating material 54 can be formed. In some embodiments, the fins 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the upper surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown within the trenches, and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer to form the fins 52. Furthermore, in some embodiments, heteroepitaxial structures can also be used for the fins 52. For example, the fins 52 can be recessed, and a material different from the fins 52 can be epitaxially grown over the recessed fins 52. In such embodiments, the fins 52 comprise the recessed material and an epitaxially grown material disposed above the recessed material. In a further embodiment, a dielectric layer can be formed above the upper surface of the substrate 50, and trenches can be etched through the dielectric layer. The heteroepitaxial structure can then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed to allow the heteroepitaxial structure to protrude from the dielectric layer to form fins 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be doped in situ during growth, which can exclude previous and subsequent implantations, although in-situ doping and implantation doping can be used together.

[0078] Furthermore, it is advantageous that the material epitaxially grown in the n-type region 50N (e.g., an N-type metal-oxide-semiconductor region) differs from the material in the p-type region 50P (e.g., a P-type metal-oxide-semiconductor region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si... x Ge 1-x (where x can be in the range of 0 to 1), formed from silicon carbide, pure germanium or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, or similar materials. For example, usable materials for forming group III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and similar materials.

[0079] exist Figure 3In this process, the insulating material 54 is recessed to form shallow trench isolation regions 56. The recessed insulating material 54 causes the upper portion of the fin 52 to protrude between adjacent shallow trench isolation regions 56. Furthermore, the upper surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (e.g., disc-shaped), or a combination thereof, as shown in the figure. The upper surface of the shallow trench isolation region 56 can be formed into a flat, convex, and / or concave shape by appropriate etching. The shallow trench isolation region 56 can be recessed using an acceptable etching process, such as a process selective for the material of the insulating material 54 (e.g., etching the material of the insulating material at a faster rate than etching the material of the fin 52). For example, diluted hydrofluoric acid (dHF) can be used for oxide removal.

[0080] Furthermore, suitable well regions (not individually shown) may be formed in the fins 52 and / or the substrate 50. The well regions may have a conductivity type opposite to that of the source / drain regions, which will subsequently be formed in each n-type region 50N and p-type region 50P. In some embodiments, a p-type well region is formed in the n-type region 50N, and an n-type well region is formed in the p-type region 50P. In some embodiments, either a p-type well region or an n-type well region is formed in either the n-type region 50N or the p-type region 50P.

[0081] In embodiments with different well configurations, different implantation steps for the n-type region 50N and p-type region 50P can be achieved using masks (not individually drawn), such as photoresist. For example, the photoresist can be formed over the fins 52 and shallow trench isolation regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurities are implanted in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, and their concentration implanted in the region is equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 With approximately 10 18 cm -3 Between. The photoresist can be removed after placement, for example, through an acceptable ashing process.

[0082] After or before the placement of the p-type region 50P, a mask (not shown individually), such as photoresist, is formed over the fins 52 and shallow trench isolation regions 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, p-type impurities can be placed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the placement of p-type impurities into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like, and their placement concentration in the region is equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 With approximately 10 18 cm -3 Between. The photoresist can be removed after placement, for example, through an acceptable ashing process.

[0083] After the implantation of the n-type region 50N and the p-type region 50P, an annealing process can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In embodiments where the epitaxial structure of the fin 52 is epitaxially grown, the grown material can be in-situ doped during growth to exclude implantation, although in-situ doping and implantation doping can be used together.

[0084] exist Figure 4In this process, a dummy dielectric layer 62 is formed on fin 52. The dummy dielectric layer 62 may be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, or similar materials, and may be deposited or thermally grown using acceptable techniques. A dummy gate layer 64 is formed over the dummy dielectric layer 62, and a masking layer 66 is formed over the dummy gate layer 64. The dummy gate layer 64 may be deposited over the dummy dielectric layer 62 and subsequently planarized, for example, by chemical mechanical polishing. The masking layer 66 may be deposited over the dummy gate layer 64. The dummy gate layer 64 may be formed of a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon-germanium (poly-SiGe), metal, metal nitride, metal silicide, metal oxide, or similar materials, and may be formed by physical vapor deposition (PVD), chemical vapor deposition, or similar processes. The dummy gate layer 64 may be formed of a material having a high etching selectivity compared to the insulating material, such as the shallow trench isolation region 56, and / or the dummy dielectric layer 62. The mask layer 66 may be formed of a dielectric material such as silicon nitride, silicon oxynitride compound, or the like. In this example, the monolayer dummy gate layer 64 and the monolayer mask layer 66 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 62 covers the fin 52 and the shallow trench isolation region 56, such that the dummy dielectric layer 62 extends over the shallow trench isolation region 56 and between the dummy gate layer 64 and the shallow trench isolation region 56. In another embodiment, the dummy dielectric layer 62 covers only the fin 52.

[0085] exist Figure 5 In this process, mask layer 66 is formed using acceptable photolithography and etching techniques to form mask 76. The pattern of mask 76 is then transferred to dummy gate layer 64 using acceptable etching techniques to form dummy gate 74. The pattern of mask 76 may optionally be further transferred to dummy dielectric layer 62 using acceptable etching techniques to form dummy dielectric 72. Dummy gate 74 covers each channel region 58 of fin 52. The pattern of mask 76 may be used to physically separate adjacent dummy gate 74. Dummy gate 74 may also have a length direction substantially perpendicular to the length direction of fin 52 (within process variations). Mask 76 may be removed during the patterning of dummy gate 74 or during subsequent processes.

[0086] Figures 6A to 25C The various additional steps of the apparatus for manufacturing an embodiment are illustrated. Figures 6A to 25CThe diagram illustrates either the n-type region 50N or the p-type region 50P. For example, the illustrated structure may apply to both the n-type region 50N and the p-type region 50P. The differences (if any) between the structures of the n-type region 50N and the p-type region 50P are explained in the description accompanying each figure.

[0087] exist Figures 6A to 6C In this configuration, gate spacer 82 is formed above fin 52, on mask 76 (if present), on the exposed sidewalls of dummy gate 74, and dummy dielectric 72. Gate spacer 82 can be formed by conformal deposition of one or more dielectric materials followed by etching of the dielectric material. Acceptable dielectric materials may include silicon nitride, silicon carbonitride (SiCN), silicon oxynitride, silicon oxycarbonitride (SiOCN), or the like. Gate spacer 82 can be formed by conformal deposition processes such as chemical vapor deposition, atomic layer deposition (ALD), or similar processes. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, can be performed to pattern the dielectric material. Etching may be anisotropic. The dielectric material, when etched, has a portion left on the sidewalls of dummy gate 74 (which subsequently forms gate spacer 82, see...). Figure 6C In some embodiments, the etching used to form the gate spacer 82 is adjustable such that the dielectric material, when etched, has a portion left on the sidewalls of the fin 52 (later forming the fin spacer 84, see...). Figure 6B After etching, the fin spacers 84 (if present) and the gate spacers 82 may have straight sidewalls (as shown in the figure) or they may have circumferential sidewalls (not shown individually).

[0088] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown individually) in fin 52. In embodiments with different device types, similar to the implantation of the well region described previously, a mask (not shown individually), such as photoresist, can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of a suitable type (e.g., p-type) can be implanted into the fin 52 exposed in the p-type region 50P. The mask can then be removed. Next, a mask (not shown individually), such as photoresist, can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of a suitable type (e.g., n-type) can be implanted into the fin 52 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. During implantation, channel region 58 remains covered by the dummy gate 74, so that channel region 58 substantially maintains impurity-free implantation to form lightly doped source / drain regions. The lightly doped source / drain regions may have 10 15 cm -3 Up to 10 19 cm -3 Range of impurity concentrations. Annealing processes can be used to repair fabric damage and revitalize the fabric of impurities.

[0089] It should be noted that the foregoing disclosure typically describes the process for forming spacers and lightly doped source / drain regions. Other processes and procedures may also be used. For example, fewer or more spacers may be used, different process steps may be used, spacers may be formed and removed, and / or similar. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0090] exist Figures 7A to 7C In this configuration, epitaxial source / drain regions 88 are formed within fins 52. The epitaxial source / drain regions 88 are formed in fins 52 such that each dummy gate 74 is disposed between adjacent pairs of corresponding epitaxial source / drain regions 88. In some embodiments, the epitaxial source / drain regions 88 may extend into, and may also penetrate, the fins 52. In some embodiments, gate spacers 82 are used to separate the epitaxial source / drain regions 88 from the dummy gates 74 by an appropriate lateral distance, so that the epitaxial source / drain regions 88 do not short-circuit with the gates of subsequently formed fin field-effect transistors. The material of the epitaxial source / drain regions 88 may be selected to apply pressure to the corresponding channel regions 58, thereby improving performance.

[0091] The epitaxial source / drain region 88 in the n-type region 50N can be formed by shielding the p-type region 50P and etching the source / drain regions of the fin 52 located in the n-type region 50N to form a recess in the fin 52. The epitaxial source / drain region 88 in the n-type region 50N then epitaxially grows in the recess. The epitaxial source / drain region 88 can comprise any acceptable material suitable for an n-type device. For example, assuming the fin 52 is silicon, the epitaxial source / drain region 88 in the n-type region 50N can comprise a material that applies tensile strain to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 88 in the n-type region 50N may be referred to as the "n-type source / drain region". The epitaxial source / drain region 88 in the n-type region 50N may have surfaces rising from each surface of the fin 52 and may have facets.

[0092] The epitaxial source / drain region 88 in the p-type region 50P can be formed by shielding the n-type region 50N and etching the source / drain regions of the fin 52 located in the p-type region 50P to form a recess in the fin 52. The epitaxial source / drain region 88 in the p-type region 50P then epitaxially grows in the recess. The epitaxial source / drain region 88 can include any acceptable material suitable for a p-type device. For example, assuming the fin 52 is silicon, the epitaxial source / drain region 88 in the p-type region 50P can include a material that applies compressive strain to the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 88 in the p-type region 50P may be referred to as a "p-type source / drain region". The epitaxial source / drain region 88 in the p-type region 50P may have a surface that rises from each surface of the fin 52 and may have facets.

[0093] Epitaxial source / drain regions 88 and / or fins 52 can be formed by implanting dopants, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing process. The source / drain regions can have a density of 10... 19 cm -3 Up to 10 21 cm -3The impurity concentrations between these values. The n-type and / or p-type impurities used in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 88 can be in-situ doped during growth.

[0094] For example, the epitaxial process is used to form epitaxial source / drain regions 88, the upper surface of which has facets extending laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 88 to fuse together as if by means of... Figure 7B As illustrated. In some embodiments, adjacent epitaxial source / drain regions 88 remain separated after the epitaxial process is complete (not individually shown). In the illustrated embodiment, fin spacers 84 are formed to cover portions of the sidewalls of the fins extending beyond the shallow trench isolation region 56, thus hindering epitaxial growth. In other embodiments, using spacer etching to form gate spacers 82 can be adjusted to not form fin spacers 84, in order to allow the epitaxial source / drain regions 88 to extend to the surface of the shallow trench isolation region 56.

[0095] exist Figures 8A to 8C In this configuration, a first interlayer dielectric 94 is deposited over the epitaxial source / drain region 88, the gate spacer 82, the mask 76 (if present) or the dummy gate 74, and the shallow trench isolation region 56. The first interlayer dielectric 94 can be formed from a dielectric material, which can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, flowable chemical vapor deposition (FCVD), or similar methods. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicon glass (USG), or the like. Other insulating materials can be formed using any acceptable process.

[0096] In some embodiments, a contact etch stop layer (CESL) 92 is formed between the first interlayer dielectric 94 and the epitaxial source / drain region 88, gate spacer 82, mask 76 (if present) or dummy gate 74, and shallow trench isolation region 56. The contact etch stop layer 92 may be formed from a dielectric material having a high etch selectivity from the first interlayer dielectric 94. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by conformal deposition processes such as chemical vapor deposition, atomic layer vapor deposition, or similar processes.

[0097] exist Figures 9A to 9C In this process, a removal process is performed to make the upper surface of the first interlayer dielectric 94 flush with the upper surface of the mask 76 (if present) or dummy gate 74. In some embodiments, planarization processes such as chemical mechanical polishing, etch-back processes, combinations thereof, or similar processes may be used. The planarization process may also remove the mask 76 on the dummy gate 74 and portions of the gate spacer 82 along the sidewalls of the mask 76. After the planarization process, the first interlayer dielectric 94, the contact etch stop layer 92, the gate spacer 82, and the upper surface of the mask 76 (if present) or dummy gate 74 are substantially coplanar (within process variations). Therefore, the upper surface of the mask 76 (if present) or dummy gate 74 is exposed through the first interlayer dielectric 94. In the illustrated embodiment, the mask 76 is retained, and the planarization process makes the upper surface of the first interlayer dielectric 94 flush with the upper surface of the mask 76.

[0098] exist Figures 10A to 10C In this process, the mask 76 (if present) and the dummy gate 74 are removed during the etching process to form the recess 96. A portion of the dummy dielectric 72 within the recess 96 may also be removed. In some embodiments, only the dummy gate 74 is removed, and the dummy dielectric 72 remains exposed through the recess 96. In some embodiments, the dummy dielectric 72 is removed from the recess 96 in a first region of the die (e.g., a core logic region) and remains in the recess 96 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 74 is removed by an isotropic dry etching process. For example, the etching process may include a dry etching process that selectively etches the dummy gate 74 using reactive gases at a faster rate than the first interlayer dielectric 94 or the gate spacer 82. During removal, the dummy dielectric 72 may be used as an etch stop layer while etching the dummy gate 74. The dummy dielectric 72 may be selectively removed after the removal of the dummy gate 74. Each recess 96 exposes and / or covers the channel area 58 of its respective fin 52.

[0099] exist Figures 11A to 11C In this process, a gate dielectric 112 and a gate electrode 114 are formed to replace the gate structure. Each corresponding gate dielectric 112 and gate electrode 114 can be collectively referred to as a "gate structure". Each gate structure extends along the upper surface and sidewalls of the channel region 58 of the fin 52.

[0100] The gate dielectric 112 includes one or more gate dielectric layers disposed on the sidewalls and top surface of the fin 52 and the sidewalls of the gate spacer 82. The gate dielectric 112 may be formed of oxides (e.g., silicon oxide or metal oxides), silicates (e.g., metal silicates), combinations thereof, multilayers thereof, or the like. Additionally or alternatively, the gate dielectric 112 may be formed of a high dielectric constant material (e.g., a dielectric material having a k-value greater than 7), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material of the gate dielectric 112 may be formed by molecular beam deposition (MBD), atomic layer vapor deposition, plasma-enhanced chemical vapor deposition, and similar methods. Although illustrated as a single-layer gate dielectric 112, the gate dielectric 112 may include any number of interface layers and any number of main layers. For example, the gate dielectric 112 may include an interface layer and an overlying high dielectric constant layer.

[0101] The gate electrode 114 includes one or more gate electrode layers disposed above the gate dielectric 112. The gate electrode 114 may be formed of a metal-containing material, such as titanium nitride, titanium dioxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multiple layers thereof, or similar. Although illustrated as a single-layer gate electrode 114, the gate electrode 114 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler material.

[0102] As an example of forming a gate structure, one or more gate dielectric layers may be deposited in the recess 96. The gate dielectric layers may also be deposited on the upper surfaces of the first interlayer dielectric 94, the contact etch stop layer 92, and the gate spacer 82. Subsequently, one or more gate electrode layers may be deposited on the gate dielectric layer and within the remaining portion of the recess 96. A removal step may then be performed to remove excess portions of the gate dielectric and gate electrode layers, the excess portions being on the upper surfaces of the first interlayer dielectric 94, the contact etch stop layer 92, and the gate spacer 82. After the removal process, the gate dielectric layer has a portion remaining in the recess 96 (thus forming the gate dielectric 112). After the removal process, the gate electrode layer has a portion remaining in the recess 96 (thus forming the gate electrode 114). In some embodiments, planarization processes, such as chemical mechanical polishing, etch-back processes, combinations thereof, or similar processes, may be used. After the planarization process, the upper surfaces of the gate spacer 82, the contact etch stop layer 92, the first interlayer dielectric 94, the gate dielectric 112, and the gate electrode 114 are substantially coplanar (within process variations).

[0103] The formation of the gate dielectric 112 in the n-type region 50N and the p-type region 50P can be performed simultaneously, such that the gate dielectric 112 in each region is formed of the same material, and the formation of the gate electrode 114 can be performed simultaneously, such that the gate electrode 114 in each region is formed of the same material. In some embodiments, the gate dielectric 112 in each region can be formed by different processes, such that the gate dielectric 112 may include different materials and / or have different numbers of layers, and / or the gate electrode 114 in each region can be formed by different processes, such that the gate electrode 114 may include different materials and / or have different numbers of layers. When different processes are used, the respective masking steps can be used to mask and expose appropriate areas.

[0104] exist Figures 12A to 12C In this configuration, a gate mask 116 is formed over the gate structure (including the gate dielectric 112 and the gate electrode 114). In some embodiments, the gate mask 116 may also be formed over the gate spacer 82. A gate contact will then be formed through the gate mask 116 to contact the upper surface of the gate electrode 114.

[0105] As an example of forming the gate mask 116, the gate structure (including the gate dielectric 112 and the gate electrode 114) can be recessed using any acceptable etching process. In some embodiments (not individually drawn), the gate spacer 82 is also recessed. Dielectric material is then deposited compliantly in the recess. Acceptable dielectric materials may include silicon nitride, silicon carbide nitride, silicon oxynitride, silicon carbide nitride, or the like, which can be formed by compliant deposition processes such as chemical vapor deposition, atomic layer vapor deposition, or similar processes. Other insulating materials formed by acceptable processes may also be used. A removal process is performed to remove excess portions of the dielectric material on the upper surface of the first interlayer dielectric 94, thus forming the gate mask 116. In some embodiments, planarization processes such as chemical mechanical polishing, etch-back processes, combinations thereof, or similar processes may be used. When planarized, the dielectric material has portions remaining in the recess (which subsequently form the gate mask 116). After the planarization process, the upper surfaces of the gate spacer 82, the contact etch stop layer 92, the first interlayer dielectric 94, and the gate mask 116 are substantially coplanar (within process variations).

[0106] exist Figures 13A to 13CIn this configuration, mask 120 is formed over gate spacer 82, contact etch stop layer 92, first interlayer dielectric 94, and gate mask 116. Mask 120 can be formed by forming one or more mask layers and then patterning the mask layers with opening 122. The mask layers can be any photoresist that accepts photosensitive material, such as single-layer photoresist, double-layer photoresist, triple-layer photoresist, or the like. In some embodiments, a triple-layer photoresist comprising a bottom layer (e.g., a bottom antireflective coating (BARC) layer), a middle layer (e.g., a nitride, oxide, oxynitride, or the like), and a top layer (e.g., a photosensitive material) is used. The mask layers can be formed by spin coating, deposition processes such as chemical vapor deposition, combinations thereof, or similar processes. The mask layers can be patterned with opening 122 to form mask 120 using acceptable photolithography and etching techniques. The opening 122 is a narrow opening extending parallel to the longitudinal direction of the fin 52, and is covered by a contact etch stop layer 92, a first interlayer dielectric 94, and a gate mask 116. In some embodiments, the opening 122 extends over the multi-epitaxy source / drain region 88 and / or the multi-gate structure (including the gate dielectric 112 and the gate electrode 114).

[0107] exist Figures 14A to 14C In the etching process, the first interlayer dielectric 94 is etched using a mask 120 as an etch mask and a contact etch stop layer 92 as an etch stop layer to form a contact opening 124 for source / drain contacts. The etching can be any acceptable etching process, such as a process selective for the material of the first interlayer dielectric 94 (e.g., selecting a material for etching the first interlayer dielectric 94 at a faster rate than the materials of the gate spacer 82, the contact etch stop layer 92, and the gate mask 116). The etching process can be anisotropic. The contact opening 124 extends through the contact etch stop layer 92 after any acceptable etching process to expose the epitaxial source / drain regions 88. During etching, the gate mask 116 covers the gate structure (including the gate dielectric 112 and the gate electrode 114), thus protecting the gate structure during the etching of the contact opening 124. The etching process for forming the contact opening 124 is a self-aligned contact (SAC) etching process, in which the gate spacer 82, the contact etch stop layer 92, and the gate mask 116 are exposed to be etched during the etching of the contact opening 124. After the etching process, the mask 120 can be removed, for example by any acceptable ashing process.

[0108] exist Figures 15A to 15CIn the epitaxial source / drain contact 130, a source / drain contact 130 is formed in a contact opening 124. The source / drain contact 130 is a solid and electrically coupled epitaxial source / drain region 88. One or more spacers, such as contact spacers 132 and 134, are formed around the source / drain contact 130 in the contact opening 124. Each contact spacer 132 and contact spacer 134 may be annular in a top-down view. A metal-semiconductor alloy region 136 is formed at the interface between the epitaxial source / drain region 88 and the source / drain contact 130.

[0109] Figures 16 to 23 The formation of source / drain contacts 130, contact spacers 132 and 134, and the metal-semiconductor alloy region 136 is illustrated. It shows the formation of... Figure 15C The process steps in region 50R. During the formation of the source / drain contact 130, the recess 144 of the source / drain contact 130 (see...) Figure 19 A source / drain region 130 is formed in the epitaxial source / drain region 88 to allow for the formation of source / drain contacts 130 extending into the epitaxial source / drain region 88 (e.g., below the upper surface of the epitaxial source / drain region 88). This increases the contact area of ​​the epitaxial source / drain region 88, which reduces the contact resistance of the epitaxial source / drain region 88. After the formation of the recess 144, a planting process is performed to increase the dopant concentration in the bottom portion of the epitaxial source / drain region 88 of the recess 144. The planting process uses a pre-amorphous implant (PAI), which helps increase the dopant concentration and the dopant activation level in the desired portion of the epitaxial source / drain region 88. A metal-semiconductor alloy region 136 is then formed in the recess 144 on the portion of the epitaxial source / drain region 88 with a high dopant concentration. Therefore, the metal-semiconductor alloy region 136 has a high dopant concentration. Forming a metal-semiconductor alloy region 136 with a high doping concentration can help reduce the contact resistance to the epitaxial source / drain region 88.

[0110] for Figures 16 to 23 One or more processes described may be performed in one of the n-type region 50N and the p-type region 50P, and then repeated in the other of the n-type region 50N and the p-type region 50P. For example, the fabric planting process described later may be performed once in the n-type region 50N and then once in the p-type region 50P. Various masking steps may be used to mask and expose appropriate areas in the fabric planting process.

[0111] exist Figure 16In this configuration, spacer layer 142 is formed in contact opening 124. Spacer layer 142 may be formed of a dielectric material using a conformal deposition process, such that spacer layer 142 is formed on the upper surface of epitaxial source / drain region 88 and the sidewalls of gate spacer 82. Although not shown individually, spacer layer 142 may also be deposited on gate spacer 82 and gate mask 116 (see Figure 124). Figure 15C The upper surface of the material. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, aluminum oxide, or the like, which may be formed by chemical vapor deposition, atomic layer vapor deposition, or similar processes.

[0112] Before or after the formation of spacer layer 142, a first implantation process is performed to implant dopants in the upper portion 88U of the epitaxial source / drain region 88, thereby increasing the doping concentration of the upper portion 88U of the epitaxial source / drain region 88 and forming a first highly doped region 88D1. A metal-semiconductor alloy region will then be formed in / on the first highly doped region 88D1. The implanted dopants used to form the first highly doped region 88D1 have the same conductivity type as the epitaxial source / drain region 88. Specifically, n-type dopants are implanted in the epitaxial source / drain region 88 of the n-type region 50N, and p-type dopants are implanted in the epitaxial source / drain region 88 of the p-type region 50P. Acceptable n-type dopants include phosphorus, arsenic, tin, and the like. Acceptable p-type dopants include boron, boron difluoride (BF2), gallium, and the like.

[0113] The first implantation process is performed with a low implantation energy to ensure a shallow implantation. In some embodiments, the implantation energy of the first implantation process can range from 1,000 (1k) electron volts to 50,000 (50k) electron volts, taking into account shallow implantation. Therefore, the first implantation process results in the upper portion 88U of the epitaxial source / drain region 88 being implanted with dopant, while the lower portion 88L of the epitaxial source / drain region 88 remains unplanted. Implanting dopant in the upper portion 88U but not in the lower portion 88L of the epitaxial source / drain region 88 helps reduce the leakage current of the device. The implantation dose can be 5E13 cm⁻¹. -2 Up to 1E16cm -2 Within a certain range. The implantation can be vertical or inclined, and the inclination angle can be less than 60 degrees. During implantation, the temperature of the substrate 50 can be controlled within the range of -100 degrees Celsius to 500 degrees Celsius. In some embodiments, the first highly doped region 88D1 has a diameter of 1E20 cm. -3 Up to 1E22 cm -3 Range of doping concentrations.

[0114] exist Figure 17In this process, spacer layer 142 is patterned to form contact spacer 132. Spacer layer 142 can be patterned by etching spacer layer 142 to remove horizontal portions of spacer layer 142. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, can be performed to pattern spacer layer 142. Etching can be anisotropic. When etched, spacer layer 142 has vertical portions left on the sidewalls of gate spacer 82 (which subsequently form contact spacer 132).

[0115] Spacer layer 142 is over-etched to form recess 144 extending into epitaxial source / drain region 88. When the epitaxial source / drain region 88 is etched, contact spacer 132 helps protect the side regions of the upper portion 88U of the epitaxial source / drain region 88 to reduce loss of the first highly doped region 88D1. Source / drain contacts are subsequently formed in recess 144. Forming recess 144 increases the contact area of ​​the epitaxial source / drain region 88, which reduces the contact resistance to the epitaxial source / drain region 88. In some embodiments, after forming recess 144, the distance D1 between the upper surface of fin 52 and the bottom of recess 144 is in the range of 5 nm to 6 nm. After initially forming recess 144, the depth of recess 144 is less than the height of the first highly doped region 88D1. A timed etching process can be used to stop etching recess 144 after it reaches the desired depth.

[0116] exist Figure 18 In the contact opening 124 and the recess 144, spacer layer 146 is formed. Spacer layer 146 may be formed of a dielectric material using a conformal deposition process, such that spacer layer 146 is deposited on the upper surface of the epitaxial source / drain region 88 and the sidewalls of the contact spacer 132. Although not shown individually, spacer layer 146 may also be deposited on the contact spacer 132, the gate spacer 82, and the gate mask 116 (see Figure 144). Figure 15C On the upper surface of ). Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, aluminum oxide, or the like, which may be formed by chemical vapor deposition, atomic layer vapor deposition or similar processes.

[0117] exist Figure 19 In this process, spacer layer 146 is patterned to form contact spacers 134. Spacer layer 146 can be patterned by etching spacer layer 146 to remove horizontal portions of spacer layer 146. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, can be performed to pattern spacer layer 146. Etching can be anisotropic. When etched, spacer layer 146 has vertical portions left on contact spacers 132 and the sidewalls of epitaxial source / drain regions 88 (which subsequently form contact spacers 134).

[0118] Spacer layer 146 is over-etched to allow recess 144 to extend further into the epitaxial source / drain region 88. When etching the epitaxial source / drain region 88, contact spacers 132 and 134 help protect the side regions of the upper portion 88U of the epitaxial source / drain region 88, reducing the loss of the first highly doped region 88D1. Extending recess 144 further increases the contact area of ​​the epitaxial source / drain region 88, which further reduces the contact resistance to the epitaxial source / drain region 88. In some embodiments, after extending recess 144, the distance D2 between the upper surface of fin 52 and the bottom of recess 144 is in the range of 9 nm to 10 nm. After extending recess 144, the depth of recess 144 is greater than the height of the first highly doped region 88D1. A timed etching process can be used to stop etching recess 144 after it reaches the desired depth.

[0119] As previously mentioned, source / drain contacts will subsequently be formed in the recesses 144. Extending the recesses 144 benefits from increasing their depth, taking into account the large contact area for the epitaxial source / drain regions 88. However, also as previously mentioned, with the low implantation energy used in the first implantation process (in... Figure 16 (Description) to reduce device leakage current. Therefore, the depth of the recess 144 is greater than the height of the first highly doped region 88D1. Thus, the upper surface of the recess 144 is defined by the first highly doped region 88D1, but the lower surface of the recess 144 is partially defined by the epitaxial source / drain region 88, which has a lower doping concentration than the first highly doped region 88D1. A second implantation process will be described in more detail later (in... Figure 21 (Description) Dopant is partially implanted in the epitaxial source / drain region 88 at the bottom of the recess 144. Advantageously, this defines most of the surface of the recess 144 as a highly doped region. A metal-semiconductor alloy region will subsequently be formed in the recess 144, and the increased number of highly doped regions in the recess 144 increases the doping concentration of the metal-semiconductor alloy region, which reduces the contact resistance to the epitaxial source / drain region 88.

[0120] exist Figure 20In this process, pre-amorphous implantation is performed to form an amorphous region 148 in the epitaxial source / drain region 88. Pre-amorphous implantation can be performed by implanting amorphous impurities in a portion of the epitaxial source / drain region 88 that defines the recess 144. The amorphous impurities can be impurities with large atomic masses, taking into account the disruption of the lattice structure of the epitaxial source / drain region 88. For example, the amorphous impurities can be impurities with an atomic mass greater than 28, although other atomic masses can be used. Acceptable amorphous impurities include germanium, xenon, argon, silicon, and the like. The amorphous impurities can differ from the n-type and p-type dopants used before and after implantation. Other amorphous impurities can also be used. For example, the amorphous impurities can be n-type or p-type dopants, such as arsenic, phosphorus di(P2), and the like. Implanting amorphous impurities disrupts the lattice structure of the implanted portion of the epitaxial source / drain region 88, thus amorphizing those portions of the epitaxial source / drain region 88 to form the amorphous region 148.

[0121] Pre-amorphous implantation is performed with low implantation energy to ensure that the amorphous region 148 is shallow. Specifically, the upper portion 88U and the middle portion 88M of the epitaxial source / drain region 88 are exposed by amorphization recess 144 to form the amorphous region 148, but the lower portion 88L of the epitaxial source / drain region 88 is not amorphized. In some embodiments, the implantation energy for pre-amorphous implantation can be in the range of 1,000 (1k) electron volts to 50,000 (50k) electron volts. The implantation dose can be 5E13 cm⁻¹. -2 Up to 1E16cm -2 Within a certain range. The placement can be vertical or inclined, with an inclination angle less than 60 degrees. During placement, the temperature of the substrate 50 can be controlled within the range of -100 degrees Celsius to 500 degrees Celsius.

[0122] The contact spacer 134 can be disrupted by pre-amorphous implantation (as shown in the cross-wiring). For example, amorphous impurities can be implanted into the contact spacer 134, thus changing the material of the contact spacer 134. Thus, after pre-amorphous implantation, the contact spacer 134 includes amorphous impurities from the pre-amorphous implantation. In some embodiments, the concentration of amorphous impurities in the contact spacer 134 is in the range of 0.01 atomic percentage (0.01 at%) to 1 atomic percentage (1 at%).

[0123] exist Figure 21In the first implantation process, a second implantation process is performed to implant dopants in the amorphous region 148, thereby increasing the doping concentration of the middle portion 88M of the epitaxial source / drain region 88 and forming a second highly doped region 88D2. The amorphous region 148 will then recrystallize so that the second highly doped region 88D2 becomes part of the epitaxial source / drain region 88. A metal-semiconductor alloy region will then be formed on / in the second highly doped region 88D2. The implanted dopants in the amorphous region 148 to form the second highly doped region 88D2 have the same conductivity type as the epitaxial source / drain region 88. Specifically, n-type dopants are implanted into the amorphous region 148 in the n-type region 50N, and p-type dopants are implanted into the amorphous region 148 in the p-type region 50P. The dopants can be any dopants that are used in the first implantation process (described in...). Figure 16 The candidate dopant is described in the following description. In some embodiments, the same dopant is implanted using both a first implantation process and a second implantation process.

[0124] The second implantation process is performed with a low implantation energy to ensure a shallow implantation. In some embodiments, the implantation energy of the second implantation process can be in the range of 1,000 (1k) electron volts to 50,000 (50k) electron volts. Therefore, the second implantation process results in the amorphous region 148 being implanted to include impurities, while the lower portion 88L of the epitaxial source / drain region 88 remains unimplanted. Implanting impurities in the amorphous region 148 but not in the lower portion 88L of the epitaxial source / drain region 88 helps reduce leakage current in the device. The implantation dose can be 5E13 cm⁻¹. -2 up to 1E16 cm -2 Within a certain range. The implantation can be vertical or inclined, and the inclination angle can be less than 60 degrees. During implantation, the temperature of the substrate 50 can be controlled within the range of -100 degrees Celsius to 500 degrees Celsius. In some embodiments, the second highly doped region 88D2 has a diameter of 1E21 cm. -3 up to 3E22 cm -3 Doping concentration within the range.

[0125] Planting dopants in the amorphous region 148 helps allow the second planting process to achieve shallow planting and reduce dopant activation energy. Specifically, dopants planted in the amorphous region 148 can achieve a shallower depth and a larger activation range compared to planting in the crystalline region. Therefore, the second highly doped region 88D2 is adjacent to the recess 144 and does not extend far into the epitaxial source / drain region 88. In some embodiments, the distance D3 between the upper surface of the fin 52 and the bottom of the second highly doped region 88D2 is in the range of 5 nm to 20 nm. In some embodiments, the dopants planted in the amorphous region 148, instead of the dopants in the crystalline region, increase the dopant activation range by 5% to 50%. The second highly doped region 88D2 can therefore be rich in dopants. Increasing the doping concentration of the second highly doped region 88D2 helps increase the doping concentration of the subsequently formed metal-semiconductor alloy region, thus reducing the contact resistance to the epitaxial source / drain region 88. Furthermore, the dopants implanted in the amorphous region 148 after the extended recess 144 help reduce the loss of the second most doped region 88D2 when etching the epitaxial source / drain region 88.

[0126] The contact spacer 134 can be implanted via a second implantation process. For example, some dopants can be implanted into the contact spacer 134, thereby changing the material of the contact spacer 134. Therefore, after the second implantation process, the contact spacer 134 also includes dopants from the second doping process. In some embodiments, the concentration of dopants in the contact spacer 134 is in the range of 0.5 atomic percentages (0.5 at%) to 1.5 atomic percentages (1.5 at%). Furthermore, the presence of these dopants in the contact spacer 134 can cause surface oxidation of the contact spacer 134. In this way, the oxygen concentration of the contact spacer 134 can be increased via the second doping process.

[0127] exist Figure 22 In this process, an annealing process is performed to recrystallize the amorphous region 148. More specifically, the lattice structure of the amorphous region 148 is repaired by the annealing process, thus crystallizing the amorphous region 148 and removing the amorphous region 148 from the epitaxial source / drain region 88. In some embodiments, the annealing process includes a melting annealing process. In a melting annealing process, at least a portion of the epitaxial source / drain region 88 is melted. The annealing process may or may not include other non-melting annealing processes besides melting annealing, such as, but not limited to, millisecond annealing, which can be performed using lasers, ultraviolet light, flash lamps, etc. In a non-melting annealing process, no portion of the epitaxial source / drain region 88 is melted. The non-melting annealing process has the effect of activating dopants in the non-melting portions of the epitaxial source / drain region 88 in addition to the melted portions. Through the melting annealing process, the amorphous region 148 is recrystallized.

[0128] The amorphous region 148 has a lower melting point than the amorphous portion of the epitaxial source / drain region 88. The melting annealing process can therefore be controlled such that its temperature is greater than the melting point of the amorphous region 148 but lower than the melting point of the amorphous portion of the epitaxial source / drain region 88, so that the amorphous region 148 is molten while the amorphous portion of the epitaxial source / drain region 88 remains unmelted.

[0129] Following the recrystallization process, the dopants in the first highly doped region 88D1 and the second highly doped region 88D2 are activated. The recess 144 extends through the first highly doped region 88D1 and into (but not through) the second highly doped region 88D2. The upper surface of the recess 144 is defined by the first highly doped region 88D1, and the lower surface of the recess 144 is defined by the second highly doped region 88D2. Pre-amorphous implantation (to facilitate the extension of the recess 144) is performed after this beneficial extension. Figure 20 Description) and the second fabric planting process (with Figure 21 (Description) This allows a substantial portion of the recess 144 to be defined by a highly doped region, even when the recess 144 is deep. Furthermore, the implantation is shallow so that the second highly doped region 88D2 is immediately adjacent to the recess 144. In some embodiments, the distance D4 between the bottom of the recess 144 and the bottom of the second highly doped region 88D2 is in the range of 1 nanometer to 10 nanometers. The lower portion 88L of the epitaxial source / drain region 88 is therefore not used for implantation dopant to form the second highly doped region 88D2, which helps reduce device leakage current.

[0130] Before or after the recrystallization process, the metal-semiconductor alloy region 136 is formed on / in the first highly doped region 88D1 and the second highly doped region 88D2. The metal-semiconductor alloy region 136 may be a silicide region formed by metal silicides (e.g., titanium silicide, nickel silicide, platinum silicide, combinations thereof), a germanide region formed by metal germanides (e.g., titanium germanide, nickel germanide, platinum germanide, combinations thereof), a silicon-germanide region formed by both metal silicides and metal germanides, or similar. The metal-semiconductor alloy region 136 can be formed by depositing metal in the recess 144 followed by an annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 88 to form a low-resistance metal-semiconductor alloy, such as titanium, nickel, platinum, cobalt, tantalum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as atomic layer vapor deposition, chemical vapor deposition, physical vapor deposition, or similar processes. Any suitable annealing process can be performed to react the metal with the first highly doped region 88D1 and the second highly doped region 88D2, subsequently forming the metal-semiconductor alloy region 136. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the recess 144, for example, from the surface of the metal-semiconductor alloy region 136.

[0131] In some embodiments, a single annealing process is used to recrystallize both the amorphous region 148 and form the metal-semiconductor alloy region 136. For example, prior to recrystallization of the amorphous region 148, the metal for the metal-semiconductor alloy region 136 may be deposited on the recess 144 and the amorphous region 148. An annealing process, such as the previously described melt annealing process, may be performed subsequently.

[0132] When the metal-semiconductor alloy region 136 is formed, dopants are pulled out from portions of the epitaxial source / drain regions 88 immediately adjacent to the recess 144. Because these portions of the epitaxial source / drain regions 88 (including the first and second highly doped regions) are highly doped, the metal-semiconductor alloy region 136 is formed to have a high doping concentration. As will be described in more detail later, the metal-semiconductor alloy region 136 has a higher doping concentration than the epitaxial source / drain regions 88. Forming the metal-semiconductor alloy region 136 with a high doping concentration helps reduce the contact resistance to the epitaxial source / drain regions 88. Furthermore, because the recess 144 is deep, the increased depth of the metal-semiconductor alloy region 136 within the epitaxial source / drain regions 88 helps increase the contact area to the epitaxial source / drain regions 88. In some embodiments, the distance D5 between the upper surface of the fin 52 and the upper surface of the metal-semiconductor alloy region 136 is in the range of 0 nanometers to 10 nanometers, for example, at least 2 nanometers. The metal-semiconductor alloy region 136 is below the upper surface of the fin 52 and the epitaxial source / drain region 88.

[0133] exist Figure 23 In this embodiment, source / drain contacts 130 are formed in recesses 144 and contact openings 124. In an example of forming the source / drain contacts 130, pads (not shown individually), such as diffusion barrier layers, adhesive layers, or the like, and conductive materials may be formed in recesses 144 and contact openings 124. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive materials may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, or the like. Although not shown individually, conductive materials may also be formed in contact spacers 132, 134, gate spacer 82, and gate mask 116 (see [reference needed]). Figure 15C On the upper surface of the gate spacer 82, gate mask 116, and contact spacers 132, 134, a planarization process, such as chemical vapor deposition, can be performed to remove excess material from the upper surfaces of the gate spacer 82, gate mask 116, and contact spacers 132, 134. The remaining pads and conductive material form source / drain contacts 130 in the recess 144 and contact opening 124. The contact spacer 134 extends from the sidewall of the upper portion 88U of the epitaxial source / drain region 88 (e.g., the sidewall defining the recess 144, see...). Figure 22 Separate source / drain contacts 130. Additionally, contact spacers 134 can contact the metal-semiconductor alloy region 136.

[0134] exist Figures 24A to 24CIn this configuration, a second interlayer dielectric 154 is deposited over the gate spacer 82, the contact etch stop layer 92, the first interlayer dielectric 94, the gate mask 116, the source / drain contact 130, and the contact spacers 132 and 134. In some embodiments, the second interlayer dielectric 154 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, borosilicate glass, undoped silicon glass, or the like, which can be deposited by any suitable method, including chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or similar methods.

[0135] In some embodiments, an etch stop layer 152 is formed between the second interlayer dielectric 154 and the gate spacer 82, the contact etch stop layer 92, the first interlayer dielectric 94, the gate mask 116, the source / drain contact 130, and the contact spacers 132, 134. The etch stop layer 152 may include a dielectric material having high etch selectivity for etching from the second interlayer dielectric 154, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0136] exist Figures 25A to 25C In this configuration, a gate contact 162 and a source / drain via 164 are formed to contact the gate electrode 114 and the source / drain contact 130, respectively. The gate contact 162 is physical and electrically coupled to the gate electrode 114. The source / drain via 164 is physical and electrically coupled to the source / drain contact 130.

[0137] As an example of forming the gate contact 162 and the source / drain via 164, the opening of the gate contact 162 is formed through the second interlayer dielectric 154, the etch stop layer 152, and the gate mask 116, and the opening of the source / drain via 164 is formed through the second interlayer dielectric 154 and the etch stop layer 152. The openings can be formed using acceptable photolithography and etching techniques. Pads (not individually shown), such as diffusion barrier layers, adhesive layers, or the like, and conductive material can be formed in the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, or the like. A planarization process, such as chemical vapor deposition, can be performed to remove excess material from the upper surface of the second interlayer dielectric 154. The remaining pads and conductive material form the gate contact 162 and the source / drain via 164 in the openings. The gate contact 162 and the source / drain via 164 can be formed using different processes or the same process. Although shown as forming the same cross-section, it is preferable that each gate contact 162 and source / drain via 164 can be formed with a different cross-section, which can avoid short circuits in the contacts.

[0138] Figures 26A to 26CThis is based on some views of implementing a finned field-effect transistor. This embodiment is similar to... Figures 25A to 25C The embodiment differs in that the source / drain via 164 is omitted. Instead, the source / drain contacts 130 and contact spacers 132, 134 also extend through the etch stop layer 152 and the second interlayer dielectric 154. As an example of forming the device of this embodiment, it is described in Figures 13A to 14C The process can be performed after the formation of the etch stop layer 152 and the second interlayer dielectric 154. Specifically, the mask 120 (see...) Figures 13A to 13C It can be formed above the second interlayer dielectric 154. Contact opening 124 (see...) Figures 14A to 14C It can be formed through the second interlayer dielectric 154, the etch stop layer 152, the first interlayer dielectric 94, and the contact etch stop layer 92. (Described in...) Figures 16 to 23 The process can then be carried out in the contact opening 124.

[0139] Figure 27 The spectrum shows the concentration of each element in the embodiment device. The spectrum was generated in an experiment using energy-dispersive X-ray spectroscopy (EDS). In this experiment, the source / drain contact 130 is formed of cobalt, the metal-semiconductor alloy region 136 is formed of phosphorus-doped titanium silicide, and the epitaxial source / drain region 88 is formed of phosphorus-doped silicon. As described in the pre-amorphous implantation and previously... Figures 16 to 23 As a result of the implantation process, the device beneficially exhibits an increased doping concentration. The average doping concentration in the metal-semiconductor alloy region 136 can be improved by up to 10%. The metal-semiconductor alloy region 136 exhibits a high doping concentration throughout. In some embodiments, the metal-semiconductor alloy region 136 has an average doping concentration ranging from 5 atomic percentages (5 at%) to 25 atomic percentages (25 at%). The doping concentration (e.g., phosphorus) in the metal-semiconductor alloy region 136 is greater than the doping concentration in the epitaxial source / drain region 88. In some embodiments, the doping concentration in the metal-semiconductor alloy region 136 is 1.1 to 4 times greater than the doping concentration in the epitaxial source / drain region 88.

[0140] Furthermore, different portions of the metal-semiconductor alloy region 136 may have different doping concentrations. Specifically, the lower portion of the metal-semiconductor alloy region 136 may have a higher doping concentration than the higher portion. In some embodiments, the doping concentration of the lower portion of the metal-semiconductor alloy region 136 is greater than the doping concentration in the epitaxial source / drain region 88, and the doping concentration of the higher portion of the metal-semiconductor alloy region 136 is less than the doping concentration in the epitaxial source / drain region 88. For example... Figure 27 As shown, the metal-semiconductor alloy region 136 has a high doping concentration at a first interface I1 adjacent to the metal-semiconductor alloy region 136 and the epitaxial source / drain region 88. In some embodiments, the doping concentration of the metal-semiconductor alloy region 136 adjacent to the first interface I1 is in the range of 3 atomic percentages (3 at%) to 15 atomic percentages (15 at%). The doping concentration of the metal-semiconductor alloy region 136 adjacent to the first interface I1 is greater than the doping concentration of the metal-semiconductor alloy region 136 adjacent to the second interface I2 of the source / drain contact 130. In some embodiments, the doping concentration of the epitaxial source / drain region 88 is greater than the doping concentration of the metal-semiconductor alloy region 136 adjacent to the second interface I2, and the doping concentration of the epitaxial source / drain region 88 is less than the doping concentration of the metal-semiconductor alloy region 136 adjacent to the first interface I1. Forming a metal-semiconductor alloy region 136 with a high doping concentration helps reduce the contact resistance to the epitaxial source / drain region 88.

[0141] The embodiments offer advantages. Recesses 144 are formed such that they extend deep into the epitaxial source / drain regions 88, increasing the contact area with the epitaxial source / drain regions 88, which reduces the contact resistance of the epitaxial source / drain regions 88. A second implantation process is performed after forming the recesses 144 to increase the doping concentration of the portion of the epitaxial source / drain regions 88 at the bottom of the recesses 144. Furthermore, pre-amorphous implantation is performed before the second implantation process to improve the dopant activity of the subsequently implanted portion of the epitaxial source / drain regions 88. A metal-semiconductor alloy region 136 with a high doping concentration can then be formed. This further reduces the contact resistance of the epitaxial source / drain regions 88.

[0142] The disclosed fin field-effect transistor embodiments can also be applied to nanostructure devices such as nanostructure (e.g., nanosheets, nanowires, fully wound gates, or the like) field-effect transistors (NSFETs). In embodiments of nanostructure NSFETs, the fins are replaced by nanostructures formed by stacking alternating layers of patterned channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to the embodiments described above. After removing the dummy gate stack, the sacrificial layer in the channel region may be partially or completely removed. The alternative gate structure is formed in a manner similar to the embodiments described above, and the alternative gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the alternative gate structure may partially or completely surround the channel layer in the channel region of the nanostructure NSFET device. The interlayer dielectric and contacts for the alternative gate structure and source / drain regions may be formed in a manner similar to the embodiments described above. Nanostructure devices can be formed as disclosed in U.S. Patent No. 9,647,071, the entire contents of which are incorporated herein by reference.

[0143] Furthermore, fin-type field-effect transistors / nanostructure field-effect transistor devices can be interconnected via metallization layers in an overlay interconnect structure to form an integrated circuit. The overlay interconnect structure can be formed in a back-end of line (BEOL) process, where the metallization layer connects the gate contact 162 and the source / drain via 164. Additional features, such as passive devices, memory (e.g., magnetoresistive random access memory, resistive random access memory, phase-change random access memory, etc.), or similar components, can be integrated with the overlay interconnect structure during the back-end of line process.

[0144] In one embodiment, the device includes: a source / drain region adjacent to a channel region; an interlayer dielectric located on the source / drain region; a source / drain contact extending through the interlayer dielectric and into the source / drain region; a metal-semiconductor alloy region located between the source / drain contact and the source / drain region, the metal-semiconductor alloy region being disposed below the upper surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer surrounding the source / drain contact, the contact spacer including the first dopant and an amorphous impurity. In some embodiments of the device, the first dopant has the same conductivity type as the source / drain region. In some embodiments of the device, the source / drain region is an n-type source / drain region, and the first dopant is phosphorus, arsenic, or tin. In some embodiments of the device, the source / drain region is a p-type source / drain region, and the first dopant is boron, boron difluoride, or gallium. In some embodiments of the device, the amorphous impurity is germanium, xenon, argon, or silicon. In some embodiments of the device, a contact spacer is provided between the source / drain contact and the upper portion of the source / drain region.

[0145] In one embodiment, the device includes: a source / drain region adjacent to a channel region, the source / drain region including a first dopant; an interlayer dielectric located on the source / drain region; a source / drain contact extending through the interlayer dielectric and into the source / drain region, the source / drain contact extending below the upper surface of the channel region; and a metal-semiconductor alloy region located between the source / drain contact and the source / drain region, the metal-semiconductor alloy region including the first dopant, the lower portion of the metal-semiconductor alloy region having a larger concentration than the concentration of the first dopant in the source / drain region, and the upper portion of the metal-semiconductor alloy region having a smaller concentration than the concentration of the first dopant in the source / drain region. In some embodiments of the device, the metal-semiconductor alloy region has a first concentration of the first dopant immediately adjacent to the source / drain region and a first interface of the metal-semiconductor alloy region, and the metal-semiconductor alloy region has a second concentration of the first dopant immediately adjacent to the source / drain contact and a second interface of the metal-semiconductor alloy region, the first concentration being greater than the second concentration. In some embodiments of the device, the source / drain regions have a third concentration of the first dopant, which is less than the first concentration and greater than the second concentration. In some embodiments, the device further includes a contact spacer between the source / drain contact and the upper portion of the source / drain regions, the contact spacer comprising the first dopant. In some embodiments of the device, the contact spacer further includes an amorphous impurity, which is different from the first dopant.

[0146] In one embodiment, the method includes: depositing a first dopant in a first portion of an epitaxial source / drain region to form a first highly doped region in the epitaxial source / drain region; etching a recess in the epitaxial source / drain region, the recess extending through the first highly doped region; depositing an amorphous impurity in a second portion of the epitaxial source / drain region to form an amorphous region in the epitaxial source / drain region, the second portion of the epitaxial source / drain region being disposed at the bottom of the recess; depositing a first dopant in the amorphous region to form a second highly doped region in the epitaxial source / drain region; and annealing the epitaxial source / drain region to crystallize the amorphous region. In some embodiments, the method further includes: depositing metal on the first highly doped region and the second highly doped region; and reacting the metal with the first highly doped region and the second highly doped region to form a metal-semiconductor alloy region in the recess. In some embodiments, the method further includes: forming source / drain contacts on the recess and the metal-semiconductor alloy region. In some embodiments of the method, the amorphous impurity has an atomic mass greater than 28, and implanting the amorphous impurity in the second portion of the epitaxial source / drain region includes implanting the amorphous impurity at an implantation energy ranging from 1,000 (1k) electron volts to 50,000 (50k) electron volts. In some embodiments of the method, the amorphous impurity is germanium, xenon, argon, or silicon. In some embodiments of the method, etching a recess in the epitaxial source / drain region includes etching a recess in the epitaxial source / drain region to a first depth, the first depth being less than the height of the first highly doped region; and extending the recess into the epitaxial source / drain region to a second depth, the second depth being greater than the height of the first highly doped region. In some embodiments, the method further includes forming a contact spacer in the recess, wherein the amorphous impurity and the first dopant are implanted in the contact spacer. In some embodiments of the method, the first dopant has the same conductivity type as the epitaxial source / drain region. In some embodiments of the method, the first dopant is not implanted in the third portion of the epitaxial source / drain region, and the third portion of the epitaxial source / drain region is located below the second portion of the epitaxial source / drain region.

[0147] The foregoing outlines the features of several embodiments or examples to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Include: A source / drain region is adjacent to a channel region, the source / drain region including a first dopant; A layer of interlayer dielectric is located on the source / drain region; A source / drain contact extends through the interlayer dielectric and into the source / drain region; A metal-semiconductor alloy region is located between the source / drain contact and the source / drain region. The metal-semiconductor alloy region is disposed below an upper surface of the channel region. The metal-semiconductor alloy region includes the first dopant. A lower portion of the metal-semiconductor alloy region has a larger concentration than the concentration of the first dopant in the source / drain region, and an upper portion of the metal-semiconductor alloy region has a smaller concentration than the concentration of the first dopant in the source / drain region. as well as A contact spacer surrounds the source / drain contact, the contact spacer comprising the first dopant and an amorphous impurity.

2. The semiconductor device according to claim 1, wherein The first dopant has the same conductivity type as the source / drain region.

3. The semiconductor device according to claim 2, wherein The source / drain region is an n-type source / drain region, and the first dopant is phosphorus, arsenic, or tin.

4. The semiconductor device as claimed in claim 2, characterized in that, The source / drain region is a p-type source / drain region, and the first dopant is boron, boron difluoride, or gallium.

5. The semiconductor device as claimed in claim 1, characterized in that, The amorphous impurity is germanium, xenon, argon, or silicon.

6. The semiconductor device as claimed in claim 1, characterized in that, The contact spacer is disposed between the source / drain contact and an upper portion of the source / drain region.

7. A semiconductor device, characterized in that, Include: A source / drain region is adjacent to a channel region, the source / drain region including a first dopant; A layer of interlayer dielectric is located on the source / drain region; A source / drain contact extends through the interlayer dielectric and into the source / drain region, the source / drain contact extending below an upper surface of the channel region; as well as A metal-semiconductor alloy region is located between the source / drain contact and the source / drain region. The metal-semiconductor alloy region includes the first dopant. A lower portion of the metal-semiconductor alloy region has a larger concentration than the concentration of the first dopant in the source / drain region, and a higher portion of the metal-semiconductor alloy region has a smaller concentration than the concentration of the first dopant in the source / drain region.

8. The semiconductor device as claimed in claim 7, characterized in that, The metal-semiconductor alloy region has a first concentration of the first dopant adjacent to a first interface of the source / drain region and the metal-semiconductor alloy region, and the metal-semiconductor alloy region has a second concentration of the first dopant adjacent to a second interface of the source / drain contact and the metal-semiconductor alloy region, wherein the first concentration is greater than the second concentration.

9. The semiconductor device as claimed in claim 8, characterized in that, The source / drain region has a third concentration of the first dopant, which is less than the first concentration and greater than the second concentration.

10. The semiconductor device as claimed in claim 7, characterized in that, Also includes: A contact spacer is provided between the source / drain contact and an upper portion of the source / drain region, the contact spacer comprising the first dopant.

11. The semiconductor device as claimed in claim 10, characterized in that, The contact spacer also includes an amorphous impurity that is different from the first dopant.

12. A method for forming a semiconductor device, characterized in that, Include: A first highly doped region is formed in the epitaxial source / drain region by implanting a first dopant in a first portion of the epitaxial source / drain region. Etch a recess in the epitaxial source / drain region, the recess extending through the first highly doped region; An amorphous region is formed in the epitaxial source / drain region by implanting an amorphous impurity in a second portion of the epitaxial source / drain region, the second portion of the epitaxial source / drain region being disposed at the bottom of the recess; By planting the first dopant in the amorphous region, a second highly doped region is formed in the epitaxial source / drain region. Anneal the epitaxial source / drain region to crystallize the amorphous region; A metal is deposited on the first highly doped region and the second highly doped region; as well as The metal reacts with the first highly doped region and the second highly doped region to form a metal-semiconductor alloy region in the recess, wherein a lower portion of the metal-semiconductor alloy region has a larger concentration than the concentration of the first dopant in the source / drain region, and a higher portion of the metal-semiconductor alloy region has a smaller concentration than the concentration of the first dopant in the source / drain region.

13. The method as described in claim 12, characterized in that, The source / drain region is an n-type source / drain region, and the first dopant is phosphorus, arsenic, or tin.

14. The method as described in claim 12, characterized in that, Also includes: A source / drain contact is formed on the recess and the metal-semiconductor alloy region.

15. The method as described in claim 12, characterized in that, The amorphous impurity has an atomic mass greater than 28, and the amorphous impurity is implanted in the second portion of the epitaxial source / drain region, including: The amorphous impurity is implanted with an implantation energy ranging from 1,000 electron volts to 50,000 electron volts.

16. The method as described in claim 15, characterized in that, The amorphous impurity is germanium, xenon, argon, or silicon.

17. The method as described in claim 12, characterized in that, Etching the recess in the epitaxial source / drain region includes: The recess is etched in the epitaxial source / drain region to reach a first depth, the first depth being less than a height of the first highly doped region; and The recess extends into the epitaxial source / drain region to reach a second depth, which is greater than the height of the first highly doped region.

18. The method as described in claim 12, characterized in that, Also includes: A contact spacer is formed in the recess, wherein the amorphous impurity and the first dopant are implanted in the contact spacer.

19. The method as described in claim 12, characterized in that, The first dopant has the same conductivity type as the epitaxial source / drain region.

20. The method as described in claim 12, characterized in that, The first dopant is not implanted in a third portion of the epitaxial source / drain region, and the third portion of the epitaxial source / drain region is located below the second portion of the epitaxial source / drain region.

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