Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same, the method of fabricating the semiconductor device includes: depositing a multilayer stack on a semiconductor substrate, the multilayer stack including a plurality of sacrificial layers and a plurality of channel layers alternately; forming a dummy gate on the multilayer stack; forming a first spacer on sidewalls of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implantation energy and a first implantation dosage; and performing a second implantation process to form a second doped region, wherein the first doped region and the second doped region are in the channel layers, portions of the channel layers not covered by the first spacer and the dummy gate, the second implantation process having a second implantation energy and a second implantation dosage, the second implantation energy being greater than the first implantation energy, and the first implantation dosage being different from the second implantation dosage.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same that can control the lateral distribution of dopants. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] By continuously reducing the minimum feature size, the semiconductor industry is constantly improving the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), allowing more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems must be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device includes depositing a multilayer stack on a semiconductor substrate, wherein the multilayer stack includes alternating plurality of sacrificial layers and plurality of channel layers; forming a dummy gate on the multilayer stack; forming a first spacer wall on the sidewall of the dummy gate; performing a first implantation process to form a first doped region, wherein the first implantation process has a first implantation energy and a first implantation dose; performing a second implantation process to form a second doped region, wherein the first doped region and the second doped region are in a portion of the channel layer, this portion being not covered by the first spacer wall and the dummy gate, the second implantation process having a second implantation energy and a second implantation dose, the second implantation energy being greater than the first implantation energy, and the first implantation dose being different from the second implantation dose; after performing the first implantation process and the second implantation process, forming a second spacer wall on the first spacer wall; forming a first recess in the multilayer stack, wherein the multilayer stack is adjacent to the second spacer wall; and forming an epitaxial source / drain region in the first recess.

[0005] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device includes forming a dummy gate on a first channel region of a first channel layer and a second channel region of a second channel layer, wherein the first channel layer and the second channel layer are deposited on a semiconductor substrate; forming a first spacer wall on the sidewall of the dummy gate; performing a first implantation process to implant dopant into the first channel layer, thereby forming a plurality of first doped portions at a plurality of first ends of the first channel region; performing a second implantation process to implant dopant into the second channel layer, thereby forming a plurality of second doped portions at a plurality of second ends of the second channel region, wherein during the first implantation process and the second implantation process, the dummy gate and the first spacer walls are used as implantation masks, wherein each of the first doped portions and the second doped portions has a gradient doping profile; and after performing the first implantation process and the second implantation process, forming a second spacer wall on the sidewall of the first spacer wall.

[0006] According to one embodiment of the present disclosure, a semiconductor device includes a first channel layer, a second channel layer, a gate structure, a plurality of source / drain regions, a plurality of first doped portions, and a plurality of second doped portions. The first channel layer is on a semiconductor substrate, the second channel layer is on the first channel layer, and the gate structure surrounds the first and second channel layers. The source / drain regions are located on opposite sides of the gate structure, the first channel layer, and the second channel layer. The first doped portions are located at multiple endpoints of the first channel layers, each of which is in solid contact with an adjacent source / drain region. The doping concentration of each of the first doped portions decreases in a direction extending from the adjacent source / drain region. The second doped portions are located at multiple ends of the second channel layer, each of which is in solid contact with an adjacent source / drain region. The doping concentration of each of the second doped portions decreases in a direction extending from the adjacent source / drain region, and the doping concentration of the first and second doped portions is lower than the doping concentration of the source / drain regions. Attached Figure Description

[0007] A better understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are for illustrative purposes only and are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0008] Figure 1 This is an example illustrating nano-structured field-effect transistors (nano-FETs) in a three-dimensional view according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B and Figure 7C This is a cross-sectional view illustrating an intermediate stage of the process of a nanostructured field-effect transistor according to some embodiments of this disclosure;

[0010] Figures 8A to 8C The illustrations depict fabrication processes 61 to 63 for guiding fabrication materials or admixtures according to some embodiments of this disclosure;

[0011] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H , Figure 9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Figure 9O , Figure 9P , Figure 9Q , Figure 9R , Figure 9S , Figure 9T , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B , Figure 14C , Figure 15 , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 16G , Figure 16H , Figure 16I , Figure 16J , Figure 16K , Figure 16L , Figure 16M , Figure 16N , Figure 16O , Figure 16P , Figure 16Q , Figure 16R , Figure 16S , Figure 16T , Figure 16U , Figure 16V , Figure 17A , Figure 17B, Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A and Figure 24B This is a cross-sectional view illustrating an intermediate stage of the fabrication process of a nanostructured field-effect transistor according to some embodiments of the present disclosure.

[0012] [Symbol Explanation]

[0013] 20: Separator

[0014] 42: Plane

[0015] 44: Vector

[0016] 45, 46, 56, 67A, 67B, 69A, 69B, 69C: Areas

[0017] 49: Interface breakdown zone

[0018] 50: Substrate

[0019] 50N: n-type region

[0020] 50P:p-type area

[0021] 51, 51A, 51B, 51C: First semiconductor layer

[0022] 52, 52A, 52B, 52C: First nanostructure

[0023] 53, 53A, 53B, 53C: Second semiconductor layer

[0024] 54: Second Nanostructure

[0025] 54A, 54B, 54C: Channel Layer

[0026] 55: Nanostructures

[0027] 57, 58, 59: Doped regions

[0028] 60: Passage Area

[0029] 61, 62, 63: Fabric planting technology

[0030] 64: Multi-layer stacking

[0031] 65A, 65B

[0032] 66: Fins

[0033] 68: Shallow ditch insulation area

[0034] 70: Dummy Dielectric Layer

[0035] 71: Dummy gate dielectric

[0036] 72: Dummy gate layer

[0037] 74: Masking layer

[0038] 76: Dummy gate

[0039] 78: Mask

[0040] 81: First gap wall

[0041] 82: Second spacer wall

[0042] 83: Spacer wall

[0043] 86: First Depression

[0044] 88: Side wall depression

[0045] 90: Inner spacer wall

[0046] 91: First epitaxial material

[0047] 92: Epitaxial source / drain region

[0048] 92A: First semiconductor material layer

[0049] 92B: Second semiconductor material layer

[0050] 92C: Third semiconductor material layer

[0051] 93: Fabric implantation technology

[0052] 94: Contact Etching Stop Layer

[0053] 96: First layer interlayer dielectric

[0054] 98: Depression

[0055] 102: Gate electrode

[0056] 104: Gate Mask

[0057] 106: Interlayer dielectric of the second layer

[0058] 108, 109: Opening

[0059] 110: Silicification zone

[0060] 112: Source / Drain Contact Window

[0061] 114: Gate contact window

[0062] 120: Gate dielectric layer

[0063] 213: Axis

[0064] A-A', B-B': Cross-section

[0065] D1, D2, D3, D4, D5, D6: Distance

[0066] W1: First width

[0067] W2: Second width

[0068] W3: Third width

[0069] W4: Fourth Width

[0070] W5: Fifth Width

[0071] W6: Sixth Width

[0072] W7: Seventh Width

[0073] W8: Eighth Width

[0074] W9: Ninth Width

[0075] θ1, θ2: Inclination angles Detailed Implementation

[0076] The following disclosure provides various embodiments or illustrations to achieve different features of this disclosure. Specific examples of elements and configurations described below are used to simplify this disclosure. It is understood that such descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, in the following description, forming a first feature on or above a second feature may include some embodiments where the first and second features are in direct contact with each other; it may also include some embodiments where other features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, element symbols and / or reference numerals may be reused in multiple embodiments of this disclosure. Such reuse is for simplification and clarity purposes and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0077] Furthermore, spatial correspondence terms, such as "below," "below," "lower than," "above," and similar terms, may be used here to facilitate the explanation of the relationship between one element or feature depicted in the figure and one or more other elements or features. These spatial correspondence terms, in addition to the orientation shown in the figure, also encompass various different orientations in which the device is used or operated. The device may be placed in other orientations (e.g., rotated 90 degrees or in other orientations), and the spatial correspondence descriptions used in this disclosure may be interpreted accordingly.

[0078] Various embodiments provide performance-improving semiconductor devices and methods for manufacturing the same. These semiconductor devices may be nanostructure field-effect transistors (FETs, also known as nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), or gate-all-around field-effect transistors (GAAFETs)). These embodiments include methods for forming semiconductor nanostructures on semiconductor fins, and methods for forming dummy gates and masks on the semiconductor nanostructures and fins. A first gap wall is then formed on the sidewall of the dummy gate and the mask. Then, multiple ion implantation processes are performed on the semiconductor nanostructure using a modulated ion beam with different implantation energies and doses. Next, a second gap wall is formed along the sidewall of the first gap wall. Recesses are formed in the semiconductor nanostructure and the semiconductor fin. Next, an undoped silicon layer is formed in the recess, and an ion implantation process is performed on the silicon layer to give it a gradient doped profile. Then, the source / drain regions are formed in the recess on the gradient doped silicon layer.

[0079] Advantageous features of one or more embodiments disclosed herein include the ability to control the lateral dispersion of dopants into the channel regions of a semiconductor structure at different depths, and the ability to increase the lateral dispersion of dopants into the channel regions under the first spacer wall, the second spacer wall, and the dummy gate. This allows the dispersed dopants to extend further into the channel regions of the semiconductor structure, resulting in a shorter effective channel length, thereby reducing the channel resistance (R0). ch Secondly, the formation of a silicon layer with a gradient doped profile in the source / drain region results in a reduced electric field in the source / drain region, and thus a lower junction leakage current (I0). boff Furthermore, the method disclosed herein can be easily integrated into existing processes and provides a low-cost means of reducing junction leakage current and channel resistance.

[0080] Figure 1 This is an example of a nanostructured field-effect transistor (FET) (e.g., nanowire FET, nanosheet FET, etc.) illustrated in a three-dimensional view according to some embodiments. The nanostructured FET includes nanostructures 55 (e.g., nanosheets, nanowires, or the like) located on fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 serve as channel regions of the nanostructured FET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) 68 is disposed between adjacent fins 66, wherein fins 66 may protrude from adjacent shallow trench isolation regions 68. Although the shallow trench isolation regions 68 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein may refer alone to a semiconductor substrate or a combination of a semiconductor substrate and a shallow trench isolation region. Secondly, although the bottom portion of fin 66 and substrate 50 are depicted as a continuous single material, the bottom portion of fin 66 and / or substrate 50 may comprise one or more materials. In this document, fin 66 refers to the portion extending between adjacent shallow trench insulation regions 68.

[0081] The gate dielectric layer 120 is located on the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located on the gate dielectric layer 120. Epitaxial source / drain regions 92 are disposed on the fin 66, which is located on the opposite side of the gate dielectric layer 120 and the gate electrode 102.

[0082] Figure 1 Reference cross-sections for use in subsequent figures are illustrated. Cross-section A-A' is along the longitudinal axis of the gate electrode 102, and in the direction of current, for example, perpendicular to the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. Cross-section B-B' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions 92 of the multiple nanostructured field-effect transistor. Cross-section C-C' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fins 66 of the nanostructured field-effect transistor, and in the direction of current, for example, between the epitaxial source / drain regions 92 of the nanostructured field-effect transistor. These reference cross-sections are referenced in subsequent figures for clarity.

[0083] Some of the embodiments discussed herein are within the context of nanostructured field-effect transistors (nanoFETs) formed using a gate-last process. In other embodiments, a gate-first process is used. Some embodiments are also contemplated for planar device configurations, such as planar field-effect transistors or fin field-effect transistors (FinFETs).

[0084] Figures 2 to 8A and Figures 9A to 24B This is a cross-sectional view of an intermediate stage in the fabrication of a nanostructured field-effect transistor according to some embodiments of this disclosure. Figures 2 to 5 6A Figure 7A , Figure 10A , Figure 11A , Figure 14A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A and Figure 24A It is based on the drawing Figure 1 The reference section is A-A'. Figure 6B , Figure 7B , Figure 10B , Figure 11B , Figure 14B , Figure 16B and Figure 16C It is based on the drawing Figure 1 The reference section is B-B'. Figure 6C , Figure 7C , Figure 8A , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H , Figure 9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Figure 9O , Figure 9P , Figure 9Q , Figure 9R , Figure 9S , Figure 9T , Figure 10C , Figure 11C , Figure 12 , Figure 13 , Figure 14C , Figure 15 , Figure 16D , Figure 16E , Figure 16F , Figure 16G , Figure 16H , Figure 16I , Figure 16J , Figure 16K , Figure 16L , Figure 16M , Figure 16N , Figure 16O , Figure 16P , Figure 16Q , Figure 16R , Figure 16S , Figure 16T , Figure 16U , Figure 16V , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B It is based on the drawing Figure 1 The reference section is C-C'.

[0085] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. This insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on the substrate, typically a silicon or glass substrate. Other materials may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductor, alloy semiconductor, or a combination thereof, wherein the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, and the alloy semiconductor includes silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide or a combination thereof.

[0086] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an n-type metal-oxide-semiconductor (NMOS) transistor, for example, an n-type nanostructure field-effect transistor, and the p-type region 50P can be used to form a p-type device, such as a p-type metal-oxide-semiconductor (PMOS) transistor, for example, a p-type nanostructure field-effect transistor. The n-type region 50N can be physically separated from the p-type region 50P (as shown in separator 20), and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can also be disposed between the n-type region 50N and the p-type region 50P. Although only one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0087] The substrate 50 may be lightly doped with p-type or n-type impurities. Anti-punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an anti-punch-through region 49. During the anti-punch-through ion implantation, dopants may be implanted in both the n-type region 50N and the p-type region 50P. The conductivity of the dopants may be opposite to that of the source / drain regions to be formed in each of the n-type region 50N and the p-type region 50P. The anti-punch-through region 49 may extend below the source / drain regions subsequently formed in a nanostructured field-effect transistor, wherein the source / drain regions will be generated in a subsequent process. In some embodiments, the doping concentration in the anti-punch-through region 49 may range from approximately 1 x 10⁻⁶. 18 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 For simplicity and readability, the interface breakdown area 49 may not be shown in each subsequent figure.

[0088] Secondly, at Figure 2In this embodiment, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes an interleaved layer of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layer 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layer 53). For illustrative purposes and as discussed in more detail below, the first semiconductor layers (also referred to as sacrificial layers) 51A, 51B, and 51C will be removed, and the second semiconductor layers (also referred to as channel layers) 53A, 53B, and 53C will be patterned to form channel regions of the nanostructured field-effect transistor in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layers 51A, 51B, and 51C can be removed, and the second semiconductor layers 53A, 53B, and 53C can be patterned to form a channel region of a nanostructured field-effect transistor in the n-type region 50N. The second semiconductor layers 53A, 53B, and 53C can also be removed, and the first semiconductor layers 51A, 51B, and 51C can be patterned to form a channel region of a nanostructured field-effect transistor in the p-type region 50P. In some embodiments, the second semiconductor layers 53A, 53B, and 53C can be removed, and the first semiconductor layers 51A, 51B, and 51C can be patterned to form a channel region of a nanostructured field-effect transistor in the n-type region 50N. The first semiconductor layers 51A, 51B, and 51C can also be removed, and the second semiconductor layers 53A, 53B, and 53C can be patterned to form a channel region of a nanostructured field-effect transistor in the p-type region 50P. In some embodiments, the second semiconductor layers 53A, 53B and 53C may be removed, and the first semiconductor layers 51A, 51B and 51C may be patterned to form the channel region of the nanostructure field-effect transistor in both the n-type region 50N and the p-type region 50P.

[0089] For illustrative purposes only, the multilayer stack 64 is shown as comprising three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may comprise two or more first semiconductor layers 51 and two or more second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanostructure field-effect transistors, such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanostructure field-effect transistors, such as silicon, silicon carbide, or the like. For illustrative purposes only, the multilayer stack 64 is shown as having the lowest semiconductor layer suitable for p-type nanostructure field-effect transistors. In some embodiments, the multilayer stack 64 may be formed such that the lowest layer is a semiconductor layer suitable for n-type nanostructure field-effect transistors.

[0090] The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity towards each other. For example, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layers 53A, 53B, and 53C to be patterned to form the channel region of the nanostructured field-effect transistor. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layers 51A, 51B, and 51C are patterned to form the channel region, the second semiconductor 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layers 51A, 51B, and 51C to be patterned to form the channel region of the nanostructured field-effect transistor.

[0091] Please refer to the following: Figure 3According to some embodiments, fins 66 are formed in a substrate 50, and nanostructures 55 are formed in a multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. This etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. This etching may be anisotropic. By etching the multilayer stack 64 to form nanostructures 55, first nanostructures 52A to 52C (synthesized as first nanostructure 52) may be further defined from the first semiconductor layer 51, and second nanostructures 54A to 54C (synthesized as second nanostructure 54) may be defined from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 may be collectively referred to as nanostructure 55. In one embodiment, the height H1 from the top surface of nanostructure 55 (e.g., the top surface of the second nanostructure 54C) to the bottom surface of nanostructure 55 (e.g., the bottom surface of the first nanostructure 52A) can be 40 nm to 60 nm.

[0092] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more lithography techniques (including dual-patterning or multi-patterning processes). Generally, dual-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the patterns to be fabricated with a spacing smaller than that achievable using other single direct optical lithography processes. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using an optical lithography process. Spacer walls are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer walls can be used to pattern the fins 66.

[0093] For illustrative purposes, Figure 3 The fins 66 illustrated in the n-type region 50N and p-type region 50P have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be greater than or less than the width of the fin 66 in the p-type region 50P. Secondly, although each fin 66 and nanostructure 55 is illustrated to have a consistent width from end to end, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each fin 66 and / or nanostructure 55 continuously increases toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal.

[0094] exist Figure 4In this embodiment, a shallow trench insulating region 68 is formed adjacent to the fin 66. The shallow trench insulating region 68 can be formed by depositing an insulating material on the substrate 50, the fins 66, the nanostructure 55, and between adjacent fins 66. This insulating material can be formed, for example, of oxides (e.g., silicon oxide), silicon nitride, the like, or combinations thereof, and can be formed, for example, by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), similar methods, or combinations thereof. Other insulating materials formed by any acceptable process can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, in some embodiments, multiple layers may be used. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructures 55. Then, a filler material as described above may be formed on the liner.

[0095] Next, a removal process is applied to the insulating material to remove excess insulating material from the nanostructure 55. In some embodiments, a planarization process (such as chemical mechanical polishing (CMP), etch-back, a combination thereof, or similar methods) may be used. The planarization process exposes the nanostructure 55 so that, after the planarization process is completed, the top surface of the nanostructure 55 and the insulating material is flat.

[0096] Then, the insulating material is recessed to form shallow trench insulating regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from the adjacent shallow trench insulating regions 68. Next, the top surface of the shallow trench insulating region 68 may have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof, as illustrated. The top surface of the shallow trench insulating region 68 can be formed as flat, convex, and / or concave by suitable etching. The shallow trench insulating region 68 can be recessed using acceptable etching processes, such as etching processes selective for the insulating material (e.g., etching rate of the insulating material greater than the etching rate of the fins 66 and the nanostructures 55). For example, oxides can be removed using diluted hydrofluoric acid (dHF).

[0097] The above regarding Figures 2 to 4The discussed process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed on the top surface of a substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures may comprise alternating semiconductor materials as discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing epitaxial structures, the epitaxially grown material can be in-situ doped during growth, which can exclude previous and / or subsequent implantations, although in-situ and implantation doping can be used simultaneously.

[0098] Additionally, for illustrative purposes only, the first semiconductor layer 51 (and the formed first nanostructure 52) and the second semiconductor layer 53 (and the formed second nanostructure 54) are described and discussed herein as containing the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials or formed in different orders in the p-type region 50P and the n-type region 50N.

[0099] Furthermore, in Figure 4 In this process, suitable wells (not shown separately) can be formed in the fins 66, nanostructures 55, and / or shallow trench insulating regions 68. In some embodiments with a well configuration, different implantation steps for the n-type region 50N and p-type region 50P can be achieved by utilizing photoresist or other masks (not shown separately). For example, photoresist can be formed on the fins 66 and shallow trench insulating regions 68 in the n-type region 50N and p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin-on technique and patterned using acceptable optical lithography techniques. Once the photoresist is patterned, n-type impurities are implanted in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted in the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, and the concentration range of the implanted regions is substantially about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After application, the photoresist can be removed, for example, through an acceptable ashing process.

[0100] Before or after the implantation of the p-type region 50P, photoresist or other masks (not shown separately) are formed on the fins 66, nanostructures 55, and shallow trench insulating regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin technique and patterned using an acceptable optical lithography technique. Once the photoresist is patterned, p-type impurities are implanted in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the implantation of p-type impurities in the p-type region 50P. The p-type impurities can be, for example, boron, boron fluoride, indium, or the like, and their concentration in the region is substantially in the range of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After application, the photoresist can be removed, for example, using an acceptable ashing process.

[0101] After implantation in the n-type region 50N and p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, during growth, the growth material of the epitaxial fins can be in-situ doped to exclude implantation, although in-situ and implantation doping can be used simultaneously.

[0102] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a masking layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70 and planarized (e.g., by chemical mechanical polishing). The masking layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material, and may be selected from the group comprising amorphous silicon, polycrystalline silicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited using physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that exhibit high etch selectivity for the etch of the isolation region. The mask layer 74 may, for example, comprise silicon nitride, silicon oxynitride, or the like. In this example, the monolayer dummy gate layer 72 and the monolayer mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It is noteworthy that, for illustrative purposes only, the dummy dielectric layer 70 is shown covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that it covers the shallow trench insulating region 68 and extends between the dummy gate layer 72 and the shallow trench insulating region 68.

[0103] Figures 6A to 24B These are various additional steps in the manufacture of the apparatus of the illustrated embodiments. Figures 6A to 24B This describes the features within the n-type region 50N or the p-type region 50P. Figures 6A to 6C The mask layer 74 can be patterned using acceptable optical lithography and etching techniques (see [link]). Figure 5 The pattern of the mask 78 is then transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form the dummy gate 76 and the dummy gate dielectric 71, respectively. The dummy gate 76 covers the respective channel region 60 of the fin 66 and / or the nanostructure 55. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gate 76 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the respective fin 66.

[0104] Figures 7A to 7C In the middle, by depositing the first interstitial wall layer at Figures 6A to 6CThe illustrated structure forms the first spacer 81 and is subsequently patterned in the first spacer layer. The first spacer layer is formed on the top surface of the shallow trench insulating region 68, the top surface and sidewalls of the fins 66, the nanostructure 55 and the mask 78, and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. This first spacer layer can be formed using silicon oxide, silicon nitride, silicon oxynitride, or similar materials formed by thermal oxidation or chemical vapor deposition, atomic layer deposition, or similar methods. Next, the first spacer layer is etched to form the first spacer 81. As will be discussed in more detail below, the first spacer 81 and the second spacer 82 (illustrated later in...) Figures 10A to 10C The first spacer wall 81 is used for self-alignment in the subsequent formation of the source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processes. A suitable etching process can be used to etch the first spacer wall layer, such as isotropic etching (e.g., wet etching), anisotropic etching (e.g., dry etching), or similar processes. In one embodiment, the thickness T1 of the first spacer wall 81 ranges substantially from 3 nm to 5 nm.

[0105] exist Figure 8A In this process, multiple implantation processes 61 to 63 are performed on the nanostructure 55 and / or fin 66 to introduce dopants into exposed areas of the nanostructure 55 and / or fin 66 (e.g., areas not covered by the first spacer wall 81, dummy gate 76, and mask 78). In some embodiments, the first spacer wall 81, dummy gate 76, and mask 78 are used as implantation masks during implantation processes 61 to 63. Multiple implantation processes 61 to 63 are used to introduce dopants into different depths of the nanostructure 55 and / or fin 66 and can be performed using a high-current ion implanter or the like. Figure 8B As shown, the implantation processes 61 to 63 can guide the implantation of material (or dopants) at a tilt angle θ1 relative to axis 213, where axis 213 is perpendicular to the main surface of substrate 50 (e.g., wafer). In some embodiments, the tilt angle θ1 can be 0° to 30°. Figure 8C As shown, the implantation processes 61 to 63 can be twisted (or rotated) by an angle θ2 to guide the implantation of the substrate (or dopant), wherein the twist angle θ2 specifically refers to the angle between the wafer notch or plane 42 (e.g., when the substrate 50 is a wafer) and the vector 44, and the vector 44 is formed by projecting the direction vector of the ion beam onto the wafer. In some embodiments, the twist / rotation angle θ2 can be from 0° to 360°.

[0106] Planting processes 61 to 63 can be performed such that the planted material (dopant) is delivered using an ion beam in each planting process 61 to 63, wherein the ion beam has different planting energies and different planting doses. Each planting process 61 to 63 can introduce the dopant into a selected depth of nanostructure 55 and / or fin 66. For example, in one embodiment, using a first planting energy, planting process 61 can introduce the dopant into second nanostructure 54B / 54C and first nanostructure 52C to form a doped region 57. In one embodiment, using a second planting energy, planting process 62 can introduce the dopant into second nanostructure 54A / 54B and first nanostructure 52B to form a doped region 58. Doped region 58 is lower than doped region 57. In one embodiment, using a third planting energy, planting process 63 can introduce the dopant into second nanostructure 54A, first nanostructure 52A, and fin 66 to form a doped region 59. Doped region 59 is lower than doped region 58. In one embodiment, the third implantation energy is greater than both the first and second implantation energies, and the second implantation energy of implantation process 62 is greater than the first implantation energy of implantation process 61. In this way, the implantation process with the higher implantation energy allows the dopant to be introduced into the nanostructure 55 and / or fin 66 to a greater depth. Implantation processes 61 to 63 can be performed in any order, and implantation processes 61 to 63 can be performed to introduce the dopant into the nanostructure 55 and / or fin 66, such as... Figure 8A The depth shown. Although Figure 8A Three implantation processes 61 to 63 are illustrated, allowing for two or more implantation processes to be performed on the nanostructure 55 and / or fins 66. Although Figure 8A The doped regions 57, 58, and 59 shown overlap each other; however, in some embodiments, none of the doped regions 57, 58, and 59 overlap. In one embodiment, each doped region 57, 58, and 59 may have a gradient doping profile such that the dopant concentration decreases from the apex of each doped region 57, 58, and 59 toward the substrate 50. In one embodiment, the implantation energy and implantation dose are modulated (continued in...). Figure 9B (Note) This makes the doped regions 57, 58 and 59 (including the overlapping parts of doped regions 57, 58 and 59) have substantially uniform doping concentrations.

[0107] The implantation material may comprise ions formed from arsenic (As), phosphorus (P), antimony (Sb), boron difluoride (BF2), boron (B), combinations thereof, or the like. In one embodiment, implantation processes 61 to 63 introduce ions derived from arsenic (As) and / or phosphorus (P) into nanostructures 55 and / or fins 66 in an n-type region 50N, such as an n-type metal-oxide-semiconductor region. In one embodiment, implantation processes 61 to 63 introduce ions derived from antimony (Sb), boron difluoride (BF2), and / or boron (B) into nanostructures 55 and / or fins 66 in a p-type region 50P, such as a p-type metal-oxide-semiconductor region. In this method, the nanostructures 55 and / or fins 66 (e.g., n-type metal-oxide-semiconductor regions) in the n-type region 50N and / or the nanostructures 55 and / or fins 66 (e.g., p-type metal-oxide-semiconductor regions) in the p-type region 50P can be doped with arsenic (As), phosphorus (P), antimony (Sb), boron difluoride (BF2), boron (B), combinations thereof, or similar substances. The plant material can be delivered using an ion beam, such that after planting processes 61 to 63, the doping concentration of the dopant planted in the nanostructures 55 and / or fins 66 is substantially within the range of 1 x 10⁻⁶. 17 atoms / cm 3 Up to 1x10 21 atoms / cm 3 .

[0108] In one embodiment, the implantation processes 61 to 63 are performed at temperatures ranging from -60°C to 450°C. In one embodiment, when the implantation material contains ions formed from arsenic (As), the implantation material can be delivered using an ion beam with an energy substantially between 3 keV and 60 keV. In one embodiment, when the implantation material contains ions formed from phosphorus (P), the implantation material can be delivered using an ion beam with an energy substantially between 2 keV and 35 keV. In one embodiment, when the implantation material contains ions formed from antimony (Sb), the implantation material can be delivered using an ion beam with an energy substantially between 8 keV and 80 keV. In one embodiment, when the implantation material contains ions formed from boron difluoride (BF2), the implantation material can be delivered using an ion beam with an energy substantially between 3 keV and 46 keV. In one embodiment, when the implantation material contains ions formed from boron (B), the implantation material can be delivered using an ion beam with an energy substantially between 1 keV and 12 keV. In one embodiment, the available dose range is 1 x 10⁻⁶. 14 atoms / cm 2 Up to 1x10 16 atoms / cm 2 The ion beam is used to transport plant matter (admixture).

[0109] In one embodiment, before the first gap wall 81 is formed and before the second gap wall 82 is formed (hereinafter shown in... Figures 10A to 10CIt can also be used for lightly planting source / drain regions (not shown separately). In embodiments with different device types, it is compatible with... Figure 4 The same implantation process applies. When exposing the p-type region 50P, a mask (e.g., photoresist) can be formed on the n-type region 50N, and suitable types of impurities (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Next, when exposing the n-type region 50N, a mask (e.g., photoresist) can be formed on the p-type region 50P, and suitable types of impurities (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 in the n-type region. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be, for example, any of the aforementioned p-type impurities. The impurity concentration range of the slightly doped source / drain regions can substantially be, for example, about 1 x 10⁻⁶. 19 atoms / cm 3 Annealing can be performed to repair implant damage and revitalize implanted impurities.

[0110] Figure 9A The illustration depicts the movement (also known as lateral dispersion) of the dopant from doped regions 57, 58, and 59 parallel to the top surface of the substrate 50 after implantation processes 61 to 63. Following implantation processes 61 to 63, the lateral dispersion (also known as migration) of the introduced dopant occurs in the first nanostructures 52A to 52C, the second nanostructures 54A to 54C, and the fin 66. For example, after implantation processes 61 to 63, diffusion of the dopant occurs outward from doped regions 57, 58, and 59, resulting in lateral dispersion occurring in regions 65A, 67A, 69A, and 69C of the second nanostructures 54C, 54B, 54A, and fin 66, respectively. Lateral dispersion can also occur in regions 65B, 67B, and 69B of the first nanostructures 52C, 52B, and 52A, respectively. Region 65A is formed at the end of channel region 60 in the second nanostructure 54C (also referred to as channel layer 54C). Region 65A may be adjacent to doped region 57. Region 67A is formed at the end of channel region 60 in the second nanostructure 54B (also referred to as channel layer 54B). Region 67A may be adjacent to doped region 58. Region 69A is formed at the end of channel region 60 in the second nanostructure 54A (also referred to as channel layer 54A). Region 69A may be adjacent to doped region 59.

[0111] Figure 9B It is a drawing Figure 9A Detailed view of area 45. Figure 9B The diagrams previously shown are shown in Figure 9A Lateral dispersion in regions 65A, 67A, and 69A of the second nanostructures 54C, 54B, and 54A. Figure 9BAlso shown are those previously shown in Figure 9A Lateral dispersion of regions 65B, 67B, and 69B of the first nanostructures 52C, 52B, and 52A. Regions 65B, 67B, and 69B are not marked in subsequent figures. Under the first spacer wall 81, the mask 78, and the dummy gate 76, the lateral dispersion in regions 65A and 65B can extend by distances D1 and D2, respectively, such that each region 65A has a first width W1, and each region 65B has a second width W2. Under the first spacer wall 81, the mask 78, and the dummy gate 76, the lateral dispersion in regions 67A and 67B can extend by distances D3 and D4, respectively, such that each region 67A has a third width W3, and each region 67B has a fourth width W4. Under the first spacer wall 81, the mask 78, and the dummy gate 76, the lateral dispersion in regions 69A and 69B can extend by distances D5 and D6, respectively, such that each region 69A has a fifth width W5, and each region 69B has a sixth width W6. In one embodiment, the portion of the second nanostructure 54C between regions 65A and under the dummy gate 76 may have a seventh width W7. In one embodiment, the portion of the second nanostructure 54B between regions 67A and under the dummy gate 76 may have an eighth width W8. In one embodiment, the portion of the second nanostructure 54A between regions 69A and under the dummy gate 76 may have a ninth width W9. The amount of lateral dispersion and the distances D1 and D2 between regions 65A and 65B depend on the implantation dose used during implantation process 61. The amount of lateral dispersion and the distances D3 and D4 between regions 67A and 67B depend on the implantation dose used during implantation process 63. The amount of lateral dispersion and the distances D5 and D6 between regions 67A and 67B depend on the implantation dose used during implantation process 63. The higher the implantation dose used in each implantation process 61 to 63, the greater the intensity of the lateral dispersion, resulting in larger corresponding distances D1 to D6. In one embodiment, the implantation dose used during implantation processes 61 to 63 may be substantially in the range of 1 x 10⁻⁶. 14 atoms / cm 2 Up to 1x10 16 atoms / cm 2 .

[0112] Please refer to the following: Figure 9BThe distances D1 in region 65A, D3 in region 67A, and D5 in region 69A can be equal (in process variations). Similarly, the distances D2 in region 65B, D4 in region 67B, and D6 in region 69B can be equal (in process variations). This can be achieved by using a first implantation dose for implantation process 61, a second implantation dose for implantation process 62, and a third implantation dose for implantation process 63, wherein the first, second, and third implantation doses are equal. In one embodiment, one or more distances D1 to D6 may be unequal to other distances D1 to D6. In other embodiments, all distances D1 to D6 may be different from each other. In embodiments where the first nanostructure 52 and the second nanostructure 54 do not contain the same material, due to the different lateral dispersion rates of the materials, although both are implanted with a selected implantation dose, distances D1 and D2 may be different, distances D3 and D4 may be different, and distances D5 and D6 may be different. In one embodiment, the doping concentration range of regions 65A, 65B, 67A, 67B, 69A, 69B, and 69C is substantially 1 x 10⁻⁶. 18 atoms / cm 3 Up to 1x10 20 atoms / cm 3 Each of the regions 65A, 65B, 67A, 67B, 69A, 69B, and 69C may have a gradient doping profile, such that the doping concentration of regions 65A and 65B increases in the direction extending from the center of doped region 57 to the channel region 60 adjacent to doped region 57. Secondly, the doping concentration of regions 67A and 67B decreases in one direction, which extends from the center of doped region 58 to the channel region 60 adjacent to doped region 58, and the doping concentration of regions 69A, 69B, and 69C decreases in one direction, which extends from the center of doped region 59 towards the channel region 60 adjacent to doped region 59.

[0113] By utilizing implantation processes 61 to 63 with different implantation energies and dosages, dopants can be introduced into nanostructures 55 and / or fins 66 in a controlled manner to achieve different dopant and lateral dispersion profiles. Implantation processes with higher implantation energies allow the dopants to be introduced into the nanostructures 55 and / or fins 66 to greater depths. The higher the dosage used in the implantation process, the greater the intensity of the lateral dispersion, resulting in larger distances D1 to D6, where distances D1 to D6 correspond to greater lateral dispersion.

[0114] Figures 9C to 9T This is an illustration of an apparatus according to various embodiments. Unless otherwise specified, the same reference numerals denote... Figures 1 to 9B The illustrated embodiments use the same components formed by the same process. Therefore, the process steps and acceptable materials will not be described further here.

[0115] Figure 9C The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9C In this context, the distance D1 of region 65A is less than the distance D3 of region 67A, and the distance D3 of region 67A is less than the distance D5 of region 69A. This can be achieved by using a first implantation dose for implantation process 61, a second implantation dose for implantation process 62, and a third implantation dose for implantation process 63. The first implantation dose is less than the second implantation dose, and the second implantation dose is less than and the third implantation dose. Therefore, the seventh width W7 is greater than the eighth width W8, and the eighth width W8 is greater than the ninth width W9.

[0116] Figure 9D The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9D In this context, the distance D1 of region 65A is greater than the distance D3 of region 67A, and the distance D3 of region 67A is greater than the distance D5 of region 69A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63. The first implantation dose is greater than the second implantation dose, and the second implantation dose is greater than and the third implantation dose. Therefore, the seventh width W7 is less than the eighth width W8, and the eighth width W8 is less than the ninth width W9.

[0117] Figure 9E The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9EIn one embodiment, the distance D1 of region 65A is greater than the distance D5 of region 69A, and the distance D1 of region 65A is less than the distance D3 of region 67A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the first implantation dose is greater than the third implantation dose, and the first implantation dose is less than the second implantation dose. Therefore, the seventh width W7 is less than the ninth width W9, and the eighth width W8 is less than the seventh width W7. In another embodiment, the distance D1 of region 65A is less than the distance D5 of region 69A, and the distance D5 of region 69A is less than the distance D3 of region 67A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the first implantation dose is less than the third implantation dose, and the third implantation dose is less than the second implantation dose. Therefore, the seventh width W7 is greater than the ninth width W9, and the ninth width W9 is less than the eighth width W8.

[0118] Figure 9F The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9F In this context, the distance D1 of region 65A is equal to the distance D3 of region 67A, and the distance D3 of region 67A is equal to the distance D5 of region 69A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the first implantation dose is equal to the second implantation dose, and the second implantation dose is equal to the third implantation dose. Therefore, the seventh width W7, the eighth width W8, and the ninth width W9 are equal.

[0119] Figure 9G The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9GIn one embodiment, the distance D3 of region 67A is less than the distance D1 of region 65A, and the distance D1 of region 65A is less than the distance D5 of region 69A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the first implantation dose is greater than the second implantation dose, and the first implantation dose is less than the third implantation dose. Therefore, the seventh width W7 is greater than the ninth width W9, and the seventh width W7 is less than the eighth width W8. In another embodiment, the distance D3 of region 67A is less than the distance D5 of region 69A, and the distance D5 of region 69A is less than the distance D1 of region 65A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the second implantation dose is less than the third implantation dose, and the third implantation dose is less than the first implantation dose. Therefore, the eighth width W8 is greater than the ninth width W9, and the ninth width W9 is greater than the seventh width W7. In one embodiment, the distance D3 of region 67A is less than the distance D5 of region 69A, and the distance D5 of region 69A is less than the distance D1 of region 65A. This can be achieved by using a first implantation dose for implantation process 61, a second implantation dose for implantation process 62, and a third implantation dose for implantation process 63, wherein the second implantation dose is less than the third implantation dose, and the third implantation dose is less than the first implantation dose. Therefore, the eighth width W8 is greater than the ninth width W9, and the ninth width W9 is greater than the seventh width W7.

[0120] Figure 9H The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9H In this context, the distance D1 of region 65A is equal to the distance D3 of region 67A, and the distances D3 and D1 of region 65A are less than the distance D5 of region 69A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the first implantation dose is equal to the second implantation dose, and the second and first implantation doses are less than the third implantation dose. Therefore, the seventh width W7 and the eighth width W8 are equal, and the seventh width W7 and the eighth width W8 are greater than the ninth width W9.

[0121] Figure 9I The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9IIn this context, the distance D3 of region 67A is equal to the distance D5 of region 69A, and the distances D3 and D5 of regions 67A and 69A are less than the distance D1 of region 65A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the second implantation dose is equal to the third implantation dose, and both the second and third implantation doses are less than the first implantation dose. Therefore, the eighth width W8 and the ninth width W9 are equal, and the eighth width W8 and the ninth width W9 are greater than the seventh width W7.

[0122] Figure 9J The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9J In this context, the distance D1 of region 65A is equal to the distance D3 of region 67A, and the distances D1 and D3 of regions 65A are greater than the distance D5 of region 69A. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the first implantation dose is equal to the second implantation dose, and the first and second implantation doses are greater than the third implantation dose. Therefore, the seventh width W7 and the eighth width W8 are equal, and the seventh width W7 and the eighth width W8 are less than the ninth width W9.

[0123] Figure 9K The illustration shows, according to some embodiments, after the fabrication processes 61 to 63 are performed, Figure 9B Area 46. In Figure 9K In this context, the distance D1 of region 65A is less than the distance D3 of region 67A and the distance D5 of region 69A, while the distances D3 and D5 of regions 67A and 69A are equal. This can be achieved by using a first implantation dose in implantation process 61, a second implantation dose in implantation process 62, and a third implantation dose in implantation process 63, wherein the second implantation dose is equal to the third implantation dose, and the first implantation dose is less than both the second and third implantation doses. Therefore, the eighth width W8 and the ninth width W9 are equal, and the seventh width W7 is greater than both the eighth width W8 and the ninth width W9.

[0124] Figure 9L The illustration shows, according to some embodiments, after the installation processes 61 and 63 are performed, Figure 9B Region 46 is included, but the implantation process 62 is omitted. Because doped region 58 is absent, region 67A is not laterally distributed. Figure 9LIn this context, the distance D1 in region 65A is less than the distance D5 in region 69A. This can be achieved by using a first implantation dose in implantation process 61 and a third implantation dose in implantation process 63, where the third implantation dose is greater than the first implantation dose. Therefore, the seventh width W7 is greater than the ninth width W9.

[0125] Figure 9M The illustration shows, according to some embodiments, after the installation processes 61 and 63 are performed, Figure 9B Region 46 is omitted, but the implantation process 62 is omitted. Because doped region 58 is absent, region 67A is not laterally distributed. Figure 9M In this context, the distance D1 in region 65A is greater than the distance D5 in region 69A. This can be achieved by using a first implantation dose in implantation process 61 and a third implantation dose in implantation process 63, where the third implantation dose is less than the first implantation dose. Therefore, the seventh width W7 is less than the ninth width W9.

[0126] Figure 9N The illustration shows, according to some embodiments, after the installation processes 61 and 62 are performed, Figure 9B Region 46 is included, but the implantation process 63 is omitted. Because doped region 59 is absent, region 69A is not laterally distributed. Figure 9N In this context, the distance D1 in region 65A is less than the distance D3 in region 67A. This can be achieved by using a first implantation dose for implantation process 61 and a second implantation dose for implantation process 62, where the first implantation dose is less than the second implantation dose. Therefore, the seventh width W7 is greater than the eighth width W8.

[0127] Figure 9O The illustration shows, according to some embodiments, after the installation processes 61 and 62 are performed, Figure 9B Region 46 is included, but the implantation process 63 is omitted. Because doped region 59 is absent, region 69A is not laterally distributed. Figure 9O In this context, the distance D1 in region 65A is greater than the distance D3 in region 67A. This can be achieved by using a first implantation dose for implantation process 61 and a second implantation dose for implantation process 62, where the first implantation dose is greater than the second implantation dose. Therefore, the seventh width W7 is less than the eighth width W8.

[0128] Figure 9P The illustration shows, according to some embodiments, after the installation processes 61 and 62 are performed, Figure 9B Region 46 is included, but the implantation process 63 is omitted. Because doped region 59 is absent, region 69A is not laterally distributed. Figure 9PIn this context, the distance D1 of region 65A is equal to the distance D3 of region 67A. This can be achieved by performing a placement process 61 using a first placement dose and a placement process 62 using a second placement dose, wherein the first placement dose and the second placement dose are equal. Therefore, the seventh width W7 and the eighth width W8 are equal.

[0129] Figure 9Q The illustration shows, according to some embodiments, after the fabrication processes 62 and 63 are performed, Figure 9B Region 46 is included, but the implantation process 61 is omitted. Because doped region 57 is absent, region 65A is not laterally distributed. Figure 9Q In this context, the distance D3 in region 67A is less than the distance D5 in region 69A. This can be achieved by using a second implantation dose in implantation process 62 and a third implantation dose in implantation process 63, where the second implantation dose is less than the third implantation dose. Therefore, the eighth width W8 is greater than the ninth width W9.

[0130] Figure 9R The illustration shows, according to some embodiments, after the fabrication processes 62 and 63 are performed, Figure 9B Region 46 is included, but the implantation process 61 is omitted. Because doped region 57 is absent, region 65A is not laterally distributed. Figure 9R In this context, the distance D3 in region 67A is greater than the distance D5 in region 69A. This can be achieved by using a second implantation dose in implantation process 62 and a third implantation dose in implantation process 63, where the second implantation dose is greater than the third implantation dose. Therefore, the eighth width W8 is less than the ninth width W9.

[0131] Figure 9S The illustration shows, according to some embodiments, after the fabrication processes 62 and 63 are performed, Figure 9B Region 46 is included, but the implantation process 61 is omitted. Because doped region 57 is absent, region 65A is not laterally distributed. Figure 9S In this context, the distance D3 in region 67A is equal to the distance D5 in region 69A. This can be achieved by using a second implantation dose in implantation process 62 and a third implantation dose in implantation process 63, where the second and third implantation doses are equal. Therefore, the eighth width W8 is equal to the ninth width W9.

[0132] Figure 9T The illustration shows, according to some embodiments, after the fabrication process 62 is performed, Figure 9BRegion 46 is included, but implantation processes 61 and 63 are omitted. Regions 65A and 69A are not laterally distributed because doped regions 57 and 59 are absent. In some embodiments (not shown separately), implantation process 61 may be performed, but implantation processes 62 and 63 may be omitted. Regions 67A and 69A are not laterally distributed because doped regions 58 and 59 are absent. In some embodiments (not shown separately), implantation process 63 may be performed, but implantation processes 61 and 62 are omitted. Regions 65A and 67A are not laterally distributed because doped regions 57 and 58 are absent.

[0133] exist Figures 10A to 10C By depositing a second interstitial wall layer Figure 9A and Figure 9B The illustrated structure is followed by a patterned second spacer layer to form a second spacer 82. The second spacer layer is formed on the top surface of the shallow trench insulation region 68, the top surface and sidewalls of the nanostructure 55, the top surface of the mask 78, and the top surface and sidewalls of the first spacer 81. The second spacer layer can be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation or deposition (e.g., by chemical vapor deposition, atomic layer deposition, or similar methods). In one embodiment, the second spacer layer can be formed from a material with a different etching rate than the material of the first spacer 81. The second spacer layer is then etched to form the second spacer 82. The second spacer layer can be etched using a suitable etching process [e.g., isotropic etching (e.g., wet etching), anisotropic etching (e.g., dry etching), or similar processes]. In one embodiment, the thickness T2 of the second spacer 82 is substantially in the range of 3 nm to 5 nm. In the following figures, the first gap wall 81 and the second gap wall 82 may be collectively referred to as gap wall 83.

[0134] A first spacer wall 81 with a thickness T1 ranging from 3 nm to 5 nm is formed on the sidewalls of the mask 78 and the dummy gate 76. Planting processes 61 to 63 are then performed on the nanostructure 55 and / or the fin 66 to introduce dopants into the exposed areas of the nanostructure 55 and / or the fin 66, where these exposed areas are not covered by the first spacer wall 81, the dummy gate 76, and the mask 78. Planting processes 61 to 63 are performed using modulated ion beams with different planting energies and dosages. Subsequently, a second spacer wall 82 is formed on the sidewall of the first spacer wall 81. This achieves several advantages, including the ability to control the lateral dispersion of dopants entering the channel region 60 of the nanostructure 55 at different depths, and the ability to increase the lateral dispersion of dopants entering the channel region 60 under the first spacer wall 81, the second spacer wall 82, and the dummy gate 76. This allows the dispersed dopants to extend further into the channel region 60 of the nanostructure 55, resulting in a shorter effective channel length and thus reducing the channel resistance (R). ch ).

[0135] exist Figures 11A to 11C In some embodiments, a first recess 86 is formed in the nanostructure 55 and the fin 66. Epitaxial material and epitaxial source / drain regions are subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52, the second nanostructure 54, and partially through the fin 66. In one embodiment, the first recess 86 may partially extend to... Figure 11C The illustrated interface breakdown region 49. In other embodiments, the first recess 86 may extend through the interface breakdown region 49 and may further partially extend through the substrate 50. In one embodiment, the nanostructure 55 and fin 66 may be etched such that the bottom surface of the first recess 86 is disposed on... Figure 11B The shallow trench insulation region 68 shown is located below its top surface or at a similar location. In other embodiments, the top surface of the shallow trench insulation region 68 and the bottom surface of the first recess 86 may be flat.

[0136] A first recess 86 can be formed by etching the nanostructure 55 and fins 66 using an isotropic etching process (such as active ion etching, neutral particle beam etching, or similar methods). During the etching process used to form the first recess 86, spacer walls 83 and a mask 78 cover portions of the fins 66, nanostructure 55, and substrate 50. A single etching process or multiple etching processes can be used to etch each layer of the nanostructure 55. A timed etching process can be used to stop the etching of the first recess 86 after it reaches a desired depth.

[0137] exist Figure 12In the process, partial sidewalls of multiple layers of a multilayer stack 64 formed of a first semiconductor material (e.g., a first nanostructure 52) exposed by the first recess 86 are etched to form multiple sidewall recesses 88 in the n-type region 50N and the p-type region 50P. Although Figure 12 The sidewalls of the first nanostructure 52 with adjacent sidewall recesses 88 shown in the illustration are flat; these sidewalls can be convex or concave. The sidewalls can be etched using an isotropic etching process (e.g., wet etching or a similar method). In embodiments where the first nanostructure 52 may, for example, contain SiGe, and the second nanostructure 54 may, for example, contain Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52.

[0138] exist Figure 13 In the middle, an internal spacer wall 90 is formed in the sidewall recess 88. This can be achieved by depositing an internal spacer wall layer (not shown separately) in... Figure 12 The internal spacers 90 are formed in the structure shown. These first internal spacers 90 serve as the source / drain regions, gate dielectric layer 120, and gate electrode 102 (as described later) in subsequent formations. Figure 21A and Figure 21B The isolation features between (shown) will be as follows. As will be discussed in more detail below, the source / drain regions and epitaxial material will be formed in the first recess 86, and the first nanostructures 52A, 52B and 52C will be replaced by the gate dielectric layer 120 and the gate electrode 102.

[0139] This inner spacer layer can be deposited using a conformal deposition process (e.g., chemical vapor deposition, atomic layer deposition, or similar processes). The inner spacer layer may comprise materials such as silicon carbonitride (SiCN) or silicon oxycarbonitride (SiOCN). In other embodiments, silicon nitride or silicon oxynitride, or other suitable materials, such as low-k materials having a dielectric constant less than about 3.5, can be used. The inner spacer layer can then be anisotropically etched to form a first inner spacer 90. Although the outer walls of the inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54, the outer walls of the inner spacer 90 may also extend beyond or be recessed from the sidewalls of the second nanostructure 54. Furthermore, although... Figure 13 As illustrated, the outer sidewalls of the inner spacer wall 90 are flat; these sidewalls can be convex or concave. The inner spacer wall layer can be etched by anisotropic etching processes (e.g., active ion etching, neutral particle beam etching, or similar methods). Subsequent etching processes [e.g., for forming the gate dielectric layer 120 and gate electrode 102 (e.g.)] are then used. Figure 21A and Figure 21BThe etching process shown in the figure], the inner spacer wall 90 can be used to avoid affecting the subsequent formation of the source / drain regions (e.g.: Figures 16A to 16D The damage shown is as described.

[0140] exist Figures 14A to 14C In this embodiment, a first epitaxial material 91 is formed in a first recess 86. The first epitaxial material 91 can be formed from undoped silicon or the like, and can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. The parameters of the epitaxial growth process are adjusted to allow the first epitaxial material 91 to grow from bottom to top in the first recess 86, such that the growth of the first epitaxial material 91 occurs at the bottom portion of the first recess 86 before other portions of the first recess 86. In some embodiments, no growth of the first epitaxial material 91 occurs on the sidewalls of the second nanostructures 54A to 54C. In some embodiments, some growth of the first epitaxial material 91 occurs on the second nanostructures 54A to 54C, but its growth amount is less than the bottom-to-top growth amount in the first recess 86. The first epitaxial material 91 can be formed to fill the lower portion of the first recess 86 disposed in the junction breakdown region 49. For example, the first epitaxial material 91 can be disposed in the anti-breakdown region 49 / substrate 50 and the subsequently formed epitaxial source / drain region 92 (e.g. Figures 16A to 16D (As shown). During the formation of the first epitaxial material 91, no in-situ doping is performed, and therefore no dopant exists in the first epitaxial material.

[0141] Further reading Figures 14A to 14C The first epitaxial material 91 may have a curved top surface. In the illustrated embodiment, the first epitaxial material 91 may have a curved top surface and a curved bottom surface, wherein the curved top surface has a concave profile and the curved bottom surface has a convex profile. In the illustrated embodiment, the first epitaxial material 91 may substantially contact the bottom surface and sidewalls of the inner spacer wall 90. In one embodiment, the first epitaxial material 91 may have a curved top surface that curves from the first sidewall of the first inner spacer wall 90 toward the second sidewall of the second inner spacer wall 90. In one embodiment, the first epitaxial material 91 may have a curved top surface that curves from the first bottom surface of the first inner spacer wall 90 toward the second bottom surface of the second inner spacer wall 90. In one embodiment, the second height H2 from the lowest point of the nanostructure 55 to the lowest point of the first epitaxial material 91 may be substantially 15 nm to 35 nm. In one embodiment, the third height H3 from the lowest point of the top surface of the first epitaxial material 91 to the lowest point of the first epitaxial material 91 can be substantially 15 nm to 30 nm. For example... Figure 14CAs shown, the lowest point of the top surface of the first epitaxial material 91 is lower than the lowest surface of the nanostructure 55 (e.g., the bottom surface of the first nanostructure 52A). In one embodiment, the entire bottom surface of the first epitaxial material 91 can physically contact the interface breakdown region 49. In another embodiment, a portion of the bottom surface of the first epitaxial material 91 can physically contact the interface breakdown region 49.

[0142] exist Figure 15 In this embodiment, a doping process 93 is performed on a first epitaxial material 91 to introduce dopant into the first epitaxial material 91. The doping process 93 is suitable for creating a gradient doping profile in the first epitaxial material 91 and can be performed using high-current ion implantation or similar methods. The implanting material may comprise arsenic (As), phosphorus (P), antimony (Sb), boron difluoride (BF2), boron (B), combinations thereof, or the like. In one embodiment, the doping process 93 introduces dopant into the first epitaxial material 91 in an n-type region 50N (e.g., an n-type metal-oxide-semiconductor region), wherein the dopant is derived from arsenic (As) and / or phosphorus (P). In another embodiment, the doping process 93 introduces dopant into the first epitaxial material 91 in a p-type region 50P (e.g., a p-type metal-oxide-semiconductor region), wherein the dopant is derived from antimony (Sb), boron difluoride (BF2), and / or boron (B). In this method, arsenic (As), phosphorus (P), antimony (Sb), boron difluoride (BF2), boron (B), combinations thereof, or similar substances can be doped into the first epitaxial material 91. A placement process 93 introduces the dopant into the first epitaxial material 91, wherein the conductivity of the dopant is opposite to that of the junction breakdown region 49. The placement material can be delivered using an ion beam, such that after the placement process 93, the doping concentration of the placed dopant in the first epitaxial material 91 is in the range of 1 x 10⁻⁶. 20 atoms / cm 3 Up to 1x10 19 atoms / cm 3 After the implantation process 93, the first epitaxial material 91 can have a gradient doping profile, so the doping concentration of the first epitaxial material 91 decreases from the top surface of the first epitaxial material 91 towards the substrate 50. The doping concentration of the first epitaxial material 91 can be less than the doping concentration of the subsequently formed epitaxial source / drain region 92 (e.g., Figures 16A to 16D (As shown).

[0143] Forming a first recess 86 within the nanostructure 55 and fin 66, and subsequently forming a first epitaxial material 91 (e.g., an undoped silicon layer) within the first recess 86, achieves several advantages. A implantation process 93 is performed on the first epitaxial material 91, giving it a gradient doping profile. Next, epitaxial source / drain regions 92 are formed on the first epitaxial material 91 within the first recess 86. These advantages include reducing the amplified electric field resulting from the preceding implantation process, and reducing the junction leakage current (Ib) caused by this amplified electric field. off ) migration.

[0144] Figures 16A to 16D An epitaxial source / drain region 92 is formed on the first epitaxial material 91 within the first recess 86. In some embodiments, the epitaxial source / drain region 92 may apply stress to the second nanostructures 54A, 54B, and 54C to improve performance. Figure 16D As illustrated, epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, spacer walls 83 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, while inner spacer walls 90 are used to separate the epitaxial source / drain regions 92, the first nanostructures 52A, 52B, and 52C by a suitable lateral distance so that the epitaxial source / drain regions 92 do not short-circuit with the gates subsequently formed in the formed nanostructure field-effect transistors.

[0145] Epitaxial source / drain regions 92 in an n-type region 50N (e.g., an n-type metal-oxide-semiconductor region) can be formed by covering the p-type region 50P (e.g., a p-type metal-oxide-semiconductor region). The epitaxial source / drain regions 92 are then epitaxially grown in a first recess 86 of the n-type region 50N. The epitaxial source / drain regions 92 may contain any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 may contain materials to which tensile strain is applied in the second nanostructures 54A, 54B, and 54C, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces protruding from the respective upper surfaces of the nanostructure 55 and may have facets.

[0146] Epitaxial source / drain regions 92 in a p-type region 50P (e.g., a p-type metal-oxide-semiconductor region) can be formed by covering an n-type region 50N (e.g., an n-type metal-oxide-semiconductor region). The epitaxial source / drain regions 92 are then epitaxially grown in a first recess 86 of the n-type region 50N. The epitaxial source / drain regions 92 can contain any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain regions 92 can contain a material to which tensile strain is applied in the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 can have surfaces protruding from the top surfaces of the nanostructure 55 and can have facets.

[0147] Similar to the previously discussed process for forming lightly doped source / drain regions, dopants can be implanted into the epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 to form the source / drain region, followed by annealing. The epitaxial source / drain region 92 may have a range substantially approximately 10 19 atoms / cm 3 To about 10 21 atoms / cm 3 The impurity concentration in the epitaxial source / drain region 92. In one embodiment, the impurity (also referred to as dopant) concentration in the epitaxial source / drain region 92 is 10. 2 Up to 10 3 The doping concentration is greater than that of regions 65A, 67A, 69A, or 69C. In one embodiment, the impurity concentration (also referred to as doping concentration) of the epitaxial source / drain region 92 is greater than that of each doped region 57, 58, or 59 (as previously stated). Figure 9A The doping concentration is shown in the figure. In one embodiment, the doping concentration of the epitaxial source / drain region 92 may be greater than the doping concentration of the first epitaxial material 91. The n-type impurities and / or p-type impurities in the epitaxial source / drain region may be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain region 92 may be doped in situ during growth.

[0148] The epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P results in an upper surface of the epitaxial source / drain regions 92 having multiple facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanostructure field-effect transistor to merge, such as Figure 16B As shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown. Figure 16C As shown. In the diagram Figure 16A and Figure 16CIn some embodiments, spacer walls 83 may be formed on the top surface of the shallow trench isolation region 68 to block epitaxial growth. In some other embodiments, spacer walls 83 may cover a portion of the sidewalls of the nanostructure 55 to block epitaxial growth. In some other embodiments, the spacer wall etching used to form the spacer walls 83 may be adjusted to remove spacer wall material, allowing the epitaxial growth region to extend to the surface of the shallow trench isolation region 68.

[0149] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each first semiconductor material layer 92A, second semiconductor material layer 92B, and third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different doping concentrations. In some embodiments, the doping concentration of the first semiconductor material layer 92A may be less than that of the second semiconductor material layer 92B. In some embodiments, the doping concentration of the second semiconductor material layer 92B may be less than that of the third semiconductor material layer 92C. In some embodiments, the doping concentration of the first semiconductor material layer 92A may be greater than that of the first epitaxial material 91. In some embodiments, the doping concentration of the second semiconductor material layer 92B may be greater than that of the first epitaxial material 91. In some embodiments, the doping concentration of the third semiconductor material layer 92C may be greater than that of the first epitaxial material 91. In some embodiments, the germanium concentration of the first semiconductor material layer 92A may be less than that of the second semiconductor material layer 92B. In some embodiments, the germanium concentration of the second semiconductor material layer 92B may be less than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and a third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0150] Please refer to the following: Figures 16A to 16D The lateral dispersion in region 65A extends beneath the spacer wall 83, the shield 78, and the dummy gate 76, and extends a distance D1 from the first sidewall of the epitaxial source / drain region 92. The lateral dispersion in region 67A extends beneath the spacer wall 83, the shield 78, and the dummy gate 76, and extends a distance D3 from the first sidewall of the epitaxial source / drain region 92. The lateral dispersion in region 69A extends beneath the spacer wall 83, the shield 78, and the dummy gate 76, and extends a distance D5 from the first sidewall of the epitaxial source / drain region 92. For example... Figure 16D As shown, regions 65A, 67A, and 69A can physically contact the epitaxial source / drain regions 92. In one embodiment, region 69C can physically contact the first epitaxial material 91.

[0151] Figures 16E to 16V Draw the corresponding Figures 9C to 9T Elements of the embodiments. Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments below) represent Figures 1 to 16D In the embodiments shown, the same components are formed using the same process. Therefore, the process steps and acceptable materials will not be described further here.

[0152] Figure 16E Draw corresponding Figure 9C After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the distance D1 of region 65A is less than the distance D3 of region 67A, and the distance D3 of region 67A is less than the distance D5 of region 69A. Therefore, the seventh width W7 is greater than the eighth width W8, and the eighth width W8 is greater than the width W9.

[0153] Figure 16F Draw the corresponding Figure 9D After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the distance D1 of region 65A is greater than the distance D3 of region 67A, and the distance D3 of region 67A is greater than the distance D5 of region 69A. Therefore, the seventh width W7 is less than the eighth width W8, and the eighth width W8 is less than the ninth width W9.

[0154] Figure 16G Draw corresponding Figure 9E After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the distance D1 of region 65A is greater than the distance D5 of region 69A, and the distance D1 of region 65A is less than the distance D3 of region 67A. Therefore, the seventh width W7 is less than the ninth width W9, and the eighth width W8 is less than the seventh width W7. In one embodiment, the distance D1 of region 65A is less than the distance D5 of region 69A, and the distance D5 of region 69A is less than the distance D3 of region 67A. Therefore, the seventh width W7 is greater than the ninth width W9, and the ninth width W9 is greater than the eighth width W8.

[0155] Figure 16H Draw corresponding Figure 9F After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16DRegion 56. In one embodiment, the distance D1 of region 65A is equal to the distance D3 of region 67A, and the distance D3 of region 67A is equal to the distance D5 of region 69A. Therefore, the seventh width W7, the eighth width W8, and the ninth width W9 are equal.

[0156] Figure 16I Draw corresponding Figure 9G After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the distance D3 of region 67A is less than the distance D1 of region 65A, and the distance D1 of region 65A is less than the distance D5 of region 69A. Therefore, the seventh width W7 is greater than the ninth width W9, and the seventh width W7 is less than the eighth width W8. In one embodiment, the distance D3 of region 67A is less than the distance D5 of region 69A, and the distance D5 of region 69A is less than the distance D1 of region 65A. Therefore, the eighth width W8 is greater than the ninth width W9, and the ninth width W9 is greater than the seventh width W7.

[0157] Figure 16J Draw corresponding Figure 9H After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the distance D1 of region 65A is equal to the distance D3 of region 67A, and the distances D3 and D1 of region 67A are less than the distance D5 of region 69A. Therefore, the seventh width W7 is equal to the eighth width W8, and the seventh width W7 and the eighth width W8 are greater than the ninth width W9.

[0158] Figure 16K Draw corresponding Figure 9I After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the distance D3 of region 67A is equal to the distance D5 of region 69A, and the distances D3 and D5 of regions 67A and 69A are less than the distance D1 of region 65A. Therefore, the eighth width W8 is equal to the ninth width W9, and the eighth width W8 and the ninth width W9 are greater than the seventh width W7.

[0159] Figure 16L Draw corresponding Figure 9J After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16DRegion 56. In one embodiment, the spacing D1 of region 65A is equal to the spacing D3 of region 67A, and the spacing D1 of region 65A and the spacing D3 of region 67A are greater than the spacing D5 of region 69A. Therefore, the seventh width W7 is equal to the eighth width W8, and the seventh width W7 and the eighth width W8 are less than the ninth width W9.

[0160] Figure 16M Draw corresponding Figure 9K After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D1 of region 65A is less than the spacing D3 of region 67A and the spacing D5 of region 69A, and the spacing D3 of region 67A is equal to the spacing D5 of region 69A. Therefore, the eighth width W8 and the ninth width W9 are equal, and the seventh width W7 is greater than the eighth width W8 and the ninth width W9.

[0161] Figure 16N Draw corresponding Figure 9L After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D1 of region 65A is less than the spacing D5 of region 69A. Therefore, the seventh width W7 is greater than the ninth width W9.

[0162] Figure 16O Draw corresponding Figure 9M After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D1 of region 65A is greater than the spacing D5 of region 69A. Therefore, the seventh width W7 is less than the ninth width W9.

[0163] Figure 16P Draw corresponding Figure 9N After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D1 of region 65A is smaller than the spacing D3 of region 67A. Therefore, the seventh width W7 is greater than the eighth width W8.

[0164] Figure 16Q Draw corresponding Figure 9O After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D1 of region 65A is greater than the spacing D3 of region 67A. Therefore, the seventh width W7 is less than the eighth width W8.

[0165] Figure 16R Draw corresponding Figure 9PAfter forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D1 of region 65A is equal to the spacing D3 of region 67A. Therefore, the seventh width W7 and the eighth width W8 are equal.

[0166] Figure 16S Draw corresponding Figure 9Q After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D3 of region 67A is smaller than the spacing D5 of region 69A. Therefore, the eighth width W8 is greater than the ninth width W9.

[0167] Figure 16T Draw corresponding Figure 9R After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D3 of region 67A is greater than the spacing D5 of region 69A. Therefore, the eighth width W8 is less than the ninth width W9.

[0168] Figure 16U Draw corresponding Figure 9S After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the spacing D3 of region 67A is equal to the spacing D5 of region 69A. Therefore, the eighth width W8 is equal to the ninth width W9.

[0169] Figure 16V Draw corresponding Figure 9T After forming the epitaxial source / drain region 92 in the first recess 86 in the embodiment Figure 16D Region 56. In one embodiment, the portion of the second nanostructure 54B between regions 67A (e.g., a portion of channel region 60) under the spacer wall 83, mask 78, and dummy gate 76 has an eighth width W8. In other embodiments (not shown), the portion of the second nanostructure 54C between regions 65A (e.g., a portion of channel region 60) under the spacer wall 83, mask 78, and dummy gate 76 has a seventh width W7. In other embodiments (not shown), the portion of the second nanostructure 54A between regions 69A (e.g., a portion of channel region 60) under the spacer wall 83, mask 78, and dummy gate 76 has a ninth width W9.

[0170] Figures 16E to 16V In the alternative embodiments shown, different dopants and lateral distribution profiles can achieve several advantages. For example, Figure 16E , Figure 16J , Figure 16M , Figure 16N , Figure 16P and Figure 16S The embodiment can reduce the leakage current at the bottom of the epitaxial source / drain region 92. Figure 16F , Figure 16K , Figure 16L , Figure 16O , Figure 16Q and Figure 16T The embodiments described herein can be used in devices whose performance or operation is not impeded by the drain-induced barrier lowering (DIBL) effect. When it is desired that the current in two or more second nanostructures 54A to 54C (also referred to as channel layers 54A to 54C) be equal, the following methods can be used. Figure 16H , Figure 16R , Figure 16U and Figure 16V An embodiment. When used to form the first recess 86 (such as...) Figures 11A to 11C When the etching process (as shown) does not form the first recess 86 with perfectly vertical sidewalls, Figure 16G , Figure 16T and Figure 16V The embodiments can be used to form different dopant profiles as desired.

[0171] exist Figure 17A and Figure 17B In the middle, the first interlayer dielectric (ILD) 96 is deposited on Figures 16A to 16D Structurally, the first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method [chemical vapor deposition, plasma-enhanced CVD (PECVD), or flowable chemical vapor deposition]. The dielectric material may comprise phosphorus-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etchstop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain regions 92, the mask 78, and the spacer 83. The contact etch stop layer 94 may comprise a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, or the like), wherein the etch rate of this dielectric material is different from that of the material of the first interlayer dielectric 96 thereon.

[0172] exist Figure 18A and 18B In this process, a planarization process (e.g., chemical mechanical polishing) can be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and a portion of the spacer wall 83 along the sidewalls of the mask 78. After the planarization process, the top surface of the dummy gate 76, the spacer wall 83, and the first interlayer dielectric 96 is flat. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first interlayer dielectric layer 96 flush with the top surfaces of the mask 78 and the spacer wall 83.

[0173] exist Figure 19A and Figure 19B In this process, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a recess 98. A portion of the dummy gate dielectric 71 within the recess 98 may also be removed. In some embodiments, only the dummy gate 76 is removed, while the dummy gate dielectric 71 is retained, wherein the dummy gate dielectric 71 is exposed through the recess 98. In some embodiments, the dummy gate dielectric 71 is removed from a recess 98 in a first region of the die (e.g., a core logic region), but the dummy gate dielectric 71 in a recess 98 in a second region (e.g., an input / output region) is retained. In some embodiments, the dummy gate 76 is removed by an isotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 without etching the first interlayer dielectric layer 96 and the spacer wall 83. Each recess 98 exposes a multilayer stack 64 and / or is located on the multilayer stack 64. Partial multilayer stack 64 is disposed between adjacent epitaxial source / drain regions 92. During removal, when the dummy gate 76 is etched, the dummy gate dielectric 71 is used as an etch stop layer. After the dummy gate 76 is removed, the dummy gate dielectric 71 can be selectively removed again.

[0174] exist Figure 20A and Figure 20BIn this embodiment, first nanostructures 52A, 52B, and 52C are removed from regions 50N and 50P. The first nanostructures 52A, 52B, and 52C can be removed by an isotropic etching process (e.g., wet etching, dry etching, or similar methods). The etchant used to remove the first nanostructures 52A, 52B, and 52C may be selective for the second nanostructures 52A, 52B, and 52C. The second nanostructures 52A, 52B, and 52C may be subsequently referred to as channel layers 52A, 52B, and 52C, respectively. In embodiments where the first nanostructures 52A, 52B, and 52C comprise a first nanomaterial (e.g., SiGe or the like), and the second nanostructures 52A, 52B, and 52C comprise a second nanomaterial (e.g., Si, SiC, or the like), a fluorine-based etchant [e.g., hydrogen fluoride, (HF)] or the like can be used to remove multiple layers of the multilayer stack 64 of regions 50N and 50P.

[0175] exist Figure 21A and Figure 21B In this configuration, the gate dielectric layer 120 and the gate electrode 102 are formed as a replacement gate. The gate dielectric layer 120 is conformally deposited in the recess 98. The gate dielectric layer 120 can be formed on the top surface, sidewalls, and bottom surface of the second nanostructures 54A, 54B, and 54C. The gate dielectric layer 120 can also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, the spacer wall 83, and the shallow trench insulating region 68, and the sidewalls of the inner spacer wall 90.

[0176] According to some embodiments, the gate dielectric layer 120 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 120 includes a high dielectric constant material, and in these embodiments, the dielectric constant of the gate dielectric layer 120 may be substantially greater than 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 120 in the n-type region 50N and the p-type region 50P may be the same or different. The method of fabricating the gate dielectric layer 120 may include molecular beam deposition (MBD), atomic layer deposition plasma-enhanced chemical vapor deposition, or similar methods.

[0177] Gate electrode 102 is deposited on gate dielectric layer 120 and fills the remainder of second recess 98. Gate electrode 102 may comprise a metallic material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or structures thereof. For example, although in Figure 21A and Figure 21BA single-layer gate electrode 102 is illustrated. The gate electrode 102 may comprise any number of pad layers, any number of work function adjustment layers, and filler material. Any combination of multiple layers constituting the gate electrode 102 may be deposited between adjacent layers in the second nanostructure 54.

[0178] The formation of the gate dielectric layer 120 in the p-type region 50P and the n-type region 50N can occur simultaneously, such that the gate dielectric layer 120 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 120 in each region can be formed by different processes, such that the gate dielectric layer 120 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to cover and expose suitable areas.

[0179] After the first recess 98 is filled, a planarization process (e.g., chemical mechanical polishing) can be performed to remove excess material from the gate dielectric layer 120 and the gate electrode 102, where such excess material is on the top surface of the first interlayer dielectric 96. Thus, the remaining material of the gate electrode 102 and the gate dielectric layer 120 forms a replacement gate structure for a nanostructured field-effect transistor. The gate electrode 102 and the gate dielectric layer 120 can be collectively referred to as the "gate structure".

[0180] In one embodiment, the fourth height H4 from the bottom surface of the gate structure (e.g., gate dielectric layer 120 and gate electrode 102) to the bottom point of the first epitaxial material 91 can be substantially 15 nm to 30 nm. Figure 21B As shown, in one embodiment, the lowest point of the top surface of the first epitaxial material 91 is lower than the lowest point of the gate structure (e.g., the gate dielectric layer 120 and the gate electrode 102).

[0181] exist Figure 22A and Figure 22B In this design, a recessed gate structure (including a gate dielectric layer 120 and a corresponding gate electrode 102 thereon) is formed such that the recess is directly formed on the gate structure and between opposing portions of the spacer 83. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, or the like) is filled in the recess, and excess dielectric material extending on the first interlayer dielectric 96 is removed by a planarization process. The subsequently formed gate contact window (as described below for...) Figures 24A to 24B The gate contact window 114 discussed passes through the gate shield 104 to contact the top surface of the recessed gate electrode 102.

[0182] like Figure 22A and Figure 22B As further illustrated, the second interlayer dielectric 106 is deposited on the first interlayer dielectric 96 and the gate mask 104. In some embodiments, the second interlayer dielectric 106 is a flowable thin film formed by flowable chemical vapor deposition. In some embodiments, the second interlayer dielectric 106 is formed of materials such as phosphorus-doped silicon glass, boron-doped silicon glass, boron-phosphorus-doped silicon glass, undoped silicon glass, or the like, and can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar methods.

[0183] exist Figure 23A and Figure 23B In the middle, the gate contact window 114 is formed by passing through the second interlayer dielectric 106 and the gate shield 104 (shown later in the figure). Figure 24A and Figure 24B The opening 108 extends through the second interlayer dielectric 106 and the first interlayer dielectric 96 to form the source / drain contact window 112 (shown later in the diagram). Figure 24B The opening 109 is an opening in the epitaxial source / drain region 92. Openings 108 and 109 can be formed using acceptable lithography and etching techniques. Opening 108 exposes the surface of the gate structure, and opening 109 exposes the surface of the epitaxial source / drain region 92. A silicide region 110 is formed on the epitaxial source / drain region 92 by first depositing a metal (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, not shown separately) on the exposed portion of the epitaxial source / drain region 92 to form a silicide or germanide region, followed by a thermal annealing process to form the silicide region 110, wherein the metal is reactive with the material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92. Then, unreacted portions of the deposited metal are removed, for example, by an etching process.

[0184] exist Figure 24A and Figure 24B In this configuration, pads (such as diffusion barrier layers, adhesive layers, or the like) and conductive material are formed in openings 108 and 109. The pads may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (such as chemical mechanical polishing) may be performed to remove excess material from the surface of the second dielectric 106. The remaining pads and conductive material form a gate contact window 114 in opening 108 and a source / drain contact window 112 in opening 109. The gate contact window 114 is physically or electrically coupled to the gate electrode 102, and the source / drain contact window 112 is physically or electrically coupled to the epitaxial source / drain region 92.

[0185] The embodiments disclosed herein have several advantageous features. This embodiment includes forming a semiconductor nanostructure on a semiconductor fin, and forming a dummy gate and a mask on the semiconductor nanostructure and fin. Next, a first spacer wall is formed on the sidewalls of the dummy gate and mask. Next, multiple ion implantation processes are performed on the semiconductor nanostructure using modulated ion beams with different implantation energies and doses. Then, a second spacer wall is formed along the sidewalls of the first spacer wall. A recess is formed in the semiconductor nanostructure and semiconductor fin. Subsequently, an undoped silicon layer is formed in the recess, and an ion implantation process is performed on the silicon layer, resulting in a gradient doped profile. Next, a source / drain region is formed in the recess on the gradient doped silicon layer. One or more embodiments disclosed herein have the ability to control the lateral dispersion of dopants into the channel regions of the semiconductor structure at different depths, and allow increased lateral dispersion into the channel regions under the first spacer wall, the second spacer wall, and the dummy gate. This allows the dispersed dopants to extend further into the channel region of the semiconductor structure, resulting in a shorter effective channel length and thus reducing the channel resistance (R). ch Secondly, forming a silicon layer with a gradient doped profile in the source / drain region results in a low electric field in the source / drain region, which in turn leads to a lower junction leakage current (I0). boff Furthermore, the method disclosed herein can be easily integrated into existing processes and provides a lower-cost means of reducing junction leakage current and channel resistance.

[0186] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device includes depositing a multilayer stack on a semiconductor substrate, wherein the multilayer stack includes alternating plurality of sacrificial layers and plurality of channel layers; forming a dummy gate on the multilayer stack; forming a first spacer wall on the sidewall of the dummy gate; performing a first implantation process to form a first doped region, wherein the first implantation process has a first implantation energy and a first implantation dose; performing a second implantation process to form a second doped region, wherein the first doped region and the second doped region are in a portion of the channel layer, this portion being not covered by the first spacer wall and the dummy gate, the second implantation process having a second implantation energy and a second implantation dose, the second implantation energy being greater than the first implantation energy, and the first implantation dose being different from the second implantation dose; after performing the first implantation process and the second implantation process, forming a second spacer wall on the sidewall of the first spacer wall; forming a first recess in the multilayer stack, wherein the multilayer stack is adjacent to the second spacer wall; and forming an epitaxial source / drain region in the first recess. In one embodiment, the first and second implantation processes include implanting arsenic (As), phosphorus (P), antimony (Sb), boron difluoride (BF2), or boron (B) into multiple exposed regions of a multilayer stack. In one embodiment, the first and second spacer walls have a thickness ranging from 3 nm to 5 nm. In one embodiment, the doping concentration of the first and second doped regions ranges from 1 x 10⁻⁶. 17 atoms / cm 3 Up to 1x10 21 atoms / cm 3 In one embodiment, the doping concentration of the epitaxial source / drain region is greater than the doping concentration of the first doped region and the doping concentration of the second doped region. In one embodiment, dopants from the first doped region migrate in a direction parallel to the top surface of the semiconductor substrate to a first portion of the first channel layer, which is located below a dummy gate. Multiple dopants from the second doped region move in a direction parallel to the top surface of the semiconductor substrate to a second portion of the second channel layer, which is located below the dummy gate. The second channel layer is located below the first channel layer.

[0187] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device includes forming a dummy gate on a first channel region of a first channel layer and a second channel region of a second channel layer, wherein the first channel layer and the second channel layer are disposed on a semiconductor substrate and form first spacers on the sidewalls of the dummy gate; performing a first implantation process to implant a plurality of dopants in the first channel layer, thereby forming a plurality of first doped portions at a plurality of first ends in the first channel region; performing a second implantation process to implant a plurality of dopants in the second channel layer, thereby forming a plurality of second doped portions at a plurality of second ends in the second channel region, wherein during the first implantation process and the second implantation process, the dummy gate and the first spacers are used as implantation masks, and each of the first doped portions and the second doped portions has a gradient doping profile; and after performing the first implantation process and the second implantation process, forming second spacers on the sidewalls of the first spacers. In one embodiment, the doping concentration of the first doped portions and the second doped portions ranges from 1x10⁻¹⁰. 18 atoms / cm 3 Up to 1x10 20 atoms / cm 3 In one embodiment, a first implantation process forms a third doped portion in the first channel layer, each third doped portion adjacent to a corresponding first doped portion. A second implantation process forms a fourth doped portion in the second channel layer, each fourth doped portion adjacent to a corresponding second doped portion. The doping concentrations of the third and fourth doped portions are greater than the doping concentrations of the first and second doped portions. In one embodiment, the doping concentration of each of the first doped portions decreases in one direction, extending from a center of the individual first doped portion to the first channel region. Similarly, the doping concentration of each of the second doped portions decreases in one direction, extending from the center of each of the second doped portions to the second channel region. In one embodiment, the first implantation process is performed with a first implantation energy and a first implantation dose, and the second implantation process is performed with a second implantation energy and a second implantation dose, wherein the second implantation energy is greater than the first implantation energy, and the first implantation dose is different from the second implantation dose. In one embodiment, the second implantation dose is greater than the first implantation dose, and the first width of each of the first doped portions is less than the second width of each of the second doped portions. In another embodiment, the second implantation dose is less than the first implantation dose, and the first width of each of the first doped portions is greater than the second width of each of the second doped portions.

[0188] According to one embodiment of the present disclosure, a semiconductor device includes a first channel layer, a second channel layer, a gate structure, a plurality of source / drain regions, a plurality of first doped portions, and a plurality of second doped portions. The first channel layer is on a semiconductor substrate, the second channel layer is on the first channel layer, and the gate structure surrounds the first and second channel layers. The source / drain regions are located on opposite sides of the gate structure, the first channel layer, and the second channel layer. The first doped portions are located at multiple endpoints of the first channel layers, each of which is in solid contact with an adjacent source / drain region. The doping concentration of each of the first doped portions decreases in a direction extending away from the adjacent source / drain region. The second doped portions are located at multiple ends of the second channel layer, each of which is in solid contact with an adjacent source / drain region. The doping concentration of each of the second doped portions decreases in a direction extending away from the adjacent source / drain region, and the doping concentration of the first and second doped portions is lower than the doping concentration of the source / drain regions. In one embodiment, the doping concentrations of these source / drain regions are 10 times the doping concentrations of the first doped portions and the second doped portions. 2 Up to 10 times 3 The width of the first channel layer between the first doped portions is different from the second width of the second channel layer between the second doped portions. In one embodiment, the semiconductor device further includes a third channel layer and a plurality of third doped portions, wherein the third channel layer is on the second channel layer, the source / drain regions are also on opposite sides of the third channel layer, and the third doped portions are at the ends of the third channel layer, each of the third doped portions being in solid contact with an adjacent source / drain region, and the first width and the second width are different from the third width between the third channel layers of the third doped portions. In one embodiment, the first width is smaller than the second width, and the second width is smaller than the third width.

[0189] The foregoing summary describes the features of many embodiments, thus enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that other processes and structures can be designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the described embodiments. Those skilled in the art should also understand that equivalent architectures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A multilayer stack is deposited on a semiconductor substrate, wherein the multilayer stack includes alternating multiple sacrificial layers and multiple channel layers; A dummy gate is formed on the multilayer stack; A first gap wall is formed on one side wall of the dummy gate; A first implantation process is performed to form a first doped region, wherein the first implantation process has a first implantation energy and a first implantation dose. A second implantation process is performed to form a second doped region, wherein the first doped region and the second doped region are part of the plurality of channel layers, the part of which is not covered by the first spacer wall and the dummy gate, the first doped region and the second doped region have a gradient doping profile, the second implantation process has a second implantation energy and a second implantation dose, the second implantation energy is greater than the first implantation energy, and the first implantation dose is different from the second implantation dose; After the first and second fabrication processes are performed, a second gap wall is formed on one side wall of the first gap wall. A first recess is formed in the multilayer stack, wherein the multilayer stack is adjacent to the second spacer wall; and An epitaxial source / drain region is formed in the first depression.

2. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The operation of the first implantation process and the second implantation process includes implanting arsenic, phosphorus, antimony, boron difluoride, or boron into multiple exposed areas of the multilayer stack.

3. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The first and second spacer walls have a thickness ranging from 3 nm to 5 nm.

4. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, The doping concentration range of the first doped region and the second doped region is 1x10. 17 atoms / cm 3 Up to 1x10 21 atoms / cm 3 .

5. The method for manufacturing a semiconductor device as claimed in claim 4, characterized in that, The doping concentration of the epitaxial source / drain region is greater than the doping concentration of the first doped region and the doping concentration of the second doped region.

6. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, After the first implantation process and the second implantation process, multiple dopants from the first doping region migrate in a direction parallel to a top surface of the semiconductor substrate to a first portion of a first channel layer, which is located under the dummy gate. Multiple dopants from the second doping region move in a direction parallel to the top surface of the semiconductor substrate to a second portion of a second channel layer, which is located under the dummy gate. The second channel layer is located under the first channel layer.

7. The method for manufacturing a semiconductor device as claimed in claim 6, characterized in that, The first implantation dose is greater than the second implantation dose, and the first width of the first portion of the first channel layer is greater than the second width of the second portion of the second channel layer.

8. The method for manufacturing a semiconductor device as claimed in claim 6, characterized in that, The first implantation dose is less than the second implantation dose, and the first width of the first portion of the first channel layer is less than the second width of the second portion of the second channel layer.

9. A method for manufacturing a semiconductor device, characterized in that, Include: A dummy gate is formed on a first channel region of a first channel layer and a second channel region of a second channel layer, wherein the first channel layer and the second channel layer are disposed on a semiconductor substrate; A first gap wall is formed on one side wall of the dummy gate; A first implantation process is performed to implant multiple dopants into the first channel layer, thereby forming multiple first doped portions at multiple first ends in the first channel region; A second implantation process is performed to implant multiple dopants into the second channel layer, thereby forming multiple second doped portions at multiple second ends of the second channel region. In the process of the first implantation process and the second implantation process, the dummy gate and the first spacer wall are used as an implantation mask, and each of the multiple first doped portions and the multiple second doped portions has a gradient doping profile. as well as After the first and second planting processes are performed, a second gap wall is formed on one side wall of the first gap wall.

10. The method for manufacturing a semiconductor device as claimed in claim 9, characterized in that, The doping concentration range of the plurality of first doped portions and the plurality of second doped portions is 1x10⁻⁶. 18 atoms / cm 3 Up to 1x10 20 atoms / cm 3 .

11. The method for manufacturing a semiconductor device as claimed in claim 9, characterized in that, The first implantation process forms multiple third doped portions in the first channel layer, each of the multiple third doped portions being adjacent to the corresponding multiple first doped portions. The second implantation process forms multiple fourth doped portions in the second channel layer, each of the multiple fourth doped portions being adjacent to the corresponding multiple second doped portions. The doping concentration of the multiple third doped portions and the doping concentration of the multiple fourth doped portions are greater than the doping concentration of the multiple first doped portions and the doping concentration of the multiple second doped portions.

12. The method of manufacturing a semiconductor device as claimed in claim 11, characterized in that, The doping concentration of each of the plurality of first doped portions decreases in a direction extending from a center of each of the plurality of first doped portions to the first channel region, and the doping concentration of each of the plurality of second doped portions decreases in a direction extending from a center of each of the plurality of second doped portions to the second channel region.

13. The method for manufacturing a semiconductor device as claimed in claim 9, characterized in that, The first implantation process is performed with a first implantation energy and a first implantation dose, and the second implantation process is performed with a second implantation energy and a second implantation dose. The second implantation energy is greater than the first implantation energy, and the first implantation dose is different from the second implantation dose.

14. The method for manufacturing a semiconductor device as claimed in claim 13, characterized in that, The second implantation dose is greater than the first implantation dose, and the first width of each of the plurality of first doped portions is less than the second width of each of the plurality of second doped portions.

15. The method for manufacturing a semiconductor device as claimed in claim 13, characterized in that, The second implantation dose is less than the first implantation dose, and the first width of each of the plurality of first doped portions is greater than the second width of each of the second doped portions.

16. A semiconductor device, characterized in that, Include: A first channel layer is disposed on a semiconductor substrate; A second channel layer, on top of the first channel layer; A gate structure surrounds the first channel layer and the second channel layer; Multiple source / drain regions are located on opposite sides of the gate structure, the first channel layer, and the second channel layer. Multiple first doped portions are located at multiple ends of the first channel layer, each of the multiple first doped portions being in solid contact with an adjacent source / drain region, wherein the doping concentration of each of the multiple first doped portions decreases in a direction that extends away from the adjacent source / drain region. as well as A plurality of second doped portions are located at a plurality of ends of the second channel layer, each of the plurality of second doped portions being in solid contact with an adjacent source / drain region, wherein a doping concentration of each of the plurality of second doped portions decreases in a direction extending away from the adjacent source / drain region, and the doping concentration of the plurality of first doped portions and the doping concentration of the plurality of second doped portions are lower than the doping concentration of the plurality of source / drain regions, and each of the plurality of first doped portions and the plurality of second doped portions has a gradient doping profile.

17. The semiconductor device as claimed in claim 16, characterized in that, The doping concentration of the plurality of source / drain regions is greater than 10 times the doping concentration of the plurality of first doped portions and the plurality of second doped portions. 2 Up to 10 times 3 times.

18. The semiconductor device as claimed in claim 16, characterized in that, The first width of the first channel layer between the plurality of first doped portions is different from the second width of the second channel layer between the plurality of second doped portions.

19. The semiconductor device as claimed in claim 18, characterized in that, It also includes: A third channel layer, on the second channel layer, wherein the plurality of source / drain regions are also located on an opposite side of the third channel layer; and Multiple third doped portions, wherein at multiple ends of the third channel layer, each of the multiple third doped portions is in solid contact with an adjacent source / drain region, and the first width and the second width are different from a third width between the multiple third doped portions of the third channel layer.

20. The semiconductor device as claimed in claim 19, characterized in that, The first width is smaller than the second width, and the second width is smaller than the third width.

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