Battery protection chip, battery system and battery protection method

Abstract

The application provides a battery protection chip, a battery system and a battery protection method. The battery protection chip comprises: a discharge voltage limiting detection circuit, which is used for detecting a discharge driving signal output by a previous-stage battery protection chip, identifying a high or low level of the discharge driving signal according to a current flow direction of the discharge detection signal, and reducing a high or low level conversion window voltage of the discharge driving signal; and a charging voltage limiting detection circuit, which is used for detecting a charging driving signal output by the previous-stage battery protection chip, identifying a high or low level of the charging driving signal according to a current flow direction of the charging detection signal, and reducing a high or low level conversion window voltage of the charging driving signal. The battery protection chip, the battery system and the battery protection method provided by the application solve the problems of scheme 1 and scheme 2.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit design, and in particular relates to a battery protection chip, a battery system, and a battery protection method. Background Technology

[0002] Lithium batteries are widely used in various electrical appliances. Because lithium batteries may experience overcharging / over-discharging, overheating, and excessive current during charging and discharging, battery protection chips are necessary. A single lithium battery cell has a voltage of around 4V; voltages that are too high or too low can damage the battery or shorten its lifespan. When the operating voltage of an appliance is higher than 4V, multiple lithium batteries can be connected in series to increase the voltage (e.g., if the appliance's operating voltage is 16V, four lithium batteries can be connected in series to achieve that voltage). This series of batteries is called a battery pack. However, because there may be imbalances between the batteries, it is necessary to monitor not only the total voltage of the battery pack but also the voltage of each individual battery cell.

[0003] Figure 1 This is a simplified circuit for a four-cell lithium-ion battery protection chip, used to illustrate the basic working principle of the protection chip. This circuit only includes overcharge / overdischarge protection. VCC is the high potential of the power supply, VSS is the low potential, VC1, VC2, VC3, and VCC monitor the battery voltage. The discharge MOSFET (DFET) and charge MOSFET (CFET) are NMOS power transistors. The discharge driver port DDRV and the charge driver port CDRV are connected to the discharge MOSFET and charge MOSFET, respectively. When the monitored battery voltage is within the normal range, the circuit is in normal operation, and both the discharge driver port DDRV and the charge driver port CDRV output high potentials, turning on the discharge MOSFET and charge MOSFET. When a load (electrical appliance) is connected between PCK+ and PCK-, the battery discharges. When any cell is detected to be over-discharged and the voltage is too low, the circuit enters low-voltage protection mode, the discharge driver port DDRV outputs a low potential, the discharge MOSFET DFET is turned off, and the battery stops discharging. When a charger is connected between PCK+ and PCK-, the battery charges. If overcharging of any cell is detected, resulting in excessively high voltage, the circuit enters high-voltage protection mode. The charging drive port CDRV outputs a low potential, the charging MOSFET CFET turns off, and the battery stops charging. After an abnormal state occurs, the circuit must wait for the battery to return to its normal voltage range before it can return to normal operating mode.

[0004] To support higher operating voltages, cascaded battery protection chips are sometimes required. Figure 2It is a battery pack consisting of two 4-cell batteries connected in series, for a total of 8 batteries. To support cascading functionality, the chip adds a discharge control port DCTL (Discharge Control) and a charge control port CCTL (Charge Control), and the following logic is implemented through circuit design:

[0005] (1) If the discharge control port DCTL and the charge control port CCTL inputs are at high potential, then chip 1 operates and Figure 1 The output of the discharge drive port CDRV / charge drive port DDRV will only become low potential when the battery pack corresponding to the chip experiences overvoltage / undervoltage.

[0006] (2) If the discharge control port DCTL input is low potential, then the discharge drive port DDRV becomes low potential; if the charging control port CCTL input is low potential, then the charging drive port CDRV becomes low potential.

[0007] Based on this logic, Figure 2 Although chip 2 is not directly connected to the gates of the discharge MOSFET (DFET) and the charge MOSFET (CFET), if overvoltage / undervoltage is detected in cells 5-8, the signal to turn off the discharge MOSFET (DFET) or the charge MOSFET (CFET) can be transmitted through chip 1 to protect the battery. This is the working principle of cascaded battery protection chips.

[0008] MOSFETs are the basic building blocks of circuits, and their manufacturing processes vary depending on the circuit's function. Power MOSFETs, for example, need to handle large currents and withstand high voltages. GS and V DS (e.g., 60V) GS Therefore, thick gate oxide is used, resulting in high cost and large area. However, logic MOSFETs do not require large currents and only need a relatively low voltage difference (e.g., 1.2V and 0V) to represent logic "1" and "0," allowing for thin gate oxide, which is cheaper and smaller. The main problem here is that when chip 2 is used alone, the discharge drive port DDRV and the charge drive port CDRV are connected to the NMOS power transistor on the drive charging / discharging line, resulting in a large voltage difference between the high and low potentials of the drive output. However, when cascaded, the discharge drive port DDRV and the charge drive port CDRV of chip 2 are input to the logic circuit of chip 1, and the high voltage will break down the thin gate oxide MOSFET used in the logic circuit.

[0009] One proposed solution is to directly connect the level signals of the discharge drive port DDRV and the charge drive port CDRV in chip 2 to the corresponding logic circuits in chip 1 without any processing, and then use thick gate oxide MOSFETs (such as...) in the logic circuit section. Figure 3 (As shown). However, the disadvantage of this approach is that using thick-gate oxide MOSFETs results in high costs.

[0010] Another approach is to divide the high input voltage using resistors to lower the potential input to the logic circuit, thus eliminating the need for thick-gate MOSFETs (such as...) in the logic circuit. Figure 4 (As shown). However, the disadvantages of this scheme are: 1) The number of battery cells connected in series with the power protection chip is not fixed, and the battery potential is also not fixed. Therefore, the output potential when the discharge drive port DDRV and the charging drive port CDRV are high is not fixed, and the voltage division ratio of the resistor is difficult to determine accurately; 2) An additional leakage path is added from the discharge drive port DDRV to ground and from the charging drive port CDRV to ground. However, the resistor cannot be made very large due to the chip area limitation, so the current is large and the power consumption is high. Summary of the Invention

[0011] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a battery protection chip, a battery system, and a battery protection method to solve the problems of high cost in Scheme 1 and high power consumption in Scheme 2 when performing battery protection in existing cascaded battery protection chips.

[0012] To achieve the above and other related objectives, the present invention provides a battery protection chip, which includes at least: a discharge voltage limit detection circuit and a charge voltage limit detection circuit, wherein...

[0013] The discharge voltage limiting detection circuit is used to detect the discharge drive signal output by the previous stage battery protection chip, identify the level of the discharge drive signal according to the current flow direction of the discharge detection signal, and reduce the high-low level conversion window voltage of the discharge drive signal.

[0014] The charging voltage limit detection circuit is used to detect the charging drive signal output by the previous stage battery protection chip, identify the level of the charging drive signal according to the current flow direction of the charging detection signal, and reduce the high-low level conversion window voltage of the charging drive signal.

[0015] Optionally, the discharge voltage limiting detection circuit and the charge voltage limiting detection circuit have the same circuit structure, including at least: a detection module, a clamping module, and a voltage limiting identification module, wherein,

[0016] The detection module is used to detect the corresponding drive signal output by the previous stage battery protection chip and generate a corresponding detection signal;

[0017] The clamping module is connected between the chip power supply terminal and the output terminal of the detection module. It is used to perform bidirectional voltage clamping according to the current flow direction of the corresponding detection signal, so that the voltage of the current inflow port is higher than that of the current outflow port by a clamping voltage.

[0018] The identification and voltage limiting module is connected to the output terminal of the clamping module. It is used to identify the high or low level of the corresponding drive signal based on the magnitude of the output voltage of the clamping module, and reduce the high-low level switching window voltage of the corresponding drive signal based on the reference voltage.

[0019] Optionally, it further includes: a bias voltage generation module and / or an anti-spiking pulse module; wherein, the bias voltage generation module is used to provide a bias voltage for the identification voltage limiting module; the anti-spiking pulse module is connected to the output terminal of the identification voltage limiting module and is used to filter out spike voltages.

[0020] Optionally, the detection module includes: a current-limiting resistor, the first end of which is connected to the corresponding drive signal output by the previous stage battery protection chip, and the second end of which serves as the output terminal of the detection module.

[0021] Optionally, the detection module further includes a short-circuit protection resistor connected in series with the second end of the current-limiting resistor.

[0022] Optionally, the clamping module includes: a first diode and a second diode; the anode of the first diode is connected to the cathode of the second diode and the power supply terminal of the chip, and the cathode of the first diode is connected to the anode of the second diode and the output terminal of the detection module, and serves as the output terminal of the clamping module.

[0023] Optionally, the clamping module includes: at least one first PMOS transistor, wherein,

[0024] When there is one first PMOS transistor, the gate of the first PMOS transistor is connected to its drain and the power supply terminal of the chip, and the source is connected to the output terminal of the detection module and serves as the output terminal of the clamping module.

[0025] When there are two or more first PMOS transistors, the gate of each first PMOS transistor is connected to its drain, and the source of the previous first PMOS transistor is connected to the drain of the next first PMOS transistor. The drain of the first first PMOS transistor is connected to the power supply terminal of the chip, and the source of the last first PMOS transistor is connected to the output terminal of the detection module and serves as the output terminal of the clamping module.

[0026] Optionally, the identification voltage limiting module includes: a second PMOS transistor, a first resistor, a first NMOS transistor, and a first current source; the gate of the second PMOS transistor is connected to a bias voltage, the source is connected to the output terminal of the clamping module, and the drain is connected to the drain of the first NMOS transistor through the first resistor; the gate of the first NMOS transistor is connected to a reference voltage, and the source is connected to the chip reference terminal through the first current source, and serves as the output terminal of the identification voltage limiting module.

[0027] Optionally, the bias voltage generation module includes: a third PMOS transistor, a second resistor, and a second current source; the gate of the third PMOS transistor is connected to its drain, the source is connected to the chip power supply terminal, and the drain is connected to the first terminal of the second resistor; the second terminal of the second resistor is connected to the chip reference terminal through the second current source and serves as the output terminal of the bias voltage generation module.

[0028] Optionally, the battery protection chip further includes: a discharge logic circuit, a charging logic circuit, a discharge drive circuit, and a charging drive circuit, wherein,

[0029] The discharge logic circuit is connected to the output of the discharge voltage limit detection circuit. When the discharge voltage limit detection circuit outputs a high level, it generates corresponding control logic based on the discharge monitoring result of the battery protection chip. When the discharge voltage limit detection circuit outputs a low level, it generates control logic for discharge abnormality.

[0030] The discharge drive circuit is connected to the output terminal of the discharge logic circuit and is used to generate a corresponding discharge drive signal according to the control logic output by the discharge logic circuit.

[0031] The charging logic circuit is connected to the output of the charging voltage limit detection circuit. When the charging voltage limit detection circuit outputs a high level, it generates corresponding control logic based on the charging monitoring result of the battery protection chip. When the charging voltage limit detection circuit outputs a low level, it generates control logic for charging abnormality.

[0032] The charging drive circuit is connected to the output terminal of the charging logic circuit and is used to generate a corresponding charging drive signal according to the control logic output by the charging logic circuit.

[0033] Optionally, both the discharge drive circuit and the charging drive circuit are implemented using an open-drain structure or a push-pull structure.

[0034] The present invention also provides a battery system comprising: at least two battery packs and at least two battery protection chips as described in any of the preceding claims, wherein each battery protection chip corresponds one-to-one with a battery pack; wherein a discharge drive signal output by an upstream battery protection chip is connected to a discharge voltage limit detection circuit of a downstream battery protection chip, a charging drive signal output by an upstream battery protection chip is connected to a charging voltage limit detection circuit of a downstream battery protection chip, a discharge drive signal output by a downstream battery protection chip controls a discharge MOSFET, and a charging drive signal output by a downstream battery protection chip controls a charging MOSFET.

[0035] This invention also provides a method for implementing battery protection using cascaded battery protection chips, the method comprising:

[0036] The battery protection chip monitors the battery voltage of each battery in the corresponding battery pack during the charging and discharging process;

[0037] The next-level battery protection chip detects the previous-level drive signal output by the previous-level battery protection chip, identifies the level of the previous-level drive signal based on the current flow direction of the detected signal, and reduces the high-low level conversion window voltage of the previous-level drive signal.

[0038] The next-stage battery protection chip generates the next-stage drive signal based on the reduced signal level and its monitoring results.

[0039] As described above, the battery protection chip, battery system, and battery protection method of the present invention, through the design of the discharge voltage limit detection circuit and the charge voltage limit detection circuit, reduce the high-low level conversion window voltage of the previous stage discharge / charge drive signal, making it suitable for logic circuits composed of thin-gate oxide MOSFET devices, thereby reducing chip cost. Furthermore, the present invention determines the level of the previous stage discharge / charge drive signal by the current flow direction, being sensitive only to the current flow direction and insensitive to its magnitude. Therefore, it can operate normally within a relatively wide voltage range, avoiding the problem of resistor voltage division. Moreover, the present invention controls the current through MOSFETs, resulting in a smaller circuit area, lower current, and lower power consumption. Attached Figure Description

[0040] Figure 1 This is a circuit diagram showing how a single existing battery protection chip protects the battery.

[0041] Figure 2 This is a circuit diagram showing how an existing cascaded battery protection chip protects the battery.

[0042] Figure 3 Displayed as Figure 2 The diagram shows a cascaded transmission method of the drive signal in the battery protection chip.

[0043] Figure 4 Displayed as Figure 2 The diagram shows another cascaded transmission method for drive signals in the battery protection chip.

[0044] Figure 5 The diagram shows a discharge voltage limit detection circuit in the battery protection chip of the present invention.

[0045] Figure 6 The diagram shown is a schematic of the charging voltage limit detection circuit in the battery protection chip of the present invention.

[0046] Figure 7 This is a schematic diagram of the first type of clamping circuit in the battery protection chip of the present invention.

[0047] Figure 8 This is a second schematic diagram of the clamping circuit in the battery protection chip of the present invention.

[0048] Figure 9 This is a third schematic diagram of the clamping circuit in the battery protection chip described in this invention.

[0049] Figure 10 The diagram shows the waveforms of relevant signals in the battery protection chip described in this invention.

[0050] Component designation explanation

[0051] 10 Battery protection chips

[0052] 11 Discharge Limit Voltage Detection Circuit

[0053] 12 Charging voltage limit detection circuit

[0054] Detection modules 111 and 121

[0055] 112, 122 clamping modules

[0056] 113, 123 Identify voltage limiting modules

[0057] 114, 124 Bias Voltage Generation Modules

[0058] 115, 125 Anti-spiking pulse modules

[0059] 13 Discharge Logic Circuit

[0060] 14 Charging logic circuit

[0061] 15 Discharge drive circuit

[0062] 16 Charging drive circuit Detailed Implementation

[0063] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] Please see Figures 5 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] like Figure 5 and Figure 6 As shown, this embodiment provides a battery protection chip 10, which includes at least a discharge voltage limit detection circuit 11 and a charge voltage limit detection circuit 12. Further, the battery protection chip 10 also includes a discharge logic circuit 13, a charge logic circuit 14, a discharge drive circuit 15, and a charge drive circuit 16. It should be noted that the battery protection chip 10 described in this embodiment is applicable to the case of multiple chips cascaded. Of course, it is also applicable to the case of a single chip, but the superiority of this solution cannot be demonstrated.

[0066] like Figure 5 As shown, the discharge voltage limiting detection circuit 11 is used to detect the discharge drive signal output by the previous stage battery protection chip, and to identify the level of the previous stage discharge drive signal based on the current flow direction of the discharge detection signal. Furthermore, it reduces the high-low level conversion window voltage of the previous stage discharge drive signal, making the reduced signal level suitable for driving thin-gate oxide MOSFET devices, which helps reduce chip cost. In this embodiment, the discharge voltage limiting detection circuit 11 identifies the level of the previous stage discharge drive signal by the current flow direction of the discharge detection signal. It is only sensitive to the current flow direction and not to the magnitude, avoiding the problem of resistor voltage division and resulting in low power consumption.

[0067] Specifically, the discharge voltage limiting detection circuit 11 includes at least: a detection module 111, a clamping module 112, and a voltage limiting identification module 113. Further, the discharge voltage limiting detection circuit 11 also includes a bias voltage generation module 114 and / or an anti-spiking pulse module 115. In this embodiment, the discharge voltage limiting detection circuit 11 includes: a detection module 111, a clamping module 112, an anti-spiking pulse module 113, a bias voltage generation module 114, and an anti-spiking pulse module 115.

[0068] The detection module 111 is used to detect the previous stage discharge drive signal and generate the discharge detection signal.

[0069] As an example, the detection module 111 includes a current-limiting resistor Rcl1; wherein, the first end of the current-limiting resistor Rcl1 is connected to the previous stage discharge drive signal, and the second end of the current-limiting resistor Rcl1 serves as the output terminal of the detection module 111 to output the discharge detection signal. Further, the detection module 111 also includes a short-circuit protection resistor Rsp1, connected in series with the second end of the current-limiting resistor Rcl1, to prevent damage to the chip due to overcurrent when the current-limiting resistor Rcl1 is short-circuited. It should be noted that when the detection module 111 includes both the current-limiting resistor Rcl1 and the short-circuit protection resistor Rsp1, the first end of the short-circuit protection resistor Rsp1 is connected to the second end of the current-limiting resistor Rcl1, and the second end of the short-circuit protection resistor Rsp1 serves as the output terminal of the detection module 111. In this case, the second end of the current-limiting resistor Rcl1 will no longer serve as the output terminal of the detection module 111. In practical applications, the current-limiting resistor Rcl1 can be set inside or outside the battery protection chip 10, which does not affect this embodiment; optionally, the current-limiting resistor Rcl1 is set outside the battery protection chip 10 to facilitate resistance adjustment.

[0070] The clamping module 112 is connected between the chip power supply terminal VCC and the output terminal of the detection module 111. It is used to perform bidirectional voltage clamping according to the current flow direction of the discharge detection signal, so that the voltage of the current inflow port is higher than that of the current outflow port by a clamping voltage Vclamp.

[0071] In this embodiment, the current magnitude of the discharge detection signal corresponds to the high or low level of the previous stage discharge drive signal, and also determines the current flow direction in the clamping module 112, thereby obtaining a voltage value at the output terminal (i.e., at node A11) that is related to the high or low level of the previous stage discharge drive signal. If the previous stage discharge drive signal is low, the current of the discharge detection signal is less than I11 or even 0. In this case, the current flow direction in the clamping module 112 is from VCC to A11, and the voltage at node A11 is clamped at VCC-Vclamp. If the previous stage discharge drive signal is high, the current of the discharge detection signal is greater than I11. In this case, the current flow direction in the clamping module 112 is from A11 to VCC, and the voltage at node A11 is clamped at VCC+Vclamp.

[0072] As an example, the clamping module 112 includes: a first diode D11 and a second diode D21; wherein, the anode of the first diode D11 is connected to the cathode of the second diode D21 and the chip power supply terminal VCC, and the cathode of the first diode D11 is connected to the anode of the second diode D21 and the output terminal of the detection module 111, and serves as the output terminal of the clamping module 112 (e.g., ...). Figure 7 (As shown). This example uses two diodes to achieve bidirectional voltage clamping, ensuring that the voltage at the current-in port is higher than the voltage at the current-out port by the forward voltage of one diode.

[0073] As another example, the clamping module 112 includes: at least one first PMOS transistor P11; wherein, when the number of first PMOS transistors P11 is one, the gate of the first PMOS transistor P11 is connected to its drain and the chip power supply terminal VCC, and the source is connected to the output terminal of the detection module 111, and serves as the output terminal of the clamping module 112 (e.g., Figure 8 (As shown); When the number of first PMOS transistors P11 is greater than or equal to 2, the gate of each first PMOS transistor P11 is connected to its drain, and the source of the previous first PMOS transistor P11 is connected to the drain of the next first PMOS transistor P11. The drain of the first first PMOS transistor P11 is connected to the chip power supply terminal VCC, and the source of the last first PMOS transistor P11 is connected to the output terminal of the detection module 111, and serves as the output terminal of the clamping module 112 (as shown). Figure 9 (As shown). In this example, a diode-connected PMOS is used for bidirectional voltage clamping. To obtain a higher clamping voltage Vclamp, it can be... Figure 8 The PMOS transistor in the design is implemented using a thick-gate oxide MOSFET device; of course, it can also be implemented as follows: Figure 9 As shown, multiple thin-gate oxide MOSFET devices are connected in series to achieve this (for example, to obtain a 2V clamping voltage, three thin-gate oxide MOSFET devices can be connected in series. At low current, the voltage drop from VCC to A11 is the conduction voltage of the three parasitic diodes, which is about 2.1V. The voltage drop from A11 to VCC is 3*Vth, which is also about 2.1V, where Vth is the conduction threshold of the thin-gate oxide MOSFET device).

[0074] The identification and voltage limiting module 113 is connected to the output terminal of the clamping module 112 and is used to identify the level of the previous discharge drive signal according to the magnitude of the output voltage of the clamping module 112, and reduce the high-low level conversion window voltage of the previous discharge drive signal based on the reference voltage Vref1.

[0075] As an example, the identification voltage limiting module 113 includes: a second PMOS transistor P21, a first resistor R11, a first NMOS transistor N11, and a first current source I11; the gate of the second PMOS transistor P21 is connected to a bias voltage, its source is connected to the output terminal of the clamping module 112, and its drain is connected to the drain of the first NMOS transistor N11 through the first resistor R11; the gate of the first NMOS transistor N11 is connected to a reference voltage Vref1, and its source is connected to the chip reference terminal VSS through the first current source I11, serving as the output terminal of the identification voltage limiting module 113. Optionally, the current in the first current source I11 is provided by a current mirror.

[0076] In this embodiment, when the voltage at node A11 is VCC-Vclamp, the second PMOS transistor P21 is turned off. At this time, the first current source I11 will still attempt to draw current and pull the voltage at node A21 down to 0V. That is, the voltage limiting module 113 identifies the previous stage discharge drive signal as low level and outputs a low level. When the voltage at node A11 is VCC+Vclamp, the second PMOS transistor P21 is turned on, and the first NMOS transistor N11 is turned on under the control of the reference voltage Vref1, causing the voltage at node A21 to rise to Vr. ef1-Vth_N11, where Vth_N11 is the gate-source voltage of the first NMOS transistor N11 when its drain-source current is equal to I11. That is, the identification and limiting module 113 identifies that the previous stage discharge drive signal is high level, and uses the reference voltage Vref1 to reduce the high level, reducing the high-low level conversion window voltage of the previous stage discharge drive signal to a high-low level conversion window voltage suitable for driving the thin gate oxide MOSFET device; where the reference voltage Vref1=Vdda+Vth_N11, and Vdda is a high level suitable for driving the thin gate oxide MOSFET.

[0077] The bias voltage generation module 114 is used to provide a bias voltage to the identification voltage limiting module 113, so that the second PMOS transistor P21 in the identification voltage limiting module 113 is turned off when the voltage at node A11 is VCC-Vclamp, and turned on when the voltage at node A11 is VCC+Vclamp.

[0078] As an example, the bias voltage generation module 114 includes: a third PMOS transistor P31, a second resistor R21, and a second current source I21; the gate of the third PMOS transistor P31 is connected to its drain, the source is connected to the chip power supply terminal VCC, and the drain is connected to the first terminal of the second resistor R21; the second terminal of the second resistor R21 is connected to the chip reference terminal VSS through the second current source I21, and serves as the output terminal of the bias voltage generation module 114 for outputting the bias voltage. Optionally, the current in the second current source I21 is provided by a current mirror.

[0079] In this embodiment, the current provided by the second current source I21 passes through the third PMOS transistor P31 and the second resistor R21, generating a voltage drop of |Vgs_P31| + I21 * R21 at node A01, which is then used as the bias voltage output. Here, Vgs_P31 is the gate-source voltage of the third PMOS transistor when its drain-source current equals I21, I21 is the current provided by the second current source, and R21 is the resistance value of the second resistor. By adjusting Vgs_P31, I21, and R21, the bias voltage satisfies the following conditions: when the voltage at node A11 is VCC - Vclamp, the second PMOS transistor P21 is turned off; when the voltage at node A11 is VCC + Vclamp, the second PMOS transistor P21 is turned on.

[0080] The anti-spiking pulse module 115 is connected to the output terminal of the identification and voltage limiting module 113 and is used to filter out spike voltages and prevent false triggering.

[0081] As an example, the anti-spiking module 115 consists of a capacitor and a delay circuit. The capacitor has a filtering and voltage-stabilizing function, and combined with the delay circuit, it can prevent false triggering caused by spike voltage. It should be noted that any existing circuit consisting of a capacitor and a delay circuit with the function of filtering spike voltage is applicable to this embodiment.

[0082] like Figure 6 As shown, the charging voltage limit detection circuit 12 is used to detect the charging drive signal output by the previous stage battery protection chip, and to identify the high or low level of the previous stage charging drive signal based on the current flow direction of the charging detection signal. Furthermore, it reduces the high-low level conversion window voltage of the previous stage charging drive signal, making the reduced signal level suitable for driving thin-gate oxide MOSFET devices, which helps reduce chip cost. In this embodiment, the charging voltage limit detection circuit 12 identifies the high or low level of the previous stage charging drive signal by the current flow direction of the charging detection signal. It is only sensitive to the current flow direction and not to the magnitude, avoiding the problem of resistor voltage division and resulting in low power consumption.

[0083] Specifically, the charging voltage limiting detection circuit 12 includes at least: a detection module 121, a clamping module 122, and a voltage limiting identification module 123. Further, the charging voltage limiting detection circuit 12 also includes a bias voltage generation module 124 and / or an anti-spiking module 125. In this embodiment, the charging voltage limiting detection circuit 12 includes: a detection module 121, a clamping module 122, an anti-spiking module 123, a bias voltage generation module 124, and an anti-spiking module 125.

[0084] The detection module 121 is used to detect the previous charging drive signal and generate the charging detection signal.

[0085] As an example, the detection module 121 includes a current-limiting resistor Rcl2; wherein, the first end of the current-limiting resistor Rcl2 is connected to the previous stage charging drive signal, and the second end of the current-limiting resistor Rcl2 serves as the output terminal of the detection module 121 to output the charging detection signal. Further, the detection module 121 also includes a short-circuit protection resistor Rsp2, connected in series with the second end of the current-limiting resistor Rcl2, to prevent damage to the chip due to overcurrent when the current-limiting resistor Rcl2 is short-circuited. It should be noted that when the detection module 121 includes both the current-limiting resistor Rcl2 and the short-circuit protection resistor Rsp2, the first end of the short-circuit protection resistor Rsp2 is connected to the second end of the current-limiting resistor Rcl2, and the second end of the short-circuit protection resistor Rsp2 serves as the output terminal of the detection module 121. In this case, the second end of the current-limiting resistor Rcl2 will no longer serve as the output terminal of the detection module 121. In practical applications, the current-limiting resistor Rcl2 can be set inside or outside the battery protection chip 10, which does not affect this embodiment; optionally, the current-limiting resistor Rcl2 is set outside the battery protection chip 10 to facilitate resistance adjustment.

[0086] The clamping module 122 is connected between the chip power supply terminal VCC and the output terminal of the detection module 121. It is used to perform bidirectional voltage clamping according to the current flow direction of the charging detection signal, so that the voltage of the current inflow port is higher than that of the current outflow port by a clamping voltage Vclamp.

[0087] In this embodiment, the current magnitude of the charging detection signal corresponds to the high or low level of the previous stage charging drive signal, and also determines the current flow direction in the clamping module 122, thereby obtaining a voltage value at the output terminal (i.e., at node A12) that is related to the high or low level of the previous stage charging drive signal. If the previous stage charging drive signal is low, the current of the charging detection signal is less than I12 or even 0. In this case, the current flow direction in the clamping module 122 is from VCC to A12, and the voltage at node A12 is clamped at VCC-Vclamp. If the previous stage charging drive signal is high, the current of the charging detection signal is greater than I12. In this case, the current flow direction in the clamping module 122 is from A12 to VCC, and the voltage at node A12 is clamped at VCC+Vclamp.

[0088] As an example, the clamping module 122 includes: a first diode D12 and a second diode D22; wherein, the anode of the first diode D12 is connected to the cathode of the second diode D22 and the chip power supply terminal VCC, and the cathode of the first diode D12 is connected to the anode of the second diode D22 and the output terminal of the detection module 121, and serves as the output terminal of the clamping module 122 (e.g., ...). Figure 7 (As shown). This example uses two diodes to achieve bidirectional voltage clamping, ensuring that the voltage at the current-in port is higher than the voltage at the current-out port by the forward voltage of one diode.

[0089] As another example, the clamping module 122 includes: at least one first PMOS transistor P12; wherein, when the number of first PMOS transistors P12 is one, the gate of the first PMOS transistor P12 is connected to its drain and the chip power supply terminal VCC, and the source is connected to the output terminal of the detection module 121, and serves as the output terminal of the clamping module 122 (e.g., Figure 8 (As shown); When the number of first PMOS transistors P12 is greater than or equal to 2, the gate of each first PMOS transistor P12 is connected to its drain, and the source of the previous first PMOS transistor P12 is connected to the drain of the next first PMOS transistor P12. The drain of the first first PMOS transistor P12 is connected to the chip power supply terminal VCC, and the source of the last first PMOS transistor P12 is connected to the output terminal of the detection module 121, and serves as the output terminal of the clamping module 122 (as shown); Figure 9 (As shown). In this example, a diode-connected PMOS is used for bidirectional voltage clamping. To obtain a higher clamping voltage Vclamp, it can be... Figure 8 The PMOS transistor in the design is implemented using a thick-gate oxide MOSFET device; of course, it can also be implemented as follows: Figure 9As shown, multiple thin-gate oxide MOSFET devices are connected in series to achieve this (for example, to obtain a 2V clamping voltage, three thin-gate oxide MOSFET devices can be connected in series. At low current, the voltage drop from VCC to A12 is the conduction voltage of the three parasitic diodes, which is about 2.1V. The voltage drop from A12 to VCC is 3*Vth, which is also about 2.1V, where Vth is the conduction threshold of the thin-gate oxide MOSFET device).

[0090] The identification and voltage limiting module 123 is connected to the output terminal of the clamping module 122 and is used to identify the high or low level of the previous charging drive signal according to the magnitude of the output voltage of the clamping module 122, and reduce the high-low level conversion window voltage of the previous charging drive signal based on the reference voltage Vref2.

[0091] As an example, the identification voltage limiting module 123 includes: a second PMOS transistor P22, a first resistor R12, a first NMOS transistor N12, and a first current source I12; the gate of the second PMOS transistor P22 is connected to a bias voltage, its source is connected to the output terminal of the clamping module 122, and its drain is connected to the drain of the first NMOS transistor N12 through the first resistor R12; the gate of the first NMOS transistor N12 is connected to a reference voltage Vref2, and its source is connected to the chip reference terminal VSS through the first current source I12, serving as the output terminal of the identification voltage limiting module 123. Optionally, the current in the first current source I12 is provided by a current mirror.

[0092] In this embodiment, when the voltage at node A12 is VCC-Vclamp, the second PMOS transistor P22 is turned off. At this time, the first current source I12 will still attempt to draw current and pull the voltage at node A22 down to 0V. That is, the voltage limiting module 123 identifies the previous stage charging drive signal as low level and outputs a low level. When the voltage at node A12 is VCC+Vclamp, the second PMOS transistor P22 is turned on, and the first NMOS transistor N12 is turned on under the control of the reference voltage Vref2, causing the voltage at node A22 to rise to Vr. ef2-Vth_N12, where Vth_N12 is the gate-source voltage of the first NMOS transistor N12 when its drain-source current is equal to I12. That is, the identification and limiting module 123 identifies that the previous stage charging drive signal is high level, and uses the reference voltage Vref2 to reduce the high level, reducing the high-low level conversion window voltage of the previous stage charging drive signal to a high-low level conversion window voltage suitable for driving the thin gate oxide MOSFET device; where the reference voltage Vref2=Vdda+Vth_N12, and Vdda is a high level suitable for driving the thin gate oxide MOSFET.

[0093] The bias voltage generation module 124 is used to provide a bias voltage to the identification voltage limiting module 123 so that the second PMOS transistor P22 in the identification voltage limiting module 123 is turned off when the voltage at node A12 is VCC-Vclamp, and turned on when the voltage at node A12 is VCC+Vclamp.

[0094] As an example, the bias voltage generation module 124 includes: a third PMOS transistor P32, a second resistor R22, and a second current source I22; the gate of the third PMOS transistor P32 is connected to its drain, the source is connected to the chip power supply terminal VCC, and the drain is connected to the first terminal of the second resistor R22; the second terminal of the second resistor R22 is connected to the chip reference terminal VSS through the second current source I22, and serves as the output terminal of the bias voltage generation module 124 for outputting the bias voltage. Optionally, the current in the second current source I22 is provided by a current mirror.

[0095] In this embodiment, the current provided by the second current source I22 passes through the third PMOS transistor P32 and the second resistor R22, generating a voltage drop of |Vgs_P32| + I22 * R22 at node A02, which is then used as the bias voltage output. Here, Vgs_P32 is the gate-source voltage of the third PMOS transistor when its drain-source current equals I22, I22 is the current provided by the second current source, and R22 is the resistance value of the second resistor. By adjusting Vgs_P32, I22, and R22, the bias voltage satisfies the following conditions: when the voltage at node A12 is VCC - Vclamp, the second PMOS transistor P22 is turned off; when the voltage at node A12 is VCC + Vclamp, the second PMOS transistor P22 is turned on.

[0096] The anti-spiking pulse module 125 is connected to the output terminal of the identification and voltage limiting module 123 and is used to filter out spike voltages and prevent false triggering.

[0097] As an example, the anti-spiking module 125 consists of a capacitor and a delay circuit. The capacitor has a filtering and voltage-stabilizing function, and combined with the delay circuit, it can prevent false triggering caused by spike voltage. It should be noted that any existing circuit consisting of a capacitor and a delay circuit with the function of filtering spike voltage is applicable to this embodiment.

[0098] The discharge logic circuit 13 is connected to the output terminal of the discharge voltage limit detection circuit 11. When the discharge voltage limit detection circuit 11 outputs a high level, it generates corresponding control logic based on the discharge monitoring result of the battery protection chip. When the discharge voltage limit detection circuit 11 outputs a low level, it generates control logic for discharge abnormality.

[0099] In this embodiment, the discharge voltage limit detection circuit 11 outputs a high level, meaning the discharge drive signal output by the previous-level battery protection chip is high, indicating that the previous-level battery protection chip is monitoring normal discharge. At this time, the discharge logic circuit 13 generates corresponding control logic based on the monitoring result of the current-level battery protection chip. If the current-level battery protection chip detects an abnormal discharge, the discharge logic circuit 13 generates control logic for an abnormal discharge; otherwise, it generates control logic for normal discharge. When the discharge voltage limit detection circuit 11 outputs a low level, meaning the discharge drive signal output by the previous-level battery protection chip is low, indicating that the previous-level battery protection chip is monitoring an abnormal discharge, the discharge logic circuit 13 directly generates control logic for an abnormal discharge.

[0100] The charging logic circuit 14 is connected to the output terminal of the charging voltage limit detection circuit 12. When the charging voltage limit detection circuit 12 outputs a high level, it generates corresponding control logic based on the charging monitoring result of the battery protection chip. When the charging voltage limit detection circuit 12 outputs a low level, it generates control logic for charging abnormality.

[0101] In this embodiment, the charging voltage limit detection circuit 12 outputs a high level, meaning the previous-level charging drive signal output by the previous-level battery protection chip is high, indicating that the previous-level battery protection chip is monitoring normal charging. At this time, the charging logic circuit 14 generates corresponding control logic based on the monitoring result of the current-level battery protection chip. If the current-level battery protection chip detects an abnormal charging situation, the charging logic circuit 14 generates control logic for the abnormal charging situation; otherwise, it generates control logic for normal charging. When the charging voltage limit detection circuit 12 outputs a low level, meaning the previous-level charging drive signal output by the previous-level battery protection chip is low, indicating that the previous-level battery protection chip is monitoring an abnormal charging situation, the charging logic circuit 14 directly generates control logic for the abnormal charging situation.

[0102] The discharge drive circuit 15 is connected to the output terminal of the discharge logic circuit 13 and is used to generate a corresponding discharge drive signal based on the control logic output by the discharge logic circuit 13.

[0103] In this embodiment, when the discharge logic circuit 13 generates control logic for a discharge abnormality, the discharge drive circuit 15 generates a low-level discharge drive signal to control the discharge MOS transistor to turn off; when the discharge logic circuit 13 generates control logic for a normal discharge, the discharge drive circuit 15 generates a high-level discharge drive signal to control the discharge MOS transistor to turn on.

[0104] As an example, the discharge drive circuit 15 is implemented using an open-drain structure or a push-pull structure. For the open-drain structure, no current flows out when the chip experiences a discharge abnormality protection, but a large current flows out when the chip is operating normally. For the push-pull structure, a small current flows out when the chip experiences a discharge abnormality protection, but a large current flows out when the chip is operating normally. Here, "small current" refers to a current less than I11, and "large current" refers to a current greater than I11. It should be noted that both the open-drain and push-pull structures are well-known in the art, and therefore will not be described in detail here.

[0105] The charging drive circuit 16 is connected to the output terminal of the charging logic circuit 14 and is used to generate a corresponding charging drive signal based on the control logic output by the charging logic circuit 14.

[0106] In this embodiment, when the charging logic circuit 14 generates control logic for a charging abnormality, the charging drive circuit 16 generates a low-level local charging drive signal to control the charging MOSFET to turn off; when the charging logic circuit 14 generates control logic for normal charging, the charging drive circuit 16 generates a high-level local charging drive signal to control the charging MOSFET to turn on.

[0107] As an example, the charging drive circuit 16 is implemented using an open-drain structure or a push-pull structure. For the open-drain structure, no current flows out when the chip experiences a charging abnormality protection event, but a large current flows out when the chip is operating normally. For the push-pull structure, a small current flows out when the chip experiences a charging abnormality protection event, but a large current flows out when the chip is operating normally. Here, "small current" refers to a current less than I12, and "large current" refers to a current greater than I12. It should be noted that both the open-drain and push-pull structures are well-known in the art, and therefore will not be described in detail here.

[0108] Accordingly, this embodiment also provides a battery system, which includes at least two battery packs and at least two battery protection chips 10 as described above, wherein each battery protection chip 10 corresponds to one of the battery packs; wherein the discharge drive signal output by the previous stage battery protection chip is connected to the discharge voltage limit detection circuit 11 of the next stage battery protection chip, the charging drive signal output by the previous stage battery protection chip is connected to the charging voltage limit detection circuit 12 of the next stage battery protection chip, the discharge drive signal output by the last stage battery protection chip controls the discharge MOS transistor, and the charging drive signal output by the last stage battery protection chip controls the charging MOS transistor.

[0109] The following is based on Figure 5 and Figure 6The cascaded structure shown illustrates the working principle of the battery system described in this embodiment. Since the principles of the discharge and charging processes are the same, only the discharge process will be used as an example for explanation here.

[0110] like Figure 5 As shown, two battery packs are cascaded, and two battery protection chips are cascaded and connected to the corresponding battery packs. The battery pack voltages Vpack1 and Vpack2 both range from 18V to 40V. The voltage VCC1 at the power supply terminal of battery protection chip 1 is the same as the voltage VSS2 at the reference terminal of battery protection chip 2. For battery protection chip 2, the low potential of the discharge drive signal output by the discharge drive circuit is VSS2, and the high potential is VSS2 + Vhigh, where Vhigh ≈ Vpack2. Since the potential difference of the discharge drive signal can reach 40V, it far exceeds the operating range of thin-gate oxide MOSFET devices (generally around 5V).

[0111] For discharge drive circuits with open-drain structures:

[0112] When the battery protection chip 2 experiences a discharge abnormality, the current source of the discharge drive circuit is shut off, and no current is output from the battery protection chip 2. Since there is a current of magnitude I11 in the battery protection chip 1, this current can only flow in from VCC1, that is, from left to right through the clamping module 112. At this time, the potential at node A11 is VCC1 - Vclamp. The second PMOS transistor P21 is turned off, and the first current source I11 still attempts to draw current and pulls the voltage at node A21 down to 0V (e.g., Figure 10 (As shown). At this time, the discharge logic circuit 13 directly generates the control logic for the discharge abnormality, and the discharge drive signal 15 generates a low-level discharge drive signal to control the discharge MOS transistor to turn off, thereby realizing the discharge abnormality protection.

[0113] When the battery protection chip 2 detects normal discharge, there is a current output greater than I11 in the discharge drive circuit. At this time, current flows from right to left through the clamping module 112, and the potential at node A11 is VCC1 + Vclamp. The second PMOS transistor P21 is turned on, and the first NMOS transistor N11 is used to raise the voltage at node A21 to Vref1 - Vth - N11, that is, Vdda (e.g., ...). Figure 10 (As shown). At this time, the discharge logic circuit 13 generates corresponding control logic based on the monitoring results of the battery protection chip 1, and the discharge drive signal 15 generates corresponding discharge drive signal based on the control logic of the discharge logic circuit 13 to control the discharge MOS transistor to be turned on or off.

[0114] For a push-pull structure for the discharge drive circuit:

[0115] When the battery protection chip 2 experiences a discharge abnormality, the discharge drive circuit outputs a current less than I11. At this time, current flows from left to right through the clamping module 112, and the potential at node A11 is VCC1-Vclamp. The second PMOS transistor P21 is turned off, and the first current source I11 still attempts to draw current, pulling the voltage at node A21 down to 0V (e.g., ...). Figure 10 (As shown). At this time, the discharge logic circuit 13 directly generates the control logic for the discharge abnormality, and the discharge drive signal 15 generates a low-level discharge drive signal to control the discharge MOS transistor to turn off, thereby realizing the discharge abnormality protection.

[0116] When the battery protection chip 2 detects normal discharge, there is a current output greater than I11 in the discharge drive circuit. At this time, current flows from right to left through the clamping module 112, and the potential at node A11 is VCC1 + Vclamp. The second PMOS transistor P21 is turned on, and the first NMOS transistor N11 is used to raise the voltage at node A21 to Vref1 - Vth - N11, that is, Vdda (e.g., ...). Figure 10 (As shown). At this time, the discharge logic circuit 13 generates corresponding control logic based on the monitoring results of the battery protection chip 1, and the discharge drive signal 15 generates corresponding discharge drive signal based on the control logic of the discharge logic circuit 13 to control the discharge MOS transistor to be turned on or off.

[0117] Accordingly, this embodiment also provides a method for implementing battery protection by cascading battery protection chips, the method comprising:

[0118] 1) The battery protection chip monitors the battery voltage of each battery in the corresponding battery pack during the charging and discharging process. It should be noted that using a battery protection chip to monitor battery voltage is a well-known technology in the field and will not be elaborated here.

[0119] 2) The next-level battery protection chip detects the previous-level drive signal output by the previous-level battery protection chip, identifies the level of the previous-level drive signal based on the current flow direction of the detected signal, and reduces the high-low level conversion window voltage of the previous-level drive signal to make it suitable for driving thin gate oxide MOSFET devices.

[0120] Specifically, it can be adopted Figure 5 and Figure 6The circuit shown is used to achieve this. When the previous stage discharge / charge drive signal is low, the current of the discharge / charge detection signal is less than I11 / I12. At this time, current flows from left to right through the clamping module 112 / 122, and the voltage at node A11 / A12 is VCC-Vclamp. The second PMOS transistor P21 / P22 is turned off, and the first current source I11 / I12 attempts to draw current and pulls the voltage at node A21 / A22 down to 0V. When the previous stage discharge / charge drive signal is high, the current of the discharge / charge detection signal is greater than I11 / I12. At this time, current flows from right to left through the clamping module 112 / 122, and the voltage at node A11 / A12 is VCC+Vclamp. The second PMOS transistor P21 / P22 is turned on, and the first NMOS transistor N11 is used to raise the voltage at node A21 / A22 to Vref1-Vth_N11, which is Vdda.

[0121] 3) The next-level battery protection chip generates the next-level drive signal based on the reduced signal level and its monitoring results.

[0122] Specifically, when the reduced signal level is low, it indicates that the previous stage battery protection chip has experienced a discharge / charge abnormality. In this case, the next stage battery protection chip directly generates a low-level next-stage drive signal to control the discharge / charge MOSFET to turn off, thus achieving discharge / charge abnormality protection. When the reduced signal level is high, it indicates that the previous stage battery protection chip is discharging / charging normally. In this case, the next stage battery protection chip generates a next-stage drive signal based on its own monitoring results. If it detects a discharge / charge abnormality, it generates a low-level next-stage drive signal to control the discharge / charge MOSFET to turn off, thus achieving discharge / charge abnormality protection. Conversely, it generates a high-level next-stage drive signal to control the discharge / charge MOSFET to turn on.

[0123] In summary, the battery protection chip, battery system, and battery protection method of this invention, through the design of discharge voltage limit detection circuit and charge voltage limit detection circuit, reduce the high-low level conversion window voltage of the previous stage discharge / charge drive signal, making it suitable for logic circuits composed of thin-gate oxide MOSFET devices, thereby reducing chip cost. Furthermore, this invention determines the level of the previous stage discharge / charge drive signal by current flow direction, being sensitive only to current flow direction and insensitive to current magnitude. Therefore, it can operate normally within a wide voltage range, avoiding the problem of resistor voltage division. Moreover, this invention controls current through MOSFETs, resulting in a smaller circuit area, lower current, and lower power consumption. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A battery protection chip, characterized in that, The battery protection chip includes at least: a discharge voltage limit detection circuit and a charge voltage limit detection circuit, wherein... The discharge voltage limiting detection circuit is used to detect the discharge drive signal output by the previous stage battery protection chip, identify the level of the discharge drive signal according to the current flow direction of the discharge detection signal, and reduce the high-low level conversion window voltage of the discharge drive signal. The charging voltage limit detection circuit is used to detect the charging drive signal output by the previous stage battery protection chip, identify the level of the charging drive signal according to the current flow direction of the charging detection signal, and reduce the high-low level conversion window voltage of the charging drive signal. The discharge voltage limiting detection circuit and the charging voltage limiting detection circuit have the same circuit structure, including at least: a detection module, a clamping module, and a voltage limiting identification module. The detection module is used to detect the corresponding drive signal output by the upstream battery protection chip and generate a corresponding detection signal. The clamping module is connected between the chip power supply terminal and the output terminal of the detection module, and is used to perform bidirectional voltage clamping according to the current flow direction of the corresponding detection signal, so that the voltage at the current inflow port is higher than the voltage at the current outflow port by a clamping voltage. The voltage limiting identification module is connected to the output terminal of the clamping module, and is used to identify the level of the corresponding drive signal according to the magnitude of the output voltage of the clamping module, and reduce the high-low level conversion window voltage of the corresponding drive signal based on the reference voltage. When the corresponding drive signal is low, the current flow of the corresponding detection signal is from the chip power supply terminal to the output terminal of the detection module, and the output voltage of the clamping module is clamped at VCC-Vclamp; when the corresponding drive signal is high, the current flow of the corresponding detection signal is from the output terminal of the detection module to the chip power supply terminal, and the output voltage of the clamping module is clamped at VCC+Vclamp; where VCC is the chip power supply and Vclamp is the clamping voltage.

2. The battery protection chip according to claim 1, characterized in that, Also includes: A bias voltage generation module and / or an anti-spiking pulse module; wherein the bias voltage generation module is used to provide a bias voltage for the identification voltage limiting module; The anti-spiking pulse module is connected to the output of the identification and voltage limiting module and is used to filter out spike voltages.

3. The battery protection chip according to claim 1 or 2, characterized in that, The detection module includes: a current-limiting resistor, the first end of which is connected to the corresponding drive signal output by the previous stage battery protection chip, and the second end which serves as the output terminal of the detection module.

4. The battery protection chip according to claim 3, characterized in that, The detection module further includes a short-circuit protection resistor connected in series with the second end of the current-limiting resistor.

5. The battery protection chip according to claim 1 or 2, characterized in that, The clamping module includes a first diode and a second diode; the anode of the first diode is connected to the cathode of the second diode and the power supply terminal of the chip, and the cathode of the first diode is connected to the anode of the second diode and the output terminal of the detection module, and serves as the output terminal of the clamping module.

6. The battery protection chip according to claim 1 or 2, characterized in that, The clamping module includes: at least one first PMOS transistor, wherein... When there is one first PMOS transistor, the gate of the first PMOS transistor is connected to its drain and the power supply terminal of the chip, and the source is connected to the output terminal of the detection module and serves as the output terminal of the clamping module. When there are two or more first PMOS transistors, the gate of each first PMOS transistor is connected to its drain, and the source of the previous first PMOS transistor is connected to the drain of the next first PMOS transistor. The drain of the first first PMOS transistor is connected to the power supply terminal of the chip, and the source of the last first PMOS transistor is connected to the output terminal of the detection module and serves as the output terminal of the clamping module.

7. The battery protection chip according to claim 1 or 2, characterized in that, The identification voltage limiting module includes: a second PMOS transistor, a first resistor, a first NMOS transistor, and a first current source; the gate of the second PMOS transistor is connected to a bias voltage, the source is connected to the output terminal of the clamping module, and the drain is connected to the drain of the first NMOS transistor through the first resistor; the gate of the first NMOS transistor is connected to a reference voltage, and the source is connected to the chip reference terminal through the first current source, and serves as the output terminal of the identification voltage limiting module.

8. The battery protection chip according to claim 2, characterized in that, The bias voltage generation module includes: a third PMOS transistor, a second resistor, and a second current source; the gate of the third PMOS transistor is connected to its drain, the source is connected to the chip power supply terminal, and the drain is connected to the first terminal of the second resistor; the second terminal of the second resistor is connected to the chip reference terminal through the second current source and serves as the output terminal of the bias voltage generation module.

9. The battery protection chip according to claim 1, characterized in that, The battery protection chip further includes: a discharge logic circuit, a charging logic circuit, a discharge drive circuit, and a charging drive circuit, wherein... The discharge logic circuit is connected to the output of the discharge voltage limit detection circuit. When the discharge voltage limit detection circuit outputs a high level, it generates corresponding control logic based on the discharge monitoring result of the battery protection chip. When the discharge voltage limit detection circuit outputs a low level, it generates control logic for discharge abnormality. The discharge drive circuit is connected to the output terminal of the discharge logic circuit and is used to generate a corresponding discharge drive signal according to the control logic output by the discharge logic circuit. The charging logic circuit is connected to the output of the charging voltage limit detection circuit. When the charging voltage limit detection circuit outputs a high level, it generates corresponding control logic based on the charging monitoring result of the battery protection chip. When the charging voltage limit detection circuit outputs a low level, it generates control logic for charging abnormality. The charging drive circuit is connected to the output terminal of the charging logic circuit and is used to generate a corresponding charging drive signal according to the control logic output by the charging logic circuit.

10. The battery protection chip according to claim 9, characterized in that, Both the discharge drive circuit and the charging drive circuit are implemented using an open-drain structure or a push-pull structure.

11. A battery system, characterized in that, The battery system includes: at least two battery packs and at least two battery protection chips as described in any one of claims 1-10, wherein each battery protection chip corresponds to one of the battery packs; wherein the discharge drive signal output by the previous stage battery protection chip is connected to the discharge voltage limit detection circuit of the next stage battery protection chip, the charging drive signal output by the previous stage battery protection chip is connected to the charging voltage limit detection circuit of the next stage battery protection chip, the discharge drive signal output by the last stage battery protection chip controls the discharge MOSFET, and the charging drive signal output by the last stage battery protection chip controls the charging MOSFET.

12. A battery protection method based on the battery protection chip according to any one of claims 1-10, characterized in that, The battery protection method includes: The battery protection chip monitors the battery voltage of each battery in the corresponding battery pack during the charging and discharging process; The next-level battery protection chip detects the previous-level drive signal output by the previous-level battery protection chip, identifies the level of the previous-level drive signal based on the current flow direction of the detected signal, and reduces the high-low level conversion window voltage of the previous-level drive signal. The next-stage battery protection chip generates the next-stage drive signal based on the reduced signal level and its monitoring results.

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