Power supply voltage generation circuit and step-down switching power supply chip

Abstract

This disclosure provides a power supply voltage generation circuit and a buck switching power supply chip. The power supply voltage generation circuit includes a first power supply voltage generation circuit coupled between a first node and an internal power supply terminal. The first power supply voltage generation circuit is configured to, after the buck switching converter enters pulse frequency modulation mode, use the first node to generate the output voltage of the buck switching converter to power the internal circuit of the buck switching converter. This solves the problem of limited quiescent current reduction in buck switching power supply IC products without a feedback output voltage pin.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically, to power supply voltage generation circuits and buck switching power supply chips. Background Technology

[0002] In the design of buck switching power supply integrated circuits (ICs), to reduce the no-load quiescent current (static current), the output voltage can be used instead of the input voltage to power the internal modules of the IC. Due to the characteristics of the buck conversion ratio, the same quiescent current powered by the output voltage will be reduced at the input terminal by the ratio of the input voltage to the output voltage, i.e., Iin = Iout * Duty, where Iin is the input current, Iout is the output current, and Duty is the duty cycle. However, this method of reducing quiescent current requires the IC itself to have a feedback output voltage pin. But with the increasing cost reduction of ICs, most buck switching power supply ICs do not have a feedback output voltage pin to feed back to the internal IC. In this case, the performance of the internal modules of the IC is usually sacrificed to reduce the no-load quiescent current, but the performance sacrifice of the internal modules of the IC is also limited, so the reduction of the no-load quiescent current is also limited. Summary of the Invention

[0003] The embodiments described herein provide a power supply voltage generation circuit and a buck switching power supply chip to address the problem of limited quiescent current reduction in buck switching power supply IC products without a feedback output voltage pin.

[0004] According to a first aspect of this disclosure, a power supply voltage generation circuit is provided. The power supply voltage generation circuit includes a first power supply voltage generation circuit coupled between a first node and an internal power supply terminal. The first power supply voltage generation circuit is configured to, after a switching buck converter enters a pulse frequency modulation mode, use the first node to provide the output voltage of the switching buck converter as internal power supply for the switching buck converter. The first node is the intermediate node of the connection between two power switches in the switching buck converter, and the internal power supply terminal is the internal power supply terminal of the switching buck converter. The first power supply voltage generation circuit includes a first voltage conversion circuit and a first transistor. The first voltage conversion circuit is configured to convert the voltage of the first node into the power supply voltage required by the internal power supply terminal. The first transistor is configured to control the connection and disconnection of the first voltage conversion circuit and the internal power supply terminal according to a first logic control signal, the first logic control signal being a signal indicating whether the switching buck converter enters a pulse frequency modulation mode.

[0005] Optionally, the first power supply voltage generating circuit further includes a current-limiting resistor, wherein one end of the current-limiting resistor is coupled to the first node, and the other end of the current-limiting resistor is coupled to the first voltage conversion circuit.

[0006] Optionally, the first voltage conversion circuit includes a first low-dropout linear regulator, wherein the input terminal of the first low-dropout linear regulator is coupled to the first node, the output terminal of the first low-dropout linear regulator is coupled to the first terminal of the first transistor, the second terminal of the first transistor is coupled to the internal power supply terminal, and the control terminal of the first transistor is coupled to the first logic control signal.

[0007] Optionally, the first voltage conversion circuit includes a high-voltage MOSFET, wherein the first terminal of the high-voltage MOSFET is coupled to the first terminal of the first transistor, the second terminal of the high-voltage MOSFET is coupled to the first node, the second terminal of the first transistor is coupled to the internal power supply terminal, and the control terminal of the first transistor is coupled to the first logic control signal.

[0008] Optionally, the power supply voltage generation circuit further includes a second power supply voltage generation circuit. The second power supply voltage generation circuit is coupled between the input terminal of the switching buck converter and the internal power supply terminal. It is configured to supply power to the internal power supply terminal of the switching buck converter through the input voltage of the switching buck converter after the switching buck converter exits the pulse frequency modulation mode. The second power supply voltage generation circuit includes a second voltage conversion circuit and a second transistor. The second voltage conversion circuit is configured to convert the input voltage of the switching buck converter into the power supply voltage required by the internal power supply terminal. The second transistor is configured to control the connection and disconnection of the second voltage conversion circuit and the internal power supply terminal according to a second logic control signal. The second logic control signal is a signal indicating whether the switching buck converter has exited the pulse frequency modulation mode.

[0009] Optionally, the second voltage conversion circuit includes a second low-dropout linear regulator, wherein the input terminal of the second low-dropout linear regulator is coupled to the input voltage, the output terminal of the second low-dropout linear regulator is coupled to the first terminal of the second transistor, the second terminal of the second transistor is coupled to the internal power supply terminal, and the control terminal of the second transistor is coupled to the second logic control signal.

[0010] Optionally, the power supply voltage generation circuit further includes a power supply switching circuit, wherein the power supply switching circuit is configured to generate the first logic control signal and the second logic control signal according to an indication signal indicating whether the switching buck converter has entered the pulse frequency modulation mode, and to control the internal power supply of the switching buck converter to be supplied by the output voltage or the input voltage.

[0011] Optionally, the power supply switching circuit includes an inverter, wherein the input terminal of the inverter is coupled to the indicator signal and the control electrode of the second transistor, respectively, and the output terminal of the inverter is coupled to the control electrode of the first transistor.

[0012] Optionally, the indicator signal changes from low to high level after the switching buck converter enters the pulse frequency modulation mode for the first time period, and changes from high to low level when the switching buck converter exits the pulse frequency modulation mode.

[0013] Optionally, the first low-dropout linear regulator and the second low-dropout linear regulator have the same constant output voltage.

[0014] Optionally, the second low-dropout linear regulator is in operation during both the period when the switching buck converter enters and exits the pulse frequency modulation mode.

[0015] According to a second aspect of this disclosure, a step-down switching power supply chip is provided, including the power supply voltage generation circuit described in any one of the first aspects.

[0016] In the power supply voltage generation circuit and buck switching power supply chip of the embodiments of this disclosure, a first power supply voltage generation circuit is coupled between a first node and the internal power supply terminal of the buck switching converter. The first power supply voltage generation circuit is configured to, after the buck switching converter enters the pulse frequency modulation mode, use the first node to make the output voltage of the buck switching converter supply power to the internal power supply terminal of the buck switching converter. The first node is the middle node of the connection between the two power switching transistors in the buck switching converter. The first power supply voltage generation circuit includes: a first voltage conversion circuit and a first transistor. The first voltage conversion circuit is configured to convert the voltage of the first node into the power supply voltage required by the internal power supply terminal. The first transistor can control the connection and disconnection of the first voltage conversion circuit and the internal power supply terminal according to the signal of whether the buck switching converter enters the pulse frequency modulation mode. In the embodiments of this application, the first power supply voltage generation circuit utilizes the characteristic that the voltage of the first node is equal to the output voltage after the buck switching converter enters the pulse frequency modulation mode, and realizes that the output voltage supplies power to the internal power supply terminal of the buck switching converter through the first node. This enables buck switching power supply IC products to achieve a significant reduction in the quiescent current according to the ratio of input voltage to output voltage even without a feedback output voltage pin. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0018] Figure 1 This is a schematic block diagram of a power supply voltage generation circuit according to an embodiment of the present disclosure;

[0019] Figure 2 This is an exemplary circuit diagram of a power supply voltage generation circuit according to an embodiment of the present disclosure;

[0020] Figure 3 This is an exemplary circuit diagram of another power supply voltage generation circuit according to an embodiment of the present disclosure;

[0021] Figure 4 This is a schematic block diagram of another power supply voltage generation circuit according to an embodiment of the present disclosure;

[0022] Figure 5 This is a schematic block diagram of another power supply voltage generation circuit according to an embodiment of the present disclosure;

[0023] Figure 6 This is an exemplary circuit diagram of another power supply voltage generation circuit according to an embodiment of the present disclosure;

[0024] Figure 7 This is a waveform diagram corresponding to the power supply voltage generation circuit of this embodiment;

[0025] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0028] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0029] To address the limitation on quiescent current reduction in buck switching power supply ICs without feedback output voltage pins, a power supply voltage generation circuit for use in such ICs is proposed. This disclosure cleverly utilizes the characteristic that the voltage at the intermediate node of the connection between the two power switches equals the output voltage after the buck converter enters pulse frequency modulation mode (PFM mode), thus enabling the output voltage to power the internal circuitry of the buck converter through this intermediate node. The power supply voltage generation circuit of this disclosure will be described in detail below.

[0030] Figure 1 A schematic block diagram of a power supply voltage generation circuit 100 according to an embodiment of the present disclosure is shown. Figure 1 The first power supply voltage generation circuit 110 in the intermediate power supply voltage generation circuit 100 is coupled between the first node SW and the internal power supply terminal AVDD. The first power supply voltage generation circuit 110 is configured to provide the output voltage VOUT of the switching buck converter as internal power supply through the first node SW after the switching buck converter enters pulse frequency modulation mode (PFM mode). The first node SW is the intermediate node of the connection between the two power switches (MD1 and MD2) in the switching buck converter, and the internal power supply terminal AVDD is the internal power supply terminal of the switching buck converter. The first power supply voltage generation circuit 110 includes: a first voltage conversion circuit 111, a first transistor MP1, and...

[0031] The first voltage conversion circuit 111 is coupled to the first transistor MP1 and the first node SW, and is configured to convert the voltage of the first node SW into the power supply voltage required by the internal power supply terminal AVDD. The first transistor MP1 is configured to control the connection and disconnection of the first voltage conversion circuit 111 and the internal power supply terminal AVDD according to a first logic control signal, which is a signal indicating whether the switching buck converter enters pulse frequency modulation mode (PFM mode). Whether the first voltage conversion circuit 111 is connected to the internal power supply terminal AVDD is controlled by the first transistor MP1. When the first transistor MP1 is turned on, the first voltage conversion circuit 111 is connected to the internal power supply terminal AVDD, converting the voltage of the first node SW into the power supply voltage required by the internal power supply terminal AVDD. The conduction state of the first transistor MP1 is controlled by the first logic control signal; when the first logic control signal is low, the first transistor MP1 is turned on. The first logic control signal is determined by whether the switching buck converter enters the pulse frequency modulation mode (PFM mode). When the switching buck converter enters the PFM mode, the first logic control signal is low, and the first transistor MP1 is turned on. Then, the first voltage conversion circuit 111 is connected to the internal power supply terminal AVDD, and the voltage of the first node SW is converted into the power supply voltage required by the internal power supply terminal AVDD. Since the first node SW is the middle node of the connection between the two power switches (MD1 and MD2) in the switching buck converter, when the switching buck converter enters the PFM mode, the two power switches (MD1 and MD2) are in a high-impedance state. The first node SW is connected to the output terminal through the inductor L. Therefore, in the PFM mode, the voltage of the first node SW is equal to the output voltage VOUT. Thus, the voltage of the first node SW is converted into the power supply voltage required by the internal power supply terminal AVDD, that is, the output voltage VOUT is converted into the power supply voltage required by the internal power supply terminal AVDD, thus realizing that the output voltage VOUT is the internal power supply. It should be noted here that the pulse frequency modulation mode (PFM mode) is a deep PFM mode, meaning the load is either very light (i.e., extremely light) or unloaded, and the switching buck converter is in standby mode for an extended period, with both power switches in a high-impedance state. Additionally, the first transistor, MP1, is a P-type MOSFET.

[0032] The power supply voltage generation circuit in this embodiment utilizes the characteristic that the voltage of the first node SW equals the output voltage VOUT after the switching buck converter enters pulse frequency modulation mode (PFM mode). This enables the output voltage VOUT to power the internal circuitry of the switching buck converter via the first node SW. This allows buck switching power supply IC products to achieve a significant reduction in quiescent current relative to the ratio of input voltage VIN to output voltage VOUT, even without a feedback output voltage VOUT pin.

[0033] Furthermore, such as Figure 2 As shown, this disclosure provides an exemplary circuit diagram of a power supply voltage generation circuit 100. Figure 2 The first voltage conversion circuit 111 in the first power supply voltage generation circuit 110 of the intermediate power supply voltage generation circuit 100 includes a first low-dropout linear regulator LDO1. The input terminal of the first low-dropout linear regulator LDO1 is coupled to the first node SW, the output terminal of the first low-dropout linear regulator LDO1 is coupled to the first terminal (drain) of the first transistor MP1, the second terminal (source) of the first transistor MP1 is coupled to the internal power supply terminal AVDD, and the control terminal of the first transistor MP1 is coupled to a first logic control signal. For example... Figure 3 As shown, this disclosure provides an exemplary circuit diagram of another power supply voltage generation circuit 100. Figure 3 The first voltage conversion circuit 111 in the first power supply voltage generation circuit 110 of the power supply voltage generation circuit 100 includes a high-voltage MOSFET (specifically a P-type high-voltage MOSFET). The first terminal of the high-voltage MOSFET is coupled to the first terminal of the first transistor MP1, the second terminal of the high-voltage MOSFET is coupled to the first node SW, the second terminal of the first transistor MP1 is coupled to the internal power supply terminal AVDD, and the control terminal of the first transistor MP1 is coupled to the first logic control signal.

[0034] Figure 2 and Figure 3 Suitable for different application scenarios, specifically, Figure 3 This is suitable when the output voltage VOUT is approximately the same as the power supply voltage required by the internal power supply terminal AVDD. For example, assuming the power supply voltage required by the internal power supply terminal AVDD is 5V and the output voltage VOUT is also 5V, then it can be used. Figure 3 The circuit implementation. And because the internal power supply terminal AVDD is usually a low-voltage design, it can also be said that... Figure 3 Suitable for low-voltage output applications. Compared to... Figure 3 To be honest, Figure 2 It is more suitable for situations where the output voltage VOUT differs significantly from the power supply voltage required by the internal power supply terminal AVDD. In such cases, the output voltage VOUT must be converted.

[0035] Furthermore, such as Figure 4 As shown in the figure, this disclosure also provides a schematic block diagram of another power supply voltage generation circuit 100. Figure 4 The first power supply voltage generating circuit 110 in the power supply voltage generating circuit 100 further includes a current limiting resistor R1, wherein one end of the current limiting resistor R1 is coupled to the first node SW, and the other end of the current limiting resistor R1 is coupled to the first voltage conversion circuit 111.

[0036] The current-limiting resistor R1 is used to limit the amount of current injected into the first voltage conversion circuit 111 during the dead-zone negative voltage injection at the first node SW during normal switching (the operating state of the switching buck converter, such as PWM mode), thus preventing the induction of parasitic NPN effects. When both power transistors (MD1 and MD2) are off, the current in the inductor L flows towards the output, causing a brief negative voltage at the first node SW. Since modern MOSFETs are typically fabricated on P-substrates, requiring the design of numerous N-wells, without the current-limiting resistor R1, if the first node SW is directly connected to the input of the first voltage conversion circuit 111, it's equivalent to the entire N-well of the first voltage conversion circuit 111 being connected to a negative voltage, resulting in a large number of electrons being injected into the substrate. These electrons can induce parasitic NPN effects. If a current-limiting resistor R1 is added, the power supply current of the switching buck converter will drop significantly due to the reduced quiescent current design of PFM mode. If a large current-limiting resistor R1 is added here, the power supply in PFM mode can be guaranteed, while limiting the electrons injected into the substrate during the dead zone of normal switching, thereby suppressing the parasitic NPN effect.

[0037] Furthermore, such as Figure 5 As shown, this disclosure provides a schematic block diagram of another power supply voltage generation circuit 100. Figure 5 In the circuit, the power supply voltage generation circuit 100 further includes a second power supply voltage generation circuit 120. The second power supply voltage generation circuit 120 is coupled between the input terminal VIN of the switching buck converter and the internal power supply terminal AVDD. It is configured to supply power to the internal circuit of the switching buck converter through the input voltage VIN after the switching buck converter exits the pulse frequency modulation mode (PFM mode). The second power supply voltage generation circuit 120 includes: a second voltage conversion circuit 121 and a second transistor MP2.

[0038] The second voltage conversion circuit 121 is configured to convert the input voltage VIN of the switching buck converter into the power supply voltage required by the internal power supply terminal AVDD. The second transistor MP2 is configured to control the connection and disconnection of the second voltage conversion circuit 121 with the internal power supply terminal AVDD according to a second logic control signal, which indicates whether the switching buck converter has exited the pulse frequency modulation mode (PFM mode). The connection of the second voltage conversion circuit 121 with the internal power supply terminal AVDD is controlled by the second transistor MP2. When the second transistor MP2 is turned on, the second voltage conversion circuit 121 is connected to the internal power supply terminal AVDD, converting the input voltage VIN into the power supply voltage required by the internal power supply terminal AVDD and supplying it to AVDD. The conduction state of the second transistor MP2 is controlled by the second logic control signal; when the second logic control signal is low, the second transistor MP2 is turned on. The second logic control signal is determined by whether the buck converter exits PFM mode. When the buck converter exits PFM mode, the second logic control signal is low, which turns on the second transistor MP2. This connects the second voltage conversion circuit 121 to the internal power supply terminal AVDD, converting the input voltage VIN into the required power supply voltage for the internal power supply terminal AVDD, thus enabling the input voltage VIN to power the internal circuit. It should be noted that exiting PFM mode means the buck converter changes from standby to voltage conversion operation, such as entering PWM mode. Furthermore, regardless of whether the buck converter is in or out of PFM mode, the second voltage conversion circuit 121 remains operational to prevent the internal power supply terminal AVDD from losing power during the switching instant (the moment the output voltage VOUT switches to the input voltage VIN for internal power supply). Additionally, it should be noted that the second transistor MP2 is a P-type MOSFET.

[0039] Furthermore, such as Figure 6 As shown, this disclosure provides an exemplary circuit diagram of yet another power supply voltage generation circuit 100. Figure 6The second voltage conversion circuit 121 in the second power supply voltage generation circuit 120 includes a second low-dropout linear regulator LDO2. The input terminal of the second low-dropout linear regulator LDO2 is coupled to the input voltage VIN, and the output terminal of the second low-dropout linear regulator LDO2 is coupled to the first terminal (drain) of the second transistor MP2. The second terminal (source) of the second transistor MP2 is coupled to the internal power supply terminal AVDD, and the control terminal of the second transistor MP2 is coupled to a second logic control signal. It should be noted that the output constant voltages of the first low-dropout linear regulator LDO1 and the second low-dropout linear regulator LDO2 are the same to ensure the stability of the voltage at AVDD.

[0040] Furthermore, such as Figure 6 As shown, the power supply voltage generation circuit 100 further includes a power supply switching circuit 130, wherein the power supply switching circuit 130 is configured to generate a first logic control signal and a second logic control signal based on the indication signal PFM1 indicating whether the switching buck converter has entered pulse frequency modulation mode (PFM mode), and control the internal power supply of the switching buck converter to be supplied by the output voltage VOUT or the input voltage VIN. Specifically, as shown... Figure 6 As shown, the power supply switching circuit 130 includes an inverter 131, wherein the input terminal of the inverter 131 is coupled to the control terminal of the indicator signal PFM1 and the second transistor MP2, respectively, and the output terminal of the inverter 131 is coupled to the control terminal of the first transistor MP1. Figure 6As can be seen, the indicator signal PFM1 indicating whether the switching buck converter has entered PFM mode is the second logic control signal, and the opposite signal of the indicator signal PFM1 is the first logic control signal. It should be noted that the indicator signal PFM1 indicating whether the switching buck converter has entered PFM mode in this embodiment is not strictly consistent with the actual moment when the switching buck converter enters PFM mode. Specifically, in this embodiment, the indicator signal PFM1 indicating whether the switching buck converter has entered PFM mode changes from low to high after the first time period t when the switching buck converter enters PFM mode, and changes from high to low when the switching buck converter exits (actually exits) PFM mode. This inconsistency arises because, upon entering Pulse Frequency Modulation (PFM) mode, the voltage at the first node SW does not immediately equal the output voltage VOUT. It requires a period of high-frequency damped oscillation before stabilizing at the output voltage VOUT. Once stable, the first node SW then powers the internal circuit with the output voltage VOUT. Therefore, this application sets the indicator signal PFM1 for the switching buck converter entering PFM mode to change from low to high after the first time interval t after the switching buck converter enters PFM mode, i.e., after the first node SW obtains a stable output voltage VOUT. Figure 7 The diagram shows the waveforms of the first node SW and the indicator signal PFM1 for the switching buck converter entering pulse frequency modulation mode (PFM mode). SW represents the waveform of the first node SW, and V... SW Here, SW represents the voltage corresponding to node SW; PFM1 is the waveform of the indicator signal PFM1 indicating that the switching buck converter has entered pulse frequency modulation mode (PFM mode) in this embodiment of the present disclosure; PFM is the waveform of the indicator signal indicating that the switching buck converter has actually entered pulse frequency modulation mode (PFM mode). The rising edge difference between PFM1 and PFM is t, while the falling edge is the same.

[0041] Furthermore, in combination Figure 6 The working principle of the power supply voltage generation circuit in this embodiment is explained as follows: When PFM1 is high, MP1 is turned on and MP2 is turned off. The output voltage VOUT is connected to AVDD through LDO1 and MP1, so that the internal power supply is provided through the output voltage VOUT. When PFM1 is low, MP2 is turned on and MP1 is turned off. The input voltage VIN is connected to AVDD through LDO2 and MP2, so that the internal power supply is provided through the input voltage VIN.

[0042] Embodiments of this disclosure also provide a buck switching power supply chip, including the power supply voltage generation circuit 100 of embodiments of this disclosure. This buck switching power supply chip can be a BUCK-type chip.

[0043] In summary, the power supply voltage generation circuit in this embodiment enables the output voltage VOUT to power the internal circuitry of the buck converter via the first node SW. This allows buck switching power supply IC products to achieve a significant reduction in quiescent current relative to the ratio of input voltage VIN to output voltage VOUT, even without a feedback output voltage VOUT pin.

[0044] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0045] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0046] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0047] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A power supply voltage generating circuit, characterized in that, The power supply voltage generation circuit includes a first power supply voltage generation circuit, which is coupled between a first node and an internal power supply terminal. It is configured to, after the switching buck converter enters the pulse frequency modulation mode, use the first node to realize that the output voltage of the switching buck converter is the internal power supply of the switching buck converter. The first node is the middle node of the connection between two power switching transistors in the switching buck converter, and the internal power supply terminal is the internal power supply terminal of the switching buck converter. The first power supply voltage generation circuit includes: a first voltage conversion circuit and a first transistor. The first voltage conversion circuit is configured to convert the voltage of the first node into the power supply voltage required by the internal power supply terminal. The first transistor is configured to control the connection and disconnection of the first voltage conversion circuit and the internal power supply terminal according to a first logic control signal, wherein the first logic control signal is a signal indicating whether the switching buck converter enters a pulse frequency modulation mode.

2. The power supply voltage generating circuit according to claim 1, characterized in that, The first power supply voltage generation circuit further includes: a current-limiting resistor. One end of the current-limiting resistor is coupled to the first node, and the other end of the current-limiting resistor is coupled to the first voltage conversion circuit.

3. The power supply voltage generating circuit according to claim 2, characterized in that, The first voltage conversion circuit includes a first low-dropout linear regulator. The input terminal of the first low-dropout linear regulator is coupled to the first node, the output terminal of the first low-dropout linear regulator is coupled to the first terminal of the first transistor, the second terminal of the first transistor is coupled to the internal power supply terminal, and the control terminal of the first transistor is coupled to the first logic control signal.

4. The power supply voltage generating circuit according to claim 2, characterized in that, The first voltage conversion circuit includes a high-voltage MOSFET. Wherein, the first terminal of the high-voltage MOSFET is coupled to the first terminal of the first transistor, the second terminal of the high-voltage MOSFET is coupled to the first node, the second terminal of the first transistor is coupled to the internal power supply terminal, and the control terminal of the first transistor is coupled to the first logic control signal.

5. The power supply voltage generating circuit according to any one of claims 1 to 4, characterized in that, The power supply voltage generation circuit further includes a second power supply voltage generation circuit, which is coupled between the input terminal of the switching buck converter and the internal power supply terminal. This second power supply voltage generation circuit is configured to supply power to the internal circuit of the switching buck converter using the input voltage of the switching buck converter after the switching buck converter exits the pulse frequency modulation mode. The second power supply voltage generation circuit includes: a second voltage conversion circuit and a second transistor. The second voltage conversion circuit is configured to convert the input voltage of the switching buck converter into the power supply voltage required by the internal power supply terminal. The second transistor is configured to control the connection and disconnection of the second voltage conversion circuit with the internal power supply terminal according to a second logic control signal, the second logic control signal being a signal indicating whether the switching buck converter exits the pulse frequency modulation mode.

6. The power supply voltage generating circuit according to claim 5, characterized in that, The second voltage conversion circuit includes a second low-dropout linear regulator. The input terminal of the second low-dropout linear regulator is coupled to the input voltage, the output terminal of the second low-dropout linear regulator is coupled to the first terminal of the second transistor, the second terminal of the second transistor is coupled to the internal power supply terminal, and the control terminal of the second transistor is coupled to the second logic control signal.

7. The power supply voltage generating circuit according to claim 6, characterized in that, The power supply voltage generation circuit also includes: a power supply switching circuit. The power supply switching circuit is configured to generate the first logic control signal and the second logic control signal according to the indication signal indicating whether the switching buck converter has entered the pulse frequency modulation mode, and to control the internal power supply of the switching buck converter to be supplied by the output voltage or the input voltage.

8. The power supply voltage generating circuit according to claim 7, characterized in that, The power supply switching circuit includes: an inverter, The input terminal of the inverter is coupled to the indicator signal and the control electrode of the second transistor, respectively, and the output terminal of the inverter is coupled to the control electrode of the first transistor.

9. The power supply voltage generating circuit according to claim 8, characterized in that, The indicator signal changes from low to high after the switching buck converter enters the pulse frequency modulation mode for the first time period, and changes from high to low when the switching buck converter exits the pulse frequency modulation mode.

10. A step-down switching power supply chip, characterized in that, Includes a power supply voltage generation circuit according to any one of claims 1-9.

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