A charge pump circuit for h-bridge driving

Abstract

This invention relates to a charge pump circuit for H-bridge driving. A clock signal processing circuit generates a clock signal for a driving circuit, which in turn generates a corresponding driving voltage that acts on a charging / discharging circuit. The charging / discharging circuit is connected to a feedback control circuit, which adjusts the clock signal of the clock signal processing circuit. The feedback control circuit includes a feedback adjustment circuit. When the output voltage VCP of the charge pump circuit rises to the desired design value, the feedback adjustment circuit stops the rise of VCP. When the output voltage VCP falls, the feedback adjustment circuit outputs a signal OUT4_1 to control the clock signal of the clock signal processing circuit, thereby changing the driving voltage output by the driving circuit so that the difference between the power supply voltage VCC and the output voltage VCP of the charge pump circuit is within a preset range. With the addition of the feedback control circuit of this invention, the output voltage accuracy of the charge pump circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of charge pump circuit technology, and in particular to a charge pump circuit for H-bridge driving. Background Technology

[0002] Charge pump circuits are a crucial component of integrated circuits, serving as drive circuits for DC motors, AC motors, and stepper motors. Ideally, the output voltage of a charge pump circuit should vary with the power supply voltage. Since the power switches in an H-bridge are composed of high-power N-channel enhancement-mode MOSFETs, they require a gate voltage higher than the power supply voltage to drive them. Currently, high-voltage H-bridge drive circuits primarily employ narrow-pulse potential shifting technology, using bootstrap capacitors to obtain the gate voltage of the high-side power switches. However, to maintain the voltage across the bootstrap capacitors, the circuit must periodically charge them, resulting in the H-bridge power circuit's switches constantly being in a switching state, making it unsuitable for applications where a single bridge arm needs to be continuously conducting. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to propose a charge pump circuit for H-bridge driving, which has good output voltage accuracy.

[0004] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a charge pump circuit for H-bridge driving, wherein a clock signal is generated by a clock signal processing circuit and fed to a driving circuit, and the driving circuit generates a corresponding driving voltage to act on a charging and discharging circuit to perform charging and discharging operations; the charging and discharging circuit is connected to a feedback control circuit, and the feedback control circuit adjusts the clock signal of the clock signal processing circuit.

[0005] The feedback control circuit includes a feedback adjustment circuit 1. When the output voltage VCP of the charge pump circuit rises to the required design value, the feedback adjustment circuit 1 stops the output voltage VCP from rising. When the output voltage VCP falls, the feedback adjustment circuit 1 outputs a signal OUT4_1 to control the clock signal of the clock signal processing circuit, thereby changing the drive voltage output by the drive circuit so that the difference between the power supply voltage VCC and the output voltage VCP of the charge pump circuit is within a preset range.

[0006] Preferably, in the first feedback adjustment circuit, the output voltage VCP is connected to ground via series resistor R4_1, MOSFET MP4_1, resistor R4_2, resistor R4_3, and resistor R4_4. MOSFET MN4_1 is connected in parallel with resistor R4_4. The power supply voltage VCC is connected to the gate control terminal of MOSFET MP4_1. The output voltage VCP, after passing through resistor R4_1 and MOSFET MP4_1, serves as the positive terminal voltage of comparator one. Voltage VREF serves as the reference voltage for comparator one and comparator two. Voltage VBG serves as the reference voltage for comparator one and comparator two. The output of comparator one is connected to an inverter and then to the gate control terminal of MOSFET MN4_1. The input terminal of comparator two is connected between resistors R4_2 and R4_3. The output terminal of comparator two outputs signal OUT4_1 after passing through a switching circuit.

[0007] Preferably, when the positive terminal voltage of comparator one exceeds the negative terminal voltage, the output of comparator one flips, the MOSFET MN4_1 changes from the on state to the off state, and the adjustment voltage V4 is added to the positive terminal of comparator two to control the ripple of the output voltage VCP. At this time, the output of comparator two flips.

[0008] Preferably, after the power supply voltage VCC and the output voltage VCP are adjusted by the feedback adjustment circuit,

[0009]

[0010] Preferably, the feedback control circuit further includes a second feedback adjustment circuit, which is used to adjust the charging current I of the charging and discharging circuit. CHARGE .

[0011] Preferably, the feedback adjustment circuit two includes a current adjustment circuit, which includes an operational amplifier, MOSFETs MN5_8, MN5_9, and MN5_10, and a resistor R5_6. The positive terminal of the operational amplifier is connected to a preset V+ voltage. The output of the operational amplifier is connected to the gate control terminals of MOSFETs MN5_8 and MN5_9, then connected in series with MOSFET MN5_10 and grounded. The clock signal CK1 of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN5_10.

[0012] The power supply voltage VCC is connected to signal CP1 through resistors R5_3 and R5_5. Signal CP1 is connected to ground through one or more MOSFETs MN5_8 in series. Signal CP1 is connected to ground through MOSFET MN5_9 in series and resistor R5_6. The negative terminal of the op-amp is connected between MOSFET MN5_9 and resistor R5_6.

[0013] In the charging and discharging circuit, a MOS transistor MN6_2 is connected between the pump capacitor C6_1 and the ground terminal. The gate control terminal of the MOS transistor MN6_2 and the gate control terminal of the MOS transistor MN6_3 are connected in series with a Zener diode Z6_1 and then grounded. The signal CP1 is connected in series with the MOS transistor MN6_3 and the resistor R6_1 and then grounded.

[0014] Preferably, the charging current I after adjustment by the second feedback adjustment circuit is... CHARGE The sizes are as follows:

[0015] I CHARGE =I D_MN5_8 +I D_MN5_9 ;

[0016]

[0017]

[0018] V GS5_8 =V GS5_9 +V + ;

[0019] Among them, I D_MN5_8 I is the drain current of MOSFET MN5_8. D_MN5_9 V is the drain current of MOSFET MN5_9; GS5_8 V is the gate-source voltage of MOSFET MN5_8. GS5_9 The gate-source voltage of MOSFET MN5_9, u n C is the carrier mobility. OX V is the gate oxide capacitance per unit area of ​​MOSFET MN5_8 or MOSFET MN5_9, W is the gate width of MOSFET MN5_8 or MOSFET MN5_9, L is the gate length of MOSFET MN5_8 or MOSFET MN5_9, and V is the gate oxide capacitance per unit area of ​​MOSFET MN5_8 or MOSFET MN5_9. TH This is the threshold voltage of MOSFET MN5_8 or MOSFET MN5_9.

[0020] Preferably, the driving circuit includes a first driving circuit, in which the output voltage VCP is grounded after passing through resistor R2_1, MOSFET MN2_1, and MOSFET MN2_2; the clock signal CK3 of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN2_1, and the bias signal Bias is connected to the gate control terminal of MOSFET MN2_2.

[0021] The output voltage VCP is connected to the power supply voltage VCC through MOSFET MP2_1 and MOSFET MN2_3. The output voltage VCP is connected to the power supply voltage VCC through MOSFET MP2_2 and MOSFET MN2_4. The output voltage VCP is connected between MOSFET MP2_2 and MOSFET MN2_4 through resistor R2_2 and output signal OUT2_1.

[0022] The output voltage VCP is connected to resistor R2_1 and MOSFET MN2_1 via Zener diode Z2_1, and then to the gate control terminals of MOSFETs MP2_1 and MOSFET MN2_3. The gate control terminals of MOSFETs MP2_2 and MOSFET MN2_4 are connected to the junction between MOSFETs MP2_1 and MOSFET MN2_3.

[0023] Preferably, the driving circuit includes a second driving circuit. In the second driving circuit, the power supply voltage VCC is grounded after passing through resistor R3_1, MOSFET MN3_1, and MOSFET MN3_3; the power supply voltage VCC is grounded after passing through MOSFET MP3_1, resistor R3_2, MOSFET MN3_5, and MOSFET MN3_4; the power supply voltage VCC is grounded after passing through MOSFET MP3_2 and MOSFET MP3_3; the Zener diode Z3_1 is connected in parallel with MOSFET MP3_1; and the resistor R3_3 and the Zener diode Z3_2 are connected in parallel with MOSFET MP3_2.

[0024] The inverted clock signal CK2_NOT of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN3_1; the power supply voltage VCC is connected to the gate control terminals of MOSFETs MP3_1 and MP3_2 after passing through resistor R3_1; the clock signal CK2 of the clock signal processing circuit is connected to the gate control terminals of MOSFETs MN3_5 and MN3_2; the gate control terminal of MOSFET MP3_3 is grounded after passing through MOSFET MN3_2; the bias signal Bias is connected to the gate control terminals of MOSFETs MN3_3 and MN3_4.

[0025] The contact between resistor R3_2 and MOSFET MN3_5 is connected between MOSFETs MP3_2 and MP3_3 and outputs signal OUT3_1.

[0026] Preferably, in the charging and discharging circuit, the power supply voltage VCC is connected to the output voltage VCP through MOSFETs MN6_1 and MP6_2, and the power supply voltage VCC is grounded after passing through MOSFETs MP6_1 and MN6_2. One end of the pump capacitor C6_1 is connected between MOSFETs MN6_1 and MP6_2, and the other end of the pump capacitor C6_1 is connected between MOSFETs MP6_1 and MN6_2. The capacitor C6_2 is connected between the power supply voltage VCC and the output voltage VCP.

[0027] The beneficial effects of this invention are as follows: With the addition of the feedback control circuit, if the power supply voltage VCC is 40V, the output voltage VCP is approximately 5V higher than the power supply voltage VCC at different time stages, with a difference accuracy within 0.1V, indicating good output voltage accuracy of the charge pump circuit. With the addition of the first feedback adjustment circuit, the output voltage VCP is approximately 5V higher than the power supply voltage VCC at different time stages, with a difference accuracy within 0.1V, and the fluctuation of the output voltage VCP at different time points is small, allowing for more stable control of the output voltage VCP ripple. The addition of the second feedback adjustment circuit allows for adjustment of the charging current I of the charging and discharging circuit. CHARGE This causes the charging current I of the charging and discharging circuit to... CHARGE The size is adjustable. Attached Figure Description

[0028] Figure 1 This is a schematic block diagram of the charge pump circuit of the present invention;

[0029] Figure 2 This is a circuit diagram of the drive circuit of the charge pump circuit of the present invention.

[0030] Figure 3 This is a circuit diagram of the second drive circuit of the charge pump circuit of the present invention;

[0031] Figure 4 This is a circuit diagram of the feedback adjustment circuit one of the charge pump circuit of the present invention;

[0032] Figure 5 This is a circuit diagram of the feedback adjustment circuit two of the charge pump circuit of the present invention;

[0033] Figure 6 This is a circuit diagram of the charging and discharging circuit of the charge pump circuit of the present invention;

[0034] Figure 7 This is a simulation waveform diagram of the output voltage VCP and the power supply voltage VCC of the charge pump circuit of the present invention;

[0035] Figure 8 This is a simulation waveform diagram of the output voltage VCP of the charge pump circuit of the present invention versus the clock signal; Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and preferred embodiments. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0037] like Figure 1As shown, a charge pump circuit for H-bridge driving generates a clock signal to a drive circuit via a clock signal processing circuit. The drive circuit generates a corresponding drive voltage to act on a charge / discharge circuit, enabling the charge / discharge circuit to perform charge / discharge operations. The charge / discharge circuit is connected to a feedback control circuit, which adjusts the clock signal of the clock signal processing circuit. The feedback control circuit includes a feedback adjustment circuit. When the output voltage VCP of the charge pump circuit rises to the required design value, the feedback adjustment circuit stops the output voltage VCP from rising. When the output voltage VCP falls, the feedback adjustment circuit outputs a signal OUT4_1 to control the clock signal of the clock signal processing circuit, thereby changing the drive voltage output by the drive circuit so that the difference between the power supply voltage VCC and the output voltage VCP of the charge pump circuit is within a preset range.

[0038] After incorporating the feedback control circuit of this invention, the simulation waveforms of the output voltage VCP and the power supply voltage VCC of the charge pump circuit are shown below. Figure 7 As shown, the power supply voltage VCC is 40.0V, and the output voltage VC is about 5V higher than the power supply voltage VCC at different time stages, with the difference accuracy within 0.5V.

[0039] Specifically, in one embodiment of the present invention, such as Figure 2 As shown, the driving circuit includes a first driving circuit. In the first driving circuit, the output voltage VCP is grounded after passing through resistor R2_1, MOSFET MN2_1, and MOSFET MN2_2. The clock signal CK3 of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN2_1, and the bias signal Bias is connected to the gate control terminal of MOSFET MN2_2.

[0040] The output voltage VCP is connected to the power supply voltage VCC through MOSFET MP2_1 and MOSFET MN2_3. The output voltage VCP is connected to the power supply voltage VCC through MOSFET MP2_2 and MOSFET MN2_4. The output voltage VCP is connected between MOSFET MP2_2 and MOSFET MN2_4 through resistor R2_2 and output signal OUT2_1.

[0041] The output voltage VCP is connected to resistor R2_1 and MOSFET MN2_1 via Zener diode Z2_1, and then to the gate control terminals of MOSFETs MP2_1 and MOSFET MN2_3. The gate control terminals of MOSFETs MP2_2 and MOSFET MN2_4 are connected to the junction between MOSFETs MP2_1 and MOSFET MN2_3.

[0042] like Figure 6As shown, in the charging and discharging circuit, the power supply voltage VCC is connected to the output voltage VCP through MOSFETs MN6_1 and MP6_2. The power supply voltage VCC is grounded after passing through MOSFETs MP6_1 and MN6_2. One end of the pump capacitor C6_1 is connected between MOSFETs MN6_1 and MP6_2, and the other end of the pump capacitor C6_1 is connected between MOSFETs MP6_1 and MN6_2. The capacitor C6_2 is connected between the power supply voltage VCC and the output voltage VCP.

[0043] The source voltage of MOSFET MN6_1 in the charging circuit is the power supply voltage VCC. Therefore, the gate voltage of MOSFET MN6_1 must be higher than the power supply voltage VCC to allow MOSFET MN6_1 to leave the cutoff region. Thus, the high-level output of this driver circuit is designed to be the output voltage VCP, and the low-level output is designed to be the power supply voltage VCC. When the clock signal CK3 is low, MOSFET MN2_1 is off, and the potential at point X is the output voltage VCP. Therefore, the output of driver circuit one is the output voltage VCP. When the clock signal CK3 is high, MOSFET MN2_1 is on. The current flowing through resistor R2_1 is determined by MOSFET MN2_2. Considering that the output voltage VCP must be 5V higher than the power supply voltage VCC, the resistor R2_1 and bias current I are designed accordingly. X , making I X ×R2_1=5V, at this time the voltage V at point X is... X =VCP-I X Since ×R2_1≈VCC, the output of the drive circuit is the power supply voltage VCC.

[0044] Specifically, in one embodiment of the present invention, such as Figure 3 As shown, the driving circuit includes a second driving circuit. In the second driving circuit, the power supply voltage VCC is grounded after passing through resistor R3_1, MOSFET MN3_1, and MOSFET MN3_3; the power supply voltage VCC is grounded after passing through MOSFET MP3_1, resistor R3_2, MOSFET MN3_5, and MOSFET MN3_4; the power supply voltage VCC is grounded after passing through MOSFET MP3_2 and MOSFET MP3_3; the Zener diode Z3_1 is connected in parallel with MOSFET MP3_1; and the resistor R3_3 and the Zener diode Z3_2 are connected in parallel with MOSFET MP3_2.

[0045] The inverted signal CK2_NOT of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN3_1; the power supply voltage VCC is connected to the gate control terminals of MOSFETs MP3_1 and MP3_2 after passing through resistor R3_1; the clock signal CK2 of the clock signal processing circuit is connected to the gate control terminals of MOSFETs MN3_5 and MN3_2; the gate control terminal of MOSFET MP3_3 is grounded after passing through MOSFET MN3_2; the bias signal Bias is connected to the gate control terminals of MOSFETs MN3_3 and MN3_4; the junction between resistor R3_2 and MOSFET MN3_5 is connected between MOSFETs MP3_2 and MP3_3 and outputs the signal OUT3_1.

[0046] because Figure 6 In the charging / discharging circuit shown, the source voltage of MOSFET MP6_1 is the power supply voltage VCC. Therefore, the gate voltage of MOSFET MP6_1 must be lower than the power supply voltage VCC for MOSFET MP6_1 to leave the cutoff region. When the inverting signal CK2_NOT is low, signal CK2 is high. MOSFET MN3_1 is off, while MOSFETs MN3_2 and MN3_5 are on. Therefore, the gate voltages of MOSFETs MP3_1 and MP3_2 are the power supply voltage VCC, so MOSFETs MP3_1 and MP3_2 are off. The gate voltage of MOSFET MP3_3 is approximately low, so MOSFET MP3_3 is on. Due to the presence of Zener diode Z3_2, the output of the second driving circuit is the output voltage VCP-5. V (5V is the regulated voltage of Zener diode Z3_2); When the inverting signal CK2_NOT is high, signal CK2 is low, then MOSFET MN3_1 is turned on, and MOSFETs MN3_2 and MN3_5 are turned off. Then the gate voltages of MOSFETs MP3_1 and MP3_2 are approximately low, and MOSFETs MP3_1 and MP3_2 are in the on state. The gate voltage of MOSFET MP3_3 is approximately high, and MOSFET MP3_3 is turned off. Then the output of the second drive circuit is the power supply voltage VCC.

[0047] Specifically, in one embodiment of the present invention, such as Figure 4As shown, in the feedback adjustment circuit one, the output voltage VCP is connected to ground via series resistor R4_1, MOSFET MP4_1, resistor R4_2, resistor R4_3, and resistor R4_4. MOSFET MN4_1 is connected in parallel with resistor R4_4. The power supply voltage VCC is connected to the gate control terminal of MOSFET MP4_1. The output voltage VCP is used as the positive terminal voltage of comparator 401 after passing through resistor R4_1 and MOSFET MP4_1. Voltage VREF is used as the reference voltage for comparator 401 and comparator 402. Voltage VBG is used as the reference voltage for comparator 401 and comparator 402. The output of comparator 401 is connected to the gate control terminal of MOSFET MN4_1 after being connected to an inverter. The input terminal of comparator 402 is connected between resistor R4_2 and resistor R4_3. The output terminal of comparator 402 outputs signal OUT4_1 after passing through switch circuit 403.

[0048] The first part of the feedback adjustment circuit is used to detect the output voltage VCP. When the output voltage VCP rises to the design value, it stops rising. During the discharge phase, the output voltage VCP rises slowly, so the positive terminal voltage of comparator 401 rises. When the positive terminal voltage exceeds the negative terminal voltage, the output of comparator 401 flips, changing from low to high level. This flips the output of MOSFET MN4_1 from the on state to the off state via an inverter. An adjustment voltage V4 = I is added to the positive input of comparator 402, which consists of MP4_9 to MP4_11, MN4_6, and MN4_7. 4_4 ×R4_4 is used to control the ripple of the output voltage VCP, I 4_4 The current flowing through resistor R4_4 will cause the output of comparator 402 to flip accordingly. Subsequently, when the output voltage VCP decreases, only the output of comparator 402 will flip, feeding back the signal OUT4_1 from the first feedback adjustment circuit to control either signal CK2 or signal CK3. Therefore, the difference between the output voltage VCP and the power supply voltage VCC is determined by the ratio of resistors R4_1 to R4_2 to R4_4 and the accuracy of the reference voltage VBG, as shown in the following formula:

[0049]

[0050] The clock signal processing circuit outputs three clock signals, including clock signal CK1, clock signal CK2, and clock signal CK3. After adding the feedback adjustment circuit of this invention, the waveform of the output voltage VCP of the charge pump circuit versus the clock signals in simulation one is shown below. Figure 8As shown, the output voltage VCP is about 5V higher than the power supply voltage VCC at different time stages, and the difference is within 0.1V. Furthermore, the fluctuation of the output voltage VCP at different time points is small, only changing from 45.3309V to 45.3582V. Therefore, the ripple of the output voltage VCP can be controlled relatively smoothly.

[0051] Specifically, in one embodiment of the present invention, such as Figure 5 As shown, the feedback control circuit further includes a second feedback adjustment circuit, which is used to adjust the charging current I of the charging and discharging circuit. CHARGE .

[0052] Specifically, in one embodiment of the present invention, such as Figure 5 As shown, the feedback adjustment circuit 2 includes a current adjustment circuit 501, which includes an operational amplifier, MOSFETs MN5_8, MN5_9, and MN5_10, and a resistor R5_6. The positive terminal of the operational amplifier is connected to a preset V+ voltage. The output of the operational amplifier is connected to the gate control terminals of MOSFETs MN5_8 and MN5_9, then connected in series with MOSFET MN5_10 and grounded. The clock signal CK1 of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN5_10.

[0053] The power supply voltage VCC is connected to signal CP1 through resistors R5_3 and R5_5. Signal CP1 is connected to ground in series with MOSFET MN5_8. Signal CP1 is connected to ground in series with MOSFET MN5_9 and resistor R5_6. The negative terminal of the op-amp is connected between MOSFET MN5_9 and resistor R5_6.

[0054] In the charging and discharging circuit, a MOS transistor MN6_2 is connected between the pump capacitor C6_1 and the ground terminal. The gate control terminal of the MOS transistor MN6_2 and the gate control terminal of the MOS transistor MN6_3 are connected in series with a Zener diode Z6_1 and then grounded. The signal CP1 is connected in series with the MOS transistor MN6_3 and the resistor R6_1 and then grounded.

[0055] The second feedback adjustment circuit is used to control the charging current I during the charging phase. CHARGEThe charge on pump capacitor C6_1. In a traditional charge pump structure, at the beginning of the charging phase, the power supply voltage VCC provides a large charging current to pump capacitor C6_1. As the charge on pump capacitor C6_1 increases, the charging current gradually decreases. This significant change in charging current affects the operating state of MOSFETs MN6_1 and MN6_2, resulting in a large change in on-resistance. This invention adds a MOSFET MN6_3 to the charging / discharging circuit to sample the current flowing through MN6_2. The operational amplifier in the current adjustment circuit 501 stably controls the gate voltages of MOSFETs MN62 and MN63, thereby controlling the charging current I. CHARGE The purpose. For example... Figure 5 In the current adjustment circuit, the positive terminal V+ of the operational amplifier is designed to be obtained by voltage division of the reference voltage, with a designed value of 400mV. Based on the principle of virtual short at the input of the operational amplifier, we can obtain: V + ≈V - =400mV. This voltage determines the current flowing through resistor R5_6, and thus the current flowing through MOSFET MN5_9. Therefore, it can be seen that the charging current I can be changed by changing MOSFETs MN5_8 and MN5_9. CHARGE Size.

[0056] The charging current I after adjustment by the feedback adjustment circuit II CHARGE The sizes are as follows:

[0057] I CHARGE =I D_MN5_8 +I D_MN5_9 ;

[0058]

[0059]

[0060] V GS5_8 =V GS5_9 +V + ;

[0061] Among them, I D_MN5_8 I is the drain current of MOSFET MN5_8. D_MN5_9 V is the drain current of MOSFET MN5_9; GS5_8 V is the gate-source voltage of MOSFET MN5_8. GS5_9 The gate-source voltage of MOSFET MN5_9, u n C is the carrier mobility. OXV is the gate oxide capacitance per unit area of ​​MOSFET MN5_8 or MOSFET MN5_9, W is the gate width of MOSFET MN5_8 or MOSFET MN5_9, L is the gate length of MOSFET MN5_8 or MOSFET MN5_9, and V is the gate oxide capacitance per unit area of ​​MOSFET MN5_8 or MOSFET MN5_9. TH This is the threshold voltage of MOSFET MN5_8 or MOSFET MN5_9.

[0062] The above description is only a specific embodiment of the present invention. Various examples and illustrations do not constitute a limitation on the substantive content of the present invention. Those skilled in the art can make modifications or variations to the above-described specific embodiments after reading the specification without departing from the substance and scope of the invention.

Claims

1. A charge pump circuit for H-bridge driving, wherein a clock signal is generated by a clock signal processing circuit and fed to a driving circuit, and the driving circuit generates a corresponding driving voltage to act on a charging and discharging circuit to perform charging and discharging operations, characterized in that: The charging and discharging circuit is connected to a feedback control circuit, which adjusts the clock signal of the clock signal processing circuit. The feedback control circuit includes a feedback adjustment circuit 1. When the output voltage VCP of the charge pump circuit rises to the required design value, the feedback adjustment circuit 1 stops the output voltage VCP from rising. When the output voltage VCP falls, the feedback adjustment circuit 1 outputs a signal OUT4_1 to control the clock signal of the clock signal processing circuit, thereby changing the drive voltage output by the drive circuit so that the difference between the power supply voltage VCC and the output voltage VCP of the charge pump circuit is within a preset range. In the feedback adjustment circuit one, the output voltage VCP is connected to ground via series resistor R4_1, MOSFET MP4_1, resistor R4_2, resistor R4_3, and resistor R4_4. MOSFET MN4_1 is connected in parallel with resistor R4_4. The power supply voltage VCC is connected to the gate control terminal of MOSFET MP4_1. The output voltage VCP is used as the positive terminal voltage of comparator one (401) after passing through resistor R4_1 and MOSFET MP4_1. Voltage VREF is used as the reference voltage of comparator one (401) and comparator two (402). Voltage VBG is used as the reference voltage of comparator one (401) and comparator two (402). The output of comparator one (401) is connected to the gate control terminal of MOSFET MN4_1 after being connected to an inverter. The input terminal of comparator two (402) is connected between resistor R4_2 and resistor R4_3. The output terminal of comparator two (402) outputs signal OUT4_1 after passing through the switching circuit (403). After the power supply voltage VCC and the output voltage VCP are adjusted by the aforementioned feedback adjustment circuit, VCP-VCC= 。 2. The charge pump circuit for H-bridge driving according to claim 1, characterized in that: When the positive terminal voltage of comparator 1 (401) exceeds the negative terminal voltage, the output of comparator 1 (401) flips, and MOS transistor MN4_1 changes from the on state to the off state. An adjustment voltage V4 is added to the positive terminal of comparator 2 (402) to control the ripple of the output voltage VCP. At this time, the output of comparator 2 (402) flips.

3. The charge pump circuit for H-bridge driving according to claim 1, characterized in that: The feedback control circuit further includes a second feedback adjustment circuit, which is used to adjust the charging current of the charging and discharging circuit. .

4. The charge pump circuit for H-bridge driving according to claim 3, characterized in that: The second feedback adjustment circuit includes a current adjustment circuit (501), which includes an operational amplifier, MOSFETs MN5_8, MN5_9, and MN5_10, and a resistor R5_6. The positive terminal of the operational amplifier is connected to a preset V+ voltage. The output of the operational amplifier is connected to the gate control terminals of MOSFETs MN5_8 and MN5_9, then connected in series with MOSFET MN5_10 and grounded. The clock signal CK1 of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN5_10. The power supply voltage VCC is connected to signal CP1 through resistors R5_3 and R5_5. Signal CP1 is connected to ground through one or more MOSFETs MN5_8 in series. Signal CP1 is connected to ground through MOSFET MN5_9 in series and resistor R5_6. The negative terminal of the op-amp is connected between MOSFET MN5_9 and resistor R5_6. In the charging and discharging circuit, a MOS transistor MN6_2 is connected between the pump capacitor C6_1 and the ground terminal. The gate control terminal of the MOS transistor MN6_2 and the gate control terminal of the MOS transistor MN6_3 are connected in series with a Zener diode Z6_1 and then grounded. The signal CP1 is connected in series with the MOS transistor MN6_3 and the resistor R6_1 and then grounded.

5. The charge pump circuit for H-bridge driving according to claim 4, characterized in that: The charging current adjusted by the second feedback adjustment circuit The sizes are as follows: ； ； ； ； in, This represents the drain current of the MOSFET MN5_8. This is the drain current of MOSFET MN5_9; This refers to the gate-source voltage of the MOSFET MN5_8. This refers to the gate-source voltage of MOSFET MN5_9. The mobility of charge carriers, Let W be the gate oxide capacitance per unit area of ​​MOSFET MN5_8 or MOSFET MN5_9, W be the gate width of MOSFET MN5_8 or MOSFET MN5_9, and L be the gate length of MOSFET MN5_8 or MOSFET MN5_9. This is the threshold voltage of MOSFET MN5_8 or MOSFET MN5_9.

6. The charge pump circuit for H-bridge driving according to claim 1, characterized in that: The driving circuit includes a first driving circuit. In the first driving circuit, the output voltage VCP is grounded after passing through resistor R2_1, MOSFET MN2_1, and MOSFET MN2_2. The clock signal CK3 of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN2_1, and the bias signal Bias is connected to the gate control terminal of MOSFET MN2_2. The output voltage VCP is connected to the power supply voltage VCC through MOSFET MP2_1 and MOSFET MN2_3. The output voltage VCP is connected to the power supply voltage VCC through MOSFET MP2_2 and MOSFET MN2_4. The output voltage VCP is connected between MOSFET MP2_2 and MOSFET MN2_4 through resistor R2_2 and output signal OUT2_1. The output voltage VCP is connected to resistor R2_1 and MOSFET MN2_1 via Zener diode Z2_1, and then to the gate control terminals of MOSFETs MP2_1 and MOSFET MN2_3. The gate control terminals of MOSFETs MP2_2 and MOSFET MN2_4 are connected to the junction between MOSFETs MP2_1 and MOSFET MN2_3.

7. The charge pump circuit for H-bridge driving according to claim 1 or 5, characterized in that: The driving circuit includes a second driving circuit. In the second driving circuit, the power supply voltage VCC is grounded after passing through resistor R3_1, MOSFET MN3_1, and MOSFET MN3_3; the power supply voltage VCC is grounded after passing through MOSFET MP3_1, resistor R3_2, MOSFET MN3_5, and MOSFET MN3_4; the power supply voltage VCC is grounded after passing through MOSFET MP3_2 and MOSFET MP3_3; the Zener diode Z3_1 is connected in parallel with MOSFET MP3_1; and the resistor R3_3 and the Zener diode Z3_2 are connected in parallel with MOSFET MP3_2. The inverted clock signal CK2_NOT of the clock signal processing circuit is connected to the gate control terminal of MOSFET MN3_1; the power supply voltage VCC is connected to the gate control terminals of MOSFETs MP3_1 and MP3_2 after passing through resistor R3_1; the clock signal CK2 of the clock signal processing circuit is connected to the gate control terminals of MOSFETs MN3_5 and MN3_2; the gate control terminal of MOSFET MP3_3 is grounded after passing through MOSFET MN3_2; the bias signal Bias is connected to the gate control terminals of MOSFETs MN3_3 and MN3_4. The contact between resistor R3_2 and MOSFET MN3_5 is connected between MOSFETs MP3_2 and MP3_3 and outputs signal OUT3_1.

8. The charge pump circuit for H-bridge driving according to claim 1, characterized in that: In the charging and discharging circuit, the power supply voltage VCC is connected to the output voltage VCP through MOSFETs MN6_1 and MP6_2. The power supply voltage VCC is grounded after passing through MOSFETs MP6_1 and MN6_2. One end of the pump capacitor C6_1 is connected between MOSFETs MN6_1 and MP6_2, and the other end of the pump capacitor C6_1 is connected between MOSFETs MP6_1 and MN6_2. The capacitor C6_2 is connected between the power supply voltage VCC and the output voltage VCP.

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