Sensing device

Abstract

A sensing device is provided for operating in a reset period, an exposure period and a read period. The sensing device includes a first transistor, a second transistor, a sensing component and a third transistor. The first transistor includes a control terminal and a first terminal. The second transistor is coupled to the first transistor to set a voltage of the control terminal during the reset period. The sensing component is coupled to the first transistor to generate a sensing signal to change the voltage of the control terminal during the exposure period. The third transistor is coupled to the first transistor and has an output terminal to output an output signal corresponding to the sensing signal from the output terminal during the read period. The first transistor is an N-type transistor and the third transistor is a P-type transistor.

Description

Technical Field

[0001] This disclosure relates to a sensing device, and more particularly to a sensing device for improving image sensing speed. Background Technology

[0002] Image sensors primarily use active pixel sensors (APS) as the communication interface between the light-sensing component and the back-end readout system. The pixel circuit typically uses a source follower to transmit the signal changes generated by the light-sensing component due to illumination to the back-end readout system. If the area of ​​the sensing component increases, the operation time of the image sensor will also increase. Therefore, it is necessary to optimize the sensing speed of the image sensor. Summary of the Invention

[0003] In view of this, the present invention provides a sensing device for operation during a reset period, an exposure period, and a readout period. The sensing device includes a first transistor, a second transistor, a sensing component, and a third transistor. The first transistor includes a control terminal and a first terminal. The second transistor is coupled to the first transistor for setting the voltage of the control terminal during the reset period. The sensing component is coupled to the first transistor for changing the voltage of the control terminal during the exposure period. The third transistor is coupled to the first transistor and has an output terminal for outputting a sensing signal from the first terminal during the readout period. The first transistor is an N-type transistor, and the third transistor is a P-type transistor.

[0004] The present invention further proposes a sensing device, comprising a sensing circuit, a readout line, a current mirror, a processor, and an output transistor. The readout line is coupled to the sensing circuit. The current mirror is coupled to the readout line. The output transistor is coupled between the readout line and the processor, and the output transistor includes a first terminal, a second terminal, and a control terminal. The control terminal is coupled to the readout line, the first terminal is coupled to a reference voltage, and the second terminal is coupled to the processor. Attached Figure Description

[0005] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0006] Figure 1 This is a block diagram of a sensing device according to an embodiment of the present disclosure;

[0007] Figure 2 This is a circuit diagram of a sensing unit according to an embodiment of the present disclosure;

[0008] Figure 3 This is a circuit diagram of a switching assembly according to an embodiment of the present disclosure;

[0009] Figure 4 This is a circuit diagram of a switching assembly according to another embodiment of this disclosure;

[0010] Figure 5 This is a schematic diagram of a connection structure according to an embodiment of the present disclosure;

[0011] Figure 6 This is a circuit diagram of a sensing device according to an embodiment of the present disclosure;

[0012] Figure 7 This is a block diagram of a sensing device according to an embodiment of the present disclosure;

[0013] Figure 8 This is a circuit diagram of a readout circuit according to an embodiment of the present disclosure; and

[0014] Figure 9 This is a circuit diagram of a sensing device according to another embodiment of the present disclosure.

[0015] The annotations in the attached figures are explained as follows:

[0016] 100, 600, 700, 900: Sensing devices

[0017] 110_00,110_10,110_N0,110_01,110_11,110_N1,110_0M,110_1M,110_NM,200: Sensing Unit

[0018] 120: Multitasking

[0019] 130,500: Connection structure

[0020] 140: Processor

[0021] 300, 400: Switching components

[0022] 510: Route 1

[0023] 520: Second Route

[0024] 710, 800, 910: Reading circuit

[0025] DATA: Read line

[0026] DATA0: First read line

[0027] DATA1: Second read line

[0028] DATAN: The (N+1)th read line

[0029] T1: First transistor

[0030] T2: Second transistor

[0031] T3: Third transistor

[0032] T4: Fourth transistor

[0033] T5: Fifth transistor

[0034] T6: Sixth transistor

[0035] T7: Seventh Transistor

[0036] T8: Eighth transistor

[0037] UD: Sensing Component

[0038] NA: Positive extreme

[0039] NC: Negative Extreme

[0040] VCC1: First supply voltage

[0041] VCC2: Second supply voltage

[0042] VCC3: Third supply voltage

[0043] VCC4: Fourth supply voltage

[0044] VCC5: Fifth supply voltage

[0045] VB: Bias voltage

[0046] RST: Reset signal

[0047] SW: Switch signal

[0048] SD: Sensing signal

[0049] SEL: Selection signal

[0050] SELB: Inverting Selection Signal

[0051] SOUT: Output signal

[0052] INV: Inverter

[0053] RD: Read data

[0054] RD0: First data read

[0055] RD1: Second data read

[0056] RDN: Reading data for the (N+1)th time

[0057] TM: Mapped Transistor

[0058] TM0: First mapped transistor

[0059] TM1: Second Mapped Transistor

[0060] TMN: The (N+1)th mapped transistor

[0061] TR: Output transistor

[0062] TR0: First output transistor

[0063] TR1: Second output transistor

[0064] TRN: The (N+1)th output transistor

[0065] IR: Reference current Detailed Implementation

[0066] The following description is an embodiment of this disclosure. Its purpose is to illustrate the general principles of this disclosure and should not be construed as a limitation thereof. The scope of this disclosure is defined by the claims.

[0067] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, constituent parts, regions, layers, and / or portions, these components, constituent parts, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different components, constituent parts, regions, layers, and / or portions. Therefore, a first component, constituent part, region, layer, and / or portion discussed below may be referred to as a second component, constituent part, region, layer, and / or portion without departing from the teachings of some embodiments of this disclosure.

[0068] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this disclosure. The specific component examples and arrangements described below are merely for briefly illustrating the spirit of this disclosure and are not intended to limit its scope. Furthermore, the same component symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is solely to provide a simplified and clear explanation and is not intended to limit the relationship between the various embodiments and / or configurations discussed below.

[0069] In some embodiments of this disclosure, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include situations where both structures are movable or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means.

[0070] The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components on two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, the endpoints of the components on two circuits are connected by a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components, but are not limited thereto.

[0071] Figure 1 This is a block diagram of a sensing device according to an embodiment of this disclosure. Figure 1 As shown, the sensing device 100 includes multiple sensing units 110_00, 110_10, ..., 110_N0, 110_01, 110_11, ..., 110_N1, 110_0M, 110_1M, ..., 110_NM, a multiplexer 120, a connection structure 130, and a processor 140. Sensing units 110_00, 110_01, ..., 110_0M share a first read line DATA0, sensing units 110_10, 110_11, ..., 110_1M share a second read line DATA1, and sensing units 110_N0, 110_N1, ..., 110_NM share a (N+1)th read line DATAN.

[0072] The multitasking unit 120 includes (N+1) switching components. Figure 1 (Not shown), where (N+1) switching components are used to select the signal transmitted by one of the first read line DATA0, the second read line DATA1, ..., the (N+1)th read line DATAN as the output signal SOUT, and provide the output signal SOUT to the processor 140 via the connection structure 130, so that the processor 140 determines the image data detected by the multiple sensing units based on the data of one of the first read line DATA0, the second read line DATA1, ..., the (N+1)th read line DATAN. ​​The detailed operation of the sensing device 100 will be described in detail below.

[0073] According to one embodiment of the present invention, the sensing device 100 is located in an electronic device. The electronic device may include a display device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-emissive display device or a self-emissive display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device. The sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited thereto. Electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes (LEDs) or photodiodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs (QLEDs or QD-LEDs), but are not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any of the aforementioned arrangements and combinations, but is not limited thereto. The following description will use display devices as examples of electronic devices or splicing devices to illustrate the content of this disclosure, but this disclosure is not limited thereto.

[0074] Figure 2 This is a circuit diagram of a sensing unit according to an embodiment of this disclosure. Figure 2 As shown, the sensing unit 200 includes a first transistor T1, a second transistor T2, a sensing component UD, and a third transistor T3, but is not limited thereto. The sensing unit 200 corresponds to... Figure 1 Any one of the multiple sensing units 110_00, 110_10, ..., 110_N0, 110_01, 110_11, ..., 110_N1, 110_0M, 110_1M, ..., 110_NM.

[0075] The first transistor T1 includes a control terminal, a first terminal, and a second terminal, wherein the first terminal of the first transistor T1 receives a first supply voltage VCC1. The second transistor T2 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor T2 receives a reset signal RST, the first terminal of the second transistor T2 receives a second supply voltage VCC2, and the second terminal of the second transistor T2 is coupled to the control terminal of the first transistor T1.

[0076] The third transistor T3 includes a control terminal, a first terminal, and an output terminal. The control terminal of the third transistor T3 receives a switching signal SW. The first terminal of the third transistor T3 is coupled to the second terminal of the first transistor T1. The output terminal of the third transistor T3 is coupled to the read line DATA, where the read line DATA corresponds to… Figure 1 Any one of the first read line DATA0, the second read line DATA1, ..., the (N+1)th read line DATAN.

[0077] The sensing component UD includes an anode terminal NA and a cathode terminal NC, wherein the anode terminal NA receives a third supply voltage VCC3, and the cathode terminal NC is coupled to the control terminal of the first transistor T1 and the second terminal of the second transistor T2. It should be noted that, in this disclosure, the sensing component UD can be a photodiode or any other component capable of receiving optical signals and generating electrical signals.

[0078] According to one embodiment of this disclosure, the first transistor T1 is an N-type transistor, and the second transistor T2 or the third transistor T3 is a P-type transistor. The fact that the second transistor T2 is a P-type transistor helps reduce the leakage current flowing through it. Furthermore, the configuration of the third transistor T3 being a P-type transistor and the first transistor T1 being an N-type transistor allows the third transistor T3 to have a relatively low on-resistance under a specific bias voltage, enabling the output signal to quickly reach a steady state and reducing the influence of trace resistance on the transmission of the output signal.

[0079] According to one embodiment of the present disclosure, when the sensing unit 200 is operating during the reset period, the reset signal RST is at a low voltage level and turns on the second transistor T2, so that the second transistor T2 provides the second supply voltage VCC2 to the control terminal of the first transistor T1 and the second terminal of the second transistor T2, so as to achieve the purpose of setting the voltage of the control terminal of the first transistor T1.

[0080] According to one embodiment of this disclosure, when the sensing unit 200 operates during exposure, the reset signal RST changes from a low voltage level to a high voltage level, preventing the second transistor T2 from being turned on. This causes the sensing component UD to sense and generate a sensing signal SD, thereby changing the voltage at the control terminal of the first transistor T1 so that the voltage at the control terminal equals the voltage of the sensing signal SD. It should be noted that when the voltage of the sensing signal SD is less than the first supply voltage VCC1, the voltage at the second terminal of the first transistor T1 and the voltage at the control terminal of the first transistor T1 (i.e., the voltage of the sensing signal SD) will have a linear proportional relationship. In other words, at this time, the first transistor T1 can proportionally amplify or reduce the voltage at the control terminal, so that the voltage at the second terminal of the first transistor T1 corresponds to the voltage of the sensing signal SD generated by the sensing component UD.

[0081] According to one embodiment of this disclosure, when the sensing unit 200 is operating during the reading period, the switch signal SW is at a low voltage level, turning on the third transistor T3. The third transistor T3 has an output terminal, such that an output signal SOUT is output from the output terminal of the third transistor T3 to the read line DATA. Through the aforementioned function of the first transistor T1, the output voltage of the second terminal of the first transistor T1 is linearly proportional to the voltage of the sensing signal SD at the control terminal of the first transistor T1, so that the output signal SOUT corresponds to the sensing signal SD.

[0082] According to one embodiment of this disclosure, when the third transistor T3 is turned on, the switching signal SW can be a negative voltage, which helps to increase the source-gate voltage of the third transistor T3 and reduce the on-resistance of the third transistor T3, so that the signal of the read line DATA reaches the steady state more quickly and reduces the influence of the resistance value of the trace during the signal transmission of the read line DATA.

[0083] Please refer to Figure 1 , Figure 3 . Figure 1 The multitasking unit 120 is coupled to read lines DATA0 to DATAN and may include multiple switching components. For example... Figure 3 As shown, in one embodiment, the switching assembly 300 includes a fourth transistor T4. The fourth transistor T4 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor T4 receives a selection signal SEL, the first terminal of the fourth transistor T4 is coupled to a read line DATA, and the second terminal of the fourth transistor T4 is used to output an output signal SOUT. According to an embodiment of this disclosure, Figure 3 The read line DATA corresponds to Figure 1 The first read line DATA0, the second read line DATA1, ..., the (N+1)th read line DATAN can be selected as the output signal SOUT according to the corresponding selection signal SEL. The connection structure 130 provides the output signal SOUT to the processor 140. Figure 3 In one embodiment shown, the fourth transistor T4 may be a P-type transistor, but this disclosure is not limited thereto.

[0084] Figure 4 This is a circuit diagram of a switching assembly according to another embodiment of this disclosure. (See diagram below.) Figure 4As shown, the switching assembly 400 includes a fifth transistor T5, a sixth transistor T6, and an inverter INV. The inverter may be coupled between the control terminal of the fifth transistor T5 and the control terminal of the sixth transistor T6, but this disclosure is not limited thereto. The fifth transistor T5 includes a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor T5 receives a selection signal SEL, the first terminal of the fifth transistor T5 is coupled to a read line DATA, and the second terminal of the fifth transistor T5 outputs an output signal SOUT.

[0085] The sixth transistor T6 includes a control terminal, a first terminal, and a second terminal. The control terminal of the sixth transistor T6 receives the inverted selection signal SELB. The first terminal of the sixth transistor T6 is coupled to the read line DATA. The second terminal of the sixth transistor T6 outputs the output signal SOUT. The inverter INV is used to invert the selection signal SEL to generate the inverted selection signal SELB. According to one embodiment of this disclosure, the fifth transistor T5 is a P-type transistor and the sixth transistor T6 is an N-type transistor, but this disclosure is not limited to this.

[0086] According to one embodiment of this disclosure, Figure 4 The read line DATA corresponds to Figure 1 The first read line DATA0, the second read line DATA1, ..., the (N+1)th read line DATAN. ​​In other words, Figure 1 The multiplexer 120 includes multiple switching components 400 having a fifth transistor T5, a sixth transistor T6, and an inverter INV. These multiple switching components 400 select any one of the first read line DATA0, the second read line DATA1, ..., the (N+1)th read line DATAN according to the corresponding selection signal SEL, and provide it to the processor 140 via the connection structure 130. That is, as... Figure 1 As shown, the connection structure 130 is coupled between the sensing circuit and the processor 140.

[0087] Figure 5 This is a schematic diagram of a connection structure according to an embodiment of this disclosure. Figure 5 As shown, the link structure 500 includes a first line 510 and a second line 520, wherein the first line 510 and the second line 520 may be connected in parallel. According to other embodiments of this disclosure, the link structure 500 may include any number of lines. Figure 5 This example only uses the first line 510 and the second line 520 as examples, and is not limited to this in any way.

[0088] According to one embodiment of this disclosure, the first line 510 and the second line 520 may belong to different metal layers, such that the first line 510 and the second line 520 are connected in parallel to reduce the overall resistance value of the connection structure 500. For example, the first line 510 is formed on the first metal layer, and the second line 520 is formed on the second metal layer, wherein the first metal layer and the second metal layer are different layers. This is only for illustrative purposes, and is not intended to limit the scope in any way. In some embodiments, the first line 510 and the second line 520 may also belong to the same metal layer and be connected in parallel in a left-right configuration.

[0089] According to one embodiment of this disclosure, the first line 510 and the second line 520 are formed of a low-resistance material. For example, the sheet resistance of the first line 510 and the second line 520 may be between 0.05 ohms and 0.6 ohms (0.05 ohms ≤ sheet resistance ≤ 0.6 ohms), but are not limited thereto. According to some embodiments of this disclosure, the low-resistance materials forming the first line 510 and the second line 520 include molybdenum (Mo), copper (Cu), titanium (Ti), and aluminum (Al). According to another embodiment of this disclosure, the first line 510 and the second line 520 are formed of a multilayer metal stack, such as a stack of molybdenum, aluminum, and molybdenum (Mo / Al / Mo), but this disclosure is not limited thereto.

[0090] Figure 6 This is a circuit diagram of a sensing device according to an embodiment of this disclosure. Figure 6 As shown, the sensing device 600 includes a sensing unit 200, a switching assembly 400, and a connection structure 500, wherein the sensing unit 200 corresponds to... Figure 1 One of the multiple sensing units 110_00, ..., 110_NM, the switching assembly 400 corresponds to... Figure 1 Multiple switching components of the multitasking unit 120 ( Figure 1 (Not shown), link structure 500 corresponds to... Figure 1 The connection structure 130. According to one embodiment of this disclosure, when the sensing component UD of the sensing unit 200 senses an image, the switching component 400 causes the output signal SOUT to be output through the read line DATA according to the selection signal SEL, and is provided to via the link structure 500. Figure 1 The processor is 140.

[0091] Figure 7 This is a block diagram of a sensing device according to an embodiment of the present disclosure. The sensing device 700 and... Figure 1Compared to the sensing device 100, the sensing device 700 further includes a readout circuit 710. The readout circuit 710 is located between a plurality of sensing units 110_00, ..., 110_NM and the multiplexer 120, and is used to convert signals passing through the first readout line DATA0, the second readout line DATA1, ..., the (N+1)th readout line DATAN into first readout data RD0, second readout data RD1, ..., the (N+1)th readout data RDN. The multiplexer 120 is used to select one of the first readout data RD0, the second readout data RD1, ..., the (N+1)th readout data RDN as an output signal SOUT and transmit it to the processor 140.

[0092] Figure 8 This is a circuit diagram of a reading circuit according to an embodiment of this disclosure. Figure 8 As shown, the read circuit 800 includes a seventh transistor T7, an eighth transistor T8, a first mapping transistor TM0, a second mapping transistor TM1, ..., a (N+1)th mapping transistor TMN, a first output transistor TR0, a second output transistor TR1, ... and a (N+1)th output transistor TRN.

[0093] The seventh transistor T7 is used to generate a reference current IR and includes a control terminal, a first terminal, and a second terminal. The control terminal of the seventh transistor T7 receives a bias voltage VB, and the first terminal of the seventh transistor T7 is coupled to a fourth supply voltage VCC4. The eighth transistor T8 includes a control terminal, a first terminal, and a second terminal. The control terminal of the eighth transistor T8 is coupled to the second terminal of the seventh transistor T7 and the first terminal of the eighth transistor T8, and the second terminal of the eighth transistor T8 is coupled to ground.

[0094] The first mapping transistor TM0 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first mapping transistor TM0 is coupled to the control terminal of the eighth transistor T8, the first terminal of the first mapping transistor TM0 is coupled to the first read line DATA0, and the second terminal of the first mapping transistor TM0 is coupled to the ground terminal.

[0095] The second mapping transistor TM1 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second mapping transistor TM1 is coupled to the control terminal of the eighth transistor T8, the first terminal of the second mapping transistor TM1 is coupled to the second read line DATA1, and the second terminal of the second mapping transistor TM1 is coupled to the ground terminal.

[0096] The (N+1)th mapping transistor TMN includes a control terminal, a first terminal, and a second terminal. The control terminal of the (N+1)th mapping transistor TMN is coupled to the control terminal of the eighth transistor T8, the first terminal of the (N+1)th mapping transistor TMN is coupled to the (N+1)th read line DATAN, and the second terminal of the (N+1)th mapping transistor TMN is coupled to the ground terminal.

[0097] According to one embodiment of this disclosure, an eighth transistor T8, a first mapping transistor TM0, a second mapping transistor TM1, ..., and a (N+1)th mapping transistor TMN form a current mirror to map a reference current IR to a first read line DATA0, a second read line DATA1, ..., and a (N+1)th read line DATAN, respectively. According to some embodiments of this disclosure, the size ratio of the eighth transistor T8 to the first mapping transistor TM0, the second mapping transistor TM1, ..., and the (N+1)th mapping transistor TMN can be adjusted to amplify or reduce the current mapped by the first mapping transistor TM0, the second mapping transistor TM1, ..., and the (N+1)th mapping transistor TMN.

[0098] The first output transistor TR0 includes a control terminal, a first terminal, and a second terminal. The control terminal of the first output transistor TR0 is coupled to the first read line DATA0, the first terminal of the first output transistor TR0 is coupled to the fifth supply voltage VCC5, and the second terminal of the first output transistor TR0 is coupled to the processor (not shown) to output the first read data RD0.

[0099] The second output transistor TR1 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second output transistor TR1 is coupled to the second read line DATA1, the first terminal of the second output transistor TR1 is coupled to the fifth supply voltage VCC5, and the second terminal of the second output transistor TR1 is coupled to the processor to output the second read data RD1.

[0100] The (N+1)th output transistor TRN includes a control terminal, a first terminal, and a second terminal. The control terminal of the (N+1)th output transistor TRN is coupled to the (N+1)th read line DATAN. ​​The first terminal of the (N+1)th output transistor TRN is coupled to the fifth supply voltage VCC5. The second terminal of the (N+1)th output transistor TRN is coupled to the processor to output the (N+1)th read data RDN.

[0101] According to an embodiment of this disclosure, the first mapping transistor TM0, the second mapping transistor TM1, ... and the (N+1)th mapping transistor TMN are used to... Figure 7Data sensed by multiple sensing units 110_00, ..., 110_NM is transmitted via the first read line DATA0, the second read line DATA1, ..., the (N+1)th read line DATAN to the first output transistor TR0, the second output transistor TR1, ..., and the (N+1)th output transistor TRN, respectively. Then, through... Figure 7 The multiplexer 120 shown reads data RD0 to RDN from the first read line DATA0, the second read line DATA1, ..., and the (N+1)th read line DATAN, respectively. As mentioned earlier, the current mapped by the first mapping transistor TM0, the second mapping transistor TM1, ..., and the (N+1)th mapping transistor TMN can be amplified or reduced by adjusting the size ratio between the eighth transistor T8 and the mapping transistors TM0 to TMN in the read circuit 710. When the current through the read lines DATA0 to DATAN increases, the time to reach steady state during data reading can be reduced.

[0102] Figure 9 This is a circuit diagram of a sensing device according to another embodiment of this disclosure. Figure 9 Sensing device 900 and Figure 6 Compared to the sensing device 600, the sensing device 900 further includes a readout circuit 910, wherein the readout circuit 910 is located between the sensing unit 200 and the switching assembly 400. According to an embodiment of this disclosure, the image transistor TM of the readout circuit 910 corresponds to... Figure 8 The output transistor TR of the readout circuit 910 corresponds to any one of the first mapping transistor TM0, the second mapping transistor TM1, ..., the (N+1)th mapping transistor TMN. Figure 8 The read data RD of the read circuit 910 corresponds to any one of the first read data RD0, the second read data RD1, ..., and the (N+1)th read data RDN. The output transistor TR is coupled between the read line DATA and the processor (not shown). More specifically, the output transistor TR includes a control terminal, a first terminal, and a second terminal. The control terminal of the output transistor TR is coupled to the read line DATA, the first terminal of the output transistor TR is coupled to a reference voltage (e.g., a fifth supply voltage VCC5), and the second terminal of the output transistor TR can be coupled to the processor via the connection structure 500.

[0103] According to one embodiment of this disclosure, the sensing device 900 can have a faster readout speed. According to another embodiment of this disclosure, the sensing device 600 can occupy a smaller circuit area.

[0104] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing processes, material compositions, apparatuses, methods, and steps described in the specific embodiments of this specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this disclosure, current or future developed processes, machines, manufacturing processes, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing processes, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments.

Claims

1. A sensing device for operation during a reset period, an exposure period, and a readout period, wherein the sensing device comprises: A first transistor includes a control terminal and a first terminal; A second transistor, coupled to the first transistor, is used to set the voltage of the control terminal during the reset period; A sensing component, coupled to the first transistor, is used to generate a sensing signal during the exposure to change the voltage of the control terminal. A third transistor is coupled to the first terminal of the first transistor and has an output terminal for outputting an output signal corresponding to the sensing signal from the output terminal during the reading. A read line is coupled to the aforementioned output terminal, and A readout circuit, coupled to the above output terminal, includes: A current mirror, coupled to the read line, wherein the current mirror includes a fourth transistor, including a control terminal, a first terminal, and a second terminal, the second terminal of the fourth transistor being coupled to a ground terminal; and A power supply transistor includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the power supply transistor receives a bias voltage, the first terminal of the power supply transistor is coupled to a supply voltage, and the second terminal of the power supply transistor is coupled to the control terminal and the first terminal of the fourth transistor. The first transistor is an N-type transistor and the third transistor is a P-type transistor.

2. The sensing device as claimed in claim 1, characterized in that, The second transistor mentioned above is a P-type transistor.

3. The sensing device of claim 1 further includes an output transistor, wherein the output transistor includes a control terminal coupled to the readout line.

4. The sensing device of claim 1 further includes a multiplexer, wherein the multiplexer is coupled to the readout line, and the multiplexer includes a plurality of switching components.

5. The sensing device as claimed in claim 4, characterized in that, Each of the aforementioned switching components includes a fifth transistor and a sixth transistor, wherein the fifth transistor is a P-type transistor and the sixth transistor is an N-type transistor.

6. The sensing device of claim 5 further includes an inverter coupled between the control terminal of the fifth transistor and the control terminal of the sixth transistor.

7. The sensing device of claim 1, further comprising a processor and a connection structure, the connection structure being coupled between the sensing device and the processor, wherein the connection structure includes a first line and a second line, and the second line is connected in parallel with the first line.

8. The sensing device as claimed in claim 7, characterized in that, The first line and the second line mentioned above are at different levels.

9. The sensing device as claimed in claim 7, characterized in that, The sheet resistance values ​​of the first and second lines mentioned above are between 0.05 and 0.6 ohms.

10. A sensing device, comprising: A sensing circuit; A readout line is coupled to the aforementioned sensing circuit; A read circuit includes: A current mirror, coupled to the read line, wherein the current mirror includes a first transistor, including a control terminal, a first terminal, and a second terminal, the second terminal of the first transistor being coupled to a ground terminal; and A power supply transistor includes a control terminal, a first terminal and a second terminal, wherein the control terminal of the power supply transistor receives a bias voltage, the first terminal of the power supply transistor is coupled to a supply voltage, and the second terminal of the power supply transistor is coupled to the control terminal and the first terminal of the first transistor. One processor; as well as An output transistor is coupled between the read line and the processor. The output transistor includes a control terminal, a first terminal, and a second terminal, wherein the control terminal is coupled to the read line, the first terminal is coupled to a reference voltage, and the second terminal is coupled to the processor.

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