Photoelectric conversion device

Abstract

The present application provides a photoelectric conversion device. The photoelectric conversion device includes: a plurality of pixels; a plurality of output lines to which signals from the corresponding pixels are respectively output; an amplification unit arranged corresponding to each of the plurality of output lines and configured to amplify the signal output to the corresponding output line; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal to which a signal corresponding to the output of the amplification unit is input and a second input terminal to which a reference signal is input; and a switch connecting nodes of the plurality of output lines. The switch is turned on during a period before an offset clamping operation is completed.

Description

Technical Field

[0001] This disclosure relates to photoelectric conversion devices. Background Technology

[0002] Japanese Patent Application Publication No. 2015-56840 discloses a solid-state imaging device having an analog-to-digital (AD) conversion circuit that converts pixel signals output from pixels into digital signals. The solid-state imaging device disclosed in Japanese Patent Application Publication No. 2015-56840 reduces image quality degradation caused by stripes that may occur during the operation of the AD converter by short-circuiting the vertical signal lines between columns.

[0003] However, the method described in Japanese Patent Application Publication No. 2015-56840 may not achieve sufficient results depending on the circuit configuration of the photoelectric conversion device to be applied. Summary of the Invention

[0004] Therefore, the purpose of this disclosure is to provide a photoelectric conversion device capable of outputting high-quality signals.

[0005] According to one aspect of this disclosure, a photoelectric conversion device is provided, comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are respectively output; an amplification unit arranged corresponding to each of the plurality of output lines and configured to amplify the signals output to the corresponding output lines; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, wherein a signal corresponding to the output of the amplification unit is input to the first input terminal and a reference signal is input to the second input terminal; and a switch having a first terminal and a second terminal. The plurality of output lines include a first output line and a second output line. The first terminal is connected to a node between an amplification unit corresponding to the first output line and a comparison unit corresponding to the first output line. The second terminal is connected to a node between an amplification unit corresponding to the second output line and a comparison unit corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on potentials input to the first input terminal and the second input terminal. The switch is turned on during a period prior to the completion of the offset clamping operation.

[0006] According to another aspect of this disclosure, a photoelectric conversion device is provided, comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are respectively output; an amplification unit arranged corresponding to each of the plurality of output lines and configured to amplify the signals output to the corresponding output lines; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, wherein a signal corresponding to the output of the amplification unit is input to the first input terminal and a reference signal is input to the second input terminal; a second input capacitor arranged corresponding to each of the plurality of output lines; and a switch having a first terminal and a second terminal. The reference signal is input to the second input terminal via the second input capacitor. The plurality of output lines include a first output line and a second output line. The first terminal is connected to the second input capacitor corresponding to the first output line. The second terminal is connected to the second input capacitor corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal. The switch is turned on during a period prior to the completion of the offset clamping operation.

[0007] According to another aspect of this disclosure, a photoelectric conversion device is provided, comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are respectively output; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, wherein a signal corresponding to the output of an output line is input to the first input terminal and a reference signal is input to the second input terminal; a switch having a first terminal and a second terminal; and a first input capacitor arranged corresponding to each of the plurality of output lines. The signal corresponding to the output of an output line is input to the first input terminal via the first input capacitor. The plurality of output lines includes a first output line and a second output line. The first terminal is connected to the first input capacitor corresponding to the first output line. The second terminal is connected to the first input capacitor corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal. During a period prior to the completion of the offset clamping operation, the switch is turned on. After the completion of the offset clamping operation, the switch is turned off.

[0008] According to another aspect of this disclosure, a photoelectric conversion device is provided, comprising: a plurality of pixels; a plurality of output lines, to which signals from corresponding pixels are respectively output; a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, wherein a signal corresponding to the output of the output line is input to the first input terminal and a reference signal is input to the second input terminal; a second input capacitor arranged corresponding to each of the plurality of output lines; and a switch having a first terminal and a second terminal. The reference signal is input to the second input terminal via the second input capacitor. The plurality of output lines include a first output line and a second output line. The first terminal is connected to the second input capacitor corresponding to the first output line. The second terminal is connected to the second input capacitor corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal. The switch is turned on during a period before the offset clamping operation is completed. After the offset clamping operation is completed, the switch is turned off.

[0009] Other features of the invention will become clear from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a schematic structure of the photoelectric conversion device according to the first embodiment.

[0011] Figure 2 This is a circuit diagram illustrating the construction of the pixel and column circuits according to the first embodiment.

[0012] Figure 3A and Figure 3B This is a timing diagram illustrating the driving method of the photoelectric conversion device according to the first embodiment.

[0013] Figure 4 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to the first embodiment.

[0014] Figure 5 This is a circuit diagram illustrating the construction of the pixel and column circuits according to the second embodiment.

[0015] Figure 6 This is a circuit diagram illustrating the construction of the pixel and column circuits according to the third embodiment.

[0016] Figure 7 This is a circuit diagram illustrating the construction of the pixel and column circuits according to the fourth embodiment.

[0017] Figure 8This is a circuit diagram illustrating the construction of the pixel and column circuits according to the fourth embodiment.

[0018] Figure 9 This is a circuit diagram illustrating the construction of the pixel and column circuits according to the fifth embodiment.

[0019] Figure 10 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to the fifth embodiment.

[0020] Figure 11 This is a circuit diagram illustrating the construction of the pixel and column circuits according to the fifth embodiment.

[0021] Figure 12 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to the fifth embodiment.

[0022] Figure 13 This is a block diagram of the device according to the sixth embodiment.

[0023] Figure 14A and Figure 14B This is a block diagram of the device according to the seventh embodiment. Detailed Implementation

[0024] Preferred embodiments of the invention will now be described in detail with reference to the accompanying drawings. In the drawings, the same or corresponding elements are indicated by the same reference numerals, and their description may be omitted or simplified.

[0025] In the following first to fifth embodiments, the imaging device will be primarily described as an example of a photoelectric conversion device. However, the photoelectric conversion device of each embodiment is not limited to an imaging device, but can be applied to other devices. Examples of other devices include a ranging device and a photometer. A ranging device may be, for example, a focus detection device, a distance measuring device using time-of-flight (TOF), etc. A photometer may be a device for measuring the amount of light incident on the device.

[0026] [First Embodiment]

[0027] Figure 1 This is a block diagram illustrating a schematic configuration of a photoelectric conversion device according to a first embodiment. The photoelectric conversion device includes a pixel array 10, a current source 13, a vertical scanning circuit 14, a timing generator 15, a reference signal generation circuit 16, a counter 17, a digital signal processing circuit 18, and a readout circuit 19.

[0028] Pixel array 10 includes a plurality of pixels 100 arranged in a matrix forming multiple rows and columns. Each of the plurality of pixels 100 includes a photoelectric conversion unit, which includes a photoelectric conversion element such as a photodiode. Pixel 100 outputs a photoelectric conversion signal, which is an analog signal corresponding to the amount of incident light on the photoelectric conversion element. Pixel 100 outputs a noise signal, which is an analog signal of noise level. Pixel array 10 may include optical black pixels (not shown) whose photoelectric conversion elements are blocked from light, and the output signal of the optical black pixels is used as a reference for the black level.

[0029] In each row of the pixel array 10, a plurality of control lines 11 are arranged in a first direction ( Figure 1 The control lines 11 extend in a horizontal direction. Each of the plurality of control lines 11 is connected to each of the pixels 100 arranged in the first direction and serves as a common signal line for the pixels 100. The first direction in which the control lines 11 extend can be referred to as the row direction or the horizontal direction. The control lines 11 are connected to the vertical scan circuit 14.

[0030] In each column of the pixel array 10, the output lines 12 are arranged in a second direction intersecting the first direction. Figure 1 The output lines 12 extend in the vertical direction. Each of the output lines 12 is connected to each of the pixels 100 arranged in the second direction and serves as a common signal line for the pixels 100. The second direction in which the output lines 12 extend can be referred to as the column direction or the vertical direction. Each of the output lines 12 is connected to the readout circuit 19 and the current source 13 arranged in the corresponding column.

[0031] The vertical scanning circuit 14 is a control circuit that functions as follows: receiving control signals output from the timing generator 15, generating control signals for driving pixels 100, and supplying control signals to pixels 100 via control lines 11. Logic circuitry such as shift registers or address decoders can be used in the vertical scanning circuit 14. The vertical scanning circuit 14 drives the pixels 100 of the pixel array 10 row by row. Signals read from pixels 100 row by row are input to the readout circuit 19 via output lines 12 arranged in each column of the pixel array 10.

[0032] exist Figure 1 In the diagram, only three rows and three columns are shown for pixel 100, control line 11 and output line 12, but in reality, pixel 100, control line 11 and output line 12 can be arranged across thousands of rows and thousands of columns.

[0033] The readout circuit 19 includes a horizontal scanning circuit 25 and column circuits 20 corresponding to the output lines 12 of each column. The column circuits 20 have the function of reading out noise signals and photoelectric conversion signals output from the pixel 100 and converting these signals into digital signals, as well as the function of holding the digital signals after AD conversion. The column circuits 20 include an amplification unit 21, an analog signal holding unit 22, an AD conversion unit 23, and a digital signal holding unit 24.

[0034] Amplification unit 21 amplifies the noise signal and photoelectric conversion signal output from pixel 100 and outputs an analog signal. Analog signal holding unit 22 temporarily holds the analog signal output from amplification unit 21. Analog signal holding unit 22 outputs the held signal.

[0035] The reference signal generation circuit 16 receives the control signal output from the timing generator 15 and generates a reference signal to be supplied to the AD conversion unit 23. The reference signal is a signal with a predetermined amplitude and may include, for example, a signal whose signal level (signal amplitude) varies with time. The reference signal typically includes a ramp signal. A ramp signal is a signal whose signal level changes monotonically with time, for example, a signal whose output voltage decreases or increases monotonically with time. Additionally, a ramp signal may also include a signal whose potential changes gradually. The reference signal is not particularly limited, as long as it has an amplitude suitable for AD conversion.

[0036] AD conversion unit 23 compares the signal output from analog signal holding unit 22 with the reference signal output from reference signal generation circuit 16, and outputs the latch signal based on the comparison result to digital signal holding unit 24.

[0037] Counter 17 generates a counting signal whose value changes over time by counting the pulses of the clock signal, and outputs the counting signal to the digital signal holding unit 24.

[0038] At the timing of the change in the latch signal output from the AD conversion unit 23, the digital signal holding unit 24 holds the counting signal output from the counter 17 as a digital signal. The digital signal holding unit 24 can hold the digital values ​​of noise signals and photoelectric conversion signals.

[0039] The horizontal scanning circuit 25 sequentially supplies control signals to the digital signal holding units 24 of each column. As a result, the digital signals held in the digital signal holding units 24 of each column are sequentially transmitted to the digital signal processing circuit 18. The horizontal scanning circuit 25 can be constructed using shift registers, address decoders, etc.

[0040] The digital signal processing circuit 18 processes the digital signals output from the digital signal holding units 24 of each column and outputs the processed signals to the outside of the photoelectric conversion device. Examples of signal processing performed by the digital signal processing circuit 18 include correction processing using digital correlation double sampling, amplification processing, etc.

[0041] The timing generator 15 is a control circuit that supplies control signals for the operation and timing of the vertical scanning circuit 14, the readout circuit 19, the reference signal generation circuit 16, and the counter 17. At least a portion of the control signals supplied to the vertical scanning circuit 14, the readout circuit 19, the reference signal generation circuit 16, and the counter 17 can be supplied externally from the photoelectric conversion device.

[0042] Figure 2 This is a circuit diagram illustrating the construction of the pixel 100 and column circuit 20 according to this embodiment. Figure 2 Showing more details Figure 1 The circuit structure of two pixels 100 and the partial circuit structure of two columns of column circuits 20 in the photoelectric conversion device. Figure 2 The two columns shown are column n and column (n+1) (where "n" is a natural number). Column n and column (n+1) are sometimes simply referred to as column one and column two. When it is necessary to distinguish elements in the two columns, the index "a" indicating that the element is in column n or the index "b" indicating that the element is in column (n+1) can be added. Figure 2 The figure shows the reference numerals for some of the components. The output line 12 (12a) from pixel 100a in column n to its output signal can be referred to as the first output line, while the output line 12 (12b) from pixel 100b in column (n+1) to its output signal can be referred to as the second output line. Since the components in column n and column (n+1) have essentially the same construction, the description of the components in column (n+1) can be omitted.

[0043] Figure 2 The diagram shows pixels 100a and 100b, current source 13, amplification units 21a and 21b, analog signal holding units 22a and 22b, AD conversion units 23a and 23b, and switch 191. Figure 1 Other components are not in Figure 2 As shown in the image.

[0044] Pixel 100a includes a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

[0045] A photoelectric conversion element PD is, for example, a photodiode. The anode of the photoelectric conversion element PD is connected to a ground node, and the cathode of the photoelectric conversion element PD is connected to the source of a transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of a reset transistor M2 and the gate of an amplifying transistor M3. The node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplifying transistor M3 are connected is called the so-called floating diffusion section. The floating diffusion section has a capacitive component (floating diffusion capacitance) and acts as a charge holding component. Floating diffusion capacitance includes PN junction capacitance, wiring capacitance, etc.

[0046] The drains of reset transistor M2 and amplification transistor M3 are connected to the power supply voltage node supplied with voltage VDD. The source of amplification transistor M3 is connected to the drain of selection transistor M4. The source of selection transistor M4 is connected to output line 12.

[0047] exist Figure 2 In the case of the pixel configuration, the control lines 11 of each row include signal lines connected to the gate of the transfer transistor M1, signal lines connected to the gate of the reset transistor M2, and signal lines connected to the gate of the selection transistor M4. The control signal PTX is supplied from the vertical scan circuit 14 to the gate of the transfer transistor M1. The control signal PRES is supplied from the vertical scan circuit 14 to the gate of the reset transistor M2. The control signal PSEL is supplied from the vertical scan circuit 14 to the gate of the selection transistor M4. Multiple pixels 100a and 100b in the same row are connected to a common signal line and are simultaneously controlled by a common control signal.

[0048] In this embodiment, it is assumed that electrons are used as signal charges in the electron-hole pairs generated in the photoelectric conversion element PD by incident light. When electrons are used as signal charges, the individual transistors included in pixel 100a can be composed of N-type MOS transistors. When the individual transistors are composed of N-type MOS transistors, the corresponding transistors are turned on when a high-level control signal is supplied from the vertical scan circuit 14. When a low-level control signal is supplied from the vertical scan circuit 14, the corresponding transistors are turned off. However, the signal charge is not limited to electrons, and holes can also be used as signal charges. When holes are used as signal charges, the conductivity type of the individual transistors is opposite to that described in this embodiment. The terms "source" or "drain" of a MOS transistor can vary depending on the target function or the conductivity type of the transistor. Some or all of the terms "source" and "drain" used in this embodiment are sometimes referred to as opposite terms.

[0049] The photoelectric conversion element PD converts incident light (photoelectric conversion) into an amount of charge corresponding to the amount of incident light. A transfer transistor M1 is turned on to transfer the charge held in the photoelectric conversion element PD to node FD. The charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of node FD. As a result, node FD has a potential corresponding to the amount of charge transferred from the photoelectric conversion element PD through the charge-voltage conversion of the floating diffusion capacitance.

[0050] Select transistor M4 is turned on to connect amplifier transistor M3 to output line 12. Amplifier transistor M3 is configured such that voltage VDD is supplied to its drain and bias current is supplied from current source 13 to its source via select transistor M4, and amplifier transistor M3 constitutes an amplifier circuit (source follower circuit) with its gate as the input node. Therefore, amplifier transistor M3 outputs a signal based on the voltage of node FD to output line 12 via select transistor M4. In this sense, amplifier transistor M3 and select transistor M4 are output units that output a pixel signal corresponding to the amount of charge held in node FD.

[0051] The reset transistor M2 controls the supply of a voltage (VDD) to node FD, which is used to reset node FD in the charge-holding section. When reset transistor M2 is turned on, node FD is reset to the voltage corresponding to VDD.

[0052] Amplification unit 21a includes an input capacitor 211, a differential amplifier 212, a feedback capacitor 213, and a switch 214. The first terminal of the input capacitor 211 is the input node of amplification unit 21a. The first terminal of the input capacitor 211 is connected to the output line 12. The second terminal of the input capacitor 211 is connected to the inverting input terminal of the differential amplifier 212, the first terminal of the feedback capacitor 213, and the first terminal of the switch 214. A power supply line with a reference voltage Vc0r is connected to the non-inverting input terminal of the differential amplifier 212. The output terminal of the differential amplifier 212 is the output node of amplification unit 21a. The output terminal of the differential amplifier 212 is connected to the second terminal of the feedback capacitor 213 and the second terminal of the switch 214.

[0053] Using the circuit configuration described above, amplifier unit 21a functions as an inverting amplifier circuit that amplifies the voltage of the analog signal output to output line 12. Switch 214 is controlled to be on or off by a control signal from timing generator 15. When switch 214 changes from the on state to the off state, the potential input to input capacitor 211 is clamped. When switch 214 is off, the amplification factor of amplifier unit 21a is determined by the ratio of the capacitance value of input capacitor 211 to the capacitance value of feedback capacitor 213.

[0054] The analog signal holding unit 22a includes a switch 221, a holding capacitor 222, and an amplifier 223. The output terminal of the amplifier unit 22a is connected to the first terminal of the switch 221. The first terminal of the switch 221 is the input terminal of the analog signal holding unit 22a. The second terminal of the switch 221 is connected to the input terminal of the amplifier 223 and the holding capacitor 222. The output terminal of the amplifier 223 is the output terminal of the analog signal holding unit 22a.

[0055] Switch 221 is controlled to be on or off by a control signal from timing generator 15. When switch 221 changes from the on state to the off state, the analog signal output from amplifier unit 21a is held in holding capacitor 222. Amplifier 223 (first buffer) is a buffer circuit such as a source follower and outputs an analog signal corresponding to the potential held in holding capacitor 222. Therefore, analog signal holding unit 22a forms a sampling and holding circuit for holding the analog signal output from amplifier unit 21a.

[0056] The first terminal of switch 191 is connected to the node to which the holding capacitor 222 in the nth column is connected, and the second terminal of switch 191 is connected to the node to which the holding capacitor 222 in the (n+1)th column is connected. Switch 191 is controlled to be on or off by a control signal sw from the timing generator 15. When the control signal sw is high, switch 191 is on, and when the control signal sw is low, switch 191 is off. When switch 191 is on, the analog signals held in the holding capacitors 222 in the nth column and the analog signals held in the holding capacitors 222 in the (n+1)th column are averaged. The potential of the analog signal output from the analog signal holding unit 22a in the nth column is called comp_in[n], and the potential of the analog signal output from the analog signal holding unit 22b in the (n+1)th column is called comp_in[n+1].

[0057] The AD conversion unit 23a includes input capacitors 231 and 236, a comparator 232, switches 233 and 234, and an amplifier 235. Comparator 232 is a fully differential comparator having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and serves as the comparison unit for AD conversion. Comparator 232 compares the potentials of the first and second input terminals and outputs a signal based on the comparison result as the output signal OUT from the first and second output terminals. These output signals are input to a latch circuit (not shown). The latch circuit outputs a latch signal to the digital signal holding unit 24.

[0058] The output node of the analog signal holding unit 22a is connected to the first terminal of the input capacitor 231 (the first input capacitor). The first terminal of the input capacitor 231 is the input node of the AD conversion unit 23a. The second terminal of the input capacitor 231 is connected to the first input terminal of the comparator 232 and the first terminal of the switch 233. The second terminal of the switch 233 is connected to the first output terminal of the comparator 232.

[0059] The reference signal Vramp is input from the reference signal generation circuit 16 to the input terminal of amplifier 235. Amplifier 235 (second buffer) is a buffer circuit such as a source follower. The output terminal of amplifier 235 is connected to the first terminal of input capacitor 236 (second input capacitor). The second terminal of input capacitor 236 is connected to the second input terminal of comparator 232 and the first terminal of switch 234. The second terminal of switch 234 is connected to the second output terminal of comparator 232. Switches 233 and 234 are controlled to be on or off by the control signal comp_res from timing generator 15. When the control signal comp_res is high, switches 233 and 234 are on, and when the control signal comp_res is low, switches 233 and 234 are off.

[0060] Figure 3A This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 3A The levels of control signals comp_res and sw, the potential of reference signal Vramp, and the potentials of input signals comp_in[n] and comp_in[n+1] are shown. Furthermore, Figure 3A The “Var” symbol schematically indicates the timing distribution of the level changes of the output signals of each column of comparator 232. Figure 3A The time period from time t10 to time t17 is the period in AD conversion unit 23 during which the noise signal is converted into an AD signal by comparing the noise signal from pixel 100 with the reference signal Vramp. Figure 3A This describes the driving timing for the AD conversion of noisy signals.

[0061] At time t10, the control signal comp_res is high, and switches 233 and 234 are turned on. Therefore, the potentials of the first input terminal, second input terminal, first output terminal, and second output terminal of comparator 232 are reset. The control signal sw is low, and switch 191 is turned off.

[0062] The input signals comp_in[n] and comp_in[n+1] are signals in which noise generated in amplification unit 21 and analog signal holding unit 22 is superimposed on the noise signal output from pixel 100. The noise signal clamped by amplification unit 21 includes a charge re-injection component when switch 214 changes from the on state to the off state. Charge re-injection is a phenomenon in which, when switch 214 changes from the on state to the off state, charge located under the gate of the transistor constituting switch 214 moves to the respective inverting input and output terminals of differential amplifier 212. The charge re-injection component included in the noise signal is different for each amplification unit 21 in each column. Therefore, at time t10, the input signals comp_in[n] and comp_in[n+1] have different potentials from each other.

[0063] At time t11, the control signal sw goes high. As a result, switch 191 is turned on, and the analog signal held in the holding capacitor 222 of the nth column and the analog signal held in the holding capacitor 222 of the (n+1)th column are averaged. Therefore, the average signal held in the holding capacitors 222 of the nth and (n+1)th columns is input as the input signals comp_in[n] and comp_in[n+1] to the AD conversion unit 23 via amplifier 223. Therefore, after time t11, the input signals comp_in[n] and comp_in[n+1] are at the same potential. At time t11, the reference signal Vramp is set to the offset level.

[0064] At time t12, the control signal comp_res goes low. As a result, switches 233 and 234 are turned off. The potential at the second input terminal of comparator 232 at time t12 is the reset potential of the reference signal Vramp, which is at an offset level. The charge of the potential based on the offset level of the reference signal Vramp at time t12 is clamped to the input capacitor 236. In the following text, this operation may be referred to as the offset clamping operation. Thus, the offset clamping operation of the input capacitor 236 is completed.

[0065] The charge at the output potential of comparator 232 at time t12 is clamped to input capacitor 231. That is, the offset clamping operation of input capacitor 231 is completed. Since input signals comp_in[n] and comp_in[n+1] have the same potential, the same potential is clamped to input capacitor 231. In other words, the potential of input capacitors 231 clamped to the nth and (n+1)th columns by the offset clamping operation differs from the potential of the input signals before time t11 by ΔV. The noise signal held in input capacitor 231 includes the noise component of AD conversion unit 23. The noise component includes the charge re-injection component when switch 233 changes from the on state to the off state. The signal held in input capacitor 236 includes the charge re-injection component when switch 234 changes from the on state to the off state.

[0066] At time t13, the setting of the reference signal Vramp to the offset level is cancelled. As a result, the potential of the reference signal Vramp returns to the potential at time t10.

[0067] At time t14, the control signal sw goes low. Switch 191 is turned off, and the averaging of the analog signal held in the holding capacitor 222 in the nth column and the analog signal held in the holding capacitor 222 in the (n+1)th column is canceled. Therefore, the input signal comp_in[n] and the input signal comp_in[n+1] have different potentials from each other.

[0068] At time t15, the reference signal generation circuit 16 changes the potential of the reference signal Vramp according to time. At time t15, the counter 17 starts the clock signal counting operation.

[0069] Time t16 is the time during which the potential of the reference signal Vramp exceeds the offset level. Near time t16, the amplitude relationship between the input signals comp_in[n] and comp_in[n+1] and the reference signal Vramp is reversed, and the level of the output signal of comparator 232 changes. Consequently, a latch signal is output from the latch circuit to the digital signal holding unit 24. In response to the change in the latch signal, the digital signal holding unit 24 holds the counting signal at this time. The counting signal held in the digital signal holding unit 24 is a digital signal corresponding to the noise signal.

[0070] At time t17, the reference signal generation circuit 16 stops changing the potential of the reference signal Vramp. Then, the potential of the reference signal Vramp returns to the potential at time t10. At time t17, the counter 17 stops the clock signal counting operation and resets the count value.

[0071] After time t17, the photoelectric conversion signal is converted from analog to digital in the same way as the noise signal, and the digital signal corresponding to the photoelectric conversion signal is held in the digital signal holding unit 24. Then, the horizontal scanning circuit 25 sequentially scans the digital signal holding units 24 of each column, and the digital signal held in the digital signal holding units 24 of each column is output to the digital signal processing circuit 18.

[0072] As described above, the noise-based digital signal and the photoelectric conversion-based digital signal are output from the column circuits 20 of each column to the digital signal processing circuit 18. The photoelectric conversion-based digital signal includes a noise component. Therefore, the digital signal processing circuit 18 can generate a signal with less noise by subtracting the noise-based digital signal from the photoelectric conversion-based digital signal.

[0073] Figure 4 This is a timing diagram illustrating the driving method of the photoelectric conversion device in this embodiment when switch 191 is not turned on. (Refer to...) Figure 3A and Figure 4 To describe the effects of this embodiment.

[0074] exist Figure 3A In the driving method, during the time period from time t11 to time t14, the control signal sw is at a high level, and switch 191 is turned on. On the other hand, in Figure 4 In the driving method, during the period from time t21 to time t24 (corresponding to the period from time t11 to time t14), the control signal sw remains at a low level. Therefore, switch 191 is not turned on. Figure 4 In and Figure 3A The difference. In other words, it can be explained as... Figure 4 The case where switch 191 in this embodiment is not set is shown.

[0075] like Figure 4 As shown, at time t22, the input signals comp_in[n] and comp_in[n+1] have different potentials. Therefore, the different potentials are clamped between the input capacitors 231 in the nth column and the input capacitors 231 in the (n+1)th column. Figure 4In the example, the input signal comp_in[n] at time t22 is essentially the same as the input signal comp_in[n] at time t16. In this case, when the potential of the reference signal Vramp exceeds the offset level at time t16, the level of the output signal of the comparator 232 in the nth column changes. The input signal comp_in[n+1] at time t22 is also essentially the same as the input signal comp_in[n+1] at time t16. In this case, when the potential of the reference signal Vramp exceeds the offset level at time t16, the level of the output signal of the comparator 232 in the (n+1)th column also changes. Therefore, as Figure 4 As shown, when the switch 191 is not activated during the offset clamping operation, the output signal levels of the comparator 232 in the nth column and the output signal levels of the comparator 232 in the (n+1)th column change almost simultaneously. Therefore, as Figure 4 As shown in “Var”, the timing of the level change of the comparator 232 output signal in each column is small.

[0076] When the timing of the output signal level changes of each column's comparator 232 is small, the output signal levels of multiple comparators 232 may change simultaneously within a short period of time. This can cause noise due to factors such as IR drop and current changes. In particular, when the number of columns of pixels 100 is large, the impact of this noise is significant because a large number of comparators 232 are arranged in the photoelectric conversion device. Since this noise can propagate to other comparators 232 through power or signal wiring arranged in the column, it can be a factor that degrades the quality of the output signal. Moreover, in the stage circuit after the comparator 232, this noise may cause AD conversion errors, decreased accuracy of clock signal counting operations in counter 17, etc., thereby degrading the quality of the output signal.

[0077] On the other hand, Figure 3A In the driving method shown, switch 191 is turned on during the offset clamping operation at time t12. Therefore, the input potential of comparator 232 during the offset clamping operation at time t12 is different from the input potential of comparator 232 during the AD conversion at time t16. That is, the potential of the input signal comp_in[n] during the AD conversion is ΔV greater than its potential during the offset clamping operation. The potential of the input signal comp_in[n+1] during the AD conversion is ΔV less than its potential during the offset clamping operation.

[0078] exist Figure 3A In the driving method shown in the figure, such as Figure 3AAs indicated by "Var", the timing dispersion of the level changes of the output signals of the comparators 232 in each column is large. Therefore, the levels of the output signals of multiple comparators 232 are unlikely to change simultaneously in a short period of time, and the noise generated when the levels of the output signals of the comparators 232 in each column change can be reduced.

[0079] As described above, according to this embodiment, a photoelectric conversion device capable of outputting higher quality signals is provided.

[0080] In this embodiment, switch 191 is arranged between the signal lines of the nth column and the (n+1)th column, and the signals of these two columns are averaged by turning on switch 191 during the offset clamping operation. However, for example, switch 191 can be similarly arranged between the signal lines of the (n+1)th column and the (n+2)th column. In this case, the signals of all three columns can be averaged. Furthermore, switch 191 can be arranged between the signal lines of each column. In this case, some or all of the signals in all columns of pixel array 10 can be averaged. Furthermore, the combination of columns to be averaged or the number of columns to be averaged can be changed each time each row of pixel array 10 is read. In this case, since the timing of the level change of the output signal of comparator 232 is two-dimensionally irregular, the impact on image quality caused by this dispersion can be made less noticeable.

[0081] In this embodiment, switch 191 is controlled to be turned on during offset clamping at time t12. However, if the potential of the input signal comp_in[n] during offset clamping is different from the potential of the input signal comp_in[n] during AD conversion, switch 191 can switch from on to off before time t12.

[0082] Reference Figure 3B The timing diagram details a variation of switch 191 switching from on to off before time t12. Figure 3A The public description section may be omitted or simplified as appropriate.

[0083] At time t11, the control signal sw goes high. As a result, switch 191 is turned on, and the analog signal held in the holding capacitor 222 of the nth column and the analog signal held in the holding capacitor 222 of the (n+1)th column are averaged.

[0084] At time t31, the control signal sw goes low. Switch 191 is opened, canceling the averaging of the analog signals held in the holding capacitor 222 of the nth column and the holding capacitor 222 of the (n+1)th column. As a result, the potentials of the input signals comp_in[n] and comp_in[n+1] gradually return to the potentials at time t10.

[0085] At time t32, the control signal comp_res goes low, and the offset clamping operation is completed. Time t32 is the time before the potentials of input signals comp_in[n] and comp_in[n+1] return to the potentials at time t10.

[0086] At time t33, the offset level setting of the reference signal Vramp is canceled. As a result, the potential of the reference signal Vramp returns to the potential at time t10.

[0087] By performing the offset clamping operation after disconnecting switch 191 and canceling averaging, and before the input signal potential returns to its original potential, the potential of the input signal comp_in[n] during the offset clamping operation is different from the potential of the input signal comp_in[n] during the AD conversion operation. Note that... Figure 3B The “ΔV” shown indicates the potential difference between the input signal comp_in[n] during offset clamping and during AD conversion. Similarly, in... Figure 3B In the variant, noise generated when the output signal level of each column comparator 232 changes can be reduced, for the reason that... Figure 3A The description is the same as that in the description.

[0088] Furthermore, the photoelectric conversion device of this embodiment can have a configuration that allows the gain to be changed by altering the setting of the amplification unit 21 or the amount of change (slope) in the potential of the reference signal Vramp per unit time. In this case, the operation of switch 191 during offset clamping can be made different depending on the gain. The timing distribution of the level change of the comparator 232's output signal can vary depending on the gain. In addition, the noise level caused by the change in the output signal level may vary depending on the gain of the photoelectric conversion device. Therefore, since the optimal control method can vary depending on the gain, it may be desirable to change the operation of switch 191.

[0089] The timing of the level change of the comparator 232's output signal can vary depending on the temperature of the photoelectric conversion device. Therefore, the temperature of the photoelectric conversion device can be measured by a temperature sensor, and the operation of switch 191 during offset clamping can vary depending on the temperature.

[0090] [Second Embodiment]

[0091] The photoelectric conversion device according to this embodiment will be described. Components similar to those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0092] Figure 5 This is a circuit diagram illustrating the construction of pixel 100 and column circuit 20 according to this embodiment. In the photoelectric conversion device of this embodiment, switch 192 is provided instead of... Figure 2 Switch 191 in the middle.

[0093] The first terminal of switch 192 is connected to the node between the analog signal holding unit 22a and the AD conversion unit 23a in the nth column, and the second terminal of switch 192 is connected to the node between the analog signal holding unit 22b and the AD conversion unit 23b in the (n+1)th column. In other words, the first terminal of switch 192 is connected to the node between the amplifier 223 and the input capacitor 231 in the nth column, and the second terminal of switch 192 is connected to the node between the amplifier 223 and the input capacitor 231 in the (n+1)th column. Switch 192 is controlled to be on or off by a control signal sw from the timing generator 15. When the control signal sw is high, switch 192 is on, and when the control signal sw is low, switch 192 is off. When switch 192 is on, the analog signals input to the input capacitor 231 in the nth column and the analog signals input to the input capacitor 231 in the (n+1)th column are averaged. Other circuit configurations are similar. Figure 2 The description is the same as that in the text, so it is omitted.

[0094] The method for driving the photoelectric conversion device in this embodiment and Figure 3A The method shown is the same. That is, switch 192 is turned on during the offset clamping operation at time t12. Therefore, the input potential of comparator 232 during the offset clamping operation at time t12 is different from that during the AD conversion at time t16. In other words, the potential of the input signal comp_in[n] during the AD conversion is ΔV greater than the potential during the offset clamping. The potential of the input signal comp_in[n+1] during the AD conversion is ΔV less than the potential during the offset clamping. Therefore, as in the first embodiment, the levels of the output signals of the multiple comparators 232 will hardly change simultaneously in a short period of time, and the noise generated when the levels of the output signals of each column of comparators 232 change can be reduced.

[0095] As described above, according to this embodiment, a photoelectric conversion device capable of outputting higher quality signals is provided.

[0096] [Third Embodiment]

[0097] The photoelectric conversion device according to this embodiment will be described. Components similar to those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

[0098] Figure 6 This is a circuit diagram illustrating the construction of pixel 100 and column circuit 20 according to this embodiment. In the photoelectric conversion device of this embodiment, switch 193 is provided instead of... Figure 2 Switch 191 in the middle.

[0099] The first terminal of switch 193 is connected to the node between amplifier 235 and input capacitor 236 in column n, and the second terminal of switch 193 is connected to the node between amplifier 235 and input capacitor 236 in column (n+1). Switch 193 is controlled to be on or off by a control signal sw from timing generator 15. When control signal sw is high, switch 193 is on, and when control signal sw is low, switch 193 is off. When switch 193 is on, the analog signals input to input capacitor 236 in column n and input capacitor 236 in column (n+1) are averaged. Other circuit configurations are similar. Figure 2 The method of driving the photoelectric conversion device is the same as that in the previous section, so its description is omitted. Figure 3A The method is the same as that used in [the previous section], so its description has been omitted.

[0100] The effects of this embodiment will be described. The reference signal Vramp is input to amplifier 235 via a common reference signal line for each column. However, the output nodes of amplifier 235 in the nth column and the output nodes of amplifier 235 in the (n+1)th column may have different potentials due to variations in the performance of amplifier 235 in each column, variations in wiring resistance, etc. Figure 3A During the offset clamping operation at time t12, since the input capacitors 236 of the nth column and (n+1)th column are short-circuited via switch 193, the same potential is clamped to the input capacitors 236 of the nth column and (n+1)th column. On the other hand, during the period after time t13, switch 193 is turned off, and the output nodes of the amplifiers 235 of the nth column and (n+1)th column have different potentials due to this change. Therefore, at the AD conversion at time t16, the potentials of the reference signals input to the comparators 232 of the nth column and (n+1)th column are different from each other. Thus, the levels of the output signals of the multiple comparators 232 almost never change simultaneously, and noise generated when the levels of the output signals of the comparators 232 of each column change can be reduced.

[0101] As described above, according to this embodiment, a photoelectric conversion device capable of outputting higher quality signals is provided.

[0102] In the above description, it is assumed that during the AD conversion, the potential changes per unit time of the reference signals in column n and column (n+1) are the same; however, this embodiment is not limited to this. The potential change per unit time of the reference signal in column n may be different from the potential change per unit time of the reference signal in column (n+1).

[0103] [Fourth Embodiment]

[0104] The photoelectric conversion device according to this embodiment will be described. Components similar to those in the first to third embodiments are indicated by the same reference numerals, and the description of these components may be omitted or simplified.

[0105] Figure 7 This is a circuit diagram illustrating the construction of pixel 100 and column circuit 20 according to this embodiment. The photoelectric conversion device of this embodiment... Figure 2 The difference is that it does not include an amplification unit 21 and an analog signal holding unit 22. Figure 7 In the middle, switch 194 is set to replace Figure 2 Switch 191 in the middle.

[0106] Switch 194 is positioned between the output line 12a of the nth column and the output line 12b of the (n+1)th column. That is, the first terminal of switch 194 is connected to the output line 12a of the nth column, and the second terminal of switch 194 is connected to the output line 12b of the (n+1)th column. Switch 194 is controlled to be on or off by a control signal sw from the timing generator 15. When the control signal sw is high, switch 194 is on, and when the control signal sw is low, switch 194 is off. When switch 194 is on, the analog signals input to the input capacitor 231 of the nth column and the analog signals input to the input capacitor 231 of the (n+1)th column are averaged. Except for the absence of the amplification unit 21 and the analog signal holding unit 22, the other circuit configurations are the same as... Figure 2 The circuit construction is the same as that in the previous example, so its description is omitted.

[0107] The method for driving the photoelectric conversion device in this embodiment and Figure 3AThe method shown is the same. That is, switch 194 is turned on during the offset clamping operation at time t12. Therefore, the input potential of comparator 232 during the offset clamping operation at time t12 and the input potential of comparator 232 during the AD conversion at time t16 are different from each other. The potential of input signal comp_in[n] during AD conversion is ΔV greater than the potential during offset clamping. The potential of input signal comp_in[n+1] during AD conversion is ΔV less than the potential during offset clamping. Therefore, as in the first embodiment, the levels of the output signals of the multiple comparators 232 will hardly change simultaneously in a short period of time, and the noise generated when the levels of the output signals of each column of comparators 232 change can be reduced.

[0108] like Figure 7 The design allows for application even when switch 194 is positioned between the two output lines 12. Figure 3B The driving method shown is as follows. That is, after disconnecting switch 194 and canceling averaging, the following driving method can be applied, wherein the offset clamping operation is performed during the return from the potential at the time of averaging to the original potential.

[0109] However, it may be expected that... Figure 3A The offset clamping operation is performed during averaging, as described in the example below. An example of this will be described. Generally, output line 12 has a large parasitic capacitance and a large load resistance. For example, in a two-dimensional pixel array 10, the resistance value between the output node of pixel 100 and the input node of the AD conversion unit 23 varies depending on the row of pixel 100. Therefore, the potential difference ΔV between the potential during AD conversion and the potential when offset clamping is completed can vary depending on the row of pixel 100 to be read. Furthermore, the potential difference ΔV can vary depending on the temperature of the photoelectric conversion device and the manufacturing variations of the parasitic capacitance of output line 12. In summary, when switch 194 is arranged between the two output lines 12, it is expected that the offset clamping operation will be completed during averaging.

[0110] although Figure 7 The diagram shows a configuration where switch 194 is arranged between two output lines 12, but the switch can be configured as in the third embodiment. Figure 6 The switch 193 is connected to the output node of amplifier 235. Figure 8 This is a circuit diagram showing a variant example of the pixel 100 and column circuit 20 according to this embodiment.

[0111] like Figure 8 As shown, in this variant, switch 196 is used to replace... Figure 7Switch 194 is used in this embodiment. The first terminal of switch 196 is connected to the node between amplifier 235 and input capacitor 236 in the nth column, and the second terminal of switch 196 is connected to the node between amplifier 235 and input capacitor 236 in the (n+1)th column. Since the operation and effect of switch 196 are the same as those of switch 193 in the third embodiment, its description is omitted. Similarly, in this variant, for the same reason, noise generated when the output signal level of the comparators 232 in each column changes can be reduced.

[0112] In addition, combinations are possible. Figure 7 and Figure 8 That is, it can be set. Figure 7 Switch 194 and Figure 8 Switches 194 and 196 are both present. Switches 194 and 196 can be controlled synchronously or by different control signals.

[0113] Furthermore, the photoelectric conversion device of this embodiment can have a configuration that allows the gain to be changed by altering the setting of the amplification unit 21 or the amount of change (slope) in the potential of the reference signal Vramp per unit time. In this case, for example, the time t32 for completing the offset clamping operation can vary between time t31 and time t33 depending on the gain. The timing distribution of the level change of the output signal of comparator 232 can be changed depending on the gain. In addition, the noise level caused by the level change of the output signal can vary depending on the gain of the photoelectric conversion device. Therefore, since the optimal control method can vary depending on the gain, it is desirable to change the operation of switches 194 and 196.

[0114] [Fifth Embodiment]

[0115] The photoelectric conversion device according to this embodiment will be described. Components similar to those in the first to fourth embodiments are indicated by the same reference numerals, and the description of these components may be omitted or simplified.

[0116] Figure 9 This is a circuit diagram illustrating the construction of the pixel 100 and the column circuit 20 according to this embodiment. In the photoelectric conversion device of this embodiment, besides Figure 5 In addition to switch 192, switch 195 (output line connection switch) is also arranged.

[0117] Switch 195 is positioned between output line 12a of column n and output line 12b of column (n+1). Specifically, one terminal (the third terminal) of switch 195 is connected to output line 12a of column n, and the other terminal (the fourth terminal) of switch 195 is connected to output line 12b of column (n+1). Switch 195 is controlled to be on or off by a control signal vl_sw from timing generator 15. When control signal vl_sw is high, switch 195 is on, and when control signal vl_sw is low, switch 195 is off. When switch 195 is on, the analog signals of output line 12a of column n and output line 12b of column (n+1) are averaged.

[0118] Switch 214 is controlled by the control signal camp_res from the timing generator 15 and is controlled to be on or off. When switch 214 changes from the on state to the off state, the reset state of amplifier unit 21 is canceled, and the potential input to input capacitor 211 is clamped at this time. Due to the other circuit construction and Figure 5 The construction is the same as that in the previous example, so its description is omitted.

[0119] Figure 10 This is a timing diagram illustrating the driving method of the photoelectric conversion device according to this embodiment. Figure 10 In addition to with Figure 3A In addition to the same signals, the levels of control signals camp_res and vl_sw, the potential vline[n] of output line 12a in column n, and the potential vline[n+1] of output line 12b in column (n+1) are also shown. Because Figure 10 Operations from time t11 to time t17 in the middle Figure 3A The operations shown are the same, so their description is omitted.

[0120] At time t40, the control signal vl_sw goes high. As a result, switch 195 is turned on, and the analog signals of output line 12a in column n and output line 12b in column (n+1) are averaged. At time t40, the control signal camp_res goes high. As a result, switch 214 is turned on, and amplifier unit 21 is reset.

[0121] At time t41, the control signal vl_sw goes low. As a result, switch 195 is turned off, and the averaging of the analog signal on the output line 12a of column n and the analog signal on the output line 12b of column (n+1) is canceled.

[0122] At time t42, the control signal camp_res goes low, and switch 214 is turned off. When switch 214 transitions from the on state to the off state, the reset state of amplifier unit 21 is canceled, and the potential input to input capacitor 211 is clamped. Time t42 is the time after the averaging of the analog signal of output line 12a of column n and the analog signal of output line 12b of column (n+1) is canceled at time t41, and before the analog signals of each column output line return to their original potentials. In this operation, the potential of input capacitor 211 is clamped at time t42.

[0123] After time t42, the potentials of output lines 12a and 12b return to their pre-averaging potentials. Therefore, a difference ΔV' appears between the potential clamped to input capacitor 211 and the potentials of output lines 12a and 12b during AD conversion. Thus, as in the first embodiment, the levels of the output signals of the multiple comparators 232 are unlikely to reverse simultaneously within a short time, and noise generated when the levels of the output signals of the comparators 232 in each column change can be reduced. The potential clamped to input capacitor 211 is determined based on the characteristic changes of pixel 100. Therefore, the timing dispersion of the output signal level changes relative to the coordinates of pixel 100 in pixel array 10 is irregular. Therefore, the impact on image quality due to this dispersion can be made less noticeable.

[0124] Furthermore, the photoelectric conversion device of this embodiment can have a configuration that allows the gain to be changed by altering the setting of the amplification unit 21 or the amount (slope) of the change in the potential of the reference signal Vramp per unit time. In this case, for example, the time interval between time t41 and time t42 can vary depending on the gain. Furthermore, the timing distribution of the level change of the comparator 232's output signal can vary depending on the gain. Additionally, the noise level caused by the change in the output signal level can vary depending on the gain of the photoelectric conversion device. Therefore, since the optimal control method can vary depending on the gain, it is desirable to change the operation of the switch 195.

[0125] In addition, Figure 9 In its construction, the potential of the reference signal Vramp can vary depending on the column when the offset clamping operation is completed, and this construction can increase the timing distribution of the level change of the comparator 232's output signal. The reference... Figure 9 and Figure 11 Circuit diagram and Figure 12 The timing diagram is used to describe this variant example.

[0126] As mentioned above, Figure 9 The circuits for the nth and (n+1)th columns are shown. Additionally, Figure 11The circuits in columns (n+2) and (n+3) are shown. As described above, Figure 9 and Figure 11 The circuit diagram shows the construction of four consecutive columns of pixels 100 and column circuit 20. Columns (n+2) and (n+3) are sometimes simply referred to as the third and fourth columns, respectively. When it is necessary to distinguish elements in the two columns, an index "c" indicating that the element is in column (n+2) or an index "d" indicating that the element is in column (n+3) can be added. Figure 11 The diagram shows the reference numerals for some components. The output line 12c from pixel 100c in column (n+2) to its output signal can be referred to as the third output line, while the output line 12d from pixel 100d in column (n+3) to its output signal can be referred to as the fourth output line. Since the components in columns (n+2) and (n+3) have essentially the same construction as those in columns (n) and (n+1), except for the potential of the reference signal, a description of the circuit construction can be omitted.

[0127] like Figure 9 As shown, the reference signal Vramp is input from the reference signal generation circuit 16 to the input terminals of the amplifiers 235 in columns n and (n+1) of the array. Figure 11 As shown, a reference signal Vramp', different from the reference signal Vramp, is input from the reference signal generation circuit 16 to the input terminals of the amplifiers 235 in columns (n+2) and (n+3). Because... Figure 11 Other components shown in the diagram and Figure 9 The components shown are the same, so their descriptions are omitted.

[0128] Figure 12 This is a timing diagram illustrating a variant of the driving method for the photoelectric conversion device according to this embodiment. Besides... Figure 10 In addition to the same signal, Figure 12 The potential of the reference signal Vramp' and the potentials of the input signals comp_in[n+2] and comp_in[n+3] are also shown. Figure 12 The potentials vline[n] and vline[n+1] are not shown. During the time interval from time t40 to time t42, the reference signal Vramp and the reference signal Vramp' are at the same potential. This is because the operation during time intervals other than t51, t52, t53, and t54 is different from... Figure 10 The operations are basically the same, so their descriptions can be omitted or simplified.

[0129] At time t51, the reference signals Vramp in columns n and (n+1) are set to a first offset level. The reference signals Vramp' in columns (n+2) and (n+3) are set to a second offset level. The second offset level of the reference signal Vramp' is set to a higher potential than the first offset level of the reference signal Vramp.

[0130] At time t52, the control signal comp_res goes low. As a result, switches 233 and 234 are turned off. The potentials at the second input terminals of comparators 232 in columns n and (n+1) at time t52 are based on the reset potential of the reference signal Vramp, which serves as the first offset level. The potentials at the second input terminals of comparators 232 in columns (n+2) and (n+3) at time t52 are based on the reset potential of the reference signal Vramp', which serves as the second offset level.

[0131] At time t53, the settings of reference signals Vramp and Vramp' to the first offset level and the second offset level are cancelled. As a result, the potentials of reference signals Vramp and Vramp' return to their potentials at the time point prior to time t51.

[0132] Time t16 is the time when the potential of the reference signal Vramp exceeds the first offset level. Around time t16, the amplitude relationship between the input signals comp_in[n] and comp_in[n+1] and the reference signal Vramp is reversed, and the output levels of the comparators 232 in the nth and (n+1)th columns change.

[0133] Time t54 is the time when the potential of the reference signal Vramp' exceeds the second offset level. Near time t54, the amplitude relationship between the input signals comp_in[n+2] and comp_in[n+3] and the reference signal Vramp' is reversed, and the levels of the output signals of comparators 232 in columns (n+2) and (n+3) change.

[0134] As described above, the timing of the level change of the comparator 232 output signal in columns n and (n+1) is different from the timing of the level change of the comparator 232 output signal in columns (n+2) and (n+3). Therefore, according to this variant, such as Figure 12 As indicated by "Var", the timing of the level change of the comparator 232 output signal in each column can be increased.

[0135] [Sixth Embodiment]

[0136] The photoelectric conversion device described above can be applied to various devices. Examples of such devices include digital still cameras, digital video cameras, camera lenses, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Figure 13 This is a block diagram of a digital still camera, used as an example of a device.

[0137] Figure 13 The device 70 shown includes a barrier 706, a lens 702, an aperture 704, and an imaging device 700 (an example of a photoelectric conversion device). The device 70 also includes a signal processing unit (processing device) 708, a timing generation unit 720, an overall control / operation unit 718 (control device), a memory unit 710 (storage device), a storage medium control I / F unit 716, a storage medium 714, and an external I / F unit 712. At least one of the barrier 706, lens 702, and aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of the subject on the imaging device 700. The aperture 704 changes the amount of light passing through the lens 702. The imaging device 700 is constructed as described in the above embodiment and converts the optical image formed by the lens 702 into image data (image signal). The signal processing unit 708 performs various corrections, data compression, etc., on the imaging data output from the imaging device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / operation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The storage medium control I / F unit 716 is an interface for storing or retrieving image data on the storage medium 714, and the storage medium 714 is a removable storage medium, such as a semiconductor memory, for storing or retrieving captured image data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals, etc., can be input from outside the device. The device 70 may also include a display device (monitor, electronic viewfinder, etc.) for displaying information obtained by the photoelectric conversion device. The device includes at least a photoelectric conversion device. Furthermore, the device 70 includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (e.g., a robotic arm) that receives signals from the photoelectric conversion device to perform operations.

[0138] Each pixel may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process pixel signals based on the charge generated in the first photoelectric conversion unit and pixel signals based on the charge generated in the second photoelectric conversion unit, and to acquire distance information from the imaging device 700 to the subject.

[0139] [Seventh Embodiment]

[0140] Figure 14A and Figure 14B This is a block diagram of a device related to an in-vehicle camera according to this embodiment. Device 80 includes an imaging device 800 (an example of a photoelectric conversion device) as described in the above embodiment and a signal processing device (processing unit) that processes signals from the imaging device 800. Device 80 includes an image processing unit 801 that performs image processing on multiple image data acquired by the imaging device 800, and a disparity calculation unit 802 that calculates disparity (phase difference of a disparity image) based on the multiple image data acquired by device 80. Device 80 includes a distance measurement unit 803 that calculates the distance to an object based on the calculated disparity, and a collision determination unit 804 that determines whether a collision is possible based on the calculated distance. Here, the disparity calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition units that acquire distance information to an object. That is, the distance information is information about disparity, defocus, distance to an object, etc. The collision determination unit 804 can use any of this distance information to determine the likelihood of a collision. The distance information acquisition unit can be implemented by a specially designed hardware or software module. Furthermore, the distance information acquisition unit can be implemented by a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a combination thereof.

[0141] Device 80 is connected to vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Furthermore, device 80 is connected to control ECU 820, which acts as a control device and outputs control signals to generate braking force on the vehicle based on the determination result of collision determination unit 804. Device 80 is also connected to alarm device 830, which issues an alarm to the driver based on the determination result of collision determination unit 804. For example, when the collision probability is high according to the determination result of collision determination unit 804, control ECU 820 performs vehicle control to avoid a collision or reduce damage by braking, releasing the accelerator pedal, suppressing engine output, etc. Alarm device 830 warns the user by emitting alarms such as sound, displaying alarm information on a screen such as a car navigation system, or applying vibration to the seat belt or steering wheel. Device 80 acts as a control unit that controls the aforementioned vehicle operation.

[0142] In this embodiment, device 80 captures images of the vehicle's periphery (e.g., the front or rear). Figure 14B The device is shown in the case of capturing an image in front of the vehicle (camera range 850). The vehicle information acquisition device 810, which acts as an imaging control unit, sends instructions to the device 80 or the imaging device 800 to perform the imaging operation. With this configuration, the accuracy of distance measurement can be further improved.

[0143] While examples of controls for avoiding collisions with other vehicles have been described above, this embodiment is applicable to autonomous driving controls for following other vehicles, autonomous driving controls for not deviating from the driving lane, and so on. Furthermore, the device is not limited to vehicles such as automobiles, and can also be applied to mobile bodies (mobile devices) such as ships, aircraft, satellites, industrial robots, and civilian robots. In addition, the device can be widely applied to devices utilizing object recognition or biometric authentication, such as intelligent transportation systems (ITS), monitoring systems, etc., and is not limited to mobile bodies.

[0144] [Variant Implementation]

[0145] This invention is not limited to the embodiments described above, and various modifications are possible. For example, examples where some constructions of any embodiment are added to other embodiments or where some constructions of any embodiment are replaced with constructions of other embodiments are also embodiments of the invention. Note that although an example of providing one column circuit for a column of pixels is described in this specification, multiple output lines can be provided for a column of pixels. In this case, pixels in some rows are connected to some of the multiple output lines, while pixels in other rows are connected to other output lines. Each of the multiple output lines can be equipped with a column circuit. Alternatively, a column circuit can be provided for multiple columns of pixels.

[0146] The disclosure in this specification includes the complement of the concepts described herein. That is, for example, if the description "A is B" (A = B) is provided in this specification, even if the description "A is not B" (A ≠ B) is omitted, this specification is intended to disclose or imply "A is not B". This is because it is assumed that "A is not B" is taken into account when describing "A is B".

[0147] The disclosure in this specification includes the following structure.

[0148] (Construction 1)

[0149] A photoelectric conversion device, comprising:

[0150] Multiple pixels;

[0151] Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively;

[0152] An amplification unit is arranged corresponding to each of the plurality of output lines and is configured to amplify the signal output to the corresponding output line;

[0153] A comparison unit, arranged corresponding to each of the plurality of output lines, and having a first input terminal and a second input terminal, wherein a signal corresponding to the output of the amplification unit is input to the first input terminal, and a reference signal is input to the second input terminal; and

[0154] A switch having a first terminal and a second terminal,

[0155] The plurality of output lines include a first output line and a second output line.

[0156] The first terminal is connected to the node between the amplification unit corresponding to the first output line and the comparison unit corresponding to the first output line.

[0157] The second terminal is connected to the node between the amplification unit corresponding to the second output line and the comparison unit corresponding to the second output line.

[0158] The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first and second input terminals, and

[0159] The switch is turned on during the period prior to the completion of the offset clamping operation.

[0160] (Construction 2)

[0161] According to the photoelectric conversion device described in configuration 1, the photoelectric conversion device further includes:

[0162] Holding capacitors, which are arranged corresponding to each of the plurality of output lines, are configured to hold the signal output from the amplification unit.

[0163] Wherein, the first terminal is connected to the holding capacitor of the first output line, and

[0164] The second terminal is connected to the holding capacitor of the second output line.

[0165] (Construction 3)

[0166] According to the photoelectric conversion device described in configuration 1, the photoelectric conversion device further includes:

[0167] The first input capacitor is arranged corresponding to each of the plurality of output lines.

[0168] The signal corresponding to the output of the amplification unit is input to the first input terminal via the first input capacitor.

[0169] Wherein, the first terminal is connected to the first input capacitor of the first output line, and

[0170] The second terminal is connected to the first input capacitor of the second output line.

[0171] (Construction 4)

[0172] According to the photoelectric conversion device described in configuration 3, the photoelectric conversion device further includes:

[0173] Holding capacitors, which are arranged corresponding to each of the plurality of output lines and configured to hold the signal output from the amplification unit; and

[0174] A first buffer, which is arranged corresponding to each of the plurality of output lines, and is positioned between the holding capacitor and the first input capacitor.

[0175] Wherein, the first terminal is connected to the node between the first buffer corresponding to the first output line and the first input capacitor corresponding to the first output line, and

[0176] The second terminal is connected to the node between the first buffer corresponding to the second output line and the first input capacitor corresponding to the second output line.

[0177] (Construction 5)

[0178] A photoelectric conversion device, comprising:

[0179] Multiple pixels;

[0180] Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively;

[0181] An amplification unit is arranged corresponding to each of the plurality of output lines and is configured to amplify the signal output to the corresponding output line;

[0182] A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the amplification unit is input to the first input terminal, and a reference signal is input to the second input terminal.

[0183] A second input capacitor is arranged corresponding to each of the plurality of output lines; and

[0184] A switch having a first terminal and a second terminal,

[0185] The reference signal is input to the second input terminal via the second input capacitor.

[0186] The plurality of output lines include a first output line and a second output line.

[0187] The first terminal is connected to the second input capacitor corresponding to the first output line.

[0188] The second terminal is connected to the second input capacitor corresponding to the second output line.

[0189] The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first and second input terminals, and

[0190] The switch is turned on during the period prior to the completion of the offset clamping operation.

[0191] (Construction 6)

[0192] According to the photoelectric conversion device described in configuration 5, the photoelectric conversion device further includes:

[0193] A second buffer, which is arranged correspondingly to each of the plurality of output lines, and is positioned between the signal line to which the reference signal is supplied and the second input capacitor.

[0194] Wherein, the first terminal is connected to the node between the second buffer corresponding to the first output line and the second input capacitor corresponding to the first output line, and

[0195] The second terminal is connected to the node between the second buffer corresponding to the second output line and the second input capacitor corresponding to the second output line.

[0196] (Construction 7)

[0197] According to any one of constructions 1 to 6, the operation of the switch varies depending on the gain setting of the amplification unit.

[0198] (Construction 8)

[0199] According to any one of constructions 1 to 7, the operation of the switch varies depending on the gain setting of the comparison unit.

[0200] (Construction 9)

[0201] According to any one of constructions 1 to 8, the operation of the switch varies according to the change in the potential of the reference signal per unit time.

[0202] (Construction 10)

[0203] According to any one of constructions 1 to 9, the operation of the switch varies depending on the temperature of the photoelectric conversion device.

[0204] (Construction 11)

[0205] According to any one of constructions 1 to 10, the photoelectric conversion device is wherein the switch is turned off after the offset clamping operation is completed.

[0206] (Construction 12)

[0207] According to any one of the constructions 1 to 10, the photoelectric conversion device is wherein the offset clamping operation is performed after the switch is turned on and then off.

[0208] (Construction 13)

[0209] According to the photoelectric conversion device described in configuration 12, the potential of the reference signal begins to change over time after the switch is turned off.

[0210] (Construction 14)

[0211] According to any one of constructions 1 to 13, the photoelectric conversion device further includes:

[0212] The output line connects to a switch, which has a third terminal and a fourth terminal.

[0213] The third terminal is connected to the node between the pixel corresponding to the first output line and the amplification unit corresponding to the first output line, and

[0214] The fourth terminal is connected to the node between the pixel corresponding to the second output line and the amplification unit corresponding to the second output line.

[0215] (Construction 15)

[0216] According to the photoelectric conversion device described in configuration 14, the output line connection switch is turned on during the period before the offset clamping operation is completed.

[0217] (Construction 16)

[0218] According to any one of constructions 1 to 15, the photoelectric conversion device further includes a third output line.

[0219] Specifically, at the time point when the offset clamping operation is completed, the potential of the reference signal input to the comparison unit corresponding to the first output line and the potential of the reference signal input to the comparison unit corresponding to the third output line are different from each other.

[0220] (Construction 17)

[0221] A photoelectric conversion device, comprising:

[0222] Multiple pixels;

[0223] Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively;

[0224] A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the output line is input to the first input terminal, and a reference signal is input to the second input terminal.

[0225] A switch having a first terminal and a second terminal; and

[0226] The first input capacitor is arranged corresponding to each of the plurality of output lines.

[0227] The signal corresponding to the output of the output line is input to the first input terminal via the first input capacitor.

[0228] The plurality of output lines include a first output line and a second output line.

[0229] The first terminal is connected to the first input capacitor corresponding to the first output line.

[0230] The second terminal is connected to the first input capacitor corresponding to the second output line.

[0231] The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal.

[0232] During the period prior to completing the offset clamping operation, the switch is turned on, and

[0233] After the offset clamping operation is completed, the switch is turned off.

[0234] (Construction 18)

[0235] A photoelectric conversion device, comprising:

[0236] Multiple pixels;

[0237] Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively;

[0238] A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the output line is input to the first input terminal, and a reference signal is input to the second input terminal.

[0239] A second input capacitor is arranged corresponding to each of the plurality of output lines; and

[0240] A switch having a first terminal and a second terminal,

[0241] The reference signal is input to the second input terminal via the second input capacitor.

[0242] The plurality of output lines include a first output line and a second output line.

[0243] The first terminal is connected to the second input capacitor corresponding to the first output line.

[0244] The second terminal is connected to the second input capacitor corresponding to the second output line.

[0245] The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal.

[0246] During the period prior to completing the offset clamping operation, the switch is turned on, and

[0247] After the offset clamping operation is completed, the switch is turned off.

[0248] (Construction 19)

[0249] An apparatus comprising:

[0250] The photoelectric conversion device according to any one of constructions 1 to 18; and

[0251] Any of the following devices:

[0252] An optical device suitable for the photoelectric conversion device;

[0253] A control device configured to control the photoelectric conversion device;

[0254] A processing device configured to process signals output from the photoelectric conversion device;

[0255] A display device configured to display information obtained by the photoelectric conversion device;

[0256] A storage device configured to store information obtained by the photoelectric conversion device; and

[0257] A mechanical device configured to operate based on information obtained from the photoelectric conversion device.

[0258] (Construction 20)

[0259] According to the device described in configuration 19, the processing device processes image signals generated by a plurality of photoelectric conversion units of the photoelectric conversion device and obtains distance information about the distance from the photoelectric conversion device to the subject.

[0260] Embodiments of the invention can also be implemented by a computer that reads and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (also more fully referred to as a "non-transitory computer-readable storage medium") to perform one or more functions in the above embodiments, and / or includes a system or apparatus comprising one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing one or more functions in the above embodiments. Furthermore, embodiments of the invention can be implemented using a method by which the computer of the system or apparatus, for example, reads and executes the computer-executable instructions from the storage medium to perform one or more functions in the above embodiments, and / or controls the one or more circuits to perform one or more functions in the above embodiments. The computer may include one or more processors (e.g., central processing unit (CPU), microprocessor unit (MPU)) and may include separate computers or a network of separate processors to read and execute the computer-executable instructions. The computer-executable instructions may be supplied to the computer, for example, from a network or the storage medium. The storage medium may include, for example, a hard disk, random access memory (RAM), read-only memory (ROM), the memory of a distributed computing system, or an optical disc (such as a compact disc (CD), a digital versatile optical disc (DVD), or a Blu-ray disc (BD)). TM One or more of the following: flash memory devices and memory cards.

[0261] Other embodiments

[0262] The embodiments of the present invention can also be implemented by supplying software (programs) that perform the functions of the above embodiments to a system or device via a network or various storage media, and the computer or central processing unit (CPU) or microprocessor unit (MPU) of the system or device reads out and executes the program.

[0263] Although the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The appended claims should be interpreted in the broadest possible sense to encompass all such variations and equivalent structures and functions.

Claims

1. A photoelectric conversion device, comprising: Multiple pixels; Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively; An amplification unit is arranged corresponding to each of the plurality of output lines and is configured to amplify the signal output to the corresponding output line; A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the amplification unit is input to the first input terminal, and a reference signal is input to the second input terminal. A switch having a first terminal and a second terminal; as well as The output line connects to a switch, which has a third terminal and a fourth terminal. The plurality of output lines include a first output line and a second output line. The first terminal is connected to the node between the amplification unit corresponding to the first output line and the comparison unit corresponding to the first output line. The second terminal is connected to the node between the amplification unit corresponding to the second output line and the comparison unit corresponding to the second output line. The third terminal is connected to the node between the pixel corresponding to the first output line and the amplification unit corresponding to the first output line. The fourth terminal is connected to the node between the pixel corresponding to the second output line and the amplification unit corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first and second input terminals, and The switch is turned on during the period prior to the completion of the offset clamping operation.

2. The photoelectric conversion device according to claim 1, further comprising: Holding capacitors, which are arranged corresponding to each of the plurality of output lines, are configured to hold the signal output from the amplification unit. Wherein, the first terminal is connected to the holding capacitor of the first output line, and The second terminal is connected to the holding capacitor of the second output line.

3. The photoelectric conversion device according to claim 1, further comprising: The first input capacitor is arranged corresponding to each of the plurality of output lines. The signal corresponding to the output of the amplification unit is input to the first input terminal via the first input capacitor. Wherein, the first terminal is connected to the first input capacitor of the first output line, and The second terminal is connected to the first input capacitor of the second output line.

4. The photoelectric conversion device according to claim 3, further comprising: A holding capacitor is arranged corresponding to each of the plurality of output lines and is configured to hold the signal output from the amplification unit; as well as A first buffer, which is arranged corresponding to each of the plurality of output lines, and is positioned between the holding capacitor and the first input capacitor. Wherein, the first terminal is connected to the node between the first buffer corresponding to the first output line and the first input capacitor corresponding to the first output line, and The second terminal is connected to the node between the first buffer corresponding to the second output line and the first input capacitor corresponding to the second output line.

5. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The operation of the switch varies depending on the gain setting of the amplification unit.

6. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The operation of the switch varies depending on the gain setting of the comparison unit.

7. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The operation of the switch varies according to the change in the potential of the reference signal per unit time.

8. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The operation of the switch varies depending on the temperature of the photoelectric conversion device.

9. The photoelectric conversion device according to any one of claims 1 to 4, wherein, After the offset clamping operation is completed, the switch is turned off.

10. The photoelectric conversion device according to any one of claims 1 to 4, wherein, The offset clamping operation is completed after the switch is turned on and then off.

11. The photoelectric conversion device according to claim 10, wherein, After the switch is turned off, the potential of the reference signal begins to change over time.

12. The photoelectric conversion device according to claim 1, wherein, During the period prior to completing the offset clamping operation, the output line connection switch is turned on.

13. A photoelectric conversion device, comprising: Multiple pixels; Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively; An amplification unit is arranged corresponding to each of the plurality of output lines and is configured to amplify the signal output to the corresponding output line; A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the amplification unit is input to the first input terminal, and a reference signal is input to the second input terminal. as well as A switch having a first terminal and a second terminal, The plurality of output lines include a first output line, a second output line, and a third output line. The first terminal is connected to the node between the amplification unit corresponding to the first output line and the comparison unit corresponding to the first output line. The second terminal is connected to the node between the amplification unit corresponding to the second output line and the comparison unit corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal. During the period prior to completing the offset clamping operation, the switch is turned on, and Specifically, at the time point when the offset clamping operation is completed, the potential of the reference signal input to the comparison unit corresponding to the first output line and the potential of the reference signal input to the comparison unit corresponding to the third output line are different from each other.

14. A photoelectric conversion device, comprising: Multiple pixels; Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively; An amplification unit is arranged corresponding to each of the plurality of output lines and is configured to amplify the signal output to the corresponding output line; A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the amplification unit is input to the first input terminal, and a reference signal is input to the second input terminal. A second input capacitor is arranged corresponding to each of the plurality of output lines; as well as A switch having a first terminal and a second terminal, The reference signal is input to the second input terminal via the second input capacitor. The plurality of output lines include a first output line and a second output line. The first terminal is connected to the second input capacitor corresponding to the first output line. The second terminal is connected to the second input capacitor corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first and second input terminals, and The switch is turned on during the period prior to the completion of the offset clamping operation.

15. The photoelectric conversion device according to claim 14, further comprising: A second buffer, which is arranged correspondingly to each of the plurality of output lines, and is positioned between the signal line to which the reference signal is supplied and the second input capacitor. Wherein, the first terminal is connected to the node between the second buffer corresponding to the first output line and the second input capacitor corresponding to the first output line, and The second terminal is connected to the node between the second buffer corresponding to the second output line and the second input capacitor corresponding to the second output line.

16. A photoelectric conversion device, comprising: Multiple pixels; Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively; A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the output line is input to the first input terminal, and a reference signal is input to the second input terminal. A switch having a first terminal and a second terminal; A first input capacitor is arranged corresponding to each of the plurality of output lines; as well as The output line connects to a switch, which has a third terminal and a fourth terminal. The signal corresponding to the output of the output line is input to the first input terminal via the first input capacitor. The plurality of output lines include a first output line and a second output line. The first terminal is connected to the first input capacitor corresponding to the first output line. The second terminal is connected to the first input capacitor corresponding to the second output line. The third terminal is connected to the node between the pixel corresponding to the first output line and the amplification unit corresponding to the first output line. The fourth terminal is connected to the node between the pixel corresponding to the second output line and the amplification unit corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal. During the period prior to completing the offset clamping operation, the switch is turned on, and After the offset clamping operation is completed, the switch is turned off.

17. A photoelectric conversion device, comprising: Multiple pixels; Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively; A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the output line is input to the first input terminal, and a reference signal is input to the second input terminal. A switch having a first terminal and a second terminal; as well as The first input capacitor is arranged corresponding to each of the plurality of output lines. The signal corresponding to the output of the output line is input to the first input terminal via the first input capacitor. The plurality of output lines include a first output line, a second output line, and a third output line. The first terminal is connected to the first input capacitor corresponding to the first output line. The second terminal is connected to the first input capacitor corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal. During the period prior to completing the offset clamping operation, the switch is turned on. After the offset clamping operation is completed, the switch is turned off, and Specifically, at the time point when the offset clamping operation is completed, the potential of the reference signal input to the comparison unit corresponding to the first output line and the potential of the reference signal input to the comparison unit corresponding to the third output line are different from each other.

18. A photoelectric conversion device, comprising: Multiple pixels; Multiple output lines, and signals from corresponding pixels are output to the multiple output lines respectively; A comparison unit is arranged corresponding to each of the plurality of output lines and has a first input terminal and a second input terminal. A signal corresponding to the output of the output line is input to the first input terminal, and a reference signal is input to the second input terminal. A second input capacitor is arranged corresponding to each of the plurality of output lines; as well as A switch having a first terminal and a second terminal, The reference signal is input to the second input terminal via the second input capacitor. The plurality of output lines include a first output line and a second output line. The first terminal is connected to the second input capacitor corresponding to the first output line. The second terminal is connected to the second input capacitor corresponding to the second output line. The comparison unit is configured to perform an offset clamping operation based on the potentials input to the first input terminal and the second input terminal. During the period prior to completing the offset clamping operation, the switch is turned on, and After the offset clamping operation is completed, the switch is turned off.

19. An apparatus comprising a photoelectric conversion device according to any one of claims 1 to 18, the apparatus further comprising: Any of the following devices: An optical device suitable for the photoelectric conversion device; A control device configured to control the photoelectric conversion device; A processing device configured to process signals output from the photoelectric conversion device; A display device configured to display information obtained by the photoelectric conversion device; A storage device configured to store information obtained by the photoelectric conversion device; as well as A mechanical device configured to operate based on information obtained from the photoelectric conversion device.

20. The device according to claim 19, wherein, The processing device processes the image signals generated by the multiple photoelectric conversion units of the photoelectric conversion device, and obtains distance information about the distance from the photoelectric conversion device to the subject.

Images