A three-dimensional SONOS type FLASH device facing storage and calculation integration and a working method thereof

Abstract

The application discloses a three-dimensional SONOS type FLASH device facing integration of storage and calculation and a working method thereof, and belongs to the semiconductor field.The three-dimensional SONOS type FLASH device comprises a silicon substrate, a shallow trench isolation, a drain end, a gate oxide layer, a selection tube polysilicon layer, a side wall, an oxide-nitride-oxide dielectric layer, a SONOS tube polysilicon layer, a silicon channel region, a source end, a dielectric layer and a source end metal layer; the shallow trench isolation and the drain end are located above the silicon substrate; the gate oxide layer and the selection tube polysilicon layer are located above the shallow trench isolation; the side wall is located on the top of the selection tube polysilicon layer; the oxide-nitride-oxide dielectric layer and the SONOS tube polysilicon layer are located above the side wall; the silicon channel region is located above the drain end; the source end is located on the top of the silicon channel region; the dielectric layer is located on the top of the SONOS tube polysilicon layer; and the source end metal layer is covered on the topmost part. Programming and erasing operations are realized by changing the potential of the source end and the drain end, the number of stored electrons in the silicon nitride is changed, the device unit area is reduced, and the drain disturbance is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a three-dimensional SONOS-type FLASH device for in-memory computing and its operating method. Background Technology

[0002] With the development of cloud computing and artificial intelligence (AI) applications in recent years, AI has made tremendous progress in areas such as speech recognition, virtual assistants, and machine learning platforms, leading to an explosive growth in data for intelligent applications. However, in the traditional von Neumann computing architecture, data must be transferred back and forth between the central processing unit (CPU) and memory units. Because the throughput of data exchange between computing and storage is far lower than the CPU's operating speed, it severely limits data processing speed and increases memory read power consumption, i.e., the "memory wall" and "power wall" problems. Moreover, as processor performance continues to improve, the "memory wall" and "power wall" problems become increasingly prominent.

[0003] Addressing the bottlenecks in storage and computing, solutions based on the concept of in-memory computing were proposed as early as 1969. With decreasing hardware costs, enhanced operating system scalability, and faster real-time data access, in-memory computing technology using non-von Neumann architectures has become one of the mainstream technologies in the post-Moore's Law era in recent years. It features massive parallelism, distributed storage and processing, self-organization, and self-adaptation, thus effectively reducing power consumption and increasing computing power. Therefore, promoting the domestic development of high-performance, low-power in-memory computing architectures has become a hot research topic in my country's integrated circuit field. Summary of the Invention

[0004] The purpose of this invention is to provide a three-dimensional SONOS-type FLASH device for in-memory computing and its operating method, so as to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a three-dimensional SONOS-type FLASH device for in-memory computing, comprising a silicon substrate, shallow trench isolation, drain terminal, gate oxide layer, select transistor polysilicon layer, sidewall, oxide-nitride-oxide dielectric layer, SONOS transistor polysilicon layer, silicon channel region, source terminal, dielectric layer, and source terminal metal layer.

[0006] The shallow trench isolation and the drain terminal are both located above the silicon substrate, and the shallow trench isolation and the drain terminal are arranged at intervals; the gate oxide layer and the select transistor polysilicon layer are both located above the shallow trench isolation, and the gate oxide layer is located to the side of the select transistor polysilicon layer;

[0007] The sidewall is located on top of the select transistor polysilicon layer and is in contact with the gate oxide layer; the oxide-nitride-oxide dielectric layer and the SONOS transistor polysilicon layer are both located above the sidewall, and the SONOS transistor polysilicon layer is located to the side of the oxide-nitride-oxide dielectric layer;

[0008] The silicon channel region is located above the drain end and to the side of the gate oxide layer and the oxide-nitride-oxide dielectric layer; the source end is located at the top of the silicon channel region and to the side of the oxide-nitride-oxide dielectric layer, the top surface of the source end is horizontal with the oxide-nitride-oxide dielectric layer, and both are higher than the top surface of the SONOS transistor polysilicon layer.

[0009] The dielectric layer is located on top of the polysilicon layer of the SONOS transistor, and the top surface of the dielectric layer is higher than the source end and the oxide-nitride-oxide dielectric layer; the source end metal layer is located on top of the oxide-nitride-oxide dielectric layer, the source end, and the dielectric layer.

[0010] In one embodiment, the oxide thickness of the gate oxide layer is The thickness of the polysilicon layer of the selector is: The thickness of the gate oxide layer is less than that of the selector polysilicon layer.

[0011] In one embodiment, the doping concentration of the silicon channel region is greater than the doping concentration of the silicon substrate.

[0012] In one embodiment, the sidewall is composed of silicon dioxide and silicon nitride, and the top surface of the sidewall is horizontal with the gate oxide layer, that is, the sum of the heights of the selector polysilicon layer and the sidewall is equal to the height of the gate oxide layer.

[0013] In one embodiment, the thickness of the polysilicon layer of the SONOS transistor is [missing information]. In the oxide-nitride-oxide dielectric layer, the thickness of the bottom oxide layer is... The thickness of the middle nitride layer is The thickness of the top oxide medium is

[0014] In one embodiment, the drain, the selector polysilicon layer, the SONOS polysilicon layer, and the source are all N-type doped.

[0015] This invention also provides a method for operating a three-dimensional SONOS-type FLASH device for in-memory computing. The erasure process of the three-dimensional SONOS-type FLASH device structure is as follows: a negative potential is applied to the drain terminal, the polysilicon layer of the select transistor, the source terminal, and the silicon substrate, and a positive potential is applied to the polysilicon layer of the SONOS transistor. That is, a negative voltage is applied to the word line WL of the three-dimensional SONOS-type FLASH device to be erased in the array, while a positive voltage is applied to the gate terminal SG of the select transistor, the bit line BL, the source line SL, and the substrate. This releases electrons in the oxide-nitride-oxide dielectric layer. At this time, the threshold voltage of the SONOS transistor is the erase state threshold voltage, which reduces the erasure time and increases the erasure efficiency.

[0016] In one embodiment, the drain programming process of the three-dimensional SONOS type FLASH device structure is as follows: a negative potential is applied to the drain terminal and the polysilicon layer of the select transistor, a positive potential is applied to the polysilicon layer of the SONOS transistor, the source terminal is grounded, and the silicon substrate is floated. That is, a negative voltage is applied to the bit line BL and the gate terminal SG of the three-dimensional SONOS type FLASH device to be pre-programmed at the drain in the array, wherein the gate terminal voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor. A positive voltage is applied to the word line WL, the source line SL is grounded, and the substrate is floated, so that the oxide-nitride-oxide dielectric layer performs drain electron storage.

[0017] In one embodiment, the source-side programming process of the three-dimensional SONOS-type FLASH device structure is as follows: a negative potential is applied to the source end and the polysilicon layer of the select transistor, a positive potential is applied to the polysilicon layer of the SONOS transistor, the drain end is grounded, and the silicon substrate is floated. That is, a negative voltage is applied to the source line SL and the gate end SG of the pre-programmed three-dimensional SONOS-type FLASH device in the array, wherein the gate end voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor. A positive voltage is applied to the word line WL, the bit line BL is grounded, and the substrate is floated, so that the oxide-nitride-oxide dielectric layer performs source-side electron storage. After programming operations are performed at both the source end and the drain end, the threshold voltage of the SONOS transistor is the programming state threshold voltage.

[0018] In one embodiment, the working process of the three-dimensional SONOS type FLASH device structure is as follows: a negative potential is applied to the drain terminal and the polysilicon layer of the select transistor, and a potential is applied to the polysilicon layer of the SONOS transistor, so that the potential is between the programming state and the erase state threshold voltage. The source terminal is grounded and the silicon substrate is floated, that is, a negative voltage is applied to the bit line BL and the gate terminal SG of the three-dimensional SONOS type FLASH device pre-programmed at the source terminal in the array, wherein the gate terminal voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor. The source line SL is grounded and the substrate is floated. A certain voltage value is applied to the word line WL, so that the word line voltage is between the programming state threshold voltage and the erase state threshold voltage of the three-dimensional SONOS type FLASH device, thereby putting the three-dimensional SONOS type FLASH device into the working state.

[0019] In the three-dimensional SONOS-type FLASH device and its working method for in-memory computing provided by the present invention, the programming and erasing operations of the three-dimensional SONOS-type FLASH device are performed by changing the potential of the source and drain terminals, thereby changing the number of electrons stored in silicon nitride, effectively increasing the number of resistive states of the three-dimensional SONOS-type FLASH device, reducing the area, and reducing leakage interference in the array. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a three-dimensional SONOS-type FLASH device for in-memory computing proposed in this invention;

[0021] Figure 2 This is a schematic diagram of the erasure conditions for a three-dimensional SONOS-type FLASH device for in-memory computing proposed in this invention.

[0022] Figure 3 This is a schematic diagram of the drain programming conditions for a three-dimensional SONOS-type FLASH device for in-memory computing proposed in this invention.

[0023] Figure 4 This is a schematic diagram of the source-side programming conditions for a three-dimensional SONOS-type FLASH device for in-memory computing proposed in this invention.

[0024] Figure 5 This is a schematic diagram of the workflow of a three-dimensional SONOS-type FLASH device for in-memory computing proposed in this invention. Detailed Implementation

[0025] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the three-dimensional SONOS-type FLASH device for in-memory computing and its operating method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0026] This invention provides a three-dimensional SONOS-type FLASH device for in-memory computing, such as... Figure 1 As shown, it includes a silicon substrate 1, a shallow trench isolation 2, a drain terminal 3, a gate oxide layer 4, a select transistor polysilicon layer 5, a sidewall 6, an oxide-nitride-oxide dielectric layer 7, a SONOS transistor polysilicon layer 8, a silicon channel region 9, a source terminal 10, a dielectric layer 11, and a source terminal metal layer 12.

[0027] The shallow trench isolation 2 and the drain terminal 3 are both located above the silicon substrate 1, and the shallow trench isolation 2 and the drain terminal 3 are arranged at intervals; the drain terminal 3 is N-type doped. The gate oxide layer 4 and the select transistor polysilicon layer 5 are both located above the shallow trench isolation 2; the gate oxide layer 4 is located to the side of the select transistor polysilicon layer 5, and the height of the gate oxide layer 4 is higher than that of the select transistor polysilicon layer 5, wherein the oxide thickness of the gate oxide layer 4 is [missing information]. The polysilicon layer 5 of the selector is N-type doped, and its thickness is [missing information]. The thickness of the gate oxide layer 4 is less than that of the selector polysilicon layer 5.

[0028] The sidewall 6 is composed of silicon dioxide and silicon nitride, located on top of the selector polysilicon layer 5, and in contact with the gate oxide layer 4. The top surface of the sidewall 6 is horizontal with the gate oxide layer 4, that is, the sum of the heights of the selector polysilicon layer 5 and the sidewall 6 is equal to the height of the gate oxide layer 4.

[0029] Both the oxide-nitride-oxide dielectric layer 7 and the SONOS transistor polysilicon layer 8 are located above the sidewall 6, and the SONOS transistor polysilicon layer 8 is located to the side of the oxide-nitride-oxide dielectric layer 7. The SONOS transistor polysilicon layer 8 is N-type doped and has a thickness of [missing information]. In the oxide-nitride-oxide dielectric layer 7, the thickness of the bottom oxide layer is... The thickness of the middle nitride layer is The thickness of the top oxide medium is

[0030] The silicon channel region 9 is located above the drain terminal 3 and to the side of the gate oxide layer 4 and the oxide-nitride-oxide dielectric layer 7; wherein the doping concentration of the silicon channel region 9 is greater than the doping concentration of the silicon substrate 1.

[0031] The source terminal 10 is N-type doped, located at the top of the silicon channel region 9, and on the side of the oxide-nitride-oxide dielectric layer 7. The top surface of the source terminal 10 is horizontal with the oxide-nitride-oxide dielectric layer 7, and both are higher than the top surface of the SONOS tube polysilicon layer 8.

[0032] The dielectric layer 11 is located on top of the polysilicon layer 8 of the SONOS transistor, and the top surface of the dielectric layer 11 is higher than the source terminal 10 and the oxide-nitride-oxide dielectric layer 7. The source terminal metal layer 12 is located on top of the oxide-nitride-oxide dielectric layer 7, the source terminal 10, and the dielectric layer 11.

[0033] like Figure 2 As shown, the erasure process of a three-dimensional SONOS-type FLASH device for in-memory computing according to the present invention is as follows: a negative potential is applied to the drain terminal 3, the polysilicon layer 5 of the select transistor, the source terminal 10, and the silicon substrate 1, and a positive potential is applied to the polysilicon layer 8 of the SONOS transistor. That is, a negative voltage is applied to the word lines WL (including WL1 and WL2) of the three-dimensional SONOS-type FLASH device to be erased in the array, while a positive voltage is applied to the gate terminal SG (including SG1 and SG2), the bit line BL (including BL1 and BL2), the source line SL (including SL1 and SL2), and the substrate, so that electrons in the oxide-nitride-oxide dielectric layer 7 are released. At this time, the threshold voltage of the SONOS transistor is the erase state threshold voltage (ERS), which reduces the erasure time and increases the erasure efficiency.

[0034] like Figure 3 As shown, the drain programming process of a three-dimensional SONOS-type FLASH device for in-memory computing according to the present invention is as follows: a negative potential is applied to the drain terminal 3 and the polysilicon layer 5 of the select transistor, a positive potential is applied to the polysilicon layer 8 of the SONOS transistor, the source terminal 10 is grounded, and the silicon substrate 1 is floated. That is, a negative voltage is applied to the bit lines BL (including BL1 and BL2) and the gate terminals SG (including SG1 and SG2) of the three-dimensional SONOS-type FLASH device to be pre-drain programmed in the array, wherein the gate terminal voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor. A positive voltage is applied to the word lines WL (including WL1 and WL2), the source lines SL (including SL1 and SL2) are grounded, and the substrate is floated, so that the oxide-nitride-oxide dielectric layer 7 performs drain electron storage.

[0035] like Figure 4As shown, the source-side programming process of a three-dimensional SONOS-type FLASH device for in-memory computing according to the present invention is as follows: a negative potential is applied to the source terminal 10 and the polysilicon layer 5 of the select transistor, a positive potential is applied to the polysilicon layer 8 of the SONOS transistor, the drain terminal 3 is grounded, and the silicon substrate 1 is floated. That is, a negative voltage is applied to the source line SL (including SL1 and SL2) and the gate terminal SG (including SG1 and SG2) of the three-dimensional SONOS-type FLASH device pre-programmed in the array, wherein the gate terminal voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor. A positive voltage is applied to the word line WL (including WL1 and WL2), the bit line BL (including BL1 and BL2) is grounded, and the substrate is floated, so that the oxide-nitride-oxide dielectric layer 7 performs source-side electron storage. After programming operations are performed at both the source and drain terminals, the threshold voltage of the SONOS transistor is the programming state threshold voltage (PGM).

[0036] like Figure 5 As shown, the workflow of a three-dimensional SONOS-type FLASH device for in-memory computing according to the present invention is as follows: a negative potential is applied to the drain terminal 3 and the polysilicon layer 5 of the select transistor, and a potential is applied to the polysilicon layer 8 of the SONOS transistor (this potential depends on the programming state and erase state threshold voltages) so that the potential is between the programming state and erase state threshold voltages. The source terminal 10 is grounded and the silicon substrate 1 is floated, that is, a negative voltage is applied to the bit lines BL (including BL1 and BL2) and the gate terminals SG (including SG1 and SG2) of the three-dimensional SONOS-type FLASH device pre-programmed at the source terminal in the array, wherein the gate terminal voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor. The source lines SL (including SL1 and SL2) are grounded and the substrate is floated. A certain voltage value (located between ERS and PGM) is applied to the word lines WL (including WL1 and WL2) so that the word line voltage is between the programming state threshold voltage and the erase state threshold voltage of the three-dimensional SONOS-type FLASH device, thereby putting the three-dimensional SONOS-type FLASH device into the working state.

[0037] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A three-dimensional SONOS-type FLASH device for in-memory computing, characterized in that, It includes a silicon substrate (1), shallow trench isolation (2), drain terminal (3), gate oxide layer (4), select transistor polysilicon layer (5), sidewall (6), oxide-nitride-oxide dielectric layer (7), SONOS transistor polysilicon layer (8), silicon channel region (9), source terminal (10), dielectric layer (11) and source terminal metal layer (12); The shallow trench isolation (2) and the drain terminal (3) are both located above the silicon substrate (1), and the shallow trench isolation (2) and the drain terminal (3) are arranged at intervals; the gate oxide layer (4) and the select transistor polysilicon layer (5) are both located above the shallow trench isolation (2), and the gate oxide layer (4) is located to the side of the select transistor polysilicon layer (5); The sidewall (6) is located on top of the selector polysilicon layer (5) and is in contact with the gate oxide layer (4); the oxide-nitride-oxide dielectric layer (7) and the SONOS transistor polysilicon layer (8) are both located above the sidewall (6), and the SONOS transistor polysilicon layer (8) is located to the side of the oxide-nitride-oxide dielectric layer (7); The silicon channel region (9) is located above the drain end (3) and to the side of the gate oxide layer (4) and the oxide-nitride-oxide dielectric layer (7); the source end (10) is located at the top of the silicon channel region (9) and to the side of the oxide-nitride-oxide dielectric layer (7). The top surface of the source end (10) is horizontal to the oxide-nitride-oxide dielectric layer (7) and is higher than the top surface of the SONOS tube polysilicon layer (8). The dielectric layer (11) is located on top of the polysilicon layer (8) of the SONOS transistor, and the top surface of the dielectric layer (11) is higher than the source end (10) and the oxide-nitride-oxide dielectric layer (7); the source end metal layer (12) is located on top of the oxide-nitride-oxide dielectric layer (7), the source end (10) and the dielectric layer (11).

2. The three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 1, characterized in that, The oxide thickness of the gate oxide layer (4) is The thickness of the polysilicon layer (5) of the selector is The thickness of the gate oxide layer (4) is less than that of the selector polysilicon layer (5).

3. The three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 1, characterized in that, The doping concentration of the silicon channel region (9) is greater than that of the silicon substrate (1).

4. The three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 1, characterized in that, The sidewall (6) is composed of silicon dioxide and silicon nitride. The top surface of the sidewall (6) is horizontal with the gate oxide layer (4), that is, the sum of the heights of the selector polysilicon layer (5) and the sidewall (6) is equal to the height of the gate oxide layer (4).

5. The three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 1, characterized in that, The thickness of the polysilicon layer (8) of the SONOS transistor is In the oxide-nitride-oxide dielectric layer (7), the thickness of the bottom oxide layer is... The thickness of the middle nitride layer is The thickness of the top oxide medium is 6. The three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 1, characterized in that, The drain (3), the selector polysilicon layer (5), the SONOS polysilicon layer (8), and the source (10) are all N-type doped.

7. A method for operating a three-dimensional SONOS-type FLASH device for in-memory computing as described in any one of claims 1-6, characterized in that, The erasure process of the three-dimensional SONOS type FLASH device structure is as follows: a negative potential is applied to the drain terminal (3), the polysilicon layer (5) of the select transistor, the source terminal (10), and the silicon substrate (1), and a positive potential is applied to the polysilicon layer (8) of the SONOS transistor. That is, a negative voltage is applied to the word line WL of the three-dimensional SONOS type FLASH device to be erased in the array, and a positive voltage is applied to the gate terminal SG of the select transistor, the bit line BL, the source line SL and the substrate, so that the electrons in the oxide-nitride-oxide dielectric layer (7) are released. At this time, the threshold voltage of the SONOS transistor is the erase state threshold voltage, which reduces the erasure time and increases the erasure efficiency.

8. The operating method of the three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 7, characterized in that, The drain programming process of the three-dimensional SONOS type FLASH device structure is as follows: apply a negative potential to the drain terminal (3) and the polysilicon layer (5) of the select transistor, apply a positive potential to the polysilicon layer (8) of the SONOS transistor, ground the source terminal (10) and float the silicon substrate (1), that is, apply a negative voltage to the bit line BL and the gate terminal SG of the three-dimensional SONOS type FLASH device pre-drain programming in the array, wherein the gate terminal voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor, apply a positive voltage to the word line WL, ground the source line SL and float the substrate, so that the oxide-nitride-oxide dielectric layer (7) performs drain electron storage.

9. The operating method of the three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 7, characterized in that, The source-side programming process of the three-dimensional SONOS type FLASH device structure is as follows: a negative potential is applied to the source end (10) and the polysilicon layer (5) of the select transistor, a positive potential is applied to the polysilicon layer (8) of the SONOS transistor, the drain end (3) is grounded, and the silicon substrate (1) is floated. That is, a negative voltage is applied to the source line SL and the gate end SG of the three-dimensional SONOS type FLASH device pre-programmed in the array, wherein the gate end voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor, a positive voltage is applied to the word line WL, the bit line BL is grounded, and the substrate is floated, so that the oxide-nitride-oxide dielectric layer (7) performs source-side electron storage. After programming operations are performed at both the source end and the drain end, the threshold voltage of the SONOS transistor is the programming state threshold voltage.

10. The operating method of the three-dimensional SONOS-type FLASH device for in-memory computing as described in claim 7, characterized in that, The working process of the three-dimensional SONOS type FLASH device structure is as follows: a negative potential is applied to the drain terminal (3) and the polysilicon layer (5) of the select transistor, and a potential is applied to the polysilicon layer (8) of the SONOS transistor, so that the potential is between the programming state and the erase state threshold voltage. The source terminal (10) is grounded and the silicon substrate (1) is floated, that is, a negative voltage is applied to the bit line BL and the gate terminal SG of the three-dimensional SONOS type FLASH device pre-programmed at the source terminal in the array, wherein the gate terminal voltage of the select transistor is higher than or equal to the turn-on voltage of the select transistor. The source line SL is grounded and the substrate is floated. A certain voltage value is applied to the word line WL, so that the word line voltage is between the programming state threshold voltage and the erase state threshold voltage of the three-dimensional SONOS type FLASH device, thereby the three-dimensional SONOS type FLASH device is in working state.

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