Display panel and semiconductor device

Abstract

This application provides a display panel and a semiconductor device. The display panel has multiple pixel light-emitting units and multiple driving circuits. An active layer is located on one side of a substrate and includes multiple active regions. A first gate layer includes multiple gates, the orthographic projection of which overlaps with the orthographic projection of the corresponding active region on the substrate. A second gate layer is located on the side of the first gate layer away from the active layer and includes a shielding layer. A first source / drain electrode layer is located on the side of the second gate layer away from the first gate layer and includes multiple power lines arranged side-by-side. At least one of the power lines is an AC power line, and the orthographic projection of the AC power line on the substrate overlaps with the orthographic projection of the active region electrically connected to the anode on the substrate. The orthographic projection of the shielding layer on the substrate covers at least a portion of the overlapping area. This allows for ultra-high resolution display.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a display panel and a semiconductor device. Background Technology

[0002] Organic Light-Emitting Diode (OLED) display is a display technology different from traditional Liquid Crystal Display (LCD). It boasts advantages such as active light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-thinness, and low cost, making it a significant development in next-generation display devices and attracting increasing attention. An OLED display panel comprises multiple pixel units, each including a pixel driving circuit and a light-emitting element. The pixel circuit outputs a driving current to drive the light-emitting element to emit light. The pixel circuit includes at least one thin-film transistor (TFT) and at least one capacitor. The arrangement of the TFT and capacitor in the circuit can cause signal overlap, affecting the stability of the driving current and resulting in uneven brightness (mura) on the display panel. Furthermore, the pixel size also affects the display panel's resolution. Therefore, a more compact arrangement of the TFT and capacitor in the driving circuit is needed to achieve high-resolution display. Summary of the Invention

[0003] This application addresses the shortcomings of existing technologies by proposing a display panel and semiconductor device to solve the problem of uneven brightness caused by signal overlap in pixel driving circuits in existing technologies. This provides a display panel with uniform brightness and ultra-high resolution design, further improving the display effect.

[0004] This application provides a display panel. The display panel has multiple pixel light-emitting units and multiple driving circuits. Each pixel light-emitting unit includes an anode, a cathode, and a light-emitting material located between the anode and cathode. Each driving circuit includes a storage capacitor and multiple transistors. The display panel further includes a substrate, an active layer, a first gate layer, a second gate layer, and a first source / drain electrode layer. The active layer is located on one side of the substrate and includes multiple active regions, including a fifth active region. The first gate layer includes multiple gates, and the orthographic projection of each gate onto the substrate overlaps with the orthographic projection of the corresponding active region onto the substrate. The gates with overlapping regions and the active regions are components of the same transistor. The overlapping region of the active region with the gate serves as the channel of the transistor, and the regions of the active region located on both sides of the channel serve as the source and drain regions of the transistor, respectively. One of the source or drain regions of an active region is configured to be electrically connected to the anode of the pixel light-emitting unit. The multiple gates include at least a fifth gate, which is correspondingly disposed with the channel of the fifth active region and configured to be in a raised state for at least one time period. The second gate layer is located on the side of the first gate layer away from the active layer and includes a shielding layer; the first source / drain electrode layer is located on the side of the second gate layer away from the first gate layer and includes a plurality of power lines arranged side by side, the power lines being configured to input power signals to the gate, source, or drain regions of the plurality of transistors, at least one of the plurality of power lines being an AC power line, the orthographic projection of the AC power line on the substrate overlapping the orthographic projection of the active region electrically connected to the anode on the substrate; wherein the orthographic projection of the shielding layer on the substrate covers at least a portion of the overlapping region.

[0005] As can be seen from the above embodiments, in this application, by making a portion of the second gate layer in the driving circuit of the pixel light-emitting unit overlap with the AC power line in the first source-drain electrode layer, signal shielding and noise reduction of the AC signal are achieved, thereby avoiding the potential of the gate in the raised state from being affected by the sudden change, which would lead to poor display uniformity (Mura), thus improving the display light-emitting effect.

[0006] In addition, by having the AC power lines overlap with the traces in a portion of the second gate layer, the space occupied by a single pixel can be reduced, improving space utilization and enabling ultra-high resolution designs.

[0007] In one embodiment, the area of ​​the overlapping region covered by the orthographic projection of the shielding layer on the substrate is not less than 50% of the total area of ​​the overlapping region; or, the orthographic projection of the shielding layer on the substrate covers the entire overlapping region.

[0008] In one embodiment, the shielding layer serves as one capacitor plate of the storage capacitor and is electrically connected to the anode; the region of the active layer located in the overlapping region serves as at least a portion of the other capacitor plate of the storage capacitor.

[0009] In one embodiment, the plurality of transistors includes a first transistor, wherein the source or drain region of the first transistor is at the same potential as the fifth gate for a period of time, and the orthographic projection of the active region of the first transistor on the substrate does not overlap with the orthographic projection of the AC power line on the substrate.

[0010] In one embodiment, the plurality of transistors includes a second transistor, wherein the source or drain region of the second transistor is at the same potential as the fifth gate for a period of time, and the orthographic projection of the active region of the second transistor on the substrate does not overlap with the orthographic projection of the AC power line on the substrate.

[0011] In one embodiment, the display panel further includes: a second source / drain electrode layer, the second source / drain electrode layer being located on the side of the first source / drain electrode layer away from the second gate layer, and including a plurality of data lines arranged side by side; the pixel light-emitting unit being located on the side of the second source / drain electrode layer away from the first source / drain electrode layer.

[0012] In one embodiment, the active region of the transistor containing the fifth gate extends along the column direction, and the plurality of power lines all extend along the row direction.

[0013] In one embodiment, the driving circuit includes a 5T2C type circuit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a storage capacitor, and a diode capacitor. One source or drain region of the first transistor, one source or drain region of the second transistor, the gate of the fifth transistor, and one capacitor plate of the storage capacitor are all connected to the G potential. The other capacitor plate of the storage capacitor, one source or drain region of the fifth transistor, one source or drain region of the third transistor, and the anode are all connected to the S potential. The other source or drain region of the fifth transistor is connected to one source or drain region of the fourth transistor. One plate of the diode capacitor is connected to the anode, and the other plate of the diode capacitor is connected to the cathode.

[0014] In one embodiment, the plurality of power lines include a Vref power line, a G2 power line, a Vini power line, a G3 power line, an EM power line, a VDD power line, and a G1 power line. The Vref power line is connected to another source or drain region of the second transistor, the G2 power line is connected to the gate of the second transistor, the Vini power line is connected to another source or drain region of the third transistor, the G3 power line is connected to the gate of the third transistor, the EM power line is connected to the gate of the fourth transistor, the VDD power line is connected to another source or drain region of the fourth transistor, and the G1 power line is connected to the gate of the first transistor.

[0015] In one embodiment, the data line is electrically connected to the drive circuit; wherein...

[0016] Each data line corresponds to a driving circuit;

[0017] Alternatively, there may be a one-to-many correspondence between the data lines and the driving circuit.

[0018] In one embodiment, the display panel further includes a first gate insulating layer disposed between the active layer and the first gate layer and an interlayer insulating layer disposed between the first source / drain layer and the active layer;

[0019] The orthogonal projection of the first gate insulating layer onto the substrate completely covers the first gate layer.

[0020] This application also provides a semiconductor device comprising: a substrate, a raised potential layer, an AC potential layer, and a shielding layer; wherein the raised potential layer is disposed on one side of the substrate; the AC potential layer is connected to an AC power source and is disposed on the side of the raised potential layer away from the substrate, and the orthographic projection of the AC potential layer on the substrate overlaps with the orthographic projection of the raised potential layer on the substrate; the shielding layer is disposed between the raised potential layer and the AC potential layer, and the orthographic projection of the shielding layer on the substrate covers at least a portion of the overlapping area.

[0021] In one embodiment, the area of ​​the overlapping region covered by the orthographic projection of the shielding layer on the substrate is not less than 50% of the total area of ​​the overlapping region; or, the orthographic projection of the shielding layer on the substrate covers the entire overlapping region.

[0022] In one embodiment, the raised potential layer has a first state and a second state. In the first state, the raised potential layer is connected to a stable potential; in the second state, the raised potential layer is in a raised state.

[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0025] Figure 1 This is a plan view of the pixel driving circuit of a display panel according to some exemplary embodiments of this application;

[0026] Figure 2 yes Figure 1 A plan view of the active layer of the display panel shown;

[0027] Figure 3 yes Figure 1 A plan view of the first gate layer of the display panel shown;

[0028] Figure 4 yes Figure 1 A plan view of the second gate layer of the display panel shown;

[0029] Figure 5 yes Figure 1 The diagram shows a plan view of the interlayer insulating layer of the display panel.

[0030] Figure 6 yes Figure 1 A plan view of the first gate drain electrode layer of the display panel shown;

[0031] Figure 7 yes Figure 1 A plan view of the first planarization layer / second planarization layer of the display panel shown;

[0032] Figure 8 yes Figure 1 A plan view of the second source / drain electrode layer of the display panel shown;

[0033] Figure 9 yes Figures 2 to 4 The diagram shows the plan view after each film layer is stacked in sequence;

[0034] Figure 10 This is a cross-sectional view of a display panel according to some exemplary embodiments of this application;

[0035] Figure 11 This is a schematic diagram of a pixel driving circuit according to some exemplary embodiments of this application;

[0036] Figure 12 This is a timing diagram of the operation of a display panel according to some exemplary embodiments of this application.

[0037] In the picture:

[0038] 1-Substrate; 2-Buffer layer; 3-Active layer; 4-First gate insulating layer; 5-First gate layer; 6-Second gate insulating layer; 7-Second gate layer; 8-Interlayer insulating layer; 9-First source / drain electrode layer; 10-First planarization layer; 11-First passivation layer; 12-Second source / drain electrode layer; 13-Second passivation layer; 14-Second planarization layer; 15-Anode; 16-Light emitting layer; 161-Pixel limiting layer; 17-Cathode. Detailed Implementation

[0039] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0040] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0041] In this application, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component having a certain electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0042] The transistors used in the embodiments of this application can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. Since the source and drain of the TFTs used here are symmetrical, their sources and drains can be interchanged. The following examples primarily describe the case of a P-type TFT used as the driving transistor; other transistors may be of the same or different type as the driving transistor depending on the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as an N-type TFT.

[0043] For those skilled in the art, a pixel refers to a light-emitting unit in a display screen. A pixel typically comprises multiple subpixels of different colors. Pixel density (PPI, Pixels Per Inch) refers to the number of pixels per inch of a display screen. The higher the pixel density, the higher the realism.

[0044] Ultra-high resolution display technology can improve the display effect of the screen and can also be applied to a variety of special displays, such as 3D display. In 3D display, the existing display pixels are divided into multiple sub-pixels (views). Each view displays object information from different angles. With the help of microlenses, 3D display is achieved. For 3D display, the more views there are, the better the 3D display effect. However, the more views there are, the tighter the pixel layout space becomes. In actual layout, it is difficult to avoid the overlap between signals. For 5T2C internal compensation circuits or other circuit designs with floating points, the overlap of graphics at floating points, especially the overlap with AC signals, will cause voltage jumps at the floating points, affecting the lighting effect.

[0045] Therefore, how to improve space utilization while shielding interference between AC signals is a problem that urgently needs to be solved in the layout design of drive circuits.

[0046] The display panel and semiconductor device provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0047] This application provides a display panel and a semiconductor device. The display panel and display device of this application embodiment are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can complement or combine with each other.

[0048] This application provides a display panel. The display panel has multiple pixel light-emitting units and multiple driving circuits. Each pixel light-emitting unit includes an anode 15, a cathode 17, and a light-emitting material located between the anode 15 and the cathode 17. The driving circuit includes a storage capacitor and multiple transistors. The display panel also includes a substrate 1, an active layer 3, a first gate layer 5, a second gate layer 7, and a first source / drain electrode layer 9. The active layer 3 is located on one side of the substrate 1 and includes multiple active regions, among which a fifth active region ACT5 is included. The first gate layer 5 includes multiple gates, and the orthographic projection of the gates on the substrate 1 overlaps with the orthographic projection of the corresponding active regions on the substrate 1. The gates with overlapping regions and the active regions are components of the same transistor. The overlapping region of the active region with the gate serves as the channel of the transistor, and the regions on both sides of the channel of the active region serve as the source region and drain region of the transistor, respectively. The source region or drain region of one of the active regions is configured to be electrically connected to the anode 15 of the pixel light-emitting unit. At least one fifth gate GT5 is included among the multiple gates. The fifth gate GT5 is correspondingly disposed with the channel of the fifth active region ACT5, and the fifth gate GT5 is configured to be in a raised state for at least one time period. The gate corresponding to the channel of the active region electrically connected to the anode 15 is configured to be in a raised state for at least one time period. The second gate layer 7 is located on the side of the first gate layer 5 away from the active layer 3 and includes a shielding layer; the first source / drain electrode layer 9 is located on the side of the second gate layer 7 away from the first gate layer 5 and includes a plurality of power lines arranged side by side. The power lines are configured to input power signals to the gate, source, or drain regions of a plurality of transistors. At least one of the plurality of power lines is an AC power line. The orthographic projection of the AC power line on the substrate 1 overlaps with the orthographic projection of the active region electrically connected to the anode 15 on the substrate 1. The orthographic projection of the shielding layer on the substrate 1 covers at least a portion of the overlapping region.

[0049] This embodiment achieves signal shielding and noise reduction of AC signals by having a portion of the second gate layer 7 in the driving circuit of the pixel light-emitting unit overlap with the AC power line in the first source / drain electrode layer 9. This prevents the potential of the gate in the raised state from being affected by sudden changes, which would lead to poor display uniformity (Mura) and thus improve the display light-emitting effect.

[0050] In addition, by having the AC power lines overlap with the traces in a portion of the second gate layer 7, the space occupied by a single pixel can be reduced, improving space utilization and enabling ultra-high resolution design.

[0051] In some embodiments, a driving circuit corresponds one-to-one with a pixel light-emitting unit. Driven by the driving circuit, each pixel light-emitting unit emits light for display. It should be noted that the driving circuit and the pixel light-emitting unit can be integrated onto substrate 1 using common semiconductor processes. Figure 10As shown, the display panel includes, in sequence, a substrate 1, a buffer layer 2, an active layer 3, a first gate insulating layer 4, a first gate layer 5, a second gate insulating layer 6, a second gate layer 7, an interlayer insulating layer 8, a first source / drain electrode layer 9, a first planarization layer 10, a first passivation layer 11, a second source / drain electrode layer 12, a second passivation layer 13, a second planarization layer 14, an anode 15, a light-emitting layer 16 (with a pixel limiting layer 161 spaced apart), and a cathode 17.

[0052] It should be noted that substrate 1 can be a rigid or flexible substrate, such as glass, quartz, or polyimide (PI). Buffer layer 2 is an optional film layer, and its material can be silicon oxide, silicon nitride, silicon oxynitride, or a mixture thereof. Active layer 3 (ACT) can be made of polycrystalline silicon. Anode 15 can be made of ITO or IZO, and cathode 17 can be made of Mg / Ag.

[0053] Figure 1 This embodiment illustrates a layout implementation of the TFT and capacitor positions of the display panel provided in this example. Figures 2 to 8 This is a plan view illustrating the various layers of the sub-pixel layout implementation. Specifically, Figures 2 to 8 An implementation of same-layer wiring or semiconductor layer arrangement is shown.

[0054] In some embodiments, the insulating layer may be located at Figures 2 to 8 Between the layers in the structure, for example, the first gate insulating layer 4 may be located between the layers. Figure 2 layers and Figure 3 Between the layers, the second gate insulating layer 6 may be located Figure 3 layers and Figure 4 Between the layers, the insulating layer may include contact holes VH for electrical connection in the vertical direction. Figures 2 to 8 The structure of layers in the text.

[0055] like Figures 1 to 8 As shown, each side has a complete 5T2C driving circuit, which includes five thin-film transistors (TFTs), a storage capacitor Cst, and a diode capacitor Coled (not shown in the figure). Specifically, the five TFTs are transistors T1, T2, T3, T4, and T5.

[0056] It should be noted that the driving circuit included in the display substrate according to the embodiment of this application is described here using the 5T2C structure as an example. However, the driving circuit included in the display substrate according to the embodiment of this application is not limited to the 5T2C structure, and may also include 3T1C, 4T1C, 6T1C, 7T1C, etc.

[0057] The active layer 3ACT is located on one side of the substrate 1 and includes multiple active regions. Each active region corresponds to a thin-film transistor (TFT). Specifically, as shown... Figure 2 As shown, there are two active regions contained in the driving circuits symmetrically distributed along the central axis I-I'. Figures 3 to 8 Similarly, this will not be repeated later. For example, the left side corresponds to a 5T2C circuit containing 5 active regions, namely the first active region ACT1, the second active region ACT2, the third active region ACT3, the fourth active region ACT4, and the fifth active region ACT5, which correspond to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, respectively.

[0058] It should be noted that the active region may include a channel region, a source region, and a drain region. The source region and the drain region are located on opposite sides of the channel region. The orthographic projection of the active layer 3 onto the substrate 1 overlaps with the orthographic projection of the first gate layer 5 onto the substrate 1, and the overlapping region forms the channel region.

[0059] The first gate insulating layer 4 covers the active layer 3, and may be a single, continuous layer. The material of the first gate insulating layer 4 may be silicon oxide, silicon nitride, silicon oxynitride, or a composite layer thereof.

[0060] In some embodiments, the orthogonal projection of the first gate insulating layer onto the substrate 1 completely covers the first gate layer 5.

[0061] The first gate layer 5 is located on the side of the first gate insulating layer 4 away from the substrate 1, and includes a plurality of gates. Specifically, as shown in the figure... Figure 3As shown, the 5T2C circuit on either the left or right side includes five gates: a first gate GT1, a second gate GT2, a third gate GT3, a fourth gate GT4, and a fifth gate GT5, corresponding to the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5, respectively. The orthographic projection of any gate onto the substrate 1 overlaps with the projection of its corresponding active region onto the substrate 1. Gates with overlapping regions and active regions are components of the same transistor. Specifically, the first gate GT1 and its corresponding first active region ACT1 constitute the first transistor T1; the second gate GT2 and its corresponding second active region ACT2 constitute the second transistor T2; the third gate GT3 and its corresponding third active region ACT3 constitute the third transistor T3; the fourth gate GT4 and its corresponding fourth active region ACT4 constitute the fourth transistor T4; and the fifth gate GT5 and its corresponding fifth active region ACT5 constitute the fifth transistor T5. It should be noted that the orthographic projection of each active region on substrate 1 overlaps with the orthographic projection of each corresponding gate on substrate 1. The overlapping region forms the channel region of each corresponding thin-film transistor. The regions on both sides of the channel region of each active region are the source region and drain region of each thin-film transistor, respectively.

[0062] It should be noted that although the embodiments of this application illustrate that the first gate layer 5 is located on the side of the active layer 3 away from the substrate 1 (top gate design), the first gate layer 5 in the embodiments of this application can also be a bottom gate or a dual gate design. That is, the first gate layer 5 can also be located on the side of the active layer 3 close to the substrate 1, or the first gate layer can be distributed on both sides of the active layer 3 close to and away from the substrate 1. Those skilled in the art can set it flexibly, and it is not limited to this.

[0063] In some embodiments, such as Figures 11 to 12 As shown, the source or drain region of the fifth active region ACT5 is configured to be electrically connected to the anode 15 of the pixel light-emitting unit, and the gate corresponding to the channel of the fifth active region ACT5 electrically connected to the anode 15 is configured to be in a raised state during at least one time period when the pixel light-emitting unit is operating.

[0064] The second gate layer 7 is located on the side of the first gate layer 5 away from the active layer 3, and includes a shielding layer. For example... Figure 4 As shown, a portion of the second gate layer 7 forms one of the capacitor plates of the storage capacitor.

[0065] In some embodiments, the area of ​​the overlapping region covered by the orthographic projection of the shielding layer onto the substrate 1 is not less than 50% of the total area of ​​the overlapping region.

[0066] In some embodiments, the orthographic projection of the shielding layer onto the substrate 1 covers the entire overlapping area.

[0067] In some embodiments, the shielding layer serves as one capacitor plate of the storage capacitor and is electrically connected to the anode 15; a region of the active layer 3 located in the overlapping region serves as at least a portion of the other capacitor plate of the storage capacitor. Thus, a portion of the shielding layer and the active layer 3 combine to form the storage capacitor. Specifically, as... Figure 9 This is a schematic diagram of the film formed by sequentially stacking the active layer 3, the first gate layer 5, and the second gate layer 7. Figure 9 It can be seen that the shielding layer and a portion of the active layer 3 combine to form a storage capacitor.

[0068] In some embodiments, the plurality of transistors includes a first transistor, wherein the source region or drain region of the first transistor is at the same potential as the fifth gate for a period of time, and the orthographic projection of the active region of the first transistor on the substrate 1 and the orthographic projection of the AC power line on the substrate 1 do not overlap.

[0069] In some embodiments, the plurality of transistors includes a second transistor, wherein the source region or drain region of the second transistor is at the same potential as the fifth gate for a period of time, and the orthographic projection of the active region of the second transistor on the substrate 1 does not overlap with the orthographic projection of the AC power line on the substrate 1.

[0070] In some embodiments, such as Figure 11 As shown, one source or drain region of the first transistor, one source or drain region of the second transistor, the gate of the fifth transistor, and one capacitor plate of the storage capacitor are all connected to the G potential. The other capacitor plate of the storage capacitor, one source or drain region of the fifth transistor, one source or drain region of the third transistor, and the anode 15 are all connected to the S potential. The other source or drain region of the fifth transistor is connected to one source or drain region of the fourth transistor. One plate of the diode capacitor is connected to the anode 15, and the other plate of the diode capacitor is connected to the cathode 17.

[0071] The interlayer insulating layer 8 is located on the side of the second gate layer 7 away from the first gate layer 5, such as... Figure 5 As shown. The interlayer insulating layer 8 has multiple contact holes VH for electrical connection in the vertical direction. Figures 2 to 8 The structure of layers in the text.

[0072] The first source / drain electrode layer 9 is located on the side of the second gate layer 7 away from the first gate layer 5, such as... Figure 6 As shown, it includes multiple power lines arranged side by side, namely Vref power line, G2 power line, Vini power line, G3 power line, EM power line, VDD power line and G1 power line, which are configured to input power signals to the gate, source or drain regions of multiple transistors.

[0073] In some embodiments, the display panel further includes a first planarization layer 10, a first passivation layer 11, a second passivation layer 13, and a second planarization layer 14, such as Figure 7 As shown. The first planarization layer 10, the first passivation layer 11, the second passivation layer 13, and the second planarization layer 14 have multiple contact holes VH for electrical connection in the vertical direction. Figures 2 to 8 The structure of layers in the text.

[0074] In some embodiments, the display panel further includes: a second source / drain electrode layer 12, such as Figure 8 As shown, the second source / drain electrode layer 12 is located on the side of the first source / drain electrode layer 9 away from the second gate layer 7, and includes multiple data lines arranged side by side. The pixel light-emitting unit is located on the side of the second source / drain electrode layer 12 away from the first source / drain electrode layer 9.

[0075] It should be noted that multiple data lines extend along the column direction to provide data signals to the same column of pixels.

[0076] In some embodiments, the data lines are electrically connected to the drive circuit; wherein, there is a one-to-one correspondence between the data lines and the drive circuit.

[0077] In some embodiments, there is a one-to-many correspondence between the data lines and the driving circuits.

[0078] In some embodiments, such as Figure 6 As shown, multiple power cables include Vref power cable, G2 power cable, Vini power cable, G3 power cable, EM power cable, VDD power cable, and G1 power cable, as follows: Figure 11 As shown, the Vref power line is connected to another source or drain region of the second transistor, the G2 power line is connected to the gate of the second transistor, the Vini power line is connected to another source or drain region of the third transistor, the G3 power line is connected to the gate of the third transistor, the EM power line is connected to the gate of the fourth transistor, the VDD power line is connected to another source or drain region of the fourth transistor, and the G1 power line is connected to the gate of the first transistor.

[0079] In some embodiments, the active region of the transistor containing the fifth gate GT5 extends along the column direction, and multiple power lines extend along the row direction. For example... Figure 2 The gate of the fifth transistor T5 is in a raised state during at least one time period when the pixel light-emitting unit is working, and the fifth active region ACT5 corresponding to the fifth transistor T5 extends along the column direction. Multiple power lines, including Vref power line, G2 power line, Vini power line, G3 power line, EM power line, VDD power line and G1 power line, all extend along the row direction.

[0080] like Figures 11 to 12As shown, the display panel provided in this embodiment achieves compensation through the following four stages.

[0081] First stage (reset stage): Control the second transistor T2 to conduct under the control of the high-level signal on the G2 power line, and control the third transistor T3 to conduct under the control of the high-level signal on the Vini power line to achieve reset.

[0082] The second stage (compensation stage): The second transistor T2 is kept on under the control of a high-level signal on the G2 power line, maintaining the Vref voltage at point G. Simultaneously, the G3 power line is changed from high to low, turning off the third transistor T3. The fifth transistor T5 is turned on, charging point S until Vgs = Vth. The Vth data of the fifth transistor T5 is stored at point S, and the voltage at point S becomes Vref - Vth, thus performing voltage compensation for the fifth transistor T5.

[0083] Third stage (data writing stage): Change the G2 power line from high level to low level to turn off the second transistor T2. Change the G1 power line from low level to high level to turn on the first transistor T1, and the data line writes the data signal to point G through the gate of the first transistor T1.

[0084] The fourth stage (light-emitting stage): All transistors are turned off, and the storage capacitor Cst charges point S, so point G is in a floating state. The voltage at point S rises, and since there is a storage capacitor Cst between points S and G, the voltage at point G also rises. The potential at point S is connected to the OLED anode 15. When point S rises to the voltage of anode 15, the storage capacitor Cst between points G and S couples to point G, causing point G to rise. The rise of points G and S maintains the Vth voltage of the fifth transistor T5, which is the grayscale voltage required for the light-emitting stage.

[0085] Therefore, it can be seen that if coupling occurs between point G and the AC signal, causing the potential of point G to drop, it will affect the voltage of the fifth transistor T5, preventing the grayscale voltage from being reached, and thus affecting the light emission effect. Therefore, this embodiment adds a shielding area on the second gate layer 7 to shield the AC signal and prevent the AC signal from affecting the potential of point G.

[0086] This application also provides a semiconductor device, which includes: a substrate 1, a raised potential layer, an AC potential layer, and a shielding layer; wherein, the raised potential layer is disposed on one side of the substrate 1; the AC potential layer is connected to an AC power source and is disposed on the side of the raised potential layer away from the substrate 1, and the orthographic projection of the AC potential layer on the substrate 1 overlaps with the orthographic projection of the raised potential layer on the substrate 1; the shielding layer is disposed between the raised potential layer and the AC potential layer, and the orthographic projection of the shielding layer on the substrate 1 covers at least a portion of the overlapping area.

[0087] In some embodiments, the area of ​​the overlapping region covered by the orthographic projection of the shielding layer on the substrate 1 is not less than 50% of the total area of ​​the overlapping region; or, the orthographic projection of the shielding layer on the substrate 1 covers the entire overlapping region.

[0088] In some embodiments, the raised potential layer has a first state and a second state. In the first state, the raised potential layer is connected to a stable potential; in the second state, the raised potential layer is in a raised state.

[0089] The shielding layer in this embodiment operates on the same principle as the shielding layer in the display panel of the previous embodiment. Therefore, this semiconductor device possesses all the features and advantages similar to the aforementioned display panel, which will not be repeated here.

[0090] It should be noted that the display device can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it contains text or images. More specifically, the intended embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, orthographic projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0091] The above embodiments of this application can complement each other without causing conflict.

[0092] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0093] The terms “center,” “upper,” “lower,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0094] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0095] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0096] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display panel having a plurality of pixel light-emitting units and a plurality of driving circuits, wherein each pixel light-emitting unit includes an anode, a cathode, and a light-emitting material located between the anode and the cathode, and the driving circuit includes a storage capacitor and a plurality of transistors; characterized in that, The display panel includes: Base; An active layer, located on one side of the substrate, includes multiple active regions, including a fifth active region; A first gate layer includes multiple gates, wherein the orthographic projection of each gate onto the substrate overlaps with the orthographic projection of a corresponding active region onto the substrate, and the gates with overlapping regions and the active regions are components of the same transistor; the overlapping region of the active region with the gates serves as the channel of the transistor, and the regions of the active region located on both sides of the channel serve as the source region and drain region of the transistor, respectively; one of the source regions or drain regions of the active region is configured to be electrically connected to the anode of the pixel light-emitting unit, and the multiple gates include at least a fifth gate, which is correspondingly disposed with the channel of the fifth active region and configured to be in a raised state for at least one time period; The second gate layer is located on the side of the first gate layer away from the active layer and includes a shielding layer; A first source / drain electrode layer, located on the side of the second gate layer away from the first gate layer, includes a plurality of power lines configured to input power signals to the gate, source, or drain regions of the plurality of transistors. At least one of the plurality of power lines is an AC power line, and the orthographic projection of the AC power line on the substrate overlaps with the orthographic projection of the active region electrically connected to the anode on the substrate. Wherein, the orthographic projection of the shielding layer onto the substrate covers at least a portion of the overlapping area.

2. The display panel of claim 1, wherein, The area of ​​the overlapping region covered by the orthographic projection of the shielding layer on the substrate is not less than 50% of the total area of ​​the overlapping region; or, the orthographic projection of the shielding layer on the substrate covers the entire overlapping region.

3. The display panel of claim 1, wherein, The shielding layer serves as one of the capacitor plates of the storage capacitor and is electrically connected to the anode; The region of the active layer located in the overlapping region serves as at least a portion of another capacitor plate of the storage capacitor.

4. The display panel of claim 1, wherein, The plurality of transistors includes a first transistor, wherein for a period of time, the source region or drain region of the first transistor is at the same potential as the fifth gate, and the orthographic projection of the active region of the first transistor on the substrate and the orthographic projection of the AC power line on the substrate do not overlap. And / or, the plurality of transistors includes a second transistor, wherein for a period of time, the source region or drain region of the second transistor is at the same potential as the fifth gate, and the orthographic projection of the active region of the second transistor on the substrate does not overlap with the orthographic projection of the AC power line on the substrate.

5. The display panel of claim 1, wherein, Also includes: The second source / drain electrode layer is located on the side of the first source / drain electrode layer away from the second gate layer, and includes a plurality of data lines arranged side by side. The pixel light-emitting unit is located on the side of the second source / drain electrode layer away from the first source / drain electrode layer.

6. The display panel of claim 1, wherein, The active region of the transistor containing the fifth gate extends along the column direction, and the plurality of power lines all extend along the row direction.

7. The display panel of claim 1, wherein, The driving circuit includes a 5T2C type circuit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a storage capacitor, and a diode capacitor. One source or drain region of the first transistor, one source or drain region of the second transistor, the gate of the fifth transistor, and one capacitor plate of the storage capacitor are all connected to the G potential. The other capacitor plate of the storage capacitor, one source or drain region of the fifth transistor, one source or drain region of the third transistor, and the anode are all connected to the S potential. The other source or drain region of the fifth transistor is connected to one source or drain region of the fourth transistor. One plate of the diode capacitor is connected to the anode, and the other plate of the diode capacitor is connected to the cathode.

8. The display panel of claim 7, wherein, The plurality of power lines include a Vref power line, a G2 power line, a Vini power line, a G3 power line, an EM power line, a VDD power line, and a G1 power line. The Vref power line is connected to another source or drain region of the second transistor. The G2 power line is connected to the gate of the second transistor. The Vini power line is connected to another source or drain region of the third transistor. The G3 power line is connected to the gate of the third transistor. The EM power line is connected to the gate of the fourth transistor. The VDD power line is connected to another source or drain region of the fourth transistor. The G1 power line is connected to the gate of the first transistor.

9. The display panel of claim 5, wherein, The data line is electrically connected to the drive circuit; wherein... Each data line corresponds to a driving circuit; Alternatively, there may be a one-to-many correspondence between the data lines and the driving circuit.

10. The display panel of claim 1, wherein, Also includes: A first gate insulating layer disposed between the active layer and the first gate layer and an interlayer insulating layer disposed between the first source / drain electrode layer and the active layer; The orthogonal projection of the first gate insulating layer onto the substrate completely covers the first gate layer.

11. A semiconductor device, applied to a display panel as described in any one of claims 1 to 10, characterized in that, include: Base; A raised potential layer is disposed on one side of the substrate; An AC potential layer, connected to an AC power source, is disposed on the side of the raised potential layer away from the substrate. The orthographic projection of the AC potential layer on the substrate and the orthographic projection of the raised potential layer on the substrate have an overlapping area. A shielding layer is disposed between the raised potential layer and the alternating potential layer, wherein the orthographic projection of the shielding layer on the substrate covers at least a portion of the overlapping area.

12. The semiconductor device of claim 11, wherein, The area of ​​the overlapping region covered by the orthographic projection of the shielding layer on the substrate is not less than 50% of the total area of ​​the overlapping region; or, the orthographic projection of the shielding layer on the substrate covers the entire overlapping region.

13. The semiconductor device of claim 11, wherein, The raised potential layer has a first state and a second state. In the first state, the raised potential layer is connected to a stable potential. In the second state, the raised potential layer is in a raised state.

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