Semiconductor device

Abstract

The present application provides a semiconductor device capable of preventing deterioration of a ceramic laminate substrate. A ceramic plate (20) is plate-shaped, has a front surface and a back surface opposite to the front surface, and has a plurality of ceramic particles. A metal layer (30) is joined to the front surface of the ceramic plate (20) and electrically connected to a semiconductor chip, and contains copper. A metal layer (40) is joined to the back surface of the ceramic plate (20) and contains copper. An intermediate layer (50b) is formed between the back surface of the ceramic plate (20) and the metal layer (40), and contains an oxide (51b) having magnesium. The ceramic laminate substrate (10) suppresses a decrease in the joining property of the metal layer (40) with respect to the ceramic plate (20) by the oxide (51b) having magnesium contained between the ceramic plate (20) and the metal layer (40), even when a high voltage is applied at a high temperature.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Semiconductor devices include power devices and are used as power conversion devices. Power devices are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). A semiconductor device includes a semiconductor chip and a ceramic multilayer substrate, the semiconductor chip including the power device. The ceramic multilayer substrate includes a ceramic plate, multiple metal layers formed on the front side of the ceramic plate forming a circuit pattern, and metal layers formed on the back side of the ceramic plate. The semiconductor chip, lead frame, etc., are bonded to the circuit pattern.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2017-147327 Summary of the Invention

[0004] Technical issues In such a semiconductor device, the semiconductor chip heats up when driven, and the area directly beneath the semiconductor chip is also heated. Furthermore, because a large voltage is applied to the lead frame, a large voltage is also applied to the metal layer between the front and back sides of the ceramic substrate directly beneath the lead frame. If this situation continues, it may lead to a decrease in the bonding strength between the ceramic substrate and the metal layer. Such degradation of the ceramic laminate substrate can become a cause of semiconductor device malfunction, potentially reducing the reliability of the semiconductor device.

[0005] The present invention was made in view of the following problems, and its object is to provide a semiconductor device that prevents the degradation of ceramic multilayer substrates.

[0006] Technical solution According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor chip; a bonding member; and a stacked substrate, which is plate-shaped, having a front side and a back side opposite to the front side, wherein the semiconductor chip is bonded to the front side via the bonding member, the stacked substrate comprising: a ceramic plate, which is plate-shaped, having a first main surface and a second main surface opposite to the first main surface, and having a plurality of ceramic particles; a high-potential metal layer bonded to the first main surface and comprising copper; a low-potential metal layer bonded to the second main surface and comprising copper, and having a potential lower than that of the first main surface; and an intermediate layer formed between the second main surface and the low-potential metal layer, comprising a first oxide comprising at least one of magnesium and manganese.

[0007] Technical effect According to the disclosed technology, it is possible to prevent the degradation of ceramic multilayer substrates and suppress the reduction in the reliability of semiconductor devices.

[0008] The above and other objects, features and advantages of the present invention will become clear from the following description in conjunction with the accompanying drawings, which illustrate preferred embodiments as examples of the present invention. Attached Figure Description

[0009] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a side view of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is an equivalent circuit illustrating the function implemented by the semiconductor device of the first embodiment.

[0012] Figure 4 This is a flowchart illustrating a method for manufacturing a ceramic multilayer substrate included in the semiconductor device of the first embodiment.

[0013] Figure 5 This is a schematic cross-sectional view of the ceramic laminate substrate of Comparative Example 1.

[0014] Figure 6 This is a cross-sectional schematic diagram of the ceramic multilayer substrate of Comparative Example 1 under high temperature and high voltage.

[0015] Figure 7 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Example 1-1).

[0016] Figure 8 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Example 1-1) under high temperature and high voltage.

[0017] Figure 9 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Examples 1-2).

[0018] Figure 10 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Examples 1-2) under high temperature and high voltage.

[0019] Figure 11 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Examples 1-3).

[0020] Figure 12 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Examples 1-3) under high temperature and high voltage.

[0021] Figure 13 This is a table summarizing the test results of the ceramic laminate substrate of the first embodiment.

[0022] Figure 14 This is a schematic cross-sectional view of the ceramic laminate substrate of Comparative Example 2.

[0023] Figure 15 This is a cross-sectional schematic diagram of the ceramic multilayer substrate of Comparative Example 2 under high temperature and high voltage.

[0024] Figure 16 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Example 2-1).

[0025] Figure 17 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Example 2-1) under high temperature and high voltage.

[0026] Figure 18 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Example 2-2).

[0027] Figure 19 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Example 2-2) under high temperature and high voltage.

[0028] Figure 20 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Examples 2-3).

[0029] Figure 21 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Examples 2-3) under high temperature and high voltage.

[0030] Figure 22 This is a diagram illustrating the region requiring an intermediate layer in the ceramic multilayer substrate (with a low potential back metal layer) of the third embodiment.

[0031] Figure 23 This is a diagram illustrating the region requiring an intermediate layer in the ceramic multilayer substrate (with a high potential back metal layer) of the third embodiment.

[0032] Figure 24 This is a diagram illustrating the region requiring an intermediate layer in the ceramic multilayer substrate (with a floating potential back metal layer) of the third embodiment.

[0033] Figure 25 This is a diagram illustrating the region requiring an intermediate layer in the ceramic laminate substrate of the third embodiment.

[0034] Symbol Explanation 1 Semiconductor device 10 Ceramic Multilayer Substrate 20 Ceramic Plate 21 Alumina 22 Oxides containing silicon Sodium 23 oxide 24 sodium ions 25 oxygen ions 26 Magnesium Oxide 27 Manganese oxide 30, 30a~30f Metal layers (high potential metal layers) 35 Joining components 31 and 41 possess copper oxides 40 metal layer (low potential metal layer) 50a, 50b intermediate layer 51a and 51b possess magnesium oxides 52a and 52b are oxides containing magnesium and manganese. 53a and 53b contain manganese oxides 60a, 60b, 65a, 65b semiconductor chips 61a, 61b control electrodes 62a, 62b output electrodes 66a, 66b Input Electrodes 71-75 External connection terminals 80a~80e bond wire 81-85 Wiring 90 housing 91 Sealing Components 92 heat dissipation components Detailed Implementation

[0035] The embodiments will now be described with reference to the accompanying drawings. It should be noted that in the following description, in the semiconductor device 1 shown in the drawings, "front" and "upper surface" refer to the XY planes facing upwards (+Z direction). Similarly, in the semiconductor device 1 shown in the drawings, "upper" indicates the direction facing upwards (+Z direction). In the semiconductor device 1 shown in the drawings, "back side" and "lower surface" refer to the XY planes facing downwards (-Z direction). Similarly, in the semiconductor device shown in the drawings, "lower" indicates the direction facing downwards (-Z direction). The same directionality may be indicated in other drawings as needed. "Front side," "upper surface," "upper," "back side," "lower surface," "lower," and "side" are merely expressions to facilitate the determination of relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily represent the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. Furthermore, in the following description, "main component" refers to a content of 80 vol% or more.

[0036] Additionally, in the following explanation, the content is sometimes expressed as "oxide conversion." "Oxide conversion" refers to the value calculated by converting each metallic element, confirmed through compositional analysis, into its respective oxide. For example, all elements confirmed through compositional analysis, such as aluminum, silicon, sodium, magnesium, manganese, zirconium, and yttrium, are converted into oxides such as aluminum oxide (Al₂O₃), silicon oxide (SiO₂), sodium oxide (Na₂O), magnesium oxide (MgO), manganese oxide (MnO), zirconium oxide (ZrO₂), and yttrium oxide (Y₂O₃), thus expressing the ratio of the weight of each oxide to the total weight obtained through oxide conversion. It should be noted that compositional analysis methods may include, for example, XRF (X-ray fluorescence), ICP (inductively coupled plasma) luminescence analysis, EPMA (electron probe microanalysis), and EDX (energy dispersive X-ray spectrometry).

[0037] Additionally, in the following description, "free from," "not identified," or "not formed" of elements or compounds refers to those below the determination limits in the above compositional analysis. For example, for manganese and magnesium, it means less than 0.01 wt% when converted to oxides. For example, for sodium, it means less than 0.001 wt% when converted to oxides.

[0038] [First Implementation] (Structure of a semiconductor device) use Figures 1-3 The semiconductor device of the first embodiment will be described. Figure 1 This is a top view of the semiconductor device according to the first embodiment. Figure 2 This is a side view of the semiconductor device according to the first embodiment. Figure 3This is an equivalent circuit illustrating the function implemented by the semiconductor device of the first embodiment. It should be noted that... Figure 1 Description of sealing components has been omitted. Figure 2 Observing from the +X direction Figure 1 A side view of semiconductor device 1.

[0039] The semiconductor device 1 includes at least a ceramic multilayer substrate 10, semiconductor chips 60a, 60b, 65a, and 65b, and external connection terminals 71 to 75. It may also include a housing 90 and a sealing component 91 (see reference). Figure 2 The external connection terminals 71 to 75 of the semiconductor device 1 extend upward from the front (+Z direction).

[0040] The ceramic laminate substrate 10 has a ceramic plate 20, metal layers 30a to 30f formed on the front side of the ceramic plate 20, and a metal layer 40 formed on the back side of the ceramic plate 20. It should be noted that, hereinafter, metal layers 30a to 30f are sometimes collectively referred to as metal layer 30.

[0041] The ceramic plate 20 is primarily composed of ceramic, which has good insulating and thermal conductivity. Such ceramic can be made of materials primarily composed of, for example, alumina (Al2O3) or zirconium oxide (ZrO2). Here, the ceramic is primarily composed of alumina (Al2O3). It should be noted that in the second embodiment, zirconium oxide (ZrO2) is also included. The ceramic primarily comprises ceramic particles. These ceramic particles can be made of materials primarily composed of alumina (Al2O3). Furthermore, the ceramic plate 20 may also contain grain boundary materials formed at the grain boundaries of the ceramic particles and at the triple points. Such grain boundary materials may include, for example, oxides containing silicon (second oxides). Additionally, the ceramic plate 20 is rectangular in shape when viewed from above. Furthermore, the corners may be chamfered (R-shaped or C-shaped). The thickness of the ceramic plate 20 is 0.1 mm or more and 1.0 mm or less, for example, about 0.3 mm. Details of the ceramic plate 20 will be described later.

[0042] The metal layer 30 formed on the front side of the ceramic plate 20 is mainly composed of a metal with excellent electrical conductivity. Examples of such metals include copper, aluminum, or alloys containing at least one of these. The metal layer 30 used here is mainly composed of copper. To improve corrosion resistance, the surface of the metal layer 30 may be plated. Examples of plating materials used include nickel, nickel-phosphorus alloys, and nickel-boron alloys. Multiple metal layers 30 are formed on the front side of the ceramic plate 20. For example, in the first embodiment, multiple metal layers 30a to 30f are formed on the front side of the ceramic plate 20. Hereinafter, without distinguishing between metal layers 30a to 30f, it will sometimes be referred to as metal layer 30. The metal layer 30 is electrically connected to semiconductor chips 60a, 60b, 65a, and 65b. The semiconductor chips 60a, 60b, 65a, and 65b, as well as external connection terminals 71 to 75, can be bonded to the metal layer 30 via bonding members 35 such as solder. Each metal layer 30 can be polygonal. In addition, the corners can also be chamfered (R-shaped) or chamfered (C-shaped). Multiple metal layers 30 are formed on the inner side of the ceramic plate 20. The thickness of the metal layers 30 is 0.1 mm or more and 0.5 mm or less, and can be around 0.3 mm.

[0043] The metal layer 40 formed on the back side of the ceramic plate 20 is mainly composed of a metal with excellent thermal conductivity. Such a metal can be, for example, copper, aluminum, or an alloy containing at least one of these. The metal layer 40 used here is mainly composed of copper. To improve corrosion resistance, the surface of the metal layer 40 can also be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The metal layer 40 is formed on the back side of the ceramic plate 20 in correspondence with the metal layer 30. That is, the metal layer 40 includes metal layers 30a to 30f formed on the front side of the ceramic plate 20 when viewed from above. The metal layer 40 can be connected to the heat dissipation component 92 via solder, brazing filler metal, thermal paste, etc. The ceramic laminate substrate 10 enables the heat generated in the semiconductor chips 60a, 60b, 65a, and 65b to be transferred to the heat dissipation component 92 on the outside via the metal layer 30, the ceramic plate 20, and the metal layer 40. Therefore, the ceramic plate 20 is heated when the semiconductor device 1 is in operation. Furthermore, the metal layer 40 is rectangular in shape when viewed from above. Additionally, the corners may be chamfered (R-shaped or C-shaped). The metal layer 40 is formed on the inner side of the ceramic plate 20. Moreover, it covers the area opposite to the metal layer 30. The thickness of the metal layer 40 is 0.1 mm or more and 0.5 mm or less, and can be approximately 0.3 mm.

[0044] Additionally, intermediate layers 50a and 50b are formed between the ceramic plate 20 and the metal layers 30 and 40. Intermediate layers 50a and 50b contain oxides (first oxides), which include at least one of magnesium and manganese. These oxides may be, for example, magnesium oxide (MgO), manganese oxide (MnO), (Mg,Mn)O, or (Mg,Mn)Mn₂O₄. These oxides are mostly contained in the intermediate layers 50a and 50b on the front and back sides of the ceramic plate 20.

[0045] In addition to these, the oxides contained in the intermediate layers 50a and 50b may also contain aluminum. Such oxides may include spinel crystal systems containing aluminum. Examples of spinel crystal systems include MgAl2O4, MnAl2O4, (Mg,Mn)Al2O4, and (Mg,Mn)(Al,Mn)2O4. It should be noted that the ceramic multilayer substrate 10 may include at least one of the intermediate layers 50a or 50b.

[0046] As the ceramic multilayer substrate 10 having such a structure, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate can also be used. It should be noted that the manufacturing method and details of the ceramic multilayer substrate 10 will be described later.

[0047] Semiconductor chips 60a, 60b, 65a, and 65b are primarily composed of silicon or silicon carbide. Semiconductor chips 60a and 60b are switching elements. These switching elements are, for example, IGBTs and power MOSFETs. Such semiconductor chips 60a and 60b have a drain or collector as input electrodes (main electrodes) on their back side. Additionally, semiconductor chips 60a and 60b have a gate as control electrodes 61a and 61b, and a source or emitter as output electrodes 62a and 62b (main electrodes) on their front side. The back side of the aforementioned semiconductor chips 60a and 60b is bonded to metal layers 30b and 30c using solder (not shown).

[0048] Semiconductor chips 65a and 65b are diode elements. Examples of diode elements include SBD (Schottky Barrier Diode), PiN (P-intrinsic-N) diodes, and other FWD (Free Wheeling Diode) elements. These semiconductor chips 65a and 65b have a cathode as the output electrode (main electrode) on the back side and an anode as the input electrode 66a and 66b (main electrode) on the front side. The back side of the aforementioned semiconductor chips 65a and 65b is bonded to metal layers 30b and 30c using solder (not shown). It should be noted that semiconductor chips 60a, 60b, 65a, and 65b can also be RC (Reverse Conductive)-IGBT elements or RB (Reverse Blocking)-IGBT elements that combine a switching element and a diode element into a single semiconductor chip.

[0049] The bonding component 35, which joins the semiconductor chips 60a, 60b, 65a, 65b to the metal layers 30b, 30c, can be solder. Lead-free solder is used. The lead-free solder is primarily composed of an alloy containing at least two of, for example, tin, silver, copper, zinc, antimony, indium, and bismuth. Furthermore, additives may also be included in the solder. Alternatively, a sintered metal body may be used instead of solder for the bonding component 35. The sintered metal body is primarily composed of silver or a silver alloy. Furthermore, such solder and sintered metal bodies are not limited to the bonding between the semiconductor chips 60a, 60b and the metal layers 30b, 30c, but can also be used for the bonding of external connection terminals 71-75 to the metal layers 30a, 30e, 30c, 30f, 30d, as described later.

[0050] The external connection terminals 71 to 75 are respectively formed in the shape of a plate, a prism, or a cylinder. In this embodiment, the prism shape is shown as an example. One end of each of the external connection terminals 71 to 75 is electrically and mechanically bonded to the metal layers 30a, 30e, 30c, 30f, and 30d of the ceramic laminate substrate 10. The other end of each extends from the sealing member 91. The other end can be connected to an external device (not shown).

[0051] External connection terminals 71-75 are primarily composed of a metal with excellent electrical conductivity. Examples of such metals include aluminum, copper, iron, nickel, or alloys containing at least one of these. To improve corrosion resistance, the surfaces of external connection terminals 71-75 may be plated. Examples of plating materials used include nickel, nickel-phosphorus alloys, and nickel-boron alloys. Furthermore, the bonding between external connection terminals 71-75 and metal layers 30a, 30e, 30c, 30f, and 30d can be performed using solder and metal sintering bodies, similar to the bonding of semiconductor chips 60a, 60b, 65a, and 65b. Alternatively, the bonding between external connection terminals 71-75 and metal layers 30a, 30e, 30c, 30f, and 30d can be achieved through direct bonding using ultrasonic waves or lasers.

[0052] Bonding wires 80a-80e are primarily composed of a metal with excellent electrical conductivity. Such metals are made of aluminum, copper, or an alloy containing at least one of these metals. Bonding wire 80a mechanically and electrically connects metal layers 30a and 30b. Bonding wire 80d mechanically and electrically connects metal layer 30e and the control electrode 61a of semiconductor chip 60a. Bonding wire 80b mechanically and electrically connects the output electrode 62a of semiconductor chip 60a, the input electrode 66a of semiconductor chip 65a, and metal layer 30c. Bonding wire 80e mechanically and electrically connects metal layer 30f and the control electrode 61b of semiconductor chip 60b. Bonding wire 80c mechanically and electrically connects the output electrode 62b of semiconductor chip 60b, the input electrode 66b of semiconductor chip 65b, and metal layer 30d. It should be noted that the diameter of the bonding wires 80d and 80e used for control is, for example, 25 μm or more and 400 μm or less, and the diameter of the bonding wires 80a to 80c used for main current is 250 μm or more and 600 μm or less.

[0053] The housing 90 houses the metal layer 30 on the front side of the ceramic laminate substrate 10, the semiconductor chips 60a, 60b, 65a, 65b, and one end of the external connection terminals 71-75. The other end of the external connection terminals 71-75 may also extend upwards (in the +Z direction) from the front side of the housing. The housing 90 is made of resin. This resin is primarily composed of thermoplastic resin. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0054] The sealing member 91 can seal the inside of the housing 90. That is, the sealing member 91 seals the metal layer 30 on the front side of the ceramic multilayer substrate 10, the semiconductor chips 60a, 60b, 65a, 65b, and one end of the external connection terminals 71-75. The sealing member 91 includes, for example, a thermosetting resin and a filler contained in the thermosetting resin. The thermosetting resin is, for example, epoxy resin, phenolic resin, or maleimide resin. As an example of such a sealing member, there is epoxy resin containing a filler. The filler is an inorganic material. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. In addition to the above materials, the sealing member 91 can also be a silicone gel.

[0055] In addition, such as Figure 3 As shown, semiconductor device 1 constitutes a half-bridge circuit including upper arm A and lower arm B. Connection point P is connected to the positive terminal of an external power supply (not shown). Connection point P is connected to connection point C1 of the collector of semiconductor chip 60a via wiring 81. Connection point M is connected to a load (not shown). Connection point M is connected to connection points E1C2 of the emitter of semiconductor chip 60a and the collector of semiconductor chip 60b via wiring 83. Connection point N is connected to the negative terminal of an external power supply (not shown). Connection point N is connected to connection point E2 of the emitter of semiconductor chip 60b via wiring 85. Here, when semiconductor device 1 is operating, connection point P has a higher potential than connection point M. Therefore, the potential of wiring 81 is higher than the potential of wiring 83. Furthermore, the potential of connection point M is higher than the potential of connection point N. Therefore, the potential of wiring 83 is higher than the potential of wiring 85. The potential of wiring 81 can be 250V higher than the potential of wiring 83 but less than 1000V. In addition, the potential of wiring 83 can be more than 250V higher and less than 1000V higher than the potential of wiring 85.

[0056] Connection points G1 and G2 are connected to the control power supply (not shown). Connection point G1 is connected to the control electrode 61a of the semiconductor chip 60a via wiring 82. Figure 3 Illustrations omitted; please refer to the original text. Figure 1 Connection point G2 is connected to the control electrode 61b of semiconductor chip 60b via wiring 84. Figure 3 Illustrations omitted; please refer to the original text. Figure 1 )connect.

[0057] The upper arm A of the semiconductor device 1 includes metal layers 30a, 30b, and 30e of the ceramic multilayer substrate 10, semiconductor chips 60a and 65a, external connection terminals 71, 73, and 72, and bonding wires 80a, 80b, and 80d connecting them. The lower arm B of the semiconductor device 1 includes metal layers 30d, 30c, and 30f of the ceramic multilayer substrate 10, semiconductor chips 60b and 65b, external connection terminals 75, 73, and 74, and bonding wires 80c and 80e connecting them. Furthermore, the upper arm A and lower arm B are connected by electrically connecting the metal layers 30b and 30c using the bonding wire 80b. Thus, the semiconductor device 1 can function as a half-bridge circuit including the upper arm A and the lower arm B.

[0058] Wiring 81 includes an external connection terminal 71 as a P-terminal (positive electrode), a metal layer 30a connected to the external connection terminal 71, a metal layer 30b on which semiconductor chips 60a and 65a are disposed, and a bonding wire 80a connecting the metal layers 30a and 30b. Wiring 83 includes an external connection terminal 73 as an M-terminal, a metal layer 30c on which the external connection terminal 73 and semiconductor chips 60b and 65b are disposed, and a bonding wire 80b connecting the metal layer 30c to semiconductor chips 60a and 65a. Wiring 85 includes an external connection terminal 75 as an N-terminal (negative electrode), a metal layer 30d on which the external connection terminal 75 is disposed, and a bonding wire 80c connecting the metal layer 30d to semiconductor chips 60b and 65b.

[0059] Therefore, when the semiconductor device 1 is operating, if the metal layer 40 formed on the back side of the ceramic plate 20 is grounded such that it has the same potential as the N terminal, the metal layer 40 becomes a low potential relative to the metal layers 30a, 30b, and 30c corresponding to the wirings 81 and 83. That is, in this case, the low-potential metal layer is the metal layer 40 formed on the back side of the ceramic plate 20, and the high-potential metal layers are the metal layers 30a, 30b, and 30c formed on the front side of the ceramic plate 20. For example, the potential of the metal layer 40 is 500V or more lower than 2000V lower than the potential of the metal layers 30a and 30b. In addition, the potential of the metal layer 40 is 250V or more lower than 1000V lower than the potential of the metal layer 30c.

[0060] Furthermore, when the semiconductor device 1 is operating, if the metal layer 40 formed on the back side of the ceramic plate 20 is grounded at the same potential as the M terminal, or if it is ungrounded and floating, the metal layer 40 becomes a low potential relative to the metal layers 30a and 30b corresponding to the wiring 81. That is, in this case, the low-potential metal layer is the metal layer 40 formed on the back side of the ceramic plate 20, and the high-potential metal layer is the metal layers 30a and 30b formed on the front side of the ceramic plate 20. For example, the potential of the metal layer 40 is 250V or more lower than that of the metal layers 30a and 30b, but less than 1000V. Additionally, the metal layer 30d corresponding to the wiring 85 becomes a low potential relative to the metal layer 40. That is, in this case, the low-potential metal layer is the metal layer 30d formed on the front side of the ceramic plate 20, and the high-potential metal layer is the metal layer 40 formed on the back side of the ceramic plate 20. For example, the potential of metal layer 30d is more than 250V lower and less than 1000V lower than the potential of metal layer 40.

[0061] (Method for manufacturing semiconductor devices) Next, use Figure 4 The manufacturing method of the ceramic multilayer substrate 10 included in the semiconductor device 1 will be described. Figure 4 This is a flowchart illustrating a method for manufacturing a ceramic multilayer substrate included in the semiconductor device of the first embodiment. When manufacturing the ceramic multilayer substrate 10, firstly, a ceramic plate and a metal foil are made (steps S1a and S1b). It should be noted that either step S1a or S1b can be performed first.

[0062] The fabrication of the ceramic plate is described (step S1a). First, silicon oxide (SiO2) powder is added to alumina (Al2O3) powder and stirred with a binder or the like to form a plate. Magnesium oxide (MgO) powder is coated onto the surface of the plate, and the plate is fired at a predetermined temperature for a predetermined time. The ceramic plate formed by firing in this way contains alumina as ceramic particles, and contains silicon-containing oxides (second oxides) at the grain boundaries and triple points of the ceramic particles, and magnesium oxides are formed on the surface. Alternatively, magnesium oxides may be formed at the grain boundaries and triple points of the ceramic particles. It should be noted that the coating of magnesium oxide-based powder can be omitted at this time. The average particle size of the ceramic particles is 0.5 μm or more and 25 μm or less. More preferably, it is 1 μm or more and 10 μm or less.

[0063] In the ceramic plate 20, the alumina content, calculated as oxides, is 90 wt% or more and 99 wt% or less, more preferably 92 wt% or more and 98 wt% or less. Furthermore, relative to the ceramic plate 20, the content of silicon oxides, calculated as silicon oxide (SiO2), is 0.01 wt% or more and 3.0 wt% or less, more preferably 1.0 wt% or more and 3.0 wt% or less. If the content of silicon oxides is too low, a large number of voids remain in the ceramic plate, making it prone to cracking. Conversely, if the content of silicon oxides is too high, the conduction of ions in the ceramic plate increases during the operation of the semiconductor device 1, which can easily lead to a decrease in insulation and / or a decrease in the bonding strength of the copper foil.

[0064] In addition to ceramic particles, magnesium oxide, and silicon oxide, the ceramic plate 20 also includes various materials used in its manufacture. One example of such material is a sodium oxide, such as sodium oxide (Na₂O). The content of sodium oxide relative to the total amount obtained by oxide conversion, expressed as sodium oxide (Na₂O), is 0.001 wt% or more and 0.2 wt% or less, more preferably 0.002 wt% or more and 0.2 wt% or less. If the content of sodium oxide is too low, it is difficult to refine the ceramic raw material powder. Conversely, if the content of sodium oxide is too high, β-alumina (Na₂O) is formed. 11Al2O3) can easily cause a decrease in insulation and / or strength. Preferably, the ceramic plate 20 does not contain β-alumina.

[0065] The fabrication of the metal foil is explained (step S1b). A metal foil with copper as the main component is prepared, and its surface is oxidized. This results in the formation of copper oxide (Cu) with a thickness of 10 nm or more and less than 1 μm on the surface of the metal foil. x The oxidation process involves coating with copper oxide (O). Alternatively, either wet or dry oxidation methods can be used. In wet oxidation, for example, a copper-based metal foil can be immersed in a manganese-containing solution for oxidation. Using the manganese-containing solution in wet oxidation, copper oxide and manganese oxides are formed on the surface of the metal foil. In dry oxidation, for example, the copper-based metal foil is heated in an atmospheric or oxygen atmosphere. Thus, in dry oxidation, copper oxide forms on the vast majority of the metal foil's surface, and other metals, including manganese, do not form.

[0066] Next, the front and back sides of the ceramic plate formed in step S1a are bonded to the metal foil formed in step S1b (step S2). That is, the metal foil formed in step S1b is overlapped with the front and back sides of the ceramic plate formed in step S1a, and heat treatment is performed at a predetermined temperature for a predetermined time. It should be noted that the metal layers formed on the front and back sides of the ceramic plate at this time are metal foils produced by either wet oxidation or dry oxidation. That is, metal foils produced by wet oxidation are overlapped with the front and back sides of the ceramic plate, respectively. Metal foils produced by dry oxidation are overlapped with the front and back sides of the ceramic plate 20, respectively.

[0067] If heat treatment is performed in such overlapping manner, copper oxide (Cu) will form at the interface between the ceramic plate and the metal layer. x (O). Furthermore, at the contact interface between the ceramic plate and the metal layer, an intermediate layer 50a, 50b comprising an oxide of at least one of magnesium and manganese can be formed using a predetermined method. The predetermined method may be at least one of a method of coating magnesium oxide during the firing of the ceramic plate, or a method of forming the metal layer using a wet oxidation method with a manganese-containing solution.

[0068] The ceramic laminate substrate 10 described later in Example 1-1 is obtained by coating magnesium oxide during the firing of the ceramic plate 20. Therefore, intermediate layers 50a and 50b containing magnesium oxide as the first oxide are formed at the contact interface between the ceramic plate 20 and the metal layers 30 and 40.

[0069] The ceramic laminate substrate 10 described later in Examples 1-2 was obtained by coating with magnesium oxide and forming metal layers 30 and 40 using a wet oxidation method with a manganese-containing solution during the firing of the ceramic plate 20. Therefore, intermediate layers 50a and 50b containing oxides of both magnesium and manganese as the first oxide are formed at the contact interface between the ceramic plate 20 and the metal layers 30 and 40.

[0070] The ceramic laminate substrate 10 described later in Examples 1-3 is obtained by forming metal layers 30 and 40 using a wet oxidation method with a manganese-containing solution during the firing of the ceramic plate 20. Therefore, intermediate layers 50a and 50b, comprising an oxide containing manganese as a first oxide, are formed at the contact interface between the ceramic plate 20 and the metal layers 30 and 40. Thus, the ceramic plate 20 and the metal layers 30 and 40 are appropriately bonded.

[0071] Next, the metal layers formed on the ceramic plate in step S2 are etched (step S3). That is, metal layers 30a to 30f are formed by etching the metal layers formed on the front side of the ceramic plate into a predetermined shape. Furthermore, metal layer 40 is formed by etching the metal layers formed on the back side of the ceramic plate. It should be noted that copper oxide (Cu) may not be formed on the surfaces of metal layers 30a to 30f and on the surface of metal layer 40. x Coating with copper oxide (Cu). x The coating on the ceramic plate 20 can be removed by heat treatment in a reducing atmosphere during bonding (step S2) or by surface grinding after bonding or etching. The thickness of the ceramic plate 20 is approximately 0.32 mm. The thickness of the metal layers 30 and 40 is approximately 0.3 mm.

[0072] Through the above operations, a ceramic laminate substrate 10 is manufactured, comprising intermediate layers 50a and 50b between the ceramic plate 20 and the metal layers 30 and 40. In such a ceramic laminate substrate 10, the intermediate layers 50a and 50b suppress the reduction of adhesion between the metal layers 30 and 40 and the ceramic plate 20. It should be noted that in step S1a, when magnesium oxide powder is applied, the content of magnesium oxide in the ceramic plate 20 and the intermediate layers 50a and 50b in the ceramic laminate substrate 10, relative to the total amount obtained by oxide conversion, is 0.1 wt% or more and 1.5 wt% or less when converted to magnesium oxide (MgO). Furthermore, in this case, the magnesium content obtained by magnesium oxide (MgO) is 10 wt% or more and 50 wt% or less when converted to silicon oxide (SiO2). In step S1a, without the application of magnesium oxide powder, the ceramic laminate substrate 10 contains no magnesium (less than 0.01 wt% of the detection limit). Furthermore, in step S1b, when a wet oxidation method using a manganese-containing solution is performed, the content of manganese oxides in the ceramic plate 20 and intermediate layers 50a and 50b of the ceramic laminate substrate 10, relative to the total amount obtained by oxide conversion, is calculated as manganese oxide (MnO) of 0.01 wt% or more and 0.15 wt% or less. In this case, the manganese content obtained by manganese oxide (MnO) conversion is calculated as silicon content obtained by silicon oxide (SiO2) conversion of 1.0 wt% or more and 5.0 wt% or less. In step S1b, without the wet oxidation method using a manganese-containing solution, the ceramic laminate substrate 10 contains no manganese (less than 0.01 wt% of the detection limit).

[0073] The ceramic multilayer substrate 10 of Example 1-1 described later is a case where magnesium oxide powder is coated but a wet oxidation process using a manganese-containing solution is not performed. In this case, the ceramic multilayer substrate 10 includes magnesium oxide but does not include manganese oxide. The ceramic multilayer substrate of Example 1-2 described later is a case where both magnesium oxide powder coating and a wet oxidation process using a manganese-containing solution are performed. Therefore, the ceramic multilayer substrate 10 contains both magnesium oxide and manganese oxide. The ceramic multilayer substrate 10 of Example 1-3 described later is a case where magnesium oxide powder coating is not performed but a wet oxidation process using a manganese-containing solution is performed. Therefore, the ceramic multilayer substrate 10 does not contain magnesium oxide but contains manganese oxide. It should be noted that the ceramic multilayer substrate 100 of the comparative example described later is a case where both magnesium oxide powder coating and a wet oxidation process using a manganese-containing solution are not performed. Therefore, the ceramic laminate substrate 100 does not contain oxides containing magnesium or oxides containing manganese.

[0074] (Comparative Example 1 ceramic laminate substrate) In the following explanation of how the interlayers 50a and 50b are used to suppress the degradation of the bonding strength of the metal layers 30 and 40, firstly, as a comparative example 1, using... Figure 5 , Figure 6 as well as Figure 13 The ceramic laminate substrate excluding intermediate layers 50a and 50b is described. Figure 5 This is a schematic cross-sectional view of the ceramic multilayer substrate of Comparative Example 1. Figure 6 This is a cross-sectional schematic diagram of the ceramic multilayer substrate of Comparative Example 1 under high temperature and high voltage. Figure 13 This is a table summarizing the test results for ceramic multilayer substrates. It should be noted that... Figure 5 schematically shown Figure 2 The microscopic state within the area enclosed by the dashed line. Additionally, in Figure 6 The diagram illustrates the use of... Figure 5 The microstructure of the metal layers 30 and 40 under high temperature when a high voltage is applied. Additionally, Figure 13 The test results from Examples 1-1 to 1-3, which will be described later, are shown together with Comparative Example 1.

[0075] The ceramic plate 120 included in the ceramic laminate substrate of Comparative Example 1 is... Figure 4 The ceramic plate is manufactured without magnesium oxide coating in step S1a. The ceramic plate is primarily composed of aluminum oxide, and also contains oxides containing silicon and oxides containing sodium. Furthermore, the metal layer included in the ceramic laminate substrate of Comparative Example 1 is... Figure 4 This ceramic plate is produced by the dry oxidation method in step S1b. The ceramic plate and metal layer are then subjected to… Figure 4The ceramic multilayer substrate 100 of Comparative Example 1 is manufactured by proceeding through steps S2 and S3. The ceramic multilayer substrate 100 does not contain magnesium or manganese. That is, the ceramic multilayer substrate 100 thus manufactured does not form intermediate layers 50a and 50b containing oxides of at least one of magnesium and manganese.

[0076] like Figure 5 As shown, the ceramic laminate substrate 100 thus manufactured is constructed by sequentially stacking a metal layer 40, a ceramic plate 120, and a metal layer 30 from bottom to top. The ceramic plate 120 contains at least alumina 21 (Al2O3) particles, and contains silicon oxide 22 (Si-O) and sodium oxide 23 (Na2O) at its grain boundaries and triple points. Furthermore, the metal layers 30 and 40 are primarily composed of copper (Cu) and are constructed in an oxygen-free manner. Copper oxides 31 and 41 (Cu-O) are formed at the boundaries between the metal layers 30 and 40 and the ceramic plate 120, respectively.

[0077] The results of the peel strength evaluation test for such a ceramic laminate substrate 100 are explained. The peel strength evaluation test refers to measuring the peel strength of the metal layers 30 and 40 of the ceramic laminate substrate 100 relative to the ceramic plate 120 before and after the reliability test. Next, a test is conducted to evaluate the bonding strength of the metal layers 30 and 40 relative to the ceramic plate 120 based on the measurement results. It should be noted that the peel strength value is obtained by averaging the measured values ​​at 40.

[0078] First, in reliability testing, the half-bridge circuit is continuously operated for a predetermined time in a predetermined on / off mode under high-temperature conditions. It should be noted that the metal layer 40 formed on the back side of the ceramic plate 120 is grounded so that it is at the same potential as the N terminal. Therefore, the metal layer 30 formed on the front side of the ceramic plate 120 is a high-potential metal layer, and the metal layer 40 formed on the back side is a low-potential metal layer. This continuous operation is performed on the front side of the ceramic laminate substrate 100.

[0079] The peel strength was measured as follows. In the ceramic laminate substrate 100, a strip pattern of predetermined width was formed on a portion of the metal layers 30 and 40. One end of the strip-shaped metal layers 30 and 40 was peeled from the ceramic plate 120, and the peeled end was peeled off at a predetermined length along a direction perpendicular to the main surface of the ceramic laminate substrate 100 at a certain speed. The load under this tension was measured.

[0080] The evaluation is based on the change in peel strength of the metal layers 30 and 40 included in the ceramic laminate substrate 100 before and after the reliability test. Regarding the peel strength before the reliability test, if the peel strength after the reliability test is 95% or higher, it is rated as "Excellent"; if it is less than 95% but more than 90%, it is rated as "Good"; if it is less than 90% but more than 60%, it is rated as "Acceptable"; and if it is less than 60%, it is rated as "Unacceptable" (refer to...). Figure 13 It should be noted that... Figure 13 Examples 1-1 to 1-3 and Comparative Example 1 are shown, along with the ceramic plate, metal layer, intermediate layer, and test results used in this evaluation.

[0081] like Figure 13 As shown in the far right column, the evaluation results for Comparative Example 1 are "Excellent" on the front side of the ceramic laminate substrate 100, but "Unacceptable" on the back side. That is, reliability testing shows that the ceramic laminate substrate 100 exhibits reduced bonding strength between the metal layer 40 and the back side of the ceramic plate 120. The reasons for this are not yet fully explained, nor are they limited by theory; the following considerations are possible.

[0082] The ceramic laminate substrate 100 after reliability testing becomes as follows Figure 6 The composition is as shown. By applying high-potential (positive electrode) and low-potential (negative electrode) voltages to metal layers 30 and 40 at high temperatures, sodium oxide 23 (refer to...) is... Figure 5 ) separated into sodium ions 24 (Na + ) and oxygen ions 25 (O 2- Sodium ions 24 move toward the low-potential metal layer 40, which serves as the negative electrode, via the silicon oxide 22 on the grain boundaries of aluminum oxide 21. Meanwhile, oxygen ions 25 move toward the high-potential metal layer 30, which serves as the positive electrode, via the silicon oxide 22 on the grain boundaries of aluminum oxide 21.

[0083] Oxygen ions 25 that move to the positive electrode react with copper contained in the metal layer 30 to form a copper oxide 31. At the positive electrode, the increase of copper oxide 31 enhances the bonding force with aluminum oxide 21 and silicon oxide 22.

[0084] On the other hand, sodium ions 24 that move to the negative electrode react with copper oxide 41 (see reference). Figure 5The reaction reduces copper oxide, and the copper oxide 41 at the negative electrode, after reacting with sodium ions 24, becomes Cu and is contained in the metal layer 40. Additionally, sodium ions 24 are oxidized to sodium oxide. Thus, the copper oxide 41, which has a strong bonding force with both aluminum oxide 21 and silicon oxide 22, is reduced. Furthermore, near the boundary of the metal layer 40 at the negative electrode, the concentration of sodium ions (sodium oxide 23) increases in the ceramic plate 120, making it easier for aluminum oxide 21 particles to detach. Therefore, the bonding strength between the metal layer 40 and the ceramic plate 120 decreases.

[0085] When such a ceramic multilayer substrate 100 is used instead of the ceramic multilayer substrate 10 of the semiconductor device 1, if the metal layer 40 is grounded, the metal layer 40 becomes a low potential (reference potential), the metal layer 30a becomes a high potential, and the metal layer 30c becomes an intermediate potential. Therefore, the bonding strength is reduced in the portion of the metal layer 40 opposite to the metal layers 30a and 30c (especially the high-potential metal layer 30).

[0086] It should be noted that metal layer 40 may be set to a floating potential without grounding, or the midpoint of metal layer 40 may be grounded (grounded in a manner that makes it the same potential as metal layer 30c). In these cases, metal layers 30a and 30b on the collector side of the upper arm become high potential, while metal layer 40 becomes low potential. This results in reduced bonding strength of the portion of metal layer 40 opposite to metal layers 30a and 30b. On the other hand, metal layer 30d on the emitter side of the lower arm becomes low potential, while metal layer 40 opposite to metal layer 30d becomes high potential, resulting in reduced bonding strength of metal layer 30d.

[0087] Furthermore, Examples 1-1 to 1-3, corresponding to the intermediate layers 50a and 50b, will be described below in the ceramic laminate substrate 10, which includes a ceramic plate 20 with alumina as the main component.

[0088] (Ceramic laminate substrate of Example 1-1) Next, use Figure 7 , Figure 8 as well as Figure 13 The ceramic laminate substrate 10 containing intermediate layers 50a and 50b will be described. Figure 7 This is a cross-sectional schematic diagram of the ceramic laminated substrate of the first embodiment (Example 1-1). Figure 8 This is a schematic cross-sectional view of the ceramic laminate substrate of the first embodiment (Example 1-1) under high temperature and high voltage. It should be noted that... Figure 7 schematically shown Figure 2 The microscopic state within the area enclosed by the dashed line. Additionally, in Figure 8 The diagram illustrates the use of... Figure 2The microscopic state of metal layers 30 and 40 when a high voltage is applied at high temperature.

[0089] like Figure 7 As shown, the ceramic laminate substrate 10 of Example 1-1 is constructed by sequentially stacking a metal layer 40, an intermediate layer 50b, a ceramic plate 20, an intermediate layer 50a, and a metal layer 30 from bottom to top.

[0090] Ceramic plate 20 is in Figure 4 It is manufactured by coating magnesium oxide powder in step S1a. Additionally, metal layers 30 and 40 are... Figure 4 The ceramic plate 20 is manufactured by a dry oxidation process in step S1b. Between the alumina 21 particles (grain boundaries and triple points), the ceramic plate 20 contains silicon oxide 22 and sodium oxide 23 as a second oxide. Additionally, magnesium oxide may be included.

[0091] Furthermore, intermediate layers 50a and 50b respectively contain magnesium oxides 51a and 51b (Mg-O) as first oxides. Magnesium oxides 51a and 51b are formed in large quantities on the front and back sides of the ceramic plate 20 in intermediate layers 50a and 50b, respectively. In addition, copper oxides 31 and 41 are formed at the boundaries between the metal layers 30 and 40 and the ceramic plate 20, and at the boundaries between the magnesium oxides 51a and 51b and the metal layers 30 and 40 and the ceramic plate 20, respectively.

[0092] In the ceramic laminate substrate 10 (before reliability testing), if there is too much magnesium oxide 51a and 51b, the bonding strength between the ceramic plate 20 and the metal layers 30 and 40 will decrease. Therefore, it is preferable that the intermediate layers 50a and 50b containing magnesium oxide 51a and 51b are formed such that they cover 10% or more and 80% or less of the bonding surface between the ceramic plate 20 and the metal layers 30 and 40, more preferably 20% or more and 50% or less.

[0093] Peel strength tests were also conducted on this ceramic laminate substrate 10. For example... Figure 13 As shown, the evaluation results for Example 1-1 are "Excellent" on the front side of the ceramic laminate substrate 10 and "Acceptable" on the back side. That is, the ceramic laminate substrate 10 was also subjected to reliability testing, and compared to Comparative Example 1, the bonding force of the metal layer 40 to the back side of the ceramic plate 20 was slightly improved, and the reduction in bonding strength was suppressed. The reasons for this are not yet fully explained, nor are they limited to theory, but the following considerations are possible.

[0094] The ceramic laminate substrate 10 after reliability testing becomes as follows Figure 8 The composition is as shown. By applying high-potential (positive electrode) and low-potential (negative electrode) voltages to metal layers 30 and 40 at high temperatures, sodium oxide 23 (refer to...) is... Figure 7 ) separated into sodium ions 24 (Na + ) and oxygen ions 25 (O 2- Sodium ions 24 move towards the low-potential metal layer 40, which serves as the negative electrode, through the grain boundaries of aluminum oxide 21 and the silicon-containing oxide 22 at the triple point. Meanwhile, oxygen ions 25 move towards the high-potential metal layer 30, which serves as the positive electrode, through the grain boundaries of aluminum oxide 21 and the silicon-containing oxide 22 at the triple point.

[0095] Oxygen ions 25 that move to the positive electrode react with copper in the metal layer 30 to form a copper oxide 31. Thus, the amount of copper oxide 31 increases at the positive electrode, thereby improving the bonding force between the aluminum oxide 21 and the silicon oxide 22.

[0096] On the other hand, sodium ions 24 that move to the negative electrode are in the region where magnesium oxide 51b is absent and copper oxide 41 is present (see reference). Figure 7 The reaction reduces copper oxide, and the copper oxide 41 at the negative electrode, after reacting with sodium ions 24, becomes Cu and is contained in the metal layer 40. Additionally, sodium ions 24 are oxidized to sodium oxide. Thus, the amount of copper oxide 41 with strong bonding to both aluminum oxide 21 and silicon oxide 22 is reduced. Furthermore, in the ceramic plate 20 near the boundary of the metal layer 40 at the negative electrode, the concentration of sodium ions (sodium oxide 23) increases, making it easier for aluminum oxide 21 particles to detach.

[0097] However, unlike Comparative Example 1, the ceramic laminate substrate 10 has magnesium oxide 26 disposed in the intermediate layers 50a and 50b. Therefore, the reaction between sodium ions 24 and the copper oxide 41 is hindered. Thus, at the locations where the magnesium oxide 51b is formed, the copper oxide 41 does not become Cu and remains. Furthermore, magnesium oxide 26 is present at the grain boundaries and triple points of the aluminum oxide 21. Therefore, the movement path of a portion of the silicon oxide 22 at the grain boundaries is interrupted, and the movement of a portion of the sodium ions 24 is also interrupted. Therefore, the reaction between sodium ions 24 and the copper oxide 41 is suppressed. Therefore, the bonding strength between the ceramic plate 20 and the metal layer 40 is maintained at this location.

[0098] Through the above operations, compared with the case of Comparative Example 1, the ceramic laminate substrate 10 of Example 1-1 suppressed the decrease in the bonding strength between the ceramic plate 20 and the metal layer 40, and improved the bonding strength between the metal layer 40 and the ceramic plate 20.

[0099] According to Comparative Example 1, even without the intermediate layers 50a and 50b, the bonding strength of the metal layer 30 on the front side (high potential side) of the ceramic plate 120 can be maintained to a certain extent, but the bonding strength of the metal layer 40 is reduced on the back side (low potential side) of the ceramic plate 120. The reduction in the bonding strength of the metal layer 40 is suppressed by the intermediate layer 50b between the back side (low potential side) of the ceramic plate 20 and the metal layer 40 in the ceramic laminate substrate 10 of the first embodiment. Therefore, in the ceramic laminate substrate 10, as long as there is at least an intermediate layer 50b between the back side (low potential side) of the ceramic plate 20 and the metal layer 40, the reduction in the bonding strength of the metal layer 40 can be suppressed, and the deterioration of the ceramic laminate substrate 10 can be prevented.

[0100] The aforementioned semiconductor device 1 includes: semiconductor chips 60a, 60b, 65a, and 65b; a bonding member 35; and a ceramic multilayer substrate 10, which is plate-shaped and has a front side and a back side opposite to the front side. The semiconductor chips 60a, 60b, 65a, and 65b are bonded to the front side via the bonding member 35. The ceramic multilayer substrate 10 has a ceramic plate 20, metal layers 30 and 40, and an intermediate layer 50b. The ceramic plate 20 is plate-shaped and has a first main surface (front side in the first embodiment) and a second main surface opposite to the first main surface (back side in the first embodiment), and contains ceramic particles. The metal layer 30 is bonded to the first main surface of the ceramic plate 20 by applying a high potential voltage and contains copper. The metal layer 40 is bonded to the second main surface of the ceramic plate 20 by applying a low potential voltage and contains copper. The intermediate layer 50b is formed between the second main surface of the ceramic plate 20 and the low potential metal layer 40 and contains magnesium oxide 51b. The ceramic multilayer substrate 10, through the magnesium oxide 51b contained between the ceramic plate 20 and the low-potential metal layer 40, suppresses the reduction of the bonding between the metal layer 40 and the ceramic plate 20 even when a high voltage is applied at high temperature. Therefore, it is possible to prevent the degradation of the ceramic multilayer substrate 10 and suppress the reduction of the reliability of the semiconductor device 1.

[0101] Furthermore, in the first and second embodiments, when the metal layer 40 formed on the back side of the ceramic plate 20 is grounded such that it has the same potential as the N terminal, the high-potential metal layers are the metal layers 30a, 30b, and 30c formed on the front side of the ceramic plate 20. The low-potential metal layer is the metal layer 40 formed on the back side of the ceramic plate 20.

[0102] Furthermore, in the first and second embodiments, when the metal layer 40 formed on the back side of the ceramic plate 20 is grounded to the same potential as the M terminal, or when it is ungrounded and floating, the high-potential metal layer is the metal layers 30a and 30b formed on the front side of the ceramic plate 20, and the low-potential metal layer is the metal layer 40 formed on the back side of the ceramic plate 20 opposite to the metal layers 30a and 30b. In this case, the low-potential metal layer is the metal layer 30d formed on the front side of the ceramic plate 20, and the high-potential metal layer is the metal layer 40 formed on the back side of the ceramic plate 20 opposite to the metal layer 30d.

[0103] It should be noted that, in the third embodiment, the region (location) where the intermediate layer is required based on the potential between the ceramic plate 20 and the metal layers 30 and 40 when the semiconductor device 1 is driven or stopped will be described.

[0104] It should be noted that in this embodiment, the method for forming magnesium oxide in the intermediate layers 50a and 50b is described as follows: in the ceramic plate manufacturing process (step S1a), magnesium oxide powder is coated onto the surface of the plate-shaped material, and then fired at a predetermined temperature for a predetermined time. However, this is not a limitation; in the ceramic plate manufacturing process (step S1a), a manganese-containing solution may also be coated onto the surface of the plate-shaped material and then fired. In both the ceramic plate manufacturing process (step S1a) and the metal foil manufacturing process (step S1b), magnesium or magnesium oxide can be formed on the ceramic plate or metal foil by sputtering or vapor deposition, and magnesium oxide can also be formed in the intermediate layers 50a and 50b.

[0105] Furthermore, in this embodiment, regarding the method of forming manganese oxides in the intermediate layers 50a and 50b, the method described involves immersing the metal foil in a manganese-containing solution to oxidize it during the metal foil manufacturing process (step S1b). However, this is not a limitation; during the ceramic plate manufacturing process (step S1a), manganese powder or a solution may be coated onto the surface of the plate-shaped material and then fired. During the ceramic plate manufacturing process (step S1a) or the metal foil manufacturing process (step S1b), manganese or manganese oxides can be formed on the ceramic plate or metal foil by sputtering or vapor deposition, and manganese oxides can also be formed in the intermediate layers 50a and 50b.

[0106] (Ceramic laminate substrates of Examples 1-2) In the manner of Examples 1-2, using Figure 9 , Figure 10 as well as Figure 13 , for Figure 4The process of manufacturing a ceramic plate 20 of a ceramic laminate substrate 10 by coating magnesium oxide powder in step S1a, and manufacturing metal layers 30 and 40 by wet oxidation will be described. Figure 9 This is a cross-sectional schematic diagram of the ceramic laminated substrate of the first embodiment (Examples 1-2). Figure 10 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Examples 1-2) under high temperature and high voltage. It should be noted that... Figure 9 schematically shown with Figure 2 The microscopic state of the area corresponding to the region enclosed by the dashed line. Additionally, in Figure 10 The diagram illustrates the use of... Figure 2 The microscopic state of metal layers 30 and 40 when a high voltage is applied at high temperature.

[0107] like Figure 9 As shown, the ceramic laminate substrate 10 of Examples 1-2 is constructed by sequentially stacking a metal layer 40, an intermediate layer 50b, a ceramic plate 20, an intermediate layer 50a, and a metal layer 30 from bottom to top.

[0108] Similar to Example 1-1, the ceramic plate 20 is... Figure 4 It is manufactured by coating magnesium oxide powder in step S1a. On the other hand, unlike Example 1-1, the metal layers 30 and 40 are... Figure 4 The ceramic plate 20 is manufactured by a wet oxidation process in step S1b. Between the alumina 21 particles (grain boundaries and triple points), the ceramic plate 20 contains silicon oxide 22 and sodium oxide 23 as a second oxide. Magnesium oxide may also be included.

[0109] Furthermore, metal layers 30 and 40 are primarily composed of copper. Intermediate layers 50a and 50b respectively contain magnesium and manganese oxides 52a and 52b (Mg-Mn-O) as the first oxide. The magnesium and manganese oxides 52a and 52b are formed in large quantities on the front and back sides of the ceramic plate 20 within the intermediate layers 50a and 50b, respectively. Additionally, copper oxides 31 and 41 are formed at the boundaries of metal layers 30 and 40, the ceramic plate 20, and the magnesium and manganese oxides 52a and 52b, respectively.

[0110] In Example 1-1, the coverage of the intermediate layers 50a and 50b in the ceramic laminate substrate 10 (before reliability testing) is limited, thus failing to improve the bonding strength between the ceramic plate 20 and the metal layers 30 and 40. In Example 1-2, the intermediate layers 50a and 50b, comprising oxides 52a and 52b of magnesium and manganese, can be formed more widely. Therefore, the bonding strength between the ceramic plate 20 and the metal layers 30 and 40 is improved compared to Example 1-1. Preferably, the intermediate layers 50a and 50b are formed such that they cover 20% or more and 80% or less of the bonding surface between the ceramic plate 20 and the metal layers 30 and 40.

[0111] Peel strength tests were also conducted on this ceramic laminate substrate 10. For example... Figure 13 As shown, the evaluation results for Examples 1-2 are "excellent" on both the front and back sides of the ceramic multilayer substrate 10. That is, the ceramic multilayer substrate 10 also underwent reliability testing, and compared to Examples 1-1, the bonding force of the metal layer 40 to the back side of the ceramic plate 20 was improved, and the reduction in bonding strength was suppressed. The reasons for this are not yet fully explained, nor are they limited to theory, but the following considerations are possible.

[0112] The ceramic laminate substrate 10 after reliability testing becomes as follows Figure 10 The composition is as shown. By applying high-potential (positive electrode) and low-potential (negative electrode) voltages to metal layers 30 and 40 at high temperatures, sodium oxide 23 (refer to...) is... Figure 9 The alumina ions 24 and oxygen ions 25 are separated. Sodium ions 24 move towards the low-potential metal layer 40, which serves as the negative electrode, through the grain boundaries of alumina 21 and the silicon-containing oxide 22 at the triple point. Meanwhile, oxygen ions 25 move towards the high-potential metal layer 30, which serves as the positive electrode, through the silicon-containing oxide 22 at the grain boundaries of alumina 21.

[0113] Oxygen ions 25 that move to the positive electrode react with copper in the metal layer 30 to form a copper oxide 31. Thus, the amount of copper oxide 31 increases at the positive electrode, thereby improving the bonding force between the aluminum oxide 21 and the silicon oxide 22.

[0114] However, in Examples 1-2, magnesium oxide 26 is disposed at the grain boundaries and triple points of alumina 21 in the ceramic laminate substrate 10. Furthermore, oxides 52b containing magnesium and manganese are formed at the boundaries and triple points between the alumina 21 at the negative electrode and the low-potential metal layer 40. Specifically, the region where the oxides 52b containing magnesium and manganese are formed is wider than the region containing magnesium oxide 51b in Example 1-1. Therefore, sodium ions 24 moving to the negative electrode are cut off from movement by the oxides 52b containing magnesium and manganese. Therefore, the reaction between sodium ions 24 and the oxide 41 containing copper is more hindered compared to Example 1-1. Therefore, at the boundaries of alumina 21, metal layer 40, and the oxides 52b containing magnesium and manganese, the oxide 41 containing copper does not become Cu and remains. Therefore, the bonding strength between the ceramic plate 20 and the metal layer 40 is maintained better than in Example 1-1.

[0115] Through the above operations, compared with the case of Example 1-1, the ceramic laminate substrate 10 of Example 1-2 suppresses the decrease in the bonding strength between the ceramic plate 20 and the metal layer 40, and improves the bonding strength of the metal layer 40 relative to the ceramic plate 20.

[0116] (Ceramic laminate substrates of Examples 1-3) In Examples 1-3, using Figure 11 , Figure 12 as well as Figure 13 , for Figure 4 In step S1a, the ceramic plate 20 of the ceramic laminate substrate 10 is manufactured without coating with magnesium oxide powder, and the metal layers 30 and 40 are manufactured by wet oxidation. Figure 11 This is a cross-sectional schematic diagram of the ceramic laminated substrate of the first embodiment (Examples 1-3). Figure 12 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the first embodiment (Examples 1-3) under high temperature and high voltage. It should be noted that... Figure 11 schematically shown Figure 2 The microscopic state within the area enclosed by the dashed line. Additionally, in Figure 12 The diagram illustrates the use of... Figure 2 The microscopic state of metal layers 30 and 40 when a high voltage is applied at high temperature.

[0117] like Figure 11 As shown, the ceramic laminate substrate 10 of Examples 1-3 is constructed by sequentially stacking a metal layer 40, an intermediate layer 50b, a ceramic plate 20, an intermediate layer 50a, and a metal layer 30 from bottom to top.

[0118] Unlike Examples 1-1 and 1-2, the ceramic plate 20 is... Figure 4The product is manufactured without applying magnesium oxide powder in step S1a. Furthermore, similar to Examples 1-2, metal layers 30 and 40 are... Figure 4 The ceramic plate 20 is manufactured by wet oxidation in step S1b. The ceramic plate 20 contains silicon oxide 22 and sodium oxide 23 as a second oxide between the particles (grain boundaries and triple points) of alumina 21.

[0119] Furthermore, metal layers 30 and 40 are primarily composed of copper. Intermediate layers 50a and 50b respectively contain manganese oxides 53a and 53b (Mn-O) as first oxides. Manganese oxides 53a and 53b are formed in large quantities on the front and back sides of the ceramic plate 20 within intermediate layers 50a and 50b, respectively. Additionally, copper oxides 31 and 41 are formed at the boundaries of metal layers 30 and 40, the ceramic plate 20, and the manganese oxides 53a and 53b, respectively.

[0120] In the ceramic laminate substrate 10 (before reliability testing), if there is too much manganese oxide 53a and 53b, the bonding strength between the ceramic plate 20 and the metal layers 30 and 40 will decrease. Therefore, it is preferable that the intermediate layers 50a and 50b containing manganese oxide 53a and 53b are formed such that they cover 10% or more and 80% or less of the bonding surface between the ceramic plate 20 and the metal layers 30 and 40, more preferably 20% or more and 50% or less.

[0121] Peel strength tests were also conducted on this ceramic laminate substrate 10. For example... Figure 13 As shown, the evaluation results for Examples 1-3 are "Excellent" on the front side and "Good" on the back side. That is, the ceramic multilayer substrate 10 also underwent reliability testing, and compared to Examples 1-1, the bonding force of the metal layer 40 to the back side of the ceramic plate 20 was slightly improved, and the reduction in bonding strength was suppressed. The reasons for this are not yet fully explained, nor are they limited to theory, but the following considerations are possible.

[0122] The ceramic laminate substrate 10 after reliability testing becomes as follows Figure 12 The composition is as shown. By applying high-potential (positive electrode) and low-potential (negative electrode) voltages to metal layers 30 and 40 at high temperatures, sodium oxide 23 (refer to...) is... Figure 11 The alumina ions 24 and oxygen ions 25 are separated. Sodium ions 24 move towards the low-potential metal layer 40, which serves as the negative electrode, through the grain boundaries of alumina 21 and the silicon-containing oxide 22 at the triple point. Meanwhile, oxygen ions 25 move towards the high-potential metal layer 30, which serves as the positive electrode, through the silicon-containing oxide 22 at the grain boundaries of alumina 21.

[0123] Oxygen ions 25 that move to the positive electrode react with copper in the metal layer 30 to form a copper oxide 31. Thus, the amount of copper oxide 31 increases at the positive electrode, thereby improving the bonding force between the aluminum oxide 21 and the silicon oxide 22.

[0124] On the other hand, sodium ions 24 that move to the negative electrode are in the region where manganese oxide 53b is absent and copper oxide 41 (see reference). Figure 11 The reaction reduces copper oxide, and the copper oxide 41 at the negative electrode, after reacting with sodium ions 24, becomes Cu and is contained in the metal layer 40. Additionally, sodium ions 24 are oxidized to sodium oxide. Thus, the copper oxide 41, which has a strong bonding force with both aluminum oxide 21 and silicon oxide 22, is reduced. Furthermore, at the grain boundaries and triple points of silicon oxide 22 near the boundary of the metal layer 40 at the negative electrode, the concentration of sodium ions (sodium oxide 23) increases, making it easier for aluminum oxide 21 particles to detach.

[0125] However, in the ceramic laminate substrate 10 of Examples 1-3, manganese oxide 27 is disposed in the intermediate layers 50a and 50b. Therefore, the reaction between sodium ions 24 and the copper oxide 41 is hindered. Thus, at the locations where the manganese oxide 53b is formed, the copper oxide 41 does not become Cu and remains. Furthermore, manganese oxide 27 is disposed at the grain boundaries and triple points of the aluminum oxide 21. Therefore, the movement path of a portion of the silicon oxide 22 at the grain boundaries is interrupted, and the movement of a portion of the sodium ions 24 is interrupted. Therefore, the reaction between sodium ions 24 and the copper oxide 41 is suppressed. Therefore, the bonding strength between the ceramic plate 20 and the metal layer 40 is maintained at this location. Furthermore, it is believed that the bonding strength at this location is greater than the bonding strength in Examples 1-1.

[0126] Through the above operations, compared with the case of Example 1-1, the ceramic laminate substrate 10 of Example 1-3 suppressed the decrease in the bonding strength between the ceramic plate 20 and the metal layer 40, and improved the bonding strength between the metal layer 40 and the ceramic plate 20.

[0127] [Second Implementation] Compared to the ceramic plate 20 of the first embodiment, the ceramic laminate substrate 10 of the second embodiment further includes zirconium oxide (ZrO2) in its ceramic plate 20. It should be noted that in the second embodiment, the semiconductor device 1 of the first embodiment is also used. Figure 1 and Figure 2 (This will be explained.)

[0128] (Method for manufacturing semiconductor devices) The ceramic laminate substrate 10 of the second embodiment also conforms to the first embodiment. Figure 4The manufacturing process is described in the flowchart. In the second embodiment, when manufacturing the ceramic laminate substrate 10, a ceramic plate and a metal foil are first fabricated (steps S1a and S1b). It should be noted that either step S1a or S1b can be performed first.

[0129] The fabrication of the ceramic plate is described (step S1a). First, zirconium oxide (ZrO2) powder and silicon oxide (SiO2) powder are added together to alumina (Al2O3) powder, and stirred with a binder to form a plate. Magnesium oxide (MgO) powder is coated onto the surface of the plate, and the plate is fired at a predetermined temperature for a predetermined time. The ceramic plate formed by firing in this way contains alumina as ceramic particles, and contains zirconium oxide and silicon oxide (second oxide) at the grain boundaries and triple points of the ceramic particles. Furthermore, magnesium oxide is formed on the surface. Alternatively, magnesium oxide can also be formed at the grain boundaries and triple points of the ceramic particles. Due to the presence of zirconium oxide, the flexural strength can be improved compared to the case where zirconium oxide is not present.

[0130] To manufacture the ceramic plate 20 of the second embodiment, in addition to zirconium oxide (ZrO2) powder, powders of yttrium oxide (Y2O3), magnesium oxide (MgO), or calcium oxide (CaO) may be added. Alternatively, powder of partially stabilized zirconium oxide may be added instead of zirconium oxide (ZrO2) powder. Thus, the ceramic plate 20 contains alumina as ceramic particles, and oxides (second oxides) containing partially stabilized zirconium oxide and silicon are contained at the grain boundaries and triple points of the ceramic particles. In this case, the partially stabilized zirconium oxide preferably contains 2.5 mol% to 3.5 mol% of yttrium equivalent to yttrium oxide (Y2O3) relative to the partially stabilized zirconium oxide (ZrO2). This further improves the flexural strength compared to the case with only zirconium oxide. Furthermore, the average particle size of the ceramic particles is 0.5 μm or more and 25 μm or less. More preferably, it is 1 μm or more and 10 μm or less.

[0131] In the ceramic plate 20, the alumina content, calculated as oxides, is 80 wt% or more and 95 wt% or less, more preferably 84 wt% or more and 92 wt% or less. Furthermore, the zirconium oxide content, relative to the total amount of zirconium oxide (ZrO2) calculated as oxides, is 5.0 wt% or more and 20.0 wt% or less, more preferably 8 wt% or more and 16 wt% or less. Additionally, the silicon oxide content, relative to the total amount of silicon oxide (SiO2) calculated as oxides, is 0.01 wt% or more and 3.0 wt% or less, more preferably 1.0 wt% or more and 3.0 wt% or less. If the silicon oxide content is too low, a large number of voids remain in the ceramic plate, making it prone to cracking. Conversely, if the silicon oxide content is too high, the thermal conductivity of the ceramic plate decreases, resulting in poor heat dissipation.

[0132] Furthermore, in the ceramic plate 20 of the second embodiment, in addition to ceramic particles, magnesium oxide, silicon oxide, and zirconium oxide, it also contains various materials used in manufacturing. One example of such materials is sodium oxide. For example, sodium oxide is present. The content of sodium oxide relative to the ceramic plate 20, calculated as sodium oxide (Na₂O) relative to the total amount obtained by oxide conversion, is 0.001 wt% or more and 0.2 wt% or less, more preferably 0.002 wt% or more and 0.2 wt% or less. If the content of sodium oxide is too low, it is difficult to refine the ceramic raw material powder. Furthermore, if the content of sodium oxide is too high, β-alumina is formed, which easily leads to a decrease in insulation and / or a decrease in strength. It is preferable that the ceramic plate 20 does not contain β-alumina.

[0133] The metal foil fabrication in step S1b is performed in the same manner as in the first embodiment. Furthermore, the manufacturing methods from step S2 onwards use the ceramic plate fabricated in step S1a of the second embodiment and are performed in the same manner as in the first embodiment.

[0134] Through the above operations, a ceramic laminate substrate 10 is manufactured, comprising intermediate layers 50a and 50b between the ceramic plate 20 and the metal layers 30 and 40. In such a ceramic laminate substrate 10, the intermediate layers 50a and 50b suppress the reduction of the bonding strength between the metal layers 30 and 40 and the ceramic plate 20. It should be noted that in step S1a of the second embodiment, when magnesium oxide powder is applied, the content of magnesium oxide in the ceramic plate 20 and the intermediate layers 50a and 50b in the ceramic laminate substrate 10, relative to the total amount obtained by oxide conversion, is 0.1 wt% or more and 1.5 wt% or less when converted to magnesium oxide (MgO). Furthermore, in this case, the magnesium content obtained by magnesium oxide (MgO) is 2.0 wt% or more and 20.0 wt% or less, more preferably 7.5 wt% or more and 15 wt% or less, relative to the zirconium content obtained by zirconium oxide (ZrO2). In step S1a of the second embodiment, without the application of magnesium oxide powder, magnesium is not present in the ceramic laminate substrate 10 (less than the detection limit of 0.01 wt%). Furthermore, in step S1b, when a wet oxidation method using a manganese-containing solution is performed, the manganese oxide content in the ceramic plate 20 and intermediate layers 50a and 50b of the ceramic laminate substrate 10 is 0.01 wt% or more and 0.15 wt% or less. In this case, the manganese content, converted from manganese oxide, is 0.05 wt% or more and 2 wt% or less relative to the zirconium content, converted from zirconium oxide, more preferably 0.2 wt% or more and 0.8 wt% or less. In step S1b, without the wet oxidation method using a manganese-containing solution, no manganese is detected in the ceramic laminate substrate 10, and the content is less than the detection limit of 0.01 wt%.

[0135] Furthermore, the second embodiment is not limited to this. During the fabrication of the ceramic plate (step S1a) and the metal foil (step S1b), magnesium or magnesium oxide is formed on the ceramic plate or metal foil by sputtering or vapor deposition, thereby enabling the formation of magnesium oxide in the intermediate layers 50a and 50b. In the ceramic plate fabrication process (step S1a), magnesium, or magnesium powder or solution, may be coated onto the surface of the plate-shaped material and then fired.

[0136] Furthermore, Examples 2-1 to 2-3, corresponding to the intermediate layers 50a and 50b, will be described below in the ceramic laminate substrate 10 comprising a ceramic plate mainly composed of alumina and zirconium oxide. It should be noted that in the second embodiments, the same reliability tests as in the first embodiment are also performed.

[0137] (Comparative Example 2 ceramic laminate substrate) Hereinafter, when describing the ceramic plate 20 of the second embodiment, how to suppress the reduction of the bonding strength of the metal layers 30 and 40 by using the intermediate layers 50a and 50b, firstly, as a comparative example 2, using Figure 14 and Figure 15 The ceramic laminate substrate 10 excluding the intermediate layers 50a and 50b will be described. Figure 14 This is a schematic cross-sectional view of the ceramic laminate substrate of Comparative Example 2. Figure 15 This is a schematic cross-sectional view of the ceramic multilayer substrate of Comparative Example 2 under high temperature and high voltage. It should be noted that... Figure 14 schematically shown Figure 2 The microscopic state within the area enclosed by the dashed line. Additionally, in Figure 15 The diagram illustrates the use of... Figure 2 The microscopic state of metal layers 30 and 40 when a high voltage is applied at high temperature.

[0138] The ceramic plate 120 in Comparative Example 2 is Figure 4 In step S1a (second embodiment), magnesium oxide powder is not applied. Furthermore, metal layers 30 and 40 are... Figure 4 It is manufactured by dry oxidation in step S1b.

[0139] like Figure 14 As shown, the ceramic laminate substrate 100 thus manufactured is constructed by sequentially stacking a metal layer 40, a ceramic plate 120, and a metal layer 30 from bottom to top. The ceramic plate 120 contains silicon-containing oxide 22 and zirconium oxide 28 as a second oxide between the alumina 21 particles (grain boundaries and triple points). Additionally, sodium oxide 23 may also be included. It should be noted that instead of zirconium oxide 28, an oxide containing zirconium may be used, such as partially stabilized zirconium oxide. Furthermore, similar to the first embodiment, the metal layers 30 and 40 are primarily composed of copper.

[0140] The ceramic multilayer substrate 100 of the comparative example does not contain magnesium and manganese. That is, the ceramic multilayer substrate 100 manufactured in this way does not form intermediate layers 50a, 50b containing oxides of at least one of magnesium and manganese.

[0141] The same peel strength evaluation test as in the first embodiment was also conducted on this ceramic laminate substrate 100. The evaluation results were "unacceptable" on both the front and back sides of the ceramic plate (the table illustration is omitted). The reasons for this are not yet fully explained, nor are they limited to theory, but the following considerations are possible.

[0142] like Figure 15As shown, in Comparative Example 2, a high potential (positive electrode) and a low potential (negative electrode) voltage are applied to the metal layers 30 and 40 at high temperature on the ceramic multilayer substrate 100. As a result, the copper oxide 41 (Cu-O) formed at the boundary between the metal layer 40 on the negative electrode side and the zirconium oxide 28 of the ceramic plate 120 is reduced. For example, the reaction CuO + 2e (electrons) → Cu + O is generated. 2- The reaction occurs. Therefore, on the negative electrode side, the amount of copper oxide 41 decreases, and the bonding force between the metal layer 40 and the ceramic plate 120 decreases. Then, oxygen ions 25 generated by the reduction of copper oxide 41 (Cu-O) move towards the high-potential metal layer 30, which serves as the positive electrode, through the grain boundaries of alumina 21 and zirconium oxide 28 at the triple point. The oxygen ions 25 that have moved to the positive electrode react with the copper in the metal layer 30, causing the growth of copper oxide 31. For example, Cu+O is generated. 2- → The reaction of CuO + 2e (electrons). Therefore, at the positive electrode, the amount of copper oxide 31 is excessively increased, and the bonding strength between the metal layer 30 and the ceramic plate 120 is reduced.

[0143] In the ceramic plate 120 of the ceramic laminate substrate 100 in Comparative Example 2 of the second embodiment, as described above, the movement of oxygen ions is promoted by zirconium oxide. Therefore, reduction occurs on the negative electrode side and oxidation occurs on the positive electrode side. As a result, the bonding strength of the metal layers 30, 40 with respect to the ceramic plate 120 is further reduced compared to Comparative Example 1 of the first embodiment.

[0144] (Ceramic laminate substrate of Example 2-1) Next, use Figure 16 and Figure 17 The ceramic laminate substrate 10, including intermediate layers 50a and 50b, will be described. It should be noted that Example 2-1 corresponds to Example 1-1. Figure 16 This is a cross-sectional schematic diagram of the ceramic laminated substrate according to the second embodiment (Example 2-1). Figure 17 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Example 2-1) under high temperature and high voltage. It should be noted that... Figure 16 schematically shown Figure 2 The microscopic state within the area enclosed by the dashed line. Additionally, in Figure 17 The diagram illustrates the use of... Figure 2 The microscopic state of metal layers 30 and 40 when a high voltage is applied at high temperature.

[0145] like Figure 16 As shown, the ceramic laminate substrate 10 of Example 2-1 is constructed by sequentially stacking a metal layer 40, an intermediate layer 50b, a ceramic plate 20, an intermediate layer 50a, and a metal layer 30 from bottom to top.

[0146] Ceramic plate 20 is in Figure 4 It is manufactured by coating magnesium oxide powder in step S1a (second embodiment). Furthermore, metal layers 30 and 40 are... Figure 4 It is manufactured by dry oxidation in step S1b.

[0147] The ceramic plate 20 contains silicon-containing oxide 22 and zirconium oxide 28 as a second oxide between the particles (grain boundaries and triple points) of the alumina 21. Additionally, it may contain sodium oxide 23 and / or magnesium oxide. It should be noted that instead of zirconium oxide 28, it may also contain zirconium oxide, for example, partially stabilized zirconium oxide.

[0148] Furthermore, similar to the first embodiment, the metal layers 30 and 40 are composed primarily of copper. The intermediate layers 50a and 50b respectively contain magnesium oxides 51a and 51b as first oxides. The magnesium oxides 51a and 51b are formed in large quantities in the intermediate layers 50a and 50b on the front and back sides of the ceramic plate 20, respectively. In addition, copper oxides 31 and 41 are formed at the boundaries between the metal layers 30 and 40 and the ceramic plate 20, and at the boundaries between the magnesium oxides 51a and 51b, the metal layers 30 and 40, and the ceramic plate 20.

[0149] In the ceramic laminate substrate 10 (before reliability testing), if there is too much magnesium oxide 51a and 51b, the bonding strength between the ceramic plate 20 and the metal layers 30 and 40 will decrease. Therefore, it is preferable that the intermediate layers 50a and 50b containing magnesium oxide 51a and 51b are formed such that they cover 10% or more and 80% or less of the bonding surface between the ceramic plate 20 and the metal layers 30 and 40, more preferably 20% or more and 50% or less.

[0150] Peel strength evaluation tests were also conducted on such ceramic laminate substrate 10. Based on the evaluation results of Example 2-1, the front side of ceramic laminate substrate 10 was rated "pass" and the back side was rated "pass". That is, compared to the comparative example, ceramic laminate substrate 10 slightly improved the bonding force between metal layers 30, 40 and ceramic plate 20, and suppressed the decrease in bonding strength. The reasons for this are not yet fully explained, nor are they limited to theory, but the following considerations are possible.

[0151] like Figure 17As shown, in Example 2-1, a high potential (positive electrode) and a low potential (negative electrode) voltage are applied to the metal layers 30 and 40 at high temperature in the ceramic multilayer substrate 10. In the absence of an intermediate layer 50b containing magnesium oxide 51b, copper oxide 41 (Cu-O) is reduced at the boundary between the metal layer 40 on the negative electrode side and the zirconium oxide 28 of the ceramic plate 20. However, unlike Comparative Example 2, the ceramic multilayer substrate 10 has an intermediate layer 50b containing magnesium oxide 51b on the negative electrode side. Therefore, on the negative electrode side, in the portion where the intermediate layer 50b is formed, the zirconium oxide 28 and the copper oxide 41 (Cu-O) are not in direct contact, and the reduction of the copper oxide 41 is suppressed. That is, the intermediate layer 50b hinders the reduction of the copper oxide 41. Therefore, in the portion where the intermediate layer 50b is formed, the copper oxide 41 does not become Cu and remains. Furthermore, since reduction in the negative electrode is suppressed, less oxygen ions are generated, and excessive oxidation of copper at the boundary between the metal layer 30 and the ceramic plate 20 is also suppressed on the positive electrode side. Therefore, by forming an intermediate layer 50b containing magnesium oxide 51b on the negative electrode side, the adhesion between the metal layers 30 and 40 and the ceramic plate 20 is slightly improved compared to Comparative Example 2, and the reduction in adhesion is suppressed.

[0152] Furthermore, magnesium oxide 26 can also be present at grain boundaries and triple points. This partially interrupts the movement path of oxygen ions at the grain boundaries. Consequently, redox reactions in both the positive and negative electrodes are suppressed. Additionally, the ceramic laminate substrate 10 can also form an intermediate layer 50a containing magnesium oxide 51a on the positive electrode side. Therefore, on the positive electrode side, in the portion where the intermediate layer 50b is formed, zirconium oxide 28 does not directly contact the copper oxide 31 (Cu-O), and oxidation of the metal layer 30 is suppressed. That is, the intermediate layer 50a hinders the oxidation of the metal layer 30. This further improves the adhesion of the metal layers 30 and 40 to the ceramic plate 20, suppressing any decrease in adhesion.

[0153] Through the above operations, the ceramic laminate substrate 10 of Example 2-1, like that of Example 1-1, suppresses the decrease in bonding strength between the ceramic plate 20 and the metal layer 40, and the bonding strength of the metal layer 40 relative to the ceramic plate 20 is improved. Also similar to Example 1-1, in the ceramic laminate substrate 10, as long as there is an intermediate layer 50b between at least the back side (low potential side) of the ceramic plate 20 and the metal layer 40, the decrease in the bonding strength of the metal layer 40 can be suppressed, preventing the deterioration of the ceramic laminate substrate 10.

[0154] (Ceramic laminate substrate of Example 2-2) In Example 2-2, using Figure 18 and Figure 19 , for Figure 4In step S1a (second embodiment), the ceramic plate 20 of the ceramic laminate substrate 10 is manufactured by coating magnesium oxide powder, and the metal layers 30 and 40 are manufactured by wet oxidation. Figure 18 This is a cross-sectional schematic diagram of the ceramic laminated substrate according to the second embodiment (Example 2-2). Figure 19 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Example 2-2) under high temperature and high voltage. It should be noted that... Figure 18 schematically shown with Figure 2 The microscopic state of the area corresponding to the region enclosed by the dashed line. Additionally, in Figure 19 The diagram illustrates the use of... Figure 2 The microscopic state of metal layers 30 and 40 when a high voltage is applied at high temperature.

[0155] like Figure 18 As shown, the ceramic laminate substrate 10 of Embodiment 2-2 is constructed by sequentially stacking a metal layer 40, an intermediate layer 50b, a ceramic plate 20, an intermediate layer 50a, and a metal layer 30 from bottom to top.

[0156] Similar to Example 2-1, the ceramic plate 20 is... Figure 4 It is manufactured by coating magnesium oxide powder in step S1a (second embodiment). Furthermore, unlike Example 2-1, the metal layers 30 and 40 are... Figure 4 It is manufactured by wet oxidation in step S1b.

[0157] The ceramic plate 20 contains silicon-containing oxide 22 and zirconium oxide 28 as a second oxide between the particles (grain boundaries and triple points) of the alumina 21. Additionally, it may contain sodium oxide 23 and / or magnesium oxide. It should be noted that instead of zirconium oxide 28, it may also contain zirconium oxide, for example, partially stabilized zirconium oxide.

[0158] Furthermore, metal layers 30 and 40 are primarily composed of copper. Similar to Examples 1-2, intermediate layers 50a and 50b respectively contain magnesium and manganese oxides 52a and 52b as first oxides. The magnesium and manganese oxides 52a and 52b are formed in large quantities on the front and back sides of the ceramic plate 20 in intermediate layers 50a and 50b, respectively. In addition, copper oxides 31 and 41 are formed at the boundaries of metal layers 30 and 40, ceramic plate 20, and the magnesium and manganese oxides 52a and 52b, respectively.

[0159] In Example 2-1, the coverage of the intermediate layers 50a and 50b in the ceramic laminate substrate 10 (before reliability testing) is limited, thus failing to improve the bonding strength between the ceramic plate 20 and the metal layers 30 and 40. In Example 2-2, the intermediate layers 50a and 50b, comprising oxides 52a and 52b of magnesium and manganese, can be formed more extensively. Therefore, the bonding strength between the ceramic plate 20 and the metal layers 30 and 40 is improved compared to Example 2-1. Preferably, the intermediate layers 50a and 50b are formed such that they cover 20% to 80% of the bonding surface between the ceramic plate 20 and the metal layers 30 and 40.

[0160] Peel strength evaluation tests were also conducted on the ceramic laminate substrate 10. Based on the evaluation results of Example 2-2, the front side of the ceramic laminate substrate 10 was rated "Excellent," and the back side was also rated "Excellent." That is, compared to the comparative example, the ceramic laminate substrate 10 significantly suppressed the reduction in bonding force between the metal layers 30 and 40 and the ceramic plate 20. Furthermore, compared to Example 2-1, it further suppressed the reduction in bonding force between the metal layers 30 and 40 and the ceramic plate 20. The reasons for this are not yet fully explained, nor are they limited to theory; the following considerations are possible.

[0161] like Figure 19 As shown, in Example 2-2, the ceramic multilayer substrate 10 applies high-potential (positive electrode) and low-potential (negative electrode) voltages to the metal layers 30 and 40 at high temperatures. The ceramic multilayer substrate 10 has an intermediate layer 50b on the negative electrode side, comprising oxides 52b containing magnesium and manganese. Therefore, on the negative electrode side, in the portion where the intermediate layer 50b is formed, the zirconium oxide 28 does not directly contact the copper oxide 41 (Cu-O), and the reduction of the copper oxide 41 is suppressed. That is, the intermediate layer 50b hinders the reduction of the copper oxide 41. Therefore, in the portion where the intermediate layer 50b is formed, the copper oxide 41 does not become copper and remains. Furthermore, since reduction in the negative electrode is suppressed, fewer oxygen ions are generated, and on the positive electrode side, excessive oxidation of copper at the boundary between the metal layer 30 and the ceramic plate 20 is also suppressed. Therefore, by forming an intermediate layer 50b containing oxides 52b of magnesium and manganese on the negative electrode side, the bonding force of the metal layers 30 and 40 to the ceramic plate 20 is significantly improved compared to Comparative Example 2, and the reduction in bonding strength is suppressed. Furthermore, since reduction is more inhibited than in Examples 2-1 and 2-3 described later, it is believed that the reduction in bonding force of the metal layers 30 and 40 to the ceramic plate 20 is suppressed more effectively than in Examples 2-1 and 2-3.

[0162] Furthermore, magnesium oxide 26 can also be present at grain boundaries and triple points. This partially interrupts the movement path of oxygen ions at the grain boundaries. Consequently, redox reactions in both the positive and negative electrodes are suppressed. Additionally, the ceramic laminate substrate 10 can also form an intermediate layer 50a containing oxides 52a of magnesium and manganese on the positive electrode side. Thus, on the positive electrode side, in the portion where the intermediate layer 50a is formed, zirconium oxide 28 does not directly contact the oxide 31 of copper (Cu-O), and oxidation of the metal layer 30 is suppressed. That is, the intermediate layer 50a hinders the oxidation of the metal layer 30. This further improves the adhesion of the metal layers 30 and 40 to the ceramic plate 20, suppressing any decrease in adhesion.

[0163] Through the above operations, compared with the cases of Example 2-1 and Example 2-3 described later, the ceramic laminate substrate 10 of Example 2-2 further suppresses the reduction of the bonding strength between the ceramic plate 20 and the metal layer 40, and the bonding strength of the metal layer 40 relative to the ceramic plate 20 is improved.

[0164] (Ceramic laminate substrates of Examples 2-3) In Examples 2-3, using Figure 20 and Figure 21 , for Figure 4 In step S1a (second embodiment), the ceramic plate 20 of the ceramic laminate substrate 10 is manufactured without coating with magnesium oxide powder, and the metal layers 30 and 40 are manufactured by wet oxidation. Figure 20 This is a cross-sectional schematic diagram of the ceramic laminated substrate according to the second embodiment (Examples 2-3). Figure 21 This is a cross-sectional schematic diagram of the ceramic laminate substrate of the second embodiment (Examples 2-3) under high temperature and high voltage. It should be noted that... Figure 20 schematically shown Figure 2 The microscopic state within the area enclosed by the dashed line. Additionally, in Figure 21 The diagram illustrates the use of... Figure 2 The microscopic state of metal layers 30 and 40 when a high voltage is applied at high temperature.

[0165] like Figure 20 As shown, the ceramic laminate substrate 10 of Examples 2-3 is constructed by sequentially stacking a metal layer 40, an intermediate layer 50b, a ceramic plate 20, an intermediate layer 50a, and a metal layer 30 from bottom to top.

[0166] Unlike Examples 2-1 and 2-2, the ceramic plate 20 is... Figure 4 In step S1a (second embodiment), magnesium oxide powder coating is not performed. Furthermore, similar to Examples 2-2, metal layers 30 and 40 are... Figure 4 It is manufactured by wet oxidation in step S1b.

[0167] The ceramic plate 20 contains silicon-containing oxide 22 and zirconium oxide 28 as a second oxide between the particles (grain boundaries and triple points) of the alumina 21. Additionally, sodium oxide 23 may also be included. It should be noted that, instead of zirconium oxide 28, an oxide containing zirconium may also be used, for example, partially stabilized zirconium oxide.

[0168] Furthermore, metal layers 30 and 40 are primarily composed of copper. Intermediate layers 50a and 50b respectively contain manganese oxides 53a and 53b as first oxides. Manganese oxides 53a and 53b are formed in large quantities on the front and back sides of the ceramic plate 20 within intermediate layers 50a and 50b, respectively. Additionally, copper oxides 31 and 41 are formed at the boundaries of metal layers 30 and 40, the ceramic plate 20, and the manganese oxides 53a and 53b, respectively.

[0169] In the ceramic laminate substrate 10 (before reliability testing), if there is too much manganese oxide 53a and 53b, the bonding strength between the ceramic plate 20 and the metal layers 30 and 40 will decrease. Therefore, it is preferable that the intermediate layers 50a and 50b containing manganese oxide 53a and 53b are formed such that they cover 10% or more and 80% or less of the bonding surface between the ceramic plate 20 and the metal layers 30 and 40, more preferably 20% or more and 50% or less.

[0170] Peel strength evaluation tests were also conducted on the ceramic laminate substrate 10. Based on the evaluation results of Examples 2-2, the front side of the ceramic laminate substrate 10 was rated "Excellent," and the back side was rated "Good." That is, compared to Comparative Example 2, the ceramic laminate substrate 10 suppressed the reduction in the bonding force between the metal layers 30 and 40 and the ceramic plate 20. Furthermore, compared to Example 2-1, it further suppressed the reduction in the bonding force between the metal layers 30 and 40 and the ceramic plate 20. The reasons for this are not yet fully explained and are not limited to theory; the following can be considered.

[0171] like Figure 21As shown, in Examples 2-3, the ceramic multilayer substrate 10 applies high-potential (positive electrode) and low-potential (negative electrode) voltages to the metal layers 30 and 40 at high temperatures. The ceramic multilayer substrate 10 has an intermediate layer 50b containing manganese oxide 53b disposed on the negative electrode side. Therefore, on the negative electrode side, in the portion where the intermediate layer 50b is formed, the zirconium oxide 28 does not directly contact the copper oxide 41 (Cu-O), and the reduction of the copper oxide 41 is suppressed. That is, the intermediate layer 50b hinders the reduction of the copper oxide 41. Therefore, in the portion where the intermediate layer 50b is formed, the copper oxide 41 does not become copper and remains. Furthermore, since reduction in the negative electrode is suppressed, fewer oxygen ions are generated, and excessive oxidation of copper at the boundary between the metal layer 30 and the ceramic plate 20 is also suppressed on the positive electrode side. Therefore, by forming an intermediate layer 50b containing a manganese oxide 53b on the negative electrode side, the bonding force of the metal layers 30 and 40 to the ceramic plate 20 is improved compared to Comparative Example 2, and the reduction in bonding strength is suppressed. Furthermore, since reduction is more inhibited than in Example 2-1, it is believed that the reduction in bonding force of the metal layers 30 and 40 to the ceramic plate 20 is suppressed more than in Example 2-1.

[0172] Furthermore, the ceramic laminate substrate 10 can have an intermediate layer 50a containing a manganese oxide 53a formed on the positive electrode side. Therefore, on the positive electrode side, in the portion where the intermediate layer 50b is formed, the zirconium oxide 28 and the copper oxide 31 (Cu-O) are not in direct contact, and the oxidation of the metal layer 30 is suppressed. That is, the intermediate layer 50a hinders the oxidation of the metal layer 30. This further improves the bonding strength of the metal layers 30 and 40 to the ceramic plate 20 and suppresses any decrease in bonding strength.

[0173] Through the above operations, compared with the case of Example 2-1, the ceramic laminate substrate 10 of Example 2-3 further suppresses the reduction of the bonding strength between the ceramic plate 20 and the metal layer 40, and the bonding strength of the metal layer 40 relative to the ceramic plate 20 is improved.

[0174] [Third Implementation] As described in the first and second embodiments, in the ceramic laminate substrate 10, when one of the metal layers 30 and 40 is at a high potential and the other of the metal layers 30 and 40 is at a low potential, an intermediate layer is formed at least between the low-potential metal layer and the ceramic plate 20. This suppresses the peeling of the metal layer (with the intermediate layer formed) from the ceramic plate 20.

[0175] In the third embodiment, for in Figures 1-3 In the semiconductor device 1 shown, the region where an intermediate layer is required based on the potential difference generated in the metal layers 30 and 40 of the ceramic multilayer substrate 10 when the semiconductor device 1 is running and when it is stopped will be described.

[0176] First, the situation when semiconductor device 1 is stopped will be explained. When semiconductor device 1 is stopped, the control signals input to the control electrodes 61a and 61b of semiconductor chips 60a and 60b are disconnected. Therefore, in the ceramic laminate substrate 10, metal layers 30a and 30b are at a high potential, and metal layer 30d is at a low potential. The upper arm A and lower arm B at this time are referred to as the stopped state. Furthermore, the stopping state of semiconductor device 1 corresponds to the following... Figure 22 (A) Figure 23 (A) Figure 24 (A)

[0177] The operation of semiconductor device 1 will be explained. When semiconductor device 1 is driven, the control signal input to the control electrode 61a of semiconductor chip 60a is turned on, and the control signal input to the control electrode 61b of semiconductor chip 60b is turned off. Therefore, in the ceramic laminate substrate 10, metal layers 30a, 30b, and 30c are at high potential, and metal layer 30d is at low potential. The upper arm A at this time is referred to as the driving state, and the lower arm B as the stopping state. Furthermore, the driving of semiconductor device 1 corresponds to the following... Figure 22 (B) Figure 23 (B) Figure 24 The case of (B).

[0178] Furthermore, during another driving cycle of semiconductor device 1, the control signal input to the control electrode 61a of semiconductor chip 60a is disconnected, and the control signal input to the control electrode 61b of semiconductor chip 60b is connected. Therefore, in the ceramic laminate substrate 10, metal layers 30a and 30b are at a high potential, and metal layers 30c and 30d are at a low potential. The upper arm A at this time is referred to as the stopped state, and the lower arm B as the driving state. Additionally, the driving cycles of semiconductor device 1 correspond to the following... Figure 22 (C) Figure 23 (C) Figure 24 The case of (C).

[0179] Next, use Figures 22-25 The regions requiring intermediate layers for each potential of the metal layers 30 and 40 of the ceramic multilayer substrate 10 are described. Figure 22 This is a diagram illustrating the region requiring an intermediate layer in the ceramic multilayer substrate (with a low potential back metal layer) according to the third embodiment. Figure 23 This is a diagram illustrating the region requiring an intermediate layer in the ceramic multilayer substrate (with a high potential back metal layer) of the third embodiment. Figure 24 This is a diagram illustrating the region requiring an intermediate layer in the ceramic multilayer substrate (with a floating potential back metal layer) of the third embodiment. Figure 25This is a diagram illustrating the region requiring an intermediate layer in the ceramic multilayer substrate of the third embodiment.

[0180] It should be explained that Figures 22-24 A simplified map shows Figure 2 The ceramic laminate substrate 10, semiconductor chips 60a and 60b, and external connection terminals 71 to 75 are included. Only structural components necessary for description are labeled with reference numerals. Figure 22 (A) Figure 23 (A) Figure 24 (A) corresponds to the case where the upper arm A and the lower arm B are in a stopped state. Figure 22 (B) Figure 23 (B) Figure 24 (B) corresponds to the case where the upper arm A is in a driving state and the lower arm B is in a stopped state. Figure 22 (C) Figure 23 (C) Figure 24 (C) corresponds to the case where the upper arm A is in a stopped state and the lower arm B is in a driven state. Figure 22 (D) Figure 23 (D) Figure 24 (D) shows the formation region of the intermediate layer.

[0181] according to Figure 22 The case where the metal layer 40, which serves as the back metal layer in the ceramic laminate substrate 10, has a low potential will be explained. In this case, when the upper arm A and lower arm B are in a stopped state, as... Figure 22 As shown in (A), metal layers 30a and 30b are at a high potential, and metal layer 30d is at a low potential. It should be noted that metal layer 30c is at a floating potential. In the ceramic plate 20, a potential difference exists between the high-potential metal layers 30a and 30b and the low-potential metal layer 40 (regions P1 and P2 shown by dashed lines). Therefore, it is assumed that delamination of metal layer 40 occurs between the ceramic plate 20 in region P1 and the region of metal layer 40 opposite metal layer 30a. Furthermore, it is assumed that delamination of metal layer 40 occurs between the ceramic plate 20 in region P2 and the region of metal layer 40 opposite metal layer 30b.

[0182] Next, with the upper arm A in a driving state and the lower arm B in a stopped state, as follows: Figure 22As shown in (B), metal layers 30a, 30b, and 30c are at high potential, and metal layer 30d is at low potential. In the ceramic plate 20, a potential difference is generated between the high-potential metal layers 30a, 30b, and 30c and the low-potential metal layer 40 (regions P1 to P3 shown by dashed lines). Therefore, it is assumed that delamination of metal layer 40 occurs between the ceramic plate 20 and the metal layer 40 opposite metal layer 30a in region P1. It is assumed that delamination of metal layer 40 occurs between the ceramic plate 20 and the metal layer 40 opposite metal layer 30b in region P2. It is assumed that delamination of metal layer 40 occurs between the ceramic plate 20 and the metal layer 40 opposite metal layer 30c in region P3.

[0183] Next, with the upper arm A in a stopped state and the lower arm B in a driven state, as follows: Figure 22 As shown in (C), metal layers 30a and 30b are at high potential, while metal layers 30c and 30d are at low potential. In the ceramic plate 20, a potential difference exists between the high-potential metal layers 30a and 30b and the low-potential metal layer 40 (regions P1 and P2 shown by dashed lines). Therefore, it is assumed that delamination of metal layer 40 occurs between the ceramic plate 20 in region P1 and the region of metal layer 40 opposite metal layer 30a. Furthermore, it is assumed that delamination of metal layer 40 occurs between the ceramic plate 20 in region P2 and the region of metal layer 40 opposite metal layer 30b.

[0184] In the above Figure 22 (A) ~ Figure 22 In (C), it is necessary to base the potential difference generated when semiconductor device 1 is stopped and when it is driven on, Figure 22 Regions L1 to L3, as shown in (D), form an intermediate layer. Region L1 is the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite to the metal layer 30a. Region L2 is the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite to the metal layer 30b. Region L3 is the boundary between the region of the ceramic plate 20 and the region of the metal layer 40 opposite to the metal layer 30c. Specifically, according to Figure 22 (A) ~ Figure 22 (C) It is believed that the frequency of potential difference generation between the ceramic plate 20 and the metal layer 40 opposite to the metal layers 30a and 30b is high. Therefore, at least an intermediate layer needs to be formed in the L1 and L2 regions.

[0185] according to Figure 23 The case where the metal layer 40, which serves as the back metal layer in the ceramic laminate substrate 10, is at a high potential will be explained. At this time, when the upper arm A and lower arm B are in a stopped state, as... Figure 23As shown in (A), metal layers 30a and 30b are at a high potential, and metal layer 30d is at a low potential. It should be noted that metal layer 30c is at a floating potential. In the ceramic plate 20, a potential difference is generated between the low-potential metal layer 30d and the high-potential metal layer 40 (region P4 shown by the dashed line). Therefore, it is considered that a peeling of metal layer 30d occurs between the ceramic plate 20 and metal layer 30d in region P4.

[0186] Next, with the upper arm A in a driving state and the lower arm B in a stopped state, as follows: Figure 23 As shown in (B), metal layers 30a, 30b, and 30c are at high potential, while metal layer 30d is at low potential. In the ceramic plate 20, a potential difference is generated between the low-potential metal layer 30d and the high-potential metal layer 40 (region P4, indicated by the dashed line). Therefore, it is assumed that delamination of metal layer 30d occurs between the ceramic plate 20 and metal layer 30d in region P4.

[0187] Next, with the upper arm A in a stopped state and the lower arm B in a driven state, as follows: Figure 23 As shown in (C), metal layers 30a and 30b are at high potential, while metal layers 30c and 30d are at low potential. In the ceramic plate 20, a potential difference is generated between the low-potential metal layers 30c and 30d and the high-potential metal layer 40 (regions P3 and P4 shown by dashed lines). Therefore, it is assumed that delamination of metal layer 30c occurs between the ceramic plate 20 and metal layer 30c in region P3. Furthermore, it is assumed that delamination of metal layer 30d occurs between the ceramic plate 20 and metal layer 30d in region P4.

[0188] In the above Figure 23 (A) ~ Figure 23 In (C), it is necessary to base the potential difference generated when semiconductor device 1 is stopped and when it is driven on, Figure 23 Regions L4 and L5, as shown in (D), form an intermediate layer. Region L4 is the boundary between ceramic plate 20 and metal layer 30c. Region L5 is the boundary between ceramic plate 20 and metal layer 30d. Specifically, according to Figure 23 (A) ~ Figure 23 (C) suggests that the frequency of potential difference generation between the ceramic plate 20 and the metal layer 30d is high. Therefore, an intermediate layer needs to be formed at least in the L5 region.

[0189] according to Figure 24 The case where the metal layer 40, which serves as the back metal layer in the ceramic laminate substrate 10, has a floating potential will be explained. That is, when the semiconductor device 1 is not driven, no potential is applied to the metal layer 40. At this time, when the upper arm A and the lower arm B are in a stopped state, as... Figure 24As shown in (A), metal layers 30a and 30b are at a high potential, and metal layer 30d is at a low potential. At this time, metal layer 40, as the back metal layer, has a potential corresponding to the area ratio of the potential on the front side. In this embodiment, the area of ​​the high potential becomes larger than the area of ​​the low potential (see reference). Figure 1 Therefore, metal layer 40 becomes a potential closer to a high potential than a low potential. Consequently, a potential difference is generated in ceramic plate 20 between the low-potential metal layer 30d and metal layer 40 (region P4 shown by the dashed line). Therefore, it is considered that delamination of metal layer 30d occurs between ceramic plate 20 and metal layer 30d in region P4.

[0190] Next, with the upper arm A in a driving state and the lower arm B in a stopped state, as follows: Figure 24 As shown in (B), metal layers 30a, 30b, and 30c are at high potentials, and metal layer 30d is at a low potential. At this time, metal layer 40, as the back metal layer, has a potential corresponding to the area ratio of the potential on the front side. In this embodiment, the area of ​​the high potential becomes very large compared to the area of ​​the low potential (see reference). Figure 1 Therefore, metal layer 40 becomes approximately at the same potential as the high potential. Thus, metal layer 40 becomes approximately at the same potential as metal layers 30a, 30b, and 30c. In ceramic plate 20, a potential difference is generated between the low-potential metal layer 30d and the high-potential metal layer 40 (region P4 shown by the dashed line). Therefore, it is considered that delamination of metal layer 30d occurs between ceramic plate 20 and metal layer 30d in region P4.

[0191] Next, with the upper arm A in a stopped state and the lower arm B in a driven state, as follows: Figure 24 As shown in (C), metal layers 30a and 30b have a high potential, while metal layers 30c and 30d have a low potential. At this time, metal layer 40, as the back metal layer, has a potential corresponding to the area ratio of the potential on the front side. In this embodiment, the areas of the high potential and the low potential are approximately the same (see reference). Figure 1 Therefore, metal layer 40 becomes approximately at the midpoint between high and low potentials. In ceramic plate 20, a potential difference equal to half the difference between high and low potentials occurs between high-potential metal layers 30a and 30b and metal layer 40 (regions P1 and P2 shown by dashed lines). Furthermore, a potential difference equal to half the difference between high and low potentials occurs between low-potential metal layers 30c and 30d and metal layer 40 (regions P3 and P4 shown by dashed lines). Therefore, it is assumed that delamination occurs between ceramic plate 20 and metal layer 40 in regions P1 and P2. Additionally, it is assumed that delamination occurs between ceramic plate 20 and metal layers 30c and 30d in regions P3 and P4.

[0192] In the above Figure 24(A) ~ Figure 24 In (C), it is necessary to base the potential difference generated when semiconductor device 1 is stopped and when it is driven on, Figure 24 Regions L1, L2, and L5, as shown in (D), form an intermediate layer. Region L1 is the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite to the metal layer 30a. Region L2 is the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite to the metal layer 30b. Region L5 is the boundary between the ceramic plate 20 and the metal layer 30d. Specifically, according to... Figure 24 (A) ~ Figure 24 (C) suggests that the frequency of potential difference generation between the ceramic plate 20 and the metal layer 30d is high. Therefore, an intermediate layer needs to be formed at least in the L5 region.

[0193] According to the above Figure 22 (D) Figure 23 (D) Figure 24 (D), such as Figure 25 As shown, the ceramic laminate substrate 10 needs to form intermediate layers in regions L1 to L5, indicated by dashed lines. Region L1 is the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite the metal layer 30a. Region L2 is the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite the metal layer 30b. Region L3 is the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite the metal layer 30c. Region L4 is the boundary between the ceramic plate 20 and the metal layer 30c. Region L5 is the boundary between the ceramic plate 20 and the metal layer 30d. Furthermore, considering... Figures 22-24 The frequency at which the potential difference is generated requires the formation of an intermediate layer in at least the L1, L2, and L5 regions.

[0194] On the other hand, the boundary between the ceramic plate 20 and the metal layers 30a and 30b may also be without an intermediate layer. Additionally, the boundary between the ceramic plate 20 and the region of the metal layer 40 opposite the metal layer 30d may also be without an intermediate layer.

[0195] The above only illustrates the principles of the invention. Furthermore, those skilled in the art can make various modifications and alterations. The invention is not limited to the correct structures and applications shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the invention based on the appended claims and their equivalents. For example, the ceramic plate 20 may be constructed primarily of ceramics with good insulation and thermal conductivity. Such ceramics are not limited to alumina and / or zirconium oxide. For example, aluminum nitride (AlN) and / or silicon nitride (Si3N4) may also be used as the main components. Furthermore, zirconium oxide may be added to such aluminum nitride and / or silicon nitride. Additionally, the ceramic plate 20 may also contain grain boundary materials formed at the grain boundaries of ceramic particles and triple points. Such grain boundary materials may, for example, contain oxides (second oxides) containing aluminum and / or silicon.

Claims

1. A semiconductor device, characterized in that, have: Semiconductor chips; Joining components; and A laminated substrate, which is plate-shaped, has a front side and a back side opposite to the front side, and the semiconductor chip is bonded to the front side via the bonding member. The laminated substrate has: A ceramic plate, which is plate-shaped, has a first main surface and a second main surface opposite to the first main surface, and has multiple ceramic particles; A high-potential metal layer, which is bonded to the first main surface and contains copper; A low-potential metal layer, bonded to the second main surface and comprising copper, having a potential lower than that of the first main surface; and An intermediate layer, formed between the second main surface and the low-potential metal layer, comprises a first oxide having at least one of magnesium and manganese. The first oxide is formed on a portion of the interface between the second main surface and the low-potential metal layer.

2. The semiconductor device according to claim 1, characterized in that, The first oxide is in contact with both the second main surface and the low-potential metal layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, The first main surface is the front side of the laminated substrate. The second main surface is the back side of the laminated substrate. The semiconductor chip is electrically connected to the high-potential metal layer.

4. The semiconductor device according to claim 1 or 2, characterized in that, The first main surface is the back side of the laminated substrate. The second main surface is the front side of the laminated substrate. The semiconductor chip is electrically connected to the low-potential metal layer.

5. The semiconductor device according to claim 1, characterized in that, The ceramic plate and the intermediate layer comprise at least one of magnesium, which is 0.1 wt% to 1.5 wt% in oxide form, and manganese, which is 0.01 wt% to 0.15 wt% in oxide form.

6. The semiconductor device according to claim 1, characterized in that, The intermediate layer covers more than 10% and less than 80% of the second main surface.

7. The semiconductor device according to claim 1, characterized in that, The plurality of ceramic particles and the first oxide are respectively disposed on the bonding surface between the ceramic plate and the low-potential metal layer. On the bonding surface, the first oxide is also disposed between the plurality of ceramic particles on the second main surface side.

8. The semiconductor device according to claim 7, characterized in that, The first oxide is formed in large quantities on the second main surface side of the intermediate layer.

9. The semiconductor device according to claim 1, characterized in that, The first oxide also includes an oxide containing aluminum.

10. The semiconductor device according to claim 1, characterized in that, The first oxide comprises any one of MgO, MnO, (Mg,Mn)O, and (Mg,Mn)Mn2O4.

11. The semiconductor device according to claim 9, characterized in that, The first oxide comprises a spinel crystal system containing aluminum.

12. The semiconductor device according to claim 1, characterized in that, The ceramic plate further comprises a second oxide containing silicon at at least one of the grain boundaries and triple points of the plurality of ceramic particles.

13. The semiconductor device according to claim 12, characterized in that, The silicon content in the ceramic plate, calculated in oxide form, is 0.01 wt% or more and 3.0 wt% or less.

14. The semiconductor device according to claim 12, characterized in that, The silicon content in the ceramic plate, calculated in oxide form, is more than 1.0 wt% and less than 3.0 wt%.

15. The semiconductor device according to any one of claims 12 to 14, characterized in that, The laminated substrate includes at least one of the following: It contains an oxide having the magnesium, and contains 10 wt% to 50 wt% magnesium as converted from magnesium oxide (MgO) relative to the content of the silicon as converted from silicon oxide (SiO2); as well as It contains an oxide having the manganese, and contains 1.0 wt% to 5.0 wt% of manganese oxide (MnO) relative to the content of silicon obtained by conversion of silicon oxide (SiO2).

16. The semiconductor device according to claim 1, characterized in that, The ceramic plate further comprises a second oxide containing sodium oxide at at least any one of the grain boundaries and triple points of the plurality of ceramic particles. The sodium oxide content in the ceramic plate, calculated in oxide form, is 0.001 wt% or more and 0.2 wt% or less.

17. The semiconductor device according to claim 1, characterized in that, The plurality of ceramic particles contain alumina.

18. The semiconductor device according to claim 17, characterized in that, The alumina content relative to the ceramic plate is more than 90 wt% and less than 99 wt%.

19. The semiconductor device according to claim 17 or 18, characterized in that, The ceramic plate further comprises zirconium oxide at at least one of the grain boundaries and triple points of the plurality of ceramic particles.

20. The semiconductor device according to claim 17 or 18, characterized in that, The ceramic plate further comprises, at least one of the grain boundaries and triple points of the plurality of ceramic particles, an oxide containing zirconium and yttrium.

21. The semiconductor device according to claim 19, characterized in that, The content of zirconium oxide relative to the ceramic plate, expressed as oxides, is 5.0 wt% or more and 20.0 wt% or less.

22. The semiconductor device according to claim 20, characterized in that, For oxides containing zirconium and oxides containing yttrium, the partially stabilized zirconium oxide, as converted to zirconium oxide (ZrO2), contains 2.5 mol% to 3.5 mol% of yttrium converted to yttrium oxide (Y2O3).

23. The semiconductor device according to claim 19, characterized in that, The laminated substrate comprises an oxide containing magnesium and, relative to zirconium obtained by conversion of zirconium oxide (ZrO2), comprises 2.0 wt% and 20.0 wt% of magnesium obtained by conversion of magnesium oxide (MgO).

24. The semiconductor device according to claim 19, characterized in that, The laminated substrate contains an oxide of manganese and contains 0.05 wt% to 2.0 wt% of manganese oxide (MnO) relative to zirconium oxide (ZrO2).

25. The semiconductor device according to claim 3, characterized in that, The semiconductor chip includes a first semiconductor chip and a second semiconductor chip. The high-potential metal layer includes: A positive electrode metal layer, to which a positive electrode terminal is connected; A chip metal layer, to which the first semiconductor chip is bonded; An output metal layer, on which the second semiconductor chip is bonded, and connected to an output terminal; and The negative electrode metal layer is connected to the negative electrode terminal. The intermediate layer is included in the region of the second main surface opposite to the positive electrode metal layer.

26. The semiconductor device according to claim 25, characterized in that, The intermediate layer is also included in the region on the second main surface opposite to the chip metal layer.

27. The semiconductor device according to claim 4, characterized in that, The semiconductor chip includes a first semiconductor chip and a second semiconductor chip. The low-potential metal layer includes: A positive electrode metal layer, to which a positive electrode terminal is connected; A chip metal layer, to which the first semiconductor chip is bonded; An output metal layer, on which the second semiconductor chip is bonded, and connected to an output terminal; and The negative electrode metal layer is connected to the negative electrode terminal. The intermediate layer is included in the region of the second main surface opposite to the negative electrode metal layer.

28. The semiconductor device according to claim 27, characterized in that, The intermediate layer is also included in the region of the second main surface opposite the output metal layer.

29. The semiconductor device according to claim 1 or 2, characterized in that, The first main surface is the front side of the laminated substrate. The second main surface is the back side of the laminated substrate, and the low-potential metal layer has a floating potential. The semiconductor chip is electrically connected to the high-potential metal layer.

30. The semiconductor device according to claim 29, characterized in that, The semiconductor chip includes a first semiconductor chip and a second semiconductor chip. The high-potential metal layer includes: A positive electrode metal layer, to which a positive electrode terminal is connected; A chip metal layer, to which the first semiconductor chip is bonded; An output metal layer, on which the second semiconductor chip is bonded, and connected to an output terminal; and The negative electrode metal layer is connected to the negative electrode terminal. The intermediate layer is included in the region on the first main surface opposite to the negative electrode metal layer.

31. The semiconductor device according to claim 30, characterized in that, The intermediate layer is also included in the region on the second main surface opposite to the positive electrode metal layer and the chip metal layer.

32. A semiconductor device, characterized in that, have: First semiconductor chip and second semiconductor chip; Joining components; and A laminated substrate, which is plate-shaped, has a front side and a back side opposite to the front side, and the first semiconductor chip and the second semiconductor chip are bonded to the front side via the bonding member. The laminated substrate has: A ceramic plate, which is plate-shaped, has a first main surface and a second main surface opposite to the first main surface, and has multiple ceramic particles; A first metal layer, which is bonded to the first main surface and contains copper; A second metal layer, which is bonded to the second main surface and comprises copper; and The intermediate layer comprises a first oxide having at least one of magnesium and manganese. The first metal layer includes: A positive electrode metal layer, to which a positive electrode terminal is connected; A chip metal layer, to which the first semiconductor chip is bonded; An output metal layer, on which the second semiconductor chip is bonded, and connected to an output terminal; and The negative electrode metal layer is connected to the negative electrode terminal. The intermediate layer includes a portion of the region on the second main surface that is opposite to the positive electrode metal layer and the chip metal layer, respectively, and a region on the first main surface that is opposite to the negative electrode metal layer.

33. The semiconductor device according to claim 32, characterized in that, The intermediate layer also includes a region on the second main surface opposite to the output metal layer, and a region on the first main surface opposite to the output metal layer.

34. A semiconductor device, characterized in that, have: Semiconductor chips; Joining components; A laminated substrate, which is plate-shaped, has a front side and a back side opposite to the front side, and the semiconductor chip is disposed on the front side via the bonding member. The laminated substrate has: A ceramic plate comprising a first oxide and a second oxide, and comprising 10 wt% to 50 wt% of the first oxide relative to the content of the second oxide, the first oxide comprising ceramic particles and magnesium, and the second oxide comprising silicon; and A metal layer, which is bonded to the main surface of the ceramic plate. The first oxide is formed on a portion of the interface between the main surface and the metal layer.

35. The semiconductor device according to claim 34, characterized in that, The ceramic plate also contains sodium oxide in a content of more than 0.001 wt% and less than 0.2 wt% (calculated as sodium oxide).

36. The semiconductor device according to claim 35, characterized in that, The main surface includes a first main surface and a second main surface opposite to the first main surface, wherein the concentration of sodium oxide on the second main surface is higher than the concentration of sodium oxide on the first main surface.

37. A semiconductor device, characterized in that, have: Semiconductor chips; Joining components; and A laminated substrate, which is plate-shaped, has a front side and a back side opposite to the front side, and the semiconductor chip is disposed on the front side via the bonding member. The laminated substrate has: Ceramic slabs, which contain ceramic particles; A metal layer, which is bonded to the main surface of the ceramic plate; and An intermediate layer, formed on a portion of the interface between the main surface and the metal layer, comprises a first oxide containing manganese.

38. The semiconductor device according to claim 37, characterized in that, The ceramic plate further comprises a second oxide containing silicon at at least any one of the grain boundaries and triple points of the plurality of ceramic particles. The manganese content, calculated from manganese oxide, is more than 1.0 wt% and less than 5.0 wt% relative to the silicon content, calculated from silicon oxide.

39. The semiconductor device according to claim 37, characterized in that, The ceramic plate further comprises a second oxide containing silicon at at least any one of the grain boundaries and triple points of the plurality of ceramic particles. The manganese content, calculated from manganese oxide, is between 0.05 wt% and 2 wt% relative to the zirconium content, calculated from zirconium oxide.

40. The semiconductor device according to claim 37, characterized in that, The first oxide also contains magnesium. The ceramic plate and the intermediate layer comprise at least one of magnesium, which is 0.1 wt% to 1.5 wt% in oxide form, and manganese, which is 0.01 wt% to 0.15 wt% in oxide form.

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