Differential amplifier circuit

Abstract

The differential amplifier circuit includes a basic differential amplifier circuit, which comprises: an operational amplifier that amplifies the potential difference between the output terminals of a first input resistor and a second input resistor; a feedback resistor connected to the output terminal of the first input resistor; and a first resistive element connected to the output terminal of the second input resistor. The differential amplifier circuit also includes a high-precision operational amplifier with a smaller offset or drift voltage compared to the standard operational amplifier. The high-precision operational amplifier has its inverting input terminal connected to the output terminal of the first input resistor and its output terminal connected to the output terminal of the second input resistor. Furthermore, a reference signal is input to the non-inverting input terminal of the high-precision operational amplifier, corresponding to the potential generated at the non-inverting input terminal of the operational amplifier in the case of the basic differential amplifier circuit alone.

Description

Technical Field

[0001] This invention relates to a differential amplifier circuit. Background Technology

[0002] JP2020-25254A discloses a differential amplifier circuit comprising: an operational amplifier that amplifies the potential difference between the output terminals of a pair of input resistors; a feedback resistor configured in a path for feedback from the output terminal of the operational amplifier to one of the input terminals; and a resistive element connected to the other input terminal of the operational amplifier. Summary of the Invention

[0003] In a typical differential amplifier circuit as described above, the output signal of the differential amplifier circuit will produce errors due to the offset voltage or drift voltage of the operational amplifier. Even if the offset voltage or drift voltage is replaced with a high-precision operational amplifier with a smaller offset voltage or drift voltage compared to the operational amplifier, the performance of the differential amplifier circuit, such as the gain-bandwidth product and slew rate, will still be limited due to the replacement with a high-precision operational amplifier.

[0004] This invention was made with the aim of addressing such problems, and its purpose is to maintain the performance of the operational amplifier and reduce the offset voltage or drift voltage in a differential amplifier circuit.

[0005] According to one aspect of the present invention, the differential amplifier circuit includes a basic differential amplifier circuit having: a first input resistor and a second input resistor, each receiving two potential signals; an operational amplifier amplifying the potential difference between the output terminals of the first input resistor and the second input resistor; a feedback resistor connected to the output terminal of the first input resistor; and a first resistive element connected to the output terminal of the second input resistor. The differential amplifier circuit further includes a high-precision operational amplifier, which has its inverting input terminal connected to the output terminal of the first input resistor and its output terminal connected to the output terminal of the second input resistor. The high-precision operational amplifier has a smaller offset voltage or drift voltage compared to the first operational amplifier. Furthermore, a reference signal is input to the non-inverting input terminal of the high-precision operational amplifier, corresponding to the potential generated at the non-inverting input terminal of the operational amplifier in the state of the basic differential amplifier circuit alone.

[0006] According to this scheme, by inputting a potential equivalent to that generated at the non-inverting input terminal of the high-precision operational amplifier in the state of a basic differential amplifier circuit, a difference equivalent to the offset voltage or drift voltage of the operational amplifier is obtained at the output terminal of the high-precision operational amplifier. Based on this difference, negative feedback is applied from the inverting input terminal of the operational amplifier to the non-inverting input terminal of the operational amplifier via the high-precision operational amplifier, thus reducing the potential difference between the input terminals of the operational amplifier. Therefore, the performance of the operational amplifier can be maintained and the offset voltage or drift voltage can be reduced. Attached Figure Description

[0007] Figure 1 This is a circuit diagram showing the configuration of the differential amplifier circuit according to the first embodiment of the present invention.

[0008] Figure 2 This is a circuit diagram showing the detailed configuration of the reference signal generation unit that constitutes the differential amplifier circuit of the first embodiment.

[0009] Figure 3 This is a circuit diagram showing the configuration of the differential amplifier circuit in the second embodiment.

[0010] Figure 4 This is a circuit diagram showing the detailed configuration of the high-frequency energizing section and the reference signal generating section constituting the differential amplifier circuit of the second embodiment.

[0011] Figure 5A This diagram is used to explain the operation of the differential amplifier circuit in the low-frequency region of the second embodiment.

[0012] Figure 5B This is a diagram used to explain the operation of the differential amplifier circuit in the high-frequency region of the second embodiment.

[0013] Figure 6 This is a diagram showing the setting conditions in the simulation analysis of the differential amplifier circuit of the second embodiment.

[0014] Figure 7 This is a diagram showing an example of the frequency characteristics related to the offset voltage of the differential amplifier circuit in the second embodiment.

[0015] Figure 8A This is a diagram showing an example of the frequency characteristics related to the output noise of the differential amplifier circuit in the second embodiment.

[0016] Figure 8B This is a graph showing an example of the frequency characteristics related to the output noise of a basic differential amplifier circuit, used as a comparison object.

[0017] Figure 9This is a diagram showing an example of the frequency characteristics related to the common-mode rejection ratio of the differential amplifier circuit in the second embodiment. Detailed Implementation

[0018] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0019] (First Implementation)

[0020] Figure 1 This is a circuit diagram showing the configuration of the differential amplifier circuit in the first embodiment.

[0021] The differential amplifier circuit 100 of this embodiment is an operational amplifier circuit that amplifies the difference between two potential signals. The differential amplifier circuit 100 includes a pair of input terminals 11 and 12, a basic differential amplifier circuit 20, an offset voltage suppression circuit 30, a reference signal generation unit 40, and an output terminal 50.

[0022] A pair of input terminals 11 and 12 receive a first potential signal V1 and a second potential signal V2 from the outside, respectively. Specifically, the first potential signal V1 is supplied to the first input terminal 11, and the second potential signal V2 is supplied to the second input terminal 12.

[0023] The basic differential amplifier circuit 20 includes a pair of input resistors 21, an operational amplifier 22, a feedback resistor 23, and a first resistive element 24.

[0024] A pair of input resistors 21 are two resistive elements that receive two potential signals V1 and V2 respectively. The pair of input resistors 21 consists of a first input resistor 211 and a second input resistor 212. Hereinafter, the first input resistor 211 and the second input resistor 212 will simply be referred to as input resistor 211 and input resistor 212.

[0025] In this embodiment, input resistors 211 and 212 have the same resistance value R1. As an example, the resistance value R1 is set to 2 kΩ. The input terminal of input resistor 211 is connected to the first input terminal 11, and the input terminal of input resistor 212 is connected to the second input terminal 12.

[0026] Operational amplifier 22 is an amplifier that amplifies the potential difference between its output terminal, which is the other end of the first input resistor 211, and its output terminal, which is the other end of the second input resistor 212. Operational amplifier 22 has: an inverting input terminal (-) for the potential generated at the output terminal of the input resistor 211; a non-inverting input terminal (+) for the potential generated at the output terminal of the input resistor 212; and an output terminal for outputting a differential signal based on the potential difference between the inverting input terminal (-) and the non-inverting input terminal (+).

[0027] The operational amplifier 22 in this embodiment is a general operational amplifier corresponding to DC or AC signals. Alternatively, the operational amplifier 22 may also be a high-speed operational amplifier, for example, with a gain-bandwidth product of several MHz or higher. The gain-bandwidth product of the operational amplifier 22 is an indicator of the upper limit of the frequency band where gain variation is small.

[0028] Feedback resistor 23 is a resistor element configured in the current path that feeds back from the output terminal of operational amplifier 22 to the inverting input terminal (-) and connected to the output terminal of input resistor 211. Feedback resistor 23 is connected between the output terminal and the inverting input terminal (-) of operational amplifier 22, and the amplification of the basic differential amplifier circuit 20 is changed by adjusting the resistance value R2 of feedback resistor 23.

[0029] The resistance value R2 of the feedback resistor 23 can be the same as the resistance value R1 of the input resistors 211 and 212, or it can be a different value. In this embodiment, the resistance value R2 of the feedback resistor 23 is set to be the same as the resistance value R1 of the input resistors 211 and 212, for example, 2 [kΩ].

[0030] The first resistor element 24 is a resistor element connected to the output terminal of the input resistor 212. The first resistor element 24 is connected to the reference potential terminal 9, which is set as the reference potential for the basic differential amplifier circuit 20. The amplification rate of the basic differential amplifier circuit 20 is changed by adjusting the resistance value of the first resistor element 24.

[0031] The resistance value of the first resistive element 24 is set to the same value as the resistance value of the feedback resistor 23. In this embodiment, the resistance value of the first resistive element 24 is set to the same resistance value R2 as the resistance value of the feedback resistor 23, and the reference potential terminal 9 is set to the ground potential, i.e., 0 [V].

[0032] With this configuration, in the basic differential amplifier circuit 20, the operational amplifier 22 amplifies the potential difference obtained by subtracting the second potential signal V2 from the first potential signal V1 by a factor representing the value obtained by dividing the resistance value R2 by the resistance value R1, and outputs the amplified differential signal to the output terminal 50.

[0033] Regarding the connection configuration of the basic differential amplifier circuit 20, the contact between the output terminal of the input resistor 211 and one end of the feedback resistor 23 is connected to the inverting input terminal (-) of the operational amplifier 22, and the contact between the output terminal of the operational amplifier 22 and the other end of the feedback resistor 23 is connected to the output terminal 50 of the differential amplifier circuit 100. Furthermore, the contact between the output terminal of the input resistor 212 and one end of the first resistor element 24 is connected to the non-inverting input terminal (+) of the operational amplifier 22, and the other end of the first resistor element 24 is connected to the reference potential terminal 9.

[0034] Next, the configuration of the offset voltage suppression circuit 30 connected to the basic differential amplifier circuit 20 will be explained.

[0035] The offset voltage suppression circuit 30 is an adjustment circuit used to reduce the offset voltage or drift voltage of the operational amplifier 22 that constitutes the basic differential amplifier circuit 20. The offset voltage suppression circuit 30 of this embodiment includes a high-precision operational amplifier 31 and a second resistive element 32.

[0036] The high-precision operational amplifier 31 is an amplifier with a smaller offset voltage compared to the basic differential amplifier circuit 20. In this embodiment, the amplifiers with smaller offset voltage include amplifiers with smaller offset voltage compared to operational amplifier 22 and amplifiers with smaller drift voltage compared to operational amplifier 22.

[0037] As a high-precision operational amplifier 31, examples include low-offset amplifiers, zero-drift amplifiers, or low-drift amplifiers. Zero-drift amplifiers, for example, have a general circuit configuration employing automatic zeroing, chopping, or a combination thereof.

[0038] It should be noted that the gain-bandwidth product of the high-precision operational amplifier 31, which has the configuration described above, is more likely to be narrower than that of the operational amplifier 22. In other words, the operating frequency range of the high-precision operational amplifier 31 is more likely to be narrower than that of the operational amplifier 22.

[0039] The high-precision operational amplifier 31 is configured to apply negative feedback from the output terminal of the input resistor 212 to the output terminal of the input resistor 211 via the two input terminals of the operational amplifier 22. That is, the high-precision operational amplifier 31 is configured to amplify the voltage at the output terminal of the input resistor 211 and apply a voltage to the output terminal of the input resistor 212.

[0040] Therefore, the high-precision operational amplifier 31 feeds back the potential generated at the inverting input terminal (-) of the operational amplifier 22, and applies an adjustment signal to the output terminal of the second resistive element 32 to reduce the difference between the feedback potential and the reference signal Vb.

[0041] In this embodiment, the high-precision operational amplifier 31 has: a non-inverting input terminal (+) for receiving a reference signal Vb; an inverting input terminal (-) for receiving a potential generated at the junction of the input resistor 211 and the feedback resistor 23; and an output terminal for outputting the aforementioned adjustment signal.

[0042] A reference signal Vb is input to the non-inverting input terminal (+) of the high-precision operational amplifier 31, which is equivalent to the potential generated at the non-inverting input terminal (+) of the operational amplifier 22 in the state of the basic differential amplifier circuit 20 only. The state of the basic differential amplifier circuit 20 only refers to the state obtained by removing the offset voltage suppression circuit 30 from the differential amplifier circuit 100 (circuit configuration).

[0043] Thus, a reference signal Vb is generated based on the potential generated at the non-inverting input terminal (+) of the operational amplifier 22 in the state of only the basic differential amplifier circuit 20, and is input to the non-inverting input terminal (+) of the high-precision operational amplifier 31.

[0044] Here, the magnitude of the reference signal Vb required to reduce the input offset voltage of operational amplifier 22 using high-precision operational amplifier 31 is explained in detail. It should be noted that the input offset voltage refers to the potential difference between the non-inverting input terminal (+) and the inverting input terminal (-) when the output voltage of operational amplifier 22 is 0 [V].

[0045] First, in the state obtained by omitting the offset voltage suppression circuit 30 from the differential amplifier circuit 100, the output potential V generated at the output terminal of the operational amplifier 22 is... out It can be represented by the following formula (1).

[0046] [Formula 1]

[0047]

[0048] It should be noted that R1 is the resistance value of the input resistor 21, and R2 is the resistance value of the feedback resistor 23 and the first resistive element 24. V1 is the potential generated at the first input terminal 11, and V2 is the potential generated at the second input terminal 12. off It is the input offset voltage of operational amplifier 22.

[0049] At this time, the potential V generated at the inverting input terminal (-) of operational amplifier 22 - It can be represented by the following formula (2).

[0050] [Formula 2]

[0051]

[0052] As shown in equation (2) above, the potential V generated at the inverting input terminal (-) of operational amplifier 22 - In addition to the input offset voltage V off In addition, there is also the first term potential V generated at the non-inverting input terminal (+) of operational amplifier 22. + Similarly, in the potential fed back from the inverting input terminal (-) of operational amplifier 22 to the inverting input terminal (-) of high-precision operational amplifier 31, there is also the input offset voltage V. off The potential V generated at the non-inverting input terminal (+) of operational amplifier 22 is superimposed on it. + .

[0053] Therefore, in order to use a high-precision operational amplifier 31 to reduce the input offset voltage V off Preferably, the potential V generated at the non-inverting input terminal (+) of the operational amplifier 22 is eliminated from the potential fed back to the high-precision operational amplifier 31. + .

[0054] Therefore, in this embodiment, in order to eliminate the potential V generated at the non-inverting input terminal (+) of the operational amplifier 22 from the feedback potential... + A reference signal Vb representing the potential value obtained by the following formula (3) is input to the non-inverting input terminal (+) of the high-precision operational amplifier 31.

[0055] [Formula 3]

[0056]

[0057] By setting the reference signal Vb in this way, an input offset voltage V0 of operational amplifier 22 can be supplied from the output terminal of high-precision operational amplifier 31 to the non-inverting input terminal (+) of operational amplifier 22. off A comparable potential.

[0058] It should be noted that as long as a high-precision operational amplifier 31 is used to make the input offset voltage V of operational amplifier 22... off The voltage can be reduced, therefore the input offset voltage V of operational amplifier 22 can also be reduced. off Within a smaller range, the potential value of the reference signal Vb deviates from the potential value obtained by the above formula (3). For example, in the input offset voltage V of operational amplifier 22 off If the potential value is sufficiently greater than the potential value obtained from the above formula (3), the potential value of the reference signal Vb can also be made to approach 0 [V] from the potential value obtained from the above formula (3).

[0059] The second resistor 32 is connected between the output terminal of the high-precision operational amplifier 31 and the output terminal of the input resistor 212. Thus, the second resistor 32 is positioned between the output terminal of the high-precision operational amplifier 31 and the output terminal of the second input resistor 212. The second resistor 32 is used, for example, to adjust the sensitivity of the negative feedback control of the high-precision operational amplifier 31. Furthermore, the second resistor 32 can be used to suppress oscillations in the high-precision operational amplifier 31.

[0060] The resistance value R3 of the second resistor element 32 is set such that the potential applied to the non-inverting input terminal (+) of the operational amplifier 22 according to the output signal of the high-precision operational amplifier 31 will not be excessively larger than the potential generated at the junction of the input resistor 212 and the first resistor element 24 according to the second potential signal V2.

[0061] The resistance value R3 of the second resistive element 32 can be the same as the resistance value R1 of the input resistors 211 and 212, and the resistance value R2 of the feedback resistor 23 and the first resistive element 24, or it can be a different value. In this embodiment, the resistance value R3 of the second resistive element 32 is set to the same value as the resistance values ​​R1 and R2, for example, 2 [kΩ].

[0062] It should be noted that in this embodiment, the pair of input resistors 21, feedback resistors 23, first resistor element 24 and second resistor element 32 are each implemented by a single resistor, but they can also be implemented by multiple resistors.

[0063] Next, the connection configuration of the electronic components of the offset voltage suppression circuit 30 will be explained.

[0064] The inverting input terminal (-) of the high-precision operational amplifier 31 is connected to the contact between the input resistor 211 and the feedback resistor 23, and also to the inverting input terminal (-) of the operational amplifier 22. The output terminal of the high-precision operational amplifier 31 is connected to one end of the second resistor element 32. The other end of the second resistor element 32 is connected to the contact between the input resistor 212 and the first resistor element 24, and also to the non-inverting input terminal (+) of the operational amplifier 22. Furthermore, the non-inverting input terminal (+) of the high-precision operational amplifier 31 is connected to the reference signal generation unit 40.

[0065] The reference signal generation unit 40 generates a reference signal Vb and supplies it to the non-inverting input terminal (+) of the high-precision operational amplifier 31. The reference signal generation unit 40 can be implemented by an external power supply, or it can be implemented by a circuit that generates the reference signal Vb based on the second potential signal V2 input based on the input resistor 212.

[0066] Next, the output potential V generated at the output terminal 50 of the differential amplifier circuit 100 is... outPlease provide an explanation.

[0067] First, in the differential amplifier circuit 100, the following equations (4) and (5) are derived based on Kirchhoff's laws. Furthermore, the adjustment signal V generated at the output terminal of the high-precision operational amplifier 31... LA The potential V generated at the inverting input terminal (-) of operational amplifier 22 can be expressed as shown in the following formula (6). - It can be shown in the following formula (7).

[0068] [Formula 4]

[0069]

[0070]

[0071]

[0072] V - =V + +V off …(7)

[0073] It should be noted that in the above formula (6), A is the open-loop gain of the high-precision operational amplifier 31, and V... L+ The potential value V generated at the non-inverting input terminal (+) of the high-precision operational amplifier 31. L+ This is the potential value generated at the inverting input terminal (-) of the high-precision operational amplifier 31. Here, V L- Vb serves as the reference signal representing the potential value derived from the above formula (3).

[0074] Next, if we consider the potential V generated at the inverting input terminal (-) of operational amplifier 22... - Solving the above equation (4) leads to the following equation (8): if the potential V generated at the non-inverting input terminal (+) of operational amplifier 22... + Solving the above formula (5) leads to the following formula (9).

[0075] [Formula 5]

[0076]

[0077]

[0078] Then, substitute the above equation (7) into the left side of equation (9) and the adjustment signal V on the right side of equation (9). LA Substituting into the above formula (6), we can derive the following formula (10).

[0079] [Formula 6]

[0080]

[0081] Next, if we consider the potential V generated at the inverting input terminal (-) of operational amplifier 22... - Solving equation (10) leads to the following equation (11).

[0082] [Formula 7]

[0083]

[0084] Here, if we consider the output potential V of the differential amplifier circuit 100 out To solve the equation (11) by substituting the above equation (8) into the left side, we can derive the following equation (12).

[0085] [Formula 8]

[0086]

[0087] X, Y and Z in equation (12) are shown in equation (13) below.

[0088] [Formula 9]

[0089]

[0090] Here, if the open-loop gain A of the high-precision operational amplifier 31 is sufficiently large, then the condition of the following formula (14) holds. Therefore, at the output potential V of the differential amplifier circuit 100... out In this case, as shown in equation (15) below, the input offset voltage becomes negligible. Therefore, a differential amplifier circuit 100 with no input offset voltage can be realized.

[0091] [Formula 10]

[0092] A>>X, A>>Y, 0≈Z…(14)

[0093] [Formula 11]

[0094]

[0095] Thus, in order to make the conditions of the above formula (14) true, the resistance values ​​R1 of a pair of input resistors 21, R2 of feedback resistor 23 and first resistor element 24 and R3 of second resistor element 32 are adjusted, thereby suppressing the offset voltage of operational amplifier 22.

[0096] Next, refer to Figure 2 An example of the configuration of the reference signal generation unit 40 will be described.

[0097] Figure 2This is a circuit diagram showing the detailed configuration of the reference signal generation unit 40 in this embodiment. The reference signal generation unit 40 in this embodiment is a voltage divider circuit 40A comprising a fourth resistor element 41 and a fifth resistor element 42 connected in series.

[0098] In the voltage divider circuit 40A, input terminal 401 is connected to the input terminal of input resistor 212, and input terminal 402 is connected to reference potential terminal 9. Furthermore, output terminal 403 is connected to the non-inverting input terminal (+) of high-precision operational amplifier 31.

[0099] In this embodiment, the fourth resistor 41 is a first resistor with a resistance value R1 equal to that of the input resistor 212, and the fifth resistor 42 is a second resistor with a resistance value R2 equal to that of the first resistor 24. That is, the resistance values ​​of the fourth resistor 41 and the fifth resistor 42 are set such that the voltage division ratio of the fifth resistor 42 to the fourth resistor 41 is equal to the voltage division ratio (R2 / R1) of the first resistor 24 to the input resistor 212. Thus, the reference signal Vb shown in the above formula (3) is supplied to the non-inverting input terminal (+) of the high-precision operational amplifier 31.

[0100] It should be noted that the potential of the non-inverting input terminal (+) of the high-precision operational amplifier 31 only needs to be the reference signal Vb. Therefore, the fourth resistor element 41 and the fifth resistor element 42 are not limited to having the resistance values ​​R1 and R2 mentioned above, respectively. For example, as long as the voltage division ratio of the fifth resistor element 42 to the fourth resistor element 41 is equal to the voltage division ratio of the first resistor element 24 to the input resistor 212, the resistance values ​​of the fourth resistor element 41 and the fifth resistor element 42 can also be different from the resistance values ​​R1 and R2, respectively.

[0101] One end of the fourth resistor 41 is connected to the input terminal of the input resistor 212, and the other end of the fourth resistor 41 is connected to one end of the fifth resistor 42. The other end of the fifth resistor 42 is connected to the reference potential terminal 9. Furthermore, the non-inverting input terminal (+) of the high-precision operational amplifier 31 is connected to the junction between the other end of the fourth resistor 41 and one end of the fifth resistor 42.

[0102] Thus, the reference signal generation unit 40 uses the fourth resistor element 41 and the fifth resistor element 42, which correspond to the input resistor 212 and the first resistor element 24 respectively, to divide the second potential signal V2 input to the input resistor 212, thereby generating the reference signal Vb. Therefore, an external power supply for generating the reference signal Vb is not required in the differential amplifier circuit 100.

[0103] Furthermore, by using the fourth resistor element 41 and the fifth resistor element 42 corresponding to the input resistor 212 and the first resistor element 24, and the second potential signal V2, the reference signal Vb that satisfies the above formula (3) is accurately generated, thus reliably reducing the offset voltage of the operational amplifier 22.

[0104] It should be noted that R3 can also be set to 0 in formula (13). Therefore, the second resistor element 32 may not be required in this embodiment. Furthermore, in this embodiment, it is sufficient to configure the high-precision operational amplifier 31 to apply negative feedback between the input terminals of the operational amplifier 22. For example, circuit elements may be inserted into the negative feedback loop of the high-precision operational amplifier 31.

[0105] Next, the effects of the first embodiment will be explained.

[0106] The differential amplifier circuit 100 of this embodiment includes a basic differential amplifier circuit 20, which has: a first input resistor 211 and a second input resistor 212, which are respectively input with two potential signals V1 and V2; and an operational amplifier 22, which amplifies the potential difference between the output terminals of the first input resistor 211 and the second input resistor 212. Furthermore, the basic differential amplifier circuit 20 includes: a feedback resistor 23 connected to the output terminal of the first input resistor 211; and a first resistive element 24 connected to the output terminal of the second input resistor 212.

[0107] Furthermore, the differential amplifier circuit 100 includes a high-precision operational amplifier 31, which has a smaller offset voltage or drift voltage compared to the operational amplifier 22. Additionally, the output terminal of the first input resistor 211 is directly or indirectly connected to the inverting input terminal (-) of the high-precision operational amplifier 31, and the output terminal of the second input resistor 212 is directly or indirectly connected to the output terminal of the high-precision operational amplifier 31.

[0108] Furthermore, a reference signal Vb is input to the non-inverting input terminal (+) of the high-precision operational amplifier 31, which is equivalent to the potential generated at the non-inverting input terminal (+) of the operational amplifier 22 in the state of only the basic differential amplifier circuit 20.

[0109] According to this configuration, the high-precision operational amplifier 31 is configured to apply negative feedback from the inverting input terminal (-) of the operational amplifier 22 to the non-inverting input terminal (+) of the operational amplifier 22 via the high-precision operational amplifier 31 itself. Furthermore, the reference signal Vb input to the non-inverting input terminal (+) of the high-precision operational amplifier 31 is generated based on the potential generated at the non-inverting input terminal (+) of the operational amplifier 22 in the state of only the basic differential amplifier circuit 20. Therefore, the high-precision operational amplifier 31 can acquire the potential Vb fed back from the inverting input terminal (-) of the operational amplifier 22. - The difference obtained by subtracting the reference signal Vb is used to extract a component that is equivalent to the offset voltage or drift voltage of the operational amplifier 22.

[0110] Therefore, the high-precision operational amplifier 31 operates based on the extracted difference to provide negative feedback to the non-inverting input terminal (+) of operational amplifier 22 via the inverting input terminal (-) and the high-precision operational amplifier 31. This reduces the potential difference between the input terminals of operational amplifier 22, thereby lowering the offset voltage or drift voltage of operational amplifier 22. Thus, the performance of operational amplifier 22 is maintained while reducing its input offset voltage or drift voltage.

[0111] In addition, in the differential amplifier circuit 100 of this embodiment, the second resistor element 32 is disposed between the output terminal of the high-precision operational amplifier 31 and the output terminal of the second input resistor 212. This allows for appropriate adjustment of the sensitivity of the negative feedback control of the high-precision operational amplifier 31. Therefore, oscillations in, for example, the high-precision operational amplifier 31 can be suppressed.

[0112] Furthermore, in this embodiment, the second resistor element 32 is connected between the output terminal of the high-precision operational amplifier 31 and the output terminal of the second input resistor 212. Also, the high-precision operational amplifier 31 responds to the potential V generated at the inverting input terminal (-) of the operational amplifier 22. - Feedback is provided, and a potential V is output to the second resistive element 32 to reduce the feedback. - The adjustment signal for the difference between the reference signal Vb and the reference signal.

[0113] Furthermore, the differential amplifier circuit 100 of this embodiment includes a fourth resistor element 41 and a fifth resistor element 42. One end of the fourth resistor element 41 is connected to the input terminal of the input resistor 212, and the other end of the fourth resistor element 41 is connected to the non-inverting input terminal (+) of the high-precision operational amplifier 31. One end of the fifth resistor element 42 is connected to the other end of the fourth resistor element 41, and the other end of the fifth resistor element 42 is connected to the reference potential terminal 9.

[0114] At this time, the resistance values ​​of the fourth resistor element 41 and the fifth resistor element 42 are set such that the voltage division ratio of the fifth resistor element 42 to the fourth resistor element 41 is the same as the voltage division ratio of the first resistor element 24 to the input resistor 212.

[0115] According to this configuration, the reference signal Vb shown in the above formula (3) is supplied from the junction of the fourth resistor element 41 and the fifth resistor element 42 to the non-inverting input terminal (+) of the high-precision operational amplifier 31. Thus, a potential difference equivalent to the input offset voltage of the operational amplifier 22 can be reliably extracted in the high-precision operational amplifier 31. Furthermore, an external power supply is not required, and therefore the reference signal Vb can be generated with a simple configuration.

[0116] Thus, in the differential amplifier circuit 100, by configuring the fourth resistor element 41 and the fifth resistor element 42, which correspond to the input resistor 212 and the first resistor element 24 respectively, the two opposite effects of high precision of the reference signal Vb and simplification of circuit configuration can be achieved simultaneously.

[0117] Furthermore, the reference signal Vb in this embodiment is determined by the above formula (3). Therefore, in the high-precision operational amplifier 31, the potential Vb generated from the inverting input terminal (-) of the operational amplifier 22 can be... - The input offset voltage of operational amplifier 22 is reliably extracted by subtracting the reference signal Vb and applied to the non-inverting input terminal (+) of operational amplifier 22. Therefore, the offset voltage of operational amplifier 22 can be accurately reduced.

[0118] (Second Implementation)

[0119] The high-precision operational amplifier 31 of the first embodiment is used in the high-frequency band of open-loop gain from the above formulas (12) to (14), but the upper limit of the effective frequency band of the high-precision operational amplifier 31 is lower than the gain-bandwidth product of the operational amplifier 22.

[0120] As a result, when two potential signals V1 and V2 with frequencies higher than the upper limit of the effective bandwidth of the high-precision operational amplifier 31 are input into the differential amplifier circuit 100, the output noise included in the output signal of the high-precision operational amplifier 31 will increase.

[0121] As a countermeasure, refer to Figure 3 An implementation with the following additional circuit configuration will be described, which is used to suppress the effects of increased output noise in the high-precision operational amplifier 31 in a frequency band higher than the upper limit of the effective frequency band of the high-precision operational amplifier 31.

[0122] It should be noted that the portion of the frequency band higher than the upper limit of the effective frequency band of the high-precision operational amplifier 31 is referred to as the high-frequency region, and the portion of the frequency band lower than the high-frequency region is referred to as the low-frequency region.

[0123] Figure 3 This is a circuit diagram showing the configuration of the differential amplifier circuit 101 in the second embodiment.

[0124] In addition to having, the differential amplifier circuit 101 has Figure 1 In addition to the configuration of the differential amplifier circuit 100 shown, it also includes a third resistive element 33 and a high-frequency energizing section 34.

[0125] In this embodiment, the differential amplifier circuit 101, except for the high-frequency energizing section 34, has a configuration that is basically the same as that of the differential amplifier circuit 100. Therefore, the same reference numerals are used for the same components below, and repeated descriptions are omitted.

[0126] The operational amplifier 22 in this embodiment is a high-speed operational amplifier that can operate even in the high-frequency region. For example, the gain-bandwidth product of the high-speed operational amplifier is about 100 [MHz].

[0127] The third resistor element 33 and the high-frequency energizing part 34 have the function of supplying an adjustment signal, which is part of the output of the high-precision operational amplifier 31, to the inverting input terminal (-) of the operational amplifier 22 in the high-frequency region.

[0128] In this embodiment, the third resistor element 33 is set to the same resistance value R3 as the second resistor element 32, so that the adjustment signal from the high-precision operational amplifier 31 is evenly distributed to both the inverting input terminal (-) and the non-inverting input terminal (+) of the operational amplifier 22.

[0129] One end of the third resistive element 33 is connected to the output terminal of the input resistor 211, the inverting input terminal (-) of the operational amplifier 22, and one end of the feedback resistor 23. In this embodiment, the third resistive element 33 is implemented by a single resistor, but it can also be implemented by multiple resistors. When the third resistive element 33 is implemented by multiple resistors, it is preferable to make it have the same configuration as the second resistive element 32. This allows for accurate bisection of the adjustment signal from the high-precision operational amplifier 31.

[0130] The high-frequency energizing unit 34 constitutes an energizing unit that energizes the output terminal of the high-precision operational amplifier 31 with the inverting input terminal (-) according to the increase (rise) of the frequency of the first potential signal V1 or the second potential signal V2. The high-frequency energizing unit 34 is, for example, composed of a component or switching circuit that allows high-frequency signals to pass through.

[0131] As an example, the high-frequency power-on unit 34 includes a switching circuit that switches the output terminal of the high-precision operational amplifier 31 to an on or off state based on whether the frequency of the first potential signal V1 or the second potential signal V2 is higher than a predetermined threshold. It should be noted that the predetermined threshold is preset based on the upper limit of the gain-bandwidth product of the high-precision operational amplifier 31, for example, it is set to 100 Hz.

[0132] In this example, the high-frequency energizing unit 34 receives a control signal indicating whether the frequency of the first potential signal V1 or the second potential signal V2 is below a predetermined threshold. This control signal can be generated by user input, or it can be generated by the high-frequency energizing unit 34 acquiring an output signal representing the frequency of the potential signals V1 and V2 from a frequency analysis sensor (not shown) and generating the control signal based on that output signal.

[0133] When a control signal indicating that the frequency of the first potential signal V1 or the second potential signal V2 is below a predetermined threshold is received, the high-frequency energizing unit 34 controls the switching circuit to make the output terminal of the high-precision operational amplifier 31 and the inverting input terminal (-) non-conductive. As a result, the open-loop gain of the high-precision operational amplifier 31 becomes sufficiently large, thereby reducing the offset voltage of the operational amplifier 22.

[0134] On the other hand, when a control signal indicating a frequency higher than a predetermined threshold is received, the high-frequency energizing unit 34 controls the switching circuit to make the output terminal of the high-precision operational amplifier 31 and the inverting input terminal (-) in a conducting state. As a result, the high-precision operational amplifier 31 functions as a voltage follower circuit performing unity-gain operation, and the adjustment signal output from the high-precision operational amplifier 31 is evenly distributed between the second resistive element 32 and the third resistive element 33.

[0135] Therefore, the signal obtained by equally distributing the adjustment signal from the high-precision operational amplifier 31 is input as an in-phase signal to the inverting input terminal (-) and the non-inverting input terminal (+) of the operational amplifier 22, so the in-phase signals cancel each other out in the operational amplifier 22.

[0136] Thus, the noise generated in the high-precision operational amplifier 31 due to the input of a first potential signal V1 with a frequency higher than the upper limit of the effective bandwidth of the high-precision operational amplifier 31 is removed in the operational amplifier 22.

[0137] Next, refer to Figure 4 A specific example of the configuration of the differential amplifier circuit 101 will be explained.

[0138] Figure 4This is a circuit diagram showing the detailed configuration of the differential amplifier circuit 101 in this embodiment. Figure 4 In the diagram, capacitor 34A is shown as the high-frequency energizing unit 34, and voltage divider circuit 40B is shown as the reference signal generation unit 40. Other configurations are similar to... Figure 3 The differential amplifier circuit 101 shown has the same configuration, so the configuration of capacitor 34A and voltage divider circuit 40B will be mainly described here.

[0139] Capacitor 34A is connected between the output terminal and the inverting input terminal (-) of the high-precision operational amplifier 31. Furthermore, capacitor 34A has the following characteristic: as the frequency of the first potential signal V1 increases, the impedance of capacitor 34A decreases, making it easier to conduct current.

[0140] One end of capacitor 34A is connected to the other end of the third resistor element 33 and the inverting input terminal (-) of the high-precision operational amplifier 31, and the other end of capacitor 34A is connected to one end of the second resistor element 32 and the output terminal of the high-precision operational amplifier 31.

[0141] In the capacitor 34A of this embodiment, the impedance of capacitor 34A is high below the upper limit of the effective frequency band of the high-precision operational amplifier 31, thus creating an insulated state between the output terminal and the inverting input terminal (-) of the high-precision operational amplifier 31. The upper limit of the effective frequency band of the high-precision operational amplifier 31 is, for example, the frequency at which the open-loop gain of the high-precision operational amplifier 31 is halved from its maximum value.

[0142] On the other hand, in capacitor 34A, the impedance of capacitor 34A decreases in the high-frequency region, which is higher than the upper limit of the effective frequency band of high-precision operational amplifier 31, thus energizing the output terminal of high-precision operational amplifier 31 with the inverting input terminal (-).

[0143] Therefore, the capacitance C of capacitor 34A is set such that the impedance of capacitor 34A decreases as the frequency of the AC signal input to capacitor 34A increases from near the upper limit of the effective bandwidth of high-precision operational amplifier 31. For example, the capacitance C of capacitor 34A is set to 100 [nF].

[0144] Thus, by configuring capacitor 34A in the feedback path that connects the output terminal and the inverting input terminal (-) of the high-precision operational amplifier 31, the feedback path can be switched from an insulated state to an energized state according to the increase in the frequency of the first potential signal V1.

[0145] Next, the voltage divider circuit 40B, which functions as the reference signal generation unit 40, will be described.

[0146] In addition to having the following features, the voltage divider circuit 40B also has Figure 2In addition to the voltage divider circuit 40A shown, it also includes a resistor circuit 43 located between the input terminal of the input resistor 211 and the reference potential terminal 9. The resistor circuit 43 is composed of one or more resistive elements.

[0147] The resistor circuit 43 has the same resistance value as the fourth resistor element 41 and the fifth resistor element 42 connected in series. Specifically, the resistance value of the resistor circuit 43 is set to the value (R1+R2) obtained by adding the resistance value R1 of the fourth resistor element 41 and the resistance value R2 of the fifth resistor element 42.

[0148] Therefore, the sum of the resistance values ​​of resistor circuit 43, input resistor 211, and feedback resistor 23 becomes the same as the sum of the resistance values ​​of fourth resistor element 41, fifth resistor element 42, input resistor 212, and first resistor element 24. That is, the load resistor connected to the first input terminal 11 is the same as the load resistor connected to the second input terminal 12.

[0149] Therefore, the phase of the first current signal transmitted from the first input terminal 11 to the inverting input terminal (-) of the operational amplifier 22 is easily synchronized with the phase of the second current signal transmitted from the second input terminal 12 to the non-inverting input terminal (+) of the operational amplifier 22. Therefore, with Figure 2 Compared to the voltage divider circuit 40A shown, the signal delay of the second current signal relative to the first current signal is smaller, thus reducing the output error of the operational amplifier 22 caused by the signal delay.

[0150] The resistor circuit 43 in this embodiment is composed of resistor elements 431 and 432 connected in series. Specifically, one end of resistor element 431 is connected to the input terminal of input resistor 211, and the other end of resistor element 431 is connected to one end of resistor element 432. Furthermore, the other end of resistor element 432 is connected to the reference potential terminal 9.

[0151] Resistor element 431 has the same resistance value as the fourth resistor element 41 and is composed of the same components as the fourth resistor element 41. Resistor element 432 has the same resistance value as the fifth resistor element 42 and is composed of the same components as the fifth resistor element 42.

[0152] Thus, by configuring the resistor circuit 43 in a symmetrical manner with respect to the fourth resistor element 41 and the fifth resistor element 42 constituting the voltage divider circuit 40A, the signal characteristics of the second current signal, which are associated with the configuration of the voltage divider circuit 40A, can also be applied to the first current signal. Therefore, compared to configuring only one resistor element with the same resistance value as the fourth resistor element 41 and the fifth resistor element 42, the output error of the operational amplifier 22 caused by the configuration of the voltage divider circuit 40A can be reduced.

[0153] Next, refer to Figure 5A and Figure 5B The operation of the differential amplifier circuit 101 in this embodiment will be explained.

[0154] Figure 5A This diagram illustrates the operation of the differential amplifier circuit 101 when the frequency of the first potential signal V1 is below the upper limit of the effective bandwidth of the high-precision operational amplifier 31. Figure 5B This diagram illustrates the operation of the differential amplifier circuit 101 when the frequency of the first potential signal V1 is in the high-frequency band.

[0155] like Figure 5A As shown, when the frequency of the first potential signal V1 is below the upper limit of the effective bandwidth of the high-precision operational amplifier 31, the impedance of the capacitor 34A increases, and the open-loop gain of the high-precision operational amplifier 31 becomes sufficiently large. Therefore, the high-precision operational amplifier 31 applies negative feedback from the inverting input terminal (-) of the operational amplifier 22 to the non-inverting input terminal (+) via itself to reduce the input offset voltage of the operational amplifier 22.

[0156] On the other hand, when the frequency of the first potential signal V1 is in the high-frequency band, an AC signal with a frequency higher than the upper limit of the effective frequency band is input to the high-precision operational amplifier 31. As a result, the noise generated by the high-precision operational amplifier 31 increases compared to the case where an AC signal with a frequency lower than the upper limit of the effective frequency band is input to the high-precision operational amplifier 31.

[0157] At this time, when the frequency of the first potential signal V1 is in the high-frequency band, such as Figure 5B As shown, the impedance of capacitor 34A decreases, and the output terminal of high-precision operational amplifier 31 becomes energized with respect to the inverting input terminal (-).

[0158] Therefore, the high-precision operational amplifier 31 operates as a voltage follower circuit, and the output terminal of the high-precision operational amplifier 31 is connected to a differential amplifier circuit consisting of a third resistor element 33 and a feedback resistor 23, a second resistor element 32 and a first resistor element 24, and the operational amplifier 22.

[0159] Thus, the output signal of the high-precision operational amplifier 31 is evenly distributed to a first path consisting of a third resistor 33 connected to the inverting input terminal (-) of the operational amplifier 22 and a feedback resistor 23, and a second path consisting of a second resistor 32 connected to the non-inverting input terminal (+) of the operational amplifier 22 and a first resistor 24. The bisected signals are then input as non-inverting signals to the two input terminals of the operational amplifier 22, thereby removing noise from the output signal of the high-precision operational amplifier 31 within the operational amplifier 22.

[0160] Therefore, even if the frequencies of the first potential signal V1 and the second potential signal V2 are higher than the upper limit of the effective bandwidth of the high-precision operational amplifier 31, the increased noise generated from the high-precision operational amplifier 31 can be suppressed, and the offset voltage or drift voltage of the operational amplifier 22 can be reduced.

[0161] It should be noted that in this embodiment, a voltage divider circuit 40B is used as the reference signal generation unit 40, but it can also be replaced by... Figure 2 The voltage divider circuit shown is 40A or an external power supply.

[0162] Next, refer to Figures 6 to 9 The frequency characteristics of the differential amplifier circuit 101 will be explained. More specifically, the analysis results obtained from the simulation analysis of the differential amplifier circuit 101 will be explained, and the analysis results of a general differential amplifier circuit with only the basic differential amplifier circuit 20 (excluding the offset voltage suppression circuit 30) will also be explained as a comparison.

[0163] Figure 6 This is a graph showing the numerical values ​​of the parameters of the differential amplifier circuit 101 set in the simulation analysis.

[0164] In the simulation analysis of the differential amplifier circuit 101, the resistance values ​​R1 of the first input resistor 211, the second input resistor 212, the fourth resistor element 41, and the resistor element 431 are set to 2 [kΩ], and the resistance values ​​R2 of the feedback resistor 23, the first resistor element 24, the fifth resistor element 42, and the resistor element 432 are set to 2 [kΩ]. Furthermore, the resistance values ​​R3 of the second resistor element 32 and the third resistor element 33 are also set to 2 [kΩ].

[0165] In addition, the gain-bandwidth product of operational amplifier 22 is set to 145 [MHz], and the gain-bandwidth product of high-precision operational amplifier 31 is set to 3 [MHz].

[0166] Figure 7 It means and Figure 6 The graph shows the analysis results related to the offset voltage included in the output of the differential amplifier circuit 101.

[0167] exist Figure 7 In the diagram, the analysis results of the differential amplifier circuit 101 are represented by solid lines, with the vertical axis representing the offset voltage [μV] of the output of the differential amplifier circuit 101 and the horizontal axis representing time [ms]. Here, the analysis results of the circuit configuration of the basic differential amplifier circuit 20 are represented by dashed lines as a comparison object.

[0168] like Figure 7 As shown, in the circuit configuration of only the basic differential amplifier circuit 20, the offset voltage of the output of the operational amplifier 22 is always fixed at -800 [μV] regardless of the rise in frequency of the potential signals V1 and V2.

[0169] In contrast, in the differential amplifier circuit 101 equipped with the offset voltage suppression circuit 30, the input offset voltage of the high-precision operational amplifier 31 with low offset voltage is less than that of the operational amplifier 22, and is approximately fixed at 0 (zero) [μV]. Therefore, the output offset voltage of the operational amplifier 22 is also approximately 0 [μV], just like that of the high-precision operational amplifier 31.

[0170] Thus, by configuring the high-precision operational amplifier 31, after inputting the reference signal Vb to the non-inverting input terminal (+), to apply negative feedback from the inverting input terminal (-) of the operational amplifier 22 to the non-inverting input terminal (+), the offset voltage of the output of the operational amplifier 22 can be reduced.

[0171] Next, the frequency characteristics related to the output noise of the differential amplifier circuit 101 will be explained.

[0172] Figure 8A It means and Figure 6 The graph shows the analysis results of the frequency characteristics related to the output noise of the differential amplifier circuit 101 shown. Figure 8B This is a graph showing the analysis results of the frequency characteristics related to the output noise of the basic differential amplifier circuit 20 only.

[0173] Figure 8A and Figure 8B The horizontal axis is a common frequency axis, representing the frequencies of the two potential signals V1 and V2. Figure 8A The vertical axis represents the noise voltage density per 1 Hz in the output noise of the differential amplifier circuit 101. Figure 8B The vertical axis represents the noise voltage density of the output noise of the basic differential amplifier circuit 20.

[0174] like Figure 8A and Figure 8BAs shown, in the low-frequency region, the output noise of the differential amplifier circuit 101 is very small, about one-thousandth, compared to the output noise of the basic differential amplifier circuit 20 alone, which is used as a comparison object. In other words, the 1 / f noise in the differential amplifier circuit 101 is sufficiently reduced.

[0175] The reason why the output noise becomes extremely low is as follows: the voltage signal input to the inverting input terminal (-) of operational amplifier 22 is negatively fed back to the non-inverting input terminal (+) of operational amplifier 22 via high-precision operational amplifier 31. As a result, the output noise in the low-frequency region is determined by the characteristics of high-precision operational amplifier 31, thus reducing the noise component of the signal output from operational amplifier 22.

[0176] Next, the frequency characteristics related to the common mode rejection ratio (CMRR) of the differential amplifier circuit 101 will be explained.

[0177] Figure 9 It means to express and Figure 6 The figure shows the results of a simulation analysis of the frequency characteristics related to the common-mode rejection ratio of the differential amplifier circuit 101 shown. This analysis takes into account the deviations of the resistive elements constituting the differential amplifier circuit 101.

[0178] exist Figure 9 In the diagram, the analysis results of the differential amplifier circuit 101 are represented by solid lines, with the vertical axis representing the common-mode rejection ratio of the differential amplifier circuit 101 and the horizontal axis representing the frequencies of the two potential signals V1 and V2 input to the differential amplifier circuit 101. Here, the analysis results of a typical differential amplifier circuit, i.e., only the circuit configuration of the basic differential amplifier circuit 20, are represented by dashed lines as a comparison object.

[0179] like Figure 9 As shown, in the low-frequency region, the common-mode rejection ratio of the differential amplifier circuit 101 is higher than that of the circuit consisting only of the basic differential amplifier circuit 20.

[0180] The reason is as follows Figure 8A and Figure 8B As described above, this is because negative feedback is applied from the inverting input terminal (-) of the operational amplifier 22 to the non-inverting input terminal (+) of the operational amplifier 22 via the high-precision operational amplifier 31. Furthermore, the non-inverting signal components cancel each other out in the operational amplifier 22, thereby improving the common-mode rejection ratio.

[0181] On the other hand, in the high-frequency region, the common-mode rejection ratio of the differential amplifier circuit 101 is maintained at the same level as that of the circuit consisting only of the basic differential amplifier circuit 20.

[0182] The reason is that the capacitor 34A configured in the feedback path of the high-precision operational amplifier 31 is energized, and the output signal of the high-precision operational amplifier 31, which is performing unity gain operation, is divided into two, and the resulting in-phase signal is input to the two input terminals of the operational amplifier 22.

[0183] Therefore, the in-phase signal is removed by the differential amplifier circuit consisting of operational amplifier 22, first resistor element 24, second resistor element 32, third resistor element 33, and feedback resistor 23, thus reducing the output noise of the high-precision operational amplifier 31 that occurs beyond its operating frequency range. Consequently, the common-mode rejection ratio of operational amplifier 22 is significantly reduced.

[0184] Thus, in the differential amplifier circuit 101, the common-mode rejection ratio can be equal to or higher than that of a general differential amplifier circuit, i.e., the circuit consisting only of the basic differential amplifier circuit 20, in all frequency bands below the frequency band of the basic differential amplifier circuit 20 composed of operational amplifier 22.

[0185] Next, the effects of the second embodiment will be explained.

[0186] The differential amplifier circuit 101 in this embodiment performs the same function as the differential amplifier circuit 100 in the first embodiment.

[0187] Furthermore, in this embodiment, a high-frequency energizing unit 34 is provided as an energizing unit, which energizes the output terminal of the high-precision operational amplifier 31 and the inverting input terminal (-) by increasing the frequency of the potential signal V1 input to the first input resistor 211.

[0188] According to this composition, such as Figure 5B As shown, the adjustment signal from the high-precision operational amplifier 31 is split into two, and the two in-phase signals obtained by the split are input to the two input terminals of the operational amplifier 22. Thus, the two in-phase signals obtained by the split in the operational amplifier 22 cancel each other out, thereby reducing the increased output noise in the high-precision operational amplifier 31 in the high-frequency region.

[0189] Furthermore, the high-frequency power-on unit 34 in this embodiment includes a capacitor 34A, which is connected between the output terminal and the inverting input terminal (-) of the high-precision operational amplifier 31. By using the capacitor 34A, the high-frequency power-on unit 34 can be made into a simple circuit configuration, and AC signals can be passed between the output terminal and the inverting input terminal (-) of the high-precision operational amplifier 31 in the high-frequency region.

[0190] Therefore, when the frequencies of the potential signals V1 and V2 are higher than a predetermined threshold, the high-precision operational amplifier 31 operates as a voltage follower circuit with unity gain. Furthermore, the high-precision operational amplifier 31 outputs a potential V, representing the feedback from the inverting input terminal (-) of the operational amplifier 22, to both the second resistor element 32 and the additional third resistor element 33. - The adjustment signal for the difference between the reference signal Vb and the reference signal.

[0191] Therefore, by dividing the output signal of the high-precision operational amplifier 31 into two, the resulting in-phase signals are supplied to the two input terminals of the operational amplifier 22 respectively, thereby reducing the increased noise included in the output signal of the high-precision operational amplifier 31 in the operational amplifier 22.

[0192] Furthermore, the differential amplifier circuit 101 of this embodiment also includes a third resistor element 33, which is connected between the output terminal of the first input resistor 211 and the inverting input terminal (-) of the high-precision operational amplifier 31. The third resistor element 33 has the same resistance value R3 as the second resistor element 32.

[0193] Therefore, the in-phase signal obtained by dividing the output signal of the high-precision operational amplifier 31 into two equal parts is supplied to the two input terminals of the operational amplifier 22, thereby eliminating the increased noise included in the output signal of the high-precision operational amplifier 31 in the operational amplifier 22.

[0194] In this embodiment, the differential amplifier circuit 101 includes: a fourth resistor element 41 having a resistance value R1 equal to that of the second input resistor 212; and a fifth resistor element 42 having a resistance value R2 equal to that of the first resistor element 24. That is, the resistance values ​​of the fourth resistor element 41 and the fifth resistor element 42 are set such that the voltage division ratio of the fifth resistor element 42 and the fourth resistor element 41 becomes the same as the voltage division ratio of the first resistor element 24 and the input resistor 212.

[0195] Furthermore, one end of the fourth resistor element 41 is connected to the input terminal of the second input resistor 212, and the other end of the fourth resistor element 41 is connected to one end of the fifth resistor element 42, the other end of the fifth resistor element 42 being connected to the reference potential terminal 9. Additionally, the non-inverting input terminal (+) of the high-precision operational amplifier 31 is connected between the fourth resistor element 41 and the fifth resistor element 42.

[0196] In addition, the differential amplifier circuit 101 also includes a resistor circuit 43, which is located between the input terminal of the first input resistor 211 and the reference potential terminal 9. The resistor circuit 43 has the same resistance value (R1+R2) as the fourth resistor element 41 and the fifth resistor element 42 connected in series.

[0197] Thus, by configuring a resistor circuit 43 between the input terminal of the first input resistor 211 and the reference potential terminal 9, the load resistance connected to the input terminal of the first input resistor 211 is equal to the load resistance connected to the input terminal of the second input resistor 212. Therefore, compared to the case where the resistor circuit 43 is not configured, the delay between the current signals supplied to the two input terminals of the operational amplifier 22 is reduced, thereby reducing the output error of the operational amplifier 22 caused by the delay.

[0198] The operational amplifier 22 in this embodiment is a high-speed operational amplifier with a gain-bandwidth product of several MHz or more. As a result, the performance of the high-speed operational amplifier can be maintained in the differential amplifier circuit 101, and the offset voltage or drift voltage of the high-speed operational amplifier can be reduced.

[0199] The embodiments of the present invention have been described above. However, the above embodiments only illustrate a part of the application examples of the present invention and are not intended to limit the technical scope of the present invention to the specific configurations of the above embodiments.

[0200] For example, in the first embodiment, a voltage divider circuit 40A is provided in the differential amplifier circuit 100 as a reference signal generation unit 40, but it can also be replaced by another voltage divider circuit. Figure 4 The voltage divider circuit 40B is shown. In this case, similar to the second embodiment, the delay between the current signals supplied to the two input terminals of the operational amplifier 22 can also be suppressed.

[0201] In addition, in the second embodiment, a second resistor element 32 and a third resistor element 33 are provided in the offset voltage suppression circuit 30, but it is also possible that a capacitor is connected in parallel with the second resistor element 32 and the third resistor element 33 respectively.

[0202] This application claims priority based on Japanese Patent Application No. 2020-168100, filed with the Japan Patent Office on October 2, 2020, the entire contents of which are incorporated herein by reference.

[0203] Explanation of reference numerals in the attached figures

[0204] 20: Basic differential amplifier circuit;

[0205] 21: A pair of input resistors;

[0206] 211, 212: First input resistor, second input resistor;

[0207] 23: Feedback resistor;

[0208] 24: First resistive element;

[0209] 31: High-precision operational amplifier;

[0210] 32, 33: Second and third resistive elements;

[0211] 34: High-frequency power-on section (power-on unit);

[0212] 34A: Capacitor;

[0213] 41, 42: Fourth and fifth resistive elements;

[0214] 43: Resistive circuit;

[0215] 100, 101: Differential amplifier circuit.

Claims

1. A differential amplifier circuit, comprising: A basic differential amplifier circuit has: a first input resistor and a second input resistor, which are respectively input with two potential signals; and an operational amplifier that amplifies the potential difference between the output terminals of the first input resistor and the second input resistor. The feedback resistor is connected at one end to the output terminal of the first input resistor and at the other end to the output terminal of the operational amplifier. And a first resistive element, one end of which is connected to the output terminal of the second input resistor, and the other end of which is connected to a reference potential terminal; as well as A high-precision operational amplifier, wherein the output terminal of the first input resistor is connected to the inverting input terminal and the output terminal of the second input resistor is connected to the output terminal. A reference signal is obtained by inputting a potential equivalent to the potential generated at the non-inverting input terminal of the operational amplifier in the state of only the basic differential amplifier circuit. A second resistive element is disposed between the output terminal of the high-precision operational amplifier and the output terminal of the second input resistor. To ensure that the open-loop gain of the high-precision operational amplifier is sufficiently large, the following condition must be met: Where A is the open-loop gain of the high-precision operational amplifier, and X, Y, and Z are respectively represented by the following formulas: Wherein, R1 is the resistance value of a pair of first input resistors and second input resistors, R2 is the resistance value of the first resistor element, and R3 is the resistance value of the second resistor element.

2. The differential amplifier circuit according to claim 1 further comprises: The energizing unit energizes the output terminal and the inverting input terminal of the high-precision operational amplifier by increasing the frequency of the potential signal input to the first input resistor.

3. The differential amplifier circuit according to claim 2, wherein, The power-on unit includes a capacitor connected between the output terminal and the inverting input terminal of the high-precision operational amplifier.

4. The differential amplifier circuit according to claim 2 or 3 further comprises: A third resistor is connected between the output terminal of the first input resistor and the inverting input terminal of the high-precision operational amplifier. The third resistive element has the same resistance value as the second resistive element.

5. The differential amplifier circuit according to claim 4, wherein, The high-precision operational amplifier acts as a voltage follower circuit to output adjustment signals to the second and third resistive elements when the frequency of the potential signal is higher than a specified threshold.

6. The differential amplifier circuit according to claim 1, comprising: A fourth resistor element, one end of which is connected to the input terminal of the second input resistor and the other end of which is connected to the non-inverting input terminal of the high-precision operational amplifier; and The fifth resistive element has one end connected to the other end of the fourth resistive element and the other end connected to the reference potential terminal. The resistance values ​​of the fourth and fifth resistors are set such that the voltage division ratio of the fifth resistor to the fourth resistor is the same as the voltage division ratio of the first resistor to the second input resistor.

7. The differential amplifier circuit according to claim 6 further comprises: A resistor circuit is disposed between the input terminal of the first input resistor and the reference potential terminal, the resistor circuit having the same resistance value as the fourth and fifth resistor elements connected in series.

8. The differential amplifier circuit according to claim 1, wherein, The reference signal is determined by the following formula: in, Vb is the reference signal. V2 is the potential signal input to the second input resistor.

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