Fault diagnosis architecture, fault diagnosis method, computer device and storage medium
By using a fault diagnosis input bus module, an enable condition judgment module, a fault collection and judgment module, and a fault handling measures module, the coupling of the fault diagnosis architecture is reduced, the portability and efficiency of fault diagnosis are improved, and the problem of inconvenient portability of the fault diagnosis architecture in the prior art is solved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING SELIS PHOENIX INTELLIGENT INNOVATION TECH CO LTD
- Filing Date
- 2022-12-26
- Publication Date
- 2026-07-14
AI Technical Summary
The existing fault diagnosis architecture is highly coupled, which makes fault diagnosis methods difficult to port, increases development time and cost, and reduces development efficiency and diagnosis efficiency.
The system employs a fault diagnosis input bus module, an enable condition judgment module, a fault collection and judgment module, and a fault handling measures module. Through signal mapping and bit operations, it reduces the coupling between modules and improves portability and diagnostic efficiency.
This reduces the coupling of the fault diagnosis architecture, improves the portability and efficiency of fault diagnosis, and shortens development time.
Smart Images
Figure CN116257033B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic and electrical architecture technology, and in particular to a fault diagnosis architecture, fault diagnosis method, computer equipment, and storage medium. Background Technology
[0002] With the development of automotive-related technologies, fault diagnosis of automobiles has become an indispensable and important function.
[0003] The vehicle controller can use fault diagnosis software to identify impending or existing faults in the vehicle and take appropriate measures to prevent injury to passengers or the vehicle. It also records the faults so that maintenance personnel can quickly locate and resolve them.
[0004] However, based on the current fault diagnosis architecture, the various fault diagnosis modules are highly coupled. When facing different projects, the fault diagnosis architecture is very inconvenient to port. It requires refactoring the architecture and rewriting the logic algorithm, which greatly increases development time and cost, reduces development efficiency, and also leads to low diagnostic efficiency of the fault diagnosis method. Summary of the Invention
[0005] Based on this, a fault diagnosis architecture, fault diagnosis method, computer equipment, and storage medium are provided to improve the problem of high coupling in the existing fault diagnosis architecture, which is not conducive to the development and maintenance of the fault diagnosis architecture.
[0006] On the one hand, a fault diagnosis architecture is provided, the architecture including:
[0007] The fault diagnosis input bus module is used to receive communication signals from the function module under test transmitted on the bus, and to connect the fault diagnosis input bus module and the function module under test with signal lines according to the communication signals and a preset signal mapping table.
[0008] The enable condition judgment module is used to match the communication signal with a preset fault information table to obtain an enable condition flag bit, and to perform bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0009] The fault collection and judgment module is used to perform bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and output it.
[0010] The fault handling measures module is used to receive the fault signal and look up the corresponding fault handling measures according to the fault flag bit and the fault information table;
[0011] The fault diagnosis output bus module is used to connect the fault diagnosis output bus module and the tested functional module through signal lines according to the communication signal and the signal mapping table, and output the fault flag bit and the fault handling measures.
[0012] In one embodiment, the fault diagnosis architecture further includes:
[0013] The fault level management module is used to receive the fault signal, look up the corresponding fault level according to the fault flag bit and the fault information table, filter the fault level numerically and output it.
[0014] The fault code management module is used to receive the fault signal, look up the corresponding fault code according to the fault flag bit and the fault information table, and output the fault code.
[0015] The fault diagnosis output bus module is also used to output the fault level and the fault code.
[0016] On the other hand, a fault diagnosis method is provided, which is applied to any of the above-mentioned fault diagnosis architectures, and the method steps include:
[0017] The fault diagnosis input bus module receives the communication signals transmitted on the bus from the functional module under test, and connects the functional module under test with the signal lines according to the communication signals and the preset signal mapping table.
[0018] The enable condition judgment module matches the communication signal with a preset fault information table to obtain an enable condition flag bit, and performs bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0019] The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it.
[0020] After receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table;
[0021] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag and the fault handling measures.
[0022] In one embodiment, after the fault collection and judgment module performs bitwise operations on the communication signal and the enable condition flag bit according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it, the method further includes:
[0023] After receiving the fault signal, the fault level management module searches for the fault level corresponding to the fault flag bit in the fault information table, performs numerical filtering on the fault level, and outputs it.
[0024] After receiving the fault signal, the fault code management module looks up the fault code corresponding to the fault flag bit in the fault information table and outputs the fault code.
[0025] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag, the fault handling measures, the fault level, and the fault code.
[0026] In one embodiment, it further includes:
[0027] Perform bitwise operations on the enable condition flag bits to obtain an enable signal containing the enable condition flag bits, including:
[0028] The enable condition flag is shifted bit by bit, and the shifted enable condition flags are combined by an OR operation to obtain an enable signal containing the enable condition flags, wherein the enable condition flags correspond to preset diagnostic enable conditions.
[0029] In one embodiment, it further includes:
[0030] The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it, including:
[0031] The preset diagnostic calibration value and the enable signal in the fault collection and judgment module are integrated by AND operation so that the diagnostic enable condition is mapped in the fault collection and judgment module.
[0032] In one embodiment, before integrating the preset diagnostic calibration value in the fault collection and judgment module and the enable signal through computation, the method further includes:
[0033] If the fault collection and judgment module receives a first fault trigger signal containing the enable signal, and does not receive a subsequent second fault trigger signal after a preset waiting time, then it confirms that the diagnostic enable condition corresponding to the enable signal in the first fault trigger signal is met.
[0034] In one embodiment, after receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table, including:
[0035] According to the fault information table, the fault flag bit is matched with the preset handling measure calibration value in the fault handling measure module;
[0036] The matched fault flag bit is ORed with the calibrated value of the handling measure to obtain a set of handling measures variables;
[0037] Perform a bitwise AND operation between the set of processing measures and the calibrated value of the processing measures to obtain the fault processing measure flag bit, then shift the fault processing measure flag bit and output it.
[0038] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the following architecture:
[0039] The fault diagnosis input bus module is used to receive communication signals from the function module under test transmitted on the bus, and to connect the fault diagnosis input bus module and the function module under test with signal lines according to the communication signals and a preset signal mapping table.
[0040] The enable condition judgment module is used to match the communication signal with a preset fault information table to obtain an enable condition flag bit, and to perform bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0041] The fault collection and judgment module is used to perform bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and output it.
[0042] The fault handling measures module is used to receive the fault signal and look up the corresponding fault handling measures according to the fault flag bit and the fault information table;
[0043] The fault diagnosis output bus module is used to connect the fault diagnosis output bus module and the tested functional module through signal lines according to the communication signal and the signal mapping table, and output the fault flag bit and the fault handling measures.
[0044] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:
[0045] The fault diagnosis input bus module receives the communication signals transmitted on the bus from the functional module under test, and connects the functional module under test with the signal lines according to the communication signals and the preset signal mapping table.
[0046] The enable condition judgment module matches the communication signal with a preset fault information table to obtain an enable condition flag bit, and performs bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0047] The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it.
[0048] After receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table;
[0049] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag and the fault handling measures.
[0050] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, the computer program implementing the following architecture when executed by a processor:
[0051] The fault diagnosis input bus module is used to receive communication signals from the function module under test transmitted on the bus, and to connect the fault diagnosis input bus module and the function module under test with signal lines according to the communication signals and a preset signal mapping table.
[0052] The enable condition judgment module is used to match the communication signal with a preset fault information table to obtain an enable condition flag bit, and to perform bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0053] The fault collection and judgment module is used to perform bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and output it.
[0054] The fault handling measures module is used to receive the fault signal and look up the corresponding fault handling measures according to the fault flag bit and the fault information table;
[0055] The fault diagnosis output bus module is used to connect the fault diagnosis output bus module and the tested functional module through signal lines according to the communication signal and the signal mapping table, and output the fault flag bit and the fault handling measures.
[0056] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:
[0057] The fault diagnosis input bus module receives the communication signals transmitted on the bus from the functional module under test, and connects the functional module under test with the signal lines according to the communication signals and the preset signal mapping table.
[0058] The enable condition judgment module matches the communication signal with a preset fault information table to obtain an enable condition flag bit, and performs bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0059] The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it.
[0060] After receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table;
[0061] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag and the fault handling measures.
[0062] The aforementioned fault diagnosis architecture, fault diagnosis method, computer equipment, and storage medium receive communication signals from the tested functional module transmitted on the bus via a fault diagnosis input bus module. Based on the communication signals and a preset signal mapping table, the module connects to the tested functional module via signal lines. An enable condition judgment module maps the communication signals to a preset fault information table to obtain an enable condition flag. Bitwise operations are performed on the enable condition flag to obtain an enable signal containing the enable condition flag. A fault collection judgment module performs bitwise operations on the communication signals and the enable signal based on the fault information table to obtain a fault signal containing a fault flag and outputs it. Upon receiving the fault signal, a fault handling measure module searches for the fault handling measure corresponding to the fault flag based on the fault information table. Finally, a fault diagnosis output bus module connects to the tested functional module via signal lines based on the communication signals and the signal mapping table, and outputs the fault flag and the fault handling measure. The above-described fault diagnosis architecture and methods reduce the coupling of the fault diagnosis architecture, improve portability, shorten the development time of the fault diagnosis architecture, and improve the efficiency of the fault diagnosis process. Attached Figure Description
[0063] Figure 1 This is a schematic diagram of the fault diagnosis architecture in one embodiment;
[0064] Figure 2 This is a flowchart illustrating a fault diagnosis method in one embodiment;
[0065] Figure 3 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0067] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0068] The structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.
[0069] The orientations or positional relationships indicated by terms such as "upper," "lower," "left," "right," "middle," "longitudinal," "lateral," "horizontal," "inner," "outer," "radial," and "circumferential" used in this specification are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the purpose of simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0070] In one embodiment, such as Figure 1 As shown, a fault diagnosis architecture is provided. Taking the application of this architecture in a vehicle as an example, it includes the following modules:
[0071] The fault diagnosis input bus module is used to receive communication signals from the function module under test transmitted on the bus, and to connect the fault diagnosis input bus module and the function module under test with signal lines according to the communication signals and a preset signal mapping table.
[0072] Here, "bus" refers to the automotive bus, which is a communication network formed by interconnecting underlying vehicle devices or instruments in the vehicle network. Automotive buses include, but are not limited to, Controller Area Network (CAN) bus, Local Interconnect Network (LIN) bus, and Vehicle Area Network (VAN) bus.
[0073] For example, based on the technical solutions of one or more automotive development projects, corresponding fault information tables can be set up according to information such as fault triggering enable conditions, fault triggering conditions, fault recovery prerequisites, fault recovery conditions, fault levels, fault handling measures, and fault codes in the technical solutions. These fault information tables can be in Excel format to facilitate reading and processing using scripting tools such as MATLAB. It should be noted that the data in these fault information tables differs from that in the signal mapping tables.
[0074] Specifically, in the fault diagnosis input bus module, the communication signals of the tested functional module transmitted on the bus are mapped through a signal mapping table using a preset MATLAB script tool, so that the fault diagnosis input bus module and the tested functional module can be connected by signal lines.
[0075] It should be noted that the tested functional module can be considered as an external module of the fault diagnosis software, and the fault diagnosis input bus module is also connected to the internal modules of the software so that the external modules and the internal modules of the software can communicate and interact through the fault diagnosis input bus module.
[0076] In an alternative implementation, when mapping according to the signal mapping table, the interface signals of the software and the interface signals of the external modules of the software can be matched according to the signal mapping table. The signal mapping table includes pre-set corresponding internal software signals and external module signals. The matched software and external modules are automatically mapped and connected through signal lines.
[0077] The enable condition judgment module is used to match the communication signal with a preset fault information table to obtain an enable condition flag bit, and to perform bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0078] The fault information table corresponding to the enable condition judgment module includes tables generated according to the fault trigger enable condition and the fault recovery prerequisite condition, respectively. The fault trigger enable condition table also contains an enable flag bit used to trigger the fault.
[0079] It should be noted that in the technical solution of the automobile development project, corresponding fault information tables are generated in advance based on the fault triggering enable conditions and fault recovery prerequisite conditions. When a communication signal is received, the communication signal is matched with these fault information tables to obtain the enable condition flag bit and output it.
[0080] To further explain, after obtaining the enable condition flag, the enable condition flag can be bitwise operated on using calculation modules such as the ArithShift module and Bitwise Or module in simulation tools such as Simulink to obtain the enable signal. The enable signal obtained after bitwise operation can be set as a uint32 (32-bit unsigned integer) signal. If the length of the enable condition flag is greater than 32 bits, the excess part will be integrated into another uint32 signal so that each bit in the signal can represent an enable condition.
[0081] The fault collection and judgment module is used to perform bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and output it.
[0082] The fault information table corresponding to the fault collection and judgment module includes tables generated according to the fault triggering conditions and fault recovery conditions, respectively.
[0083] Specifically, a diagnostic calibration value is preset in the fault collection and judgment module. The calibration value can be in the format of uint32. If a uint32 enable signal is received from the enable condition judgment module, a bitwise AND operation is performed on the diagnostic calibration value and the enable signal so that the fault collection and judgment module and the enable condition judgment module can be mapped to each other and a fault signal containing the fault flag bit is obtained and output.
[0084] The fault handling measures module is used to receive the fault signal and find the corresponding fault handling measures according to the fault flag bit and the fault information table.
[0085] The fault information table corresponding to the fault handling measures module includes: a table generated based on the fault handling measures, which contains pre-set fault handling measures.
[0086] Specifically, the fault handling measures corresponding to the fault flag can be found in the fault handling measures table based on the fault flag carried by the fault signal.
[0087] It should be noted that since there may be a one-to-many correspondence between fault flags and fault handling measures, one or more corresponding fault handling measures can be selected based on the fault flags and the switch algorithm by setting up multi-branch selection algorithms such as switch or if.
[0088] The fault diagnosis output bus module is used to connect the fault diagnosis output bus module and the tested functional module through signal lines according to the communication signal and the signal mapping table, and output the fault flag bit and the fault handling measures.
[0089] It should be noted that the understanding of the fault diagnosis output module can refer to the above explanation of the fault diagnosis input module. The output module is similar to the input module, both of which are used to connect the internal modules of the software with the external modules of the software, so that the internal modules of the software and the external modules of the software can communicate and interact. The output module outputs the fault flag and fault handling measures to the outside.
[0090] In one embodiment, it further includes:
[0091] The fault level management module is used to receive the fault signal, look up the corresponding fault level according to the fault flag bit and the fault information table, filter the fault level numerically and output it.
[0092] The fault code management module is used to receive the fault signal, look up the corresponding fault code according to the fault flag bit and the fault information table, and output the fault code.
[0093] The fault diagnosis output bus module is also used to output the fault level and the fault code.
[0094] The fault information table corresponding to the fault level management module includes: a fault level table generated based on the fault level; the fault information table corresponding to the fault code management module includes: a fault code table generated based on the fault code; the fault code refers to the fault code reflected by the vehicle's computer ECU (Electronic Control Unit) after a fault occurs.
[0095] Specifically, after receiving a fault signal, the fault level management module searches for one or more fault levels corresponding to the fault flag bit of the fault signal according to the corresponding fault information table, performs numerical filtering on the fault level, and can output the fault level with the largest value.
[0096] After receiving a fault signal, the fault code management module searches for the fault code corresponding to the fault flag bit of the fault signal in the corresponding fault information table and outputs it.
[0097] The fault diagnosis output bus module will summarize and output the fault levels and fault codes obtained from the fault level management module and the fault code management module.
[0098] In the above fault diagnosis architecture, the overall fault diagnosis architecture is combined through the fault diagnosis input bus module, enable condition judgment module, fault collection judgment module, fault handling measures module and fault diagnosis output bus module, which improves the portability of the fault diagnosis architecture and reduces the coupling between the modules of the architecture.
[0099] The fault diagnosis architecture receives communication signals from the tested functional module transmitted on the bus. Based on the communication signals and a preset signal mapping table, it connects the fault diagnosis input bus module to the tested functional module via signal lines. It maps the communication signals to a preset fault information table to obtain an enable condition flag. It performs bitwise operations on the enable condition flag to obtain an enable signal containing the enable condition flag. Based on the fault information table, it performs bitwise operations on the communication signals and the enable signal to obtain a fault signal containing a fault flag and outputs it. It receives the fault signal and searches for corresponding fault handling measures based on the fault flag and the fault information table. It connects the fault diagnosis output bus module to the tested functional module via signal lines based on the communication signals and the signal mapping table, and outputs the fault flag and the fault handling measures to improve the efficiency of fault diagnosis.
[0100] It should be noted that each module in the above fault diagnosis architecture can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or they can be stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.
[0101] In one embodiment, such as Figure 2 As shown, a fault diagnosis method is provided, which is illustrated by applying the method to the fault diagnosis architecture in the above embodiments, including the following steps:
[0102] Step 201: The fault diagnosis input bus module receives the communication signal of the function module under test transmitted on the bus, and connects the function module under test with the signal line according to the communication signal and the preset signal mapping table.
[0103] Specifically, in the fault diagnosis input bus module, the communication signals of the tested functional module transmitted on the bus are mapped through a signal mapping table using a preset MATLAB script tool, so that the fault diagnosis input bus module and the tested functional module can be connected by signal lines.
[0104] For example, based on the technical solutions of one or more automotive development projects, corresponding fault information tables can be set up according to information such as fault triggering enable conditions, fault triggering conditions, fault recovery prerequisites, fault recovery conditions, fault levels, fault handling measures, and fault codes in the technical solutions. These fault information tables can be in Excel format to facilitate reading and processing using scripting tools such as MATLAB. It should be noted that the data in these fault information tables differs from that in the signal mapping tables.
[0105] The tested functional module can be considered as an external module of the fault diagnosis software, while the fault diagnosis input bus module is also connected to the internal modules of the software, so that the external modules and internal modules of the software can communicate and interact through the fault diagnosis input bus module.
[0106] In an alternative implementation, when mapping according to the signal mapping table, the interface signals of the software and the interface signals of the external modules of the software can be matched according to the signal mapping table. The signal mapping table includes pre-set corresponding internal software signals and external module signals. The matched software and external modules are automatically mapped and connected through signal lines.
[0107] Step 202: The enable condition judgment module matches the communication signal with a preset fault information table to obtain an enable condition flag bit, and performs bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0108] The fault information table corresponding to the enable condition judgment module includes tables generated according to the fault trigger enable condition and the fault recovery prerequisite condition, respectively. The fault trigger enable condition table also contains an enable flag bit used to trigger the fault.
[0109] It should be noted that in the technical solution of the automobile development project, corresponding fault information tables are generated in advance based on the fault triggering enable conditions and fault recovery prerequisite conditions. When a communication signal is received, the communication signal is matched with these fault information tables to obtain the enable condition flag bit and output it.
[0110] To further explain, after obtaining the enable condition flag, the enable condition flag can be bitwise operated on using calculation modules such as the ArithShift module and Bitwise Or module in simulation tools such as Simulink to obtain the enable signal. The enable signal obtained after bitwise operation can be set as a uint32 (32-bit unsigned integer) signal. If the length of the enable condition flag is greater than 32 bits, the excess part will be integrated into another uint32 signal so that each bit in the signal can represent an enable condition.
[0111] Step 203: The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it.
[0112] The fault information table corresponding to the fault collection and judgment module includes tables generated according to the fault triggering conditions and fault recovery conditions, respectively.
[0113] Specifically, a diagnostic calibration value is preset in the fault collection and judgment module. The calibration value can be in the format of uint32. If a uint32 enable signal is received from the enable condition judgment module, bit operations are performed on the diagnostic calibration value and the enable signal so that the fault collection and judgment module and the enable condition judgment module can map to each other and obtain a fault signal containing the fault flag bit and output it.
[0114] Step 204: After receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table.
[0115] The fault information table corresponding to the fault handling measures module includes: a table generated based on the fault handling measures, which contains pre-set fault handling measures.
[0116] Specifically, the fault handling measures corresponding to the fault flag can be found in the fault handling measures table based on the fault flag carried by the fault signal.
[0117] It should be noted that since there may be a one-to-many correspondence between fault flags and fault handling measures, one or more corresponding fault handling measures can be selected based on the fault flags and the switch algorithm by setting up multi-branch selection algorithms such as switch or if.
[0118] Step 205: The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag and the fault handling measures.
[0119] It should be noted that the understanding of the fault diagnosis output module can refer to the above explanation of the fault diagnosis input module. The output module is similar to the input module, both of which are used to connect the internal modules of the software with the external modules of the software, so that the internal modules of the software and the external modules of the software can communicate and interact. The output module outputs the fault flag and fault handling measures to the outside.
[0120] In one embodiment, after the fault collection and judgment module performs bitwise operations on the communication signal and the enable condition flag bit according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it, the method further includes:
[0121] After receiving the fault signal, the fault level management module searches for the fault level corresponding to the fault flag bit in the fault information table, performs numerical filtering on the fault level, and outputs it.
[0122] After receiving the fault signal, the fault code management module looks up the fault code corresponding to the fault flag bit in the fault information table and outputs the fault code.
[0123] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag, the fault handling measures, the fault level, and the fault code.
[0124] The fault information table corresponding to the fault level management module includes: a fault level table generated based on the fault level; the fault information table corresponding to the fault code management module includes: a fault code table generated based on the fault code; the fault code refers to the fault code reflected by the vehicle's computer ECU (Electronic Control Unit) after a vehicle malfunctions.
[0125] Specifically, after the fault level management module receives a fault signal, it searches for one or more fault levels corresponding to the fault flag bit of the fault signal according to the corresponding fault information table, performs numerical filtering on the fault level, and can output the fault level with the largest value.
[0126] After receiving a fault signal, the fault code management module searches for the fault code corresponding to the fault flag bit of the fault signal in the corresponding fault information table and outputs it.
[0127] The fault diagnosis output bus module summarizes and outputs the obtained fault levels and fault codes.
[0128] In one embodiment, bitwise operations are performed on the enable condition flag to obtain an enable signal containing the enable condition flag, including:
[0129] The enable condition flag is shifted bit by bit, and the shifted enable condition flags are combined by an OR operation to obtain an enable signal containing the enable condition flags, wherein the enable condition flags correspond to preset diagnostic enable conditions.
[0130] For example, after obtaining the enable condition flag, the enable condition flag can be shifted using calculation modules such as the ArithShift module and Bitwise Or module in simulation tools such as Simulink. Then, the enable flag can be integrated to obtain the enable signal through bitwise OR operation based on Bitwise Or. The enable signal obtained after bitwise operation can be set to a uint32 (32-bit unsigned integer) format signal. If the length of the enable condition flag is greater than 32 bits, the excess part will be integrated into another uint32 signal so that each bit in the signal can represent an enable condition.
[0131] In one embodiment, the fault collection and judgment module performs bitwise operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing a fault flag bit and outputs it, including:
[0132] The preset diagnostic calibration value and the enable signal in the fault collection and judgment module are integrated by AND operation so that the diagnostic enable condition is mapped in the fault collection and judgment module.
[0133] Specifically, a diagnostic calibration value is pre-set in the fault collection and judgment module. The calibration value can be in the format of uint32. If a uint32 enable signal is received from the enable condition judgment module, a bitwise AND operation is performed on the diagnostic calibration value and the enable signal so that the fault collection and judgment module and the enable condition judgment module can be mapped to each other and a fault signal containing the fault flag bit is obtained and output.
[0134] In one embodiment, before integrating the preset diagnostic calibration value in the fault collection and judgment module and the enable signal through computation, the method further includes:
[0135] If the fault collection and judgment module receives a first fault trigger signal containing the enable signal, and does not receive a subsequent second fault trigger signal after a preset waiting time, then it confirms that the diagnostic enable condition corresponding to the enable signal in the first fault trigger signal is met.
[0136] Among them, the fault trigger signals include, but are not limited to, enable signals, message communication signals when diagnosing the module under test, hard-wired signals, etc. The "first" and "second" here are only explained in terms of timing.
[0137] For example, a delay can be made on the fault triggering condition using a method such as debounce. A preset period is used to delay the execution of the fault triggering action. If the fault is triggered again within the preset period, the period is recalculated until the period ends, and then the action is executed. This is to prevent the fault triggering frequency from being too fast, which would result in a large number of requests being sent and the response speed being significantly slower than the triggering, thus affecting the efficiency of fault diagnosis.
[0138] Specifically, when the first fault trigger signal is received, the timer starts counting. If no subsequent second fault trigger signal is received within the preset waiting time, the fault can be considered valid. The fault collection and judgment module collects the corresponding faults through the diagnostic enable conditions corresponding to the enable signal.
[0139] To further explain, after receiving the fault trigger signal, the enable signal in the fault trigger signal and other signals (such as message communication signals, hard-wired signals, etc.) can be logically ANDed. When it is determined that the enable signal and other signals meet the preset judgment conditions, the fault trigger signal is then delayed.
[0140] In one embodiment, after receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table, including:
[0141] According to the fault information table, the fault flag bit is matched with the preset handling measure calibration value in the fault handling measure module;
[0142] The matched fault flag bit is ORed with the calibrated value of the handling measure to obtain a set of handling measures variables;
[0143] Perform a bitwise AND operation between the set of processing measures and the calibrated value of the processing measures to obtain the fault processing measure flag bit, then shift the fault processing measure flag bit and output it.
[0144] Among them, the fault information table corresponding to the fault handling measures module includes: a table generated based on the fault handling measures. The fault handling measures table contains pre-set handling measure values and fault handling measures, and the handling measure values and fault handling measures correspond to each other.
[0145] It should be noted that the processing measure specification can also be data in uint32 format, where each bit in the uint32 processing measure specification can represent a fault handling measure.
[0146] To further explain, since there may be a one-to-many correspondence between fault flags and fault handling measures, multiple branch selection algorithms such as switch or if can be set to select one or more corresponding handling measures and fault handling measures based on the fault flags and the switch algorithm.
[0147] For example, based on the fault flag bit carried by the fault signal, the switch algorithm can be used to query one or more processing measure calibration values and fault processing measures that match the fault flag bit in the fault processing measure table;
[0148] A bitwise OR operation is performed between the matched fault flag bits and the calibrated value of the processing measures to obtain all fault processing measures corresponding to all fault flag bits, which are represented as a set of processing measures in uint32 format.
[0149] Then, perform a bitwise AND operation based on the set of processing measures variables and the calibrated quantity of processing measures to output the fault processing measure flag bit of each fault processing measure. The fault processing measure flag bit is shifted to the lowest bit through the ArithShift module and output as a boolean fault processing measure flag bit.
[0150] In the above fault diagnosis method, the communication signal of the functional module under test transmitted on the bus is received through the fault diagnosis architecture. Based on the communication signal and a preset signal mapping table, the fault diagnosis input bus module is connected to the functional module under test via signal lines. The communication signal is mapped to a preset fault information table to obtain an enable condition flag. The enable condition flag is then bitwise operated to obtain an enable signal containing the enable condition flag. Based on the fault information table, the communication signal and the enable signal are bitwise operated to obtain a fault signal containing a fault flag, which is then output. The fault signal is received, and the corresponding fault handling measures are found based on the fault flag and the fault information table. The fault diagnosis output bus module is connected to the functional module under test via signal lines based on the communication signal and the signal mapping table, and the fault flag and the fault handling measures are output, thereby improving the diagnostic efficiency of the fault diagnosis.
[0151] It should be noted that the fault diagnosis method provided in this application is applied to the fault diagnosis architecture provided in this application. For a detailed explanation of the fault diagnosis method, please refer to the aforementioned explanation of the fault diagnosis architecture; further details will not be repeated here. The various modules mentioned in the fault diagnosis method can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0152] It should be understood that although the steps in the flowchart above are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowchart above may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0153] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 3 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores fault diagnosis-related data. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a fault diagnosis architecture and / or fault diagnosis method.
[0154] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0155] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following architecture when executing the computer program:
[0156] The fault diagnosis input bus module is used to receive communication signals from the function module under test transmitted on the bus, and to connect the fault diagnosis input bus module and the function module under test with signal lines according to the communication signals and a preset signal mapping table.
[0157] The enable condition judgment module is used to match the communication signal with a preset fault information table to obtain an enable condition flag bit, and to perform bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0158] The fault collection and judgment module is used to perform bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and output it.
[0159] The fault handling measures module is used to receive the fault signal and look up the corresponding fault handling measures according to the fault flag bit and the fault information table;
[0160] The fault diagnosis output bus module is used to connect the fault diagnosis output bus module and the tested functional module through signal lines according to the communication signal and the signal mapping table, and output the fault flag bit and the fault handling measures.
[0161] In one embodiment, the processor also implements the following architecture when executing a computer program:
[0162] The fault level management module is used to receive the fault signal, look up the corresponding fault level according to the fault flag bit and the fault information table, filter the fault level numerically and output it.
[0163] The fault code management module is used to receive the fault signal, look up the corresponding fault code according to the fault flag bit and the fault information table, and output the fault code.
[0164] The fault diagnosis output bus module is also used to output the fault level and the fault code.
[0165] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:
[0166] The fault diagnosis input bus module receives the communication signals transmitted on the bus from the functional module under test, and connects the functional module under test with the signal lines according to the communication signals and the preset signal mapping table.
[0167] The enable condition judgment module matches the communication signal with a preset fault information table to obtain an enable condition flag bit, and performs bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0168] The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it.
[0169] After receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table;
[0170] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag and the fault handling measures.
[0171] In one embodiment, the processor, when executing a computer program, also performs the following steps:
[0172] After receiving the fault signal, the fault level management module searches for the fault level corresponding to the fault flag bit in the fault information table, performs numerical filtering on the fault level, and outputs it.
[0173] After receiving the fault signal, the fault code management module looks up the fault code corresponding to the fault flag bit in the fault information table and outputs the fault code.
[0174] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag, the fault handling measures, the fault level, and the fault code.
[0175] In one embodiment, the processor, when executing a computer program, also performs the following steps:
[0176] The enable condition flag is shifted bit by bit, and the shifted enable condition flags are combined by an OR operation to obtain an enable signal containing the enable condition flags, wherein the enable condition flags correspond to preset diagnostic enable conditions.
[0177] In one embodiment, the processor, when executing a computer program, also performs the following steps:
[0178] The preset diagnostic calibration value and the enable signal in the fault collection and judgment module are integrated by AND operation so that the diagnostic enable condition is mapped in the fault collection and judgment module.
[0179] In one embodiment, the processor, when executing a computer program, also performs the following steps:
[0180] If the fault collection and judgment module receives a first fault trigger signal containing the enable signal, and does not receive a subsequent second fault trigger signal after a preset waiting time, then it confirms that the diagnostic enable condition corresponding to the enable signal in the first fault trigger signal is met.
[0181] In one embodiment, the processor, when executing a computer program, also performs the following steps:
[0182] According to the fault information table, the fault flag bit is matched with the preset handling measure calibration value in the fault handling measure module;
[0183] The matched fault flag bit is ORed with the calibrated value of the handling measure to obtain a set of handling measures variables;
[0184] Perform a bitwise AND operation between the set of processing measures and the calibrated value of the processing measures to obtain the fault processing measure flag bit, then shift the fault processing measure flag bit and output it.
[0185] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program implementing the following architecture when executed by a processor:
[0186] The fault diagnosis input bus module is used to receive communication signals from the function module under test transmitted on the bus, and to connect the fault diagnosis input bus module and the function module under test with signal lines according to the communication signals and a preset signal mapping table.
[0187] The enable condition judgment module is used to match the communication signal with a preset fault information table to obtain an enable condition flag bit, and to perform bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0188] The fault collection and judgment module is used to perform bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and output it.
[0189] The fault handling measures module is used to receive the fault signal and look up the corresponding fault handling measures according to the fault flag bit and the fault information table;
[0190] The fault diagnosis output bus module is used to connect the fault diagnosis output bus module and the tested functional module through signal lines according to the communication signal and the signal mapping table, and output the fault flag bit and the fault handling measures.
[0191] In one embodiment, the computer program, when executed by a processor, also implements the following architecture:
[0192] The fault level management module is used to receive the fault signal, look up the corresponding fault level according to the fault flag bit and the fault information table, filter the fault level numerically and output it.
[0193] The fault code management module is used to receive the fault signal, look up the corresponding fault code according to the fault flag bit and the fault information table, and output the fault code.
[0194] The fault diagnosis output bus module is also used to output the fault level and the fault code.
[0195] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:
[0196] The fault diagnosis input bus module receives the communication signals transmitted on the bus from the functional module under test, and connects the functional module under test with the signal lines according to the communication signals and the preset signal mapping table.
[0197] The enable condition judgment module matches the communication signal with a preset fault information table to obtain an enable condition flag bit, and performs bit operations on the enable condition flag bit to obtain an enable signal containing the enable condition flag bit.
[0198] The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it.
[0199] After receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table;
[0200] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag and the fault handling measures.
[0201] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:
[0202] After receiving the fault signal, the fault level management module searches for the fault level corresponding to the fault flag bit in the fault information table, performs numerical filtering on the fault level, and outputs it.
[0203] After receiving the fault signal, the fault code management module looks up the fault code corresponding to the fault flag bit in the fault information table and outputs the fault code.
[0204] The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag, the fault handling measures, the fault level, and the fault code.
[0205] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:
[0206] The enable condition flag is shifted bit by bit, and the shifted enable condition flags are combined by an OR operation to obtain an enable signal containing the enable condition flags, wherein the enable condition flags correspond to preset diagnostic enable conditions.
[0207] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:
[0208] The preset diagnostic calibration value and the enable signal in the fault collection and judgment module are integrated by AND operation so that the diagnostic enable condition is mapped in the fault collection and judgment module.
[0209] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:
[0210] If the fault collection and judgment module receives a first fault trigger signal containing the enable signal, and does not receive a subsequent second fault trigger signal after a preset waiting time, then it confirms that the diagnostic enable condition corresponding to the enable signal in the first fault trigger signal is met.
[0211] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:
[0212] According to the fault information table, the fault flag bit is matched with the preset handling measure calibration value in the fault handling measure module;
[0213] The matched fault flag bit is ORed with the calibrated value of the handling measure to obtain a set of handling measures variables;
[0214] Perform a bitwise AND operation between the set of processing measures and the calibrated value of the processing measures to obtain the fault processing measure flag bit, then shift the fault processing measure flag bit and output it.
[0215] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0216] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0217] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A fault diagnosis architecture, characterized in that, include: The fault diagnosis input bus module is used to receive communication signals from the function module under test transmitted on the bus, and to connect the fault diagnosis input bus module and the function module under test with signal lines according to the communication signals and a preset signal mapping table. The enable condition judgment module is used to match the communication signal with a preset fault information table to obtain multiple enable condition flag bits, and to perform bit operations on the multiple enable condition flag bits to obtain an enable signal containing the multiple enable condition flag bits. The step of performing bitwise operations on multiple enable condition flags to obtain an enable signal containing multiple enable condition flags includes: Each of the enable condition flag bits is shifted sequentially by bits, and the shifted enable condition flag bits are combined by an OR operation to obtain an enable signal containing multiple enable condition flag bits. The fault collection and judgment module is used to perform bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and output it. The fault handling measures module is used to receive the fault signal and look up the corresponding fault handling measures according to the fault flag bit and the fault information table; The step of finding the corresponding fault handling measures based on the fault flag and the fault information table includes: According to the fault information table, the fault flag bit is matched with the preset handling measure calibration value in the fault handling measure module; The matched fault flag bit is ORed with the processing measure calibration value to obtain a set of processing measures variables containing the processing measure calibration value; Perform a bitwise AND operation between the set of processing measures and the calibrated quantity of the processing measures to obtain the fault processing measure flag bit, then shift the fault processing measure flag bit and output it; The fault diagnosis output bus module is used to connect the fault diagnosis output bus module and the tested functional module through signal lines according to the communication signal and the signal mapping table, and output the fault flag bit and the fault handling measures.
2. The fault diagnosis architecture according to claim 1, characterized in that, Also includes: The fault level management module is used to receive the fault signal, look up the corresponding fault level according to the fault flag bit and the fault information table, filter the fault level numerically and output it. The fault code management module is used to receive the fault signal, look up the corresponding fault code according to the fault flag bit and the fault information table, and output the fault code. The fault diagnosis output bus module is also used to output the fault level and the fault code.
3. A fault diagnosis method, characterized in that, The method is applied to any fault diagnosis architecture of claim 1 or 2, and the method includes: The fault diagnosis input bus module receives the communication signals transmitted on the bus from the functional module under test, and connects the functional module under test with the signal lines according to the communication signals and the preset signal mapping table. The enable condition judgment module matches the communication signal with a preset fault information table to obtain multiple enable condition flag bits, and performs bit operations on the multiple enable condition flag bits to obtain an enable signal containing the multiple enable condition flag bits. The step of performing bitwise operations on multiple enable condition flags to obtain an enable signal containing multiple enable condition flags includes: Each of the enable condition flag bits is shifted sequentially by bits, and the shifted enable condition flag bits are combined by an OR operation to obtain an enable signal containing multiple enable condition flag bits. The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it. After receiving the fault signal, the fault handling measures module searches for the fault handling measures corresponding to the fault flag bit according to the fault information table; The step of finding the corresponding fault handling measures based on the fault flag and the fault information table includes: According to the fault information table, the fault flag bit is matched with the preset handling measure calibration value in the fault handling measure module; The matched fault flag bit is ORed with the processing measure calibration value to obtain a set of processing measures variables containing the processing measure calibration value; Perform a bitwise AND operation between the set of processing measures and the calibrated quantity of the processing measures to obtain the fault processing measure flag bit corresponding to the fault processing measure. Then, shift the fault processing measure flag bit and output it. The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag and the fault handling measures.
4. The fault diagnosis method according to claim 3, characterized in that, After the fault collection and judgment module performs bitwise operations on the communication signal and the enable condition flag bit according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it, the module further includes: After receiving the fault signal, the fault level management module searches for the fault level corresponding to the fault flag bit in the fault information table, performs numerical filtering on the fault level, and outputs it. After receiving the fault signal, the fault code management module looks up the fault code corresponding to the fault flag bit in the fault information table and outputs the fault code. The fault diagnosis output bus module connects to the tested functional module via signal lines according to the communication signal and the signal mapping table, and outputs the fault flag, the fault handling measures, the fault level, and the fault code.
5. The fault diagnosis method according to claim 3, characterized in that, The fault collection and judgment module performs bit operations on the communication signal and the enable signal according to the fault information table to obtain a fault signal containing the fault flag bit and outputs it, including: The preset diagnostic calibration value and the enable signal in the fault collection and judgment module are integrated by AND operation so that the diagnostic enable condition is mapped in the fault collection and judgment module.
6. The fault diagnosis method according to claim 5, characterized in that, Before integrating the preset diagnostic calibration value and the enable signal in the fault collection and judgment module through computation, the method further includes: If the fault collection and judgment module receives a first fault trigger signal containing the enable signal, and does not receive a subsequent second fault trigger signal after a preset waiting time, then it confirms that the diagnostic enable condition corresponding to the enable signal in the first fault trigger signal is met.
7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the fault diagnosis method according to any one of claims 3 to 6.
8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the fault diagnosis method according to any one of claims 3 to 6.