An HDL-based register file single event upset injection test system and method

Abstract

The application provides an HDL-based register file single particle fault injection test system and method. The method increases a fault injection control module at an RTL level, simultaneously modifies a register file read-write port, and further increases a write port and a read port outside the normal read-write port. The read-write port is used for fault injection, and different types of single particle faults (SEU and MBU) can be injected into different positions (precise to bits) of the register file in different ways (randomly or with a certain probability). The method can obtain the effectiveness of the fault tolerance method before fault tolerance design by combining a VCS simulation tool. The fault rate change before and after fault tolerance design can be obtained through fault injection and program running result statistics, so as to determine whether the current fault tolerance algorithm is effective and provide a basis for fault tolerance method improvement.

Description

Technical Field

[0001] This invention relates to a register file single-event fault injection testing system and method based on HDL, belonging to the field of single-event effect testing technology. Background Technology

[0002] As the performance, integration, and complexity of space application processors continue to increase, the impact of single-event effects on their reliability becomes increasingly apparent. Furthermore, with the rapid development of semiconductor technology, processor clock speeds and integration levels are constantly increasing, while supply voltages are continuously decreasing, making space application processors more susceptible to high-energy particle effects. The register file, as a crucial memory between the processor pipeline and cache, is the part of the processor physically closest to the pipeline and the highest level of the processor's memory hierarchy; single-event effects there will severely impact processor functionality. As a temporary data storage node between the pipeline and cache, the register file stores data and is repeatedly accessed. Therefore, soft errors occurring in the register file can easily propagate to other parts of the processor, causing program execution failures. Register file fault-tolerant design is a vital means of improving the reliability of space application processors.

[0003] Many researchers have focused on fault-tolerant design for register files, and a comprehensive fault injection method is a crucial element in ensuring the effectiveness of such designs. Single-event fault injection methods for register files can be categorized into several types, including hardware fault injection methods, software fault injection methods, simulation fault injection methods, hybrid fault injection methods, and circuit simulation fault injection methods.

[0004] There are many fault-tolerance methods for single-event faults (SIFs) in register files, each with its own advantages and disadvantages, resulting in varying degrees of reliability improvement. The effectiveness of different register file SIF fault-tolerance methods needs to be compared in a consistent and easily implementable engineering environment. Currently, there are many methods for fault injection and result comparison, but each has its own drawbacks.

[0005] (1) Some fault injection methods only implement single-particle fault injection, and do not check and compare the operating status of the system after fault injection.

[0006] (2) Some fault injection methods cannot accurately control the type of single-particle fault injected, nor can they accurately control the location of single-particle fault injection.

[0007] (3) The single-particle fault injection method based on actual particles is closer to the actual space environment, and the fault effect is more realistic. However, this method is highly dependent on equipment, requires the assistance of specialized parts, and has a large cost. On the other hand, the fault injection of this method is highly random, and it cannot accurately inject the required fault type or inject the fault at the accurate location, so it is not suitable for verifying the fault tolerance method of the research process;

[0008] (4) Circuit-level single-event fault injection method: This method simulates single-event fault injection by changing the level of the register file circuit, and the fault type and location can be controlled. However, this method needs to be implemented at the circuit level, and the effectiveness of the fault-tolerant method cannot be determined in the RTL design stage. For a suboptimal fault-tolerant design, the cost of redesign is high. Summary of the Invention

[0009] The technical problem solved by this invention is to overcome the shortcomings of existing register file fault injection methods and provide a register file single-event fault injection test system and method based on HDL, thereby solving the problem of verifying the effectiveness of single-event fault tolerance methods for space application processor register files.

[0010] The technical solution of this invention is: a register file single-event fault injection testing system based on HDL, wherein the register file is a register stack composed of several registers, used to store intermediate variables during processor program execution. The register file is accessed concurrently through M read ports and N write ports. The system includes a fault injection read port, a fault injection write port, a read-write arbitration logic module, a fault injection control module, and a fault detection and statistics module. The fault injection read port and fault injection write port are part of the register file interface and have the same function as the register file read and write ports, and can access any register in the register file, where M and N are greater than or equal to 1.

[0011] The fault injection control module reads back the data of the register to be injected with faults through the fault injection read port according to the fault injection control parameters. Then, according to the fault type, the read data is flipped to obtain the fault data. The fault data is then written to the register to be injected with faults through the fault injection write port, and the number of fault injections and the proportion of fault types are recorded in real time.

[0012] The read / write arbitration logic module controls external read and write access to the register file. When a read instruction occurs, it determines whether any two read instructions accessing the same register within the same cycle are accessing the same register. If not, data is fetched in parallel and passed to the corresponding read port. If multiple ports access the same register, the register data at that address is fetched and allocated to each read port in parallel. When a write instruction occurs, it determines whether any two write instructions accessing the same register within the same cycle are accessing the same register. If not, data is written to the corresponding register in parallel. If multiple ports access the same register, access is based on a pre-defined priority, with higher-priority ports having priority access within the same cycle, and data from lower-priority ports being discarded. The write port used for fault injection has the lowest access priority among the N+1 write ports in the register file.

[0013] The fault detection and statistics module is used to statistically analyze the processor's operating results after different fault injections. It detects whether the program running on the processor malfunctions after a single-particle fault is injected, the type of fault, and the number of times the fault occurs. Based on the type of injected fault and the total number of injected faults, the fault rate is calculated.

[0014] Preferably, the injection control parameters include: total number of fault injections, fault type, fault ratio, fault injection method, address of the fault injection target register, flag indicating whether the toggle bit is random, and the toggle bit; the fault type includes SEU, MBU, and SEU+MBU; when the fault type is SEU or MBU, the fault ratio and fault injection method are invalid; when the fault type is SEU+MBU, the fault injection method includes random selection or proportional injection; when the fault injection method is random selection, the fault ratio is invalid; when the fault injection method is proportional injection, the fault ratio is SEU fault to be injected: MBU fault to be injected.

[0015] Preferably, the processing flow of the fault injection control module is as follows:

[0016] S1. Obtain the total number of fault injections, Sum, and proceed to step S2;

[0017] S2. Determine the type of fault to be injected. When the fault type is SEU, proceed to step S3. When the fault type is MBU, proceed to step S4. When the fault type is SEU+MBU, proceed to step S5.

[0018] S3. Inject SEU fault, inject once, inject SEU fault a total of N times. SEU Add 1, update the number of SEU injection failures N. SEU When N SEU When Sum equals N, the fault injection ends; SEU injects faults N times.SEU initialized to 0;

[0019] S4: Inject an MBU fault once, and set the MBU fault injection count N MBU increment by 1, and update the MBU fault injection count N MBU , when N MBU = Sum, the fault injection ends; the MBU fault injection count N MBU is initialized to 0;

[0020] S5: Determine whether the fault injection mode is random selection or proportional injection; perform step S5-1 for random selection, and perform step S5-2 for proportional injection;

[0021] S5-1: Randomly select to inject an SEU fault or an MBU fault; after each fault injection is completed, increment the injected random selection fault count S by 1, update the injected random selection fault count S, and when S = Sum, the fault injection ends; the injected random selection fault count S is initialized to 0;

[0022] S5-2: Obtain the fault proportion, and calculate the number of SEU faults X to be injected and the number of MBU faults Y to be injected according to the total fault injection times Sum; when X'+Y'<Sum, X'<X and Y'<Y, randomly generate an SEU or MBU fault to inject into the register file; after a single SEU injection is completed, increment the injected SEU fault count X' by 1, and update the injected SEU fault count X'; after a single MBU injection is completed, increment the MBU fault count Y' by 1, and update the injected MBU fault count Y'; when X'=X and Y'<Y, only MBU faults are injected, and after a single completion, increment the MBU fault count Y' by 1, and update the injected MBU fault count Y'; when Y'=Y and X'<X, only SEU faults are injected, and after a single completion, increment the injected SEU fault count X' by 1, and update the injected SEU fault count X'; when X'+Y'=Sum, the fault injection is completed; the injected SEU fault count X' is initialized to 0, and the injected MBU fault count Y' is initialized to 0.

[0023] Preferably, the process of injecting an SEU fault is:

[0024] Read the original data in the register according to the physical address of the register into which the fault needs to be injected;

[0025] Judge the flag indicating whether the flip bit is random; if it is random, randomly generate a flip bit, otherwise obtain the externally specified flip bit;

[0026] Flip the data of the flip bit, then write the rewritten register data back to the original register, so as to complete one SEU fault injection.

[0027] Preferably, the process of injecting an MBU fault is as follows:

[0028] As needed, inject the address of the target register for the fault and read the original data from the register.

[0029] A flag indicating whether the flip bits are random; if random, generate multiple flip bits randomly; otherwise, retrieve multiple flip bits specified externally.

[0030] After determining the data bits that need to be flipped, flip the data of these flipped bits one by one, and then write the rewritten data back to the original register, thus completing an MBU fault injection.

[0031] Preferably, the flipping refers to changing a data bit from 0 to 1 or from 1 to 0.

[0032] Another technical solution of the present invention is: a register file single-event fault injection test method based on HDL, the method comprising the following steps:

[0033] S1. Obtain fault injection control parameters, including: total number of fault injections, fault type, fault ratio, and fault injection method. The fault type includes SEU, MBU, and SEU+MBU. When the fault type is SEU or MBU, the fault ratio and fault injection method are invalid. When the fault type is SEU+MBU, the fault injection method includes random selection or proportional injection. When the fault injection method is random selection, the fault ratio is invalid. When the fault injection method is proportional injection, the fault ratio is SEU faults to be injected: MBU faults to be injected. Proceed to step S2.

[0034] S2. Determine the type of fault to be injected. When the fault type is SEU, proceed to step S3. When the fault type is MBU, proceed to step S4. When the fault type is SEU+MBU, proceed to step S5.

[0035] S3. Inject SEU fault, inject once, inject SEU fault a total of N times. SEU Add 1, update the number of SEU injection failures N. SEU When N SEU When Sum equals Sum, the fault injection ends, and proceed to step S6; the number of fault injections N by SEU is... SEU Initialize to 0;

[0036] S4. Inject MBU faults, inject once, and inject MBU faults N times. MBU Add 1, update the number of MBU injection failures N. MBU When N MBU When the value equals Sum, the fault injection ends, and the process proceeds to step S6; the number of fault injection attempts N in the MBU is... MBUinitialized to 0;

[0037] S5. First, it is determined whether the fault injection mode is random selection or proportional injection. If it is random selection, step S5-1 is executed; if it is proportional injection, step S5-2 is executed;

[0038] S5-1. An SEU fault or an MBU fault is randomly selected for injection. After each fault injection is completed, the number S of randomly selected injected faults is incremented by 1 to update S. When S=Sum, the fault injection ends, and the process proceeds to step S6; the number S of randomly selected injected faults is initialized to 0;

[0039] S5-2. A fault proportion is acquired, and according to the total number Sum of fault injections, the number X of SEU faults to be injected and the number Y of MBU faults to be injected are calculated. When X'+Y'<Sum, X'<X and Y'<Y, an SEU or MBU fault is randomly generated and injected into the register file. After a single SEU injection is completed, the number X' of injected SEU faults is incremented by 1 to update X'; after a single MBU injection is completed, the number Y' of injected MBU faults is incremented by 1 to update Y'. When X'=X and Y'<Y, only MBU faults are injected, and after each single injection is completed, the number Y' of MBU faults is incremented by 1 to update Y'. When Y'=Y and X'<X, only SEU faults are injected, and after each single injection is completed, the number X' of injected SEU faults is incremented by 1 to update X'. When X'+Y'=Sum, the fault injection ends, and the process proceeds to step S6; the number X' of injected SEU faults is initialized to 0, and the number Y' of injected MBU faults is initialized to 0;

[0040] S6. After the single-event fault is injected, it is detected whether the program running on the processor has a fault, the type of the fault that occurs, and the number of times the fault occurs, and then the fault rate is counted according to the injected fault type and the total number of injected faults.

[0041] Preferably, the fault injection control parameters further include: an address of a fault injection target register, a flag indicating whether the flip bit is random, and the flip bit. When the flag indicating whether the flip bit is random indicates randomness, the flip bit is invalid; otherwise, the flip bit is valid.

[0042] Preferably, the process of injecting an SEU fault is as follows:

[0043] The original data in the register is read according to the physical address of the register into which the fault needs to be injected.

[0044] The flag indicating whether the flip bit is random is determined. If it is random, a flip bit is randomly generated; otherwise, an externally specified flip bit is acquired.

[0045] By flipping the data in the flip bit and then writing the rewritten register data back to the original register, a SEU fault injection is completed.

[0046] Preferably, the process of injecting an MBU fault is as follows:

[0047] As needed, inject the address of the target register for the fault and read the original data from the register.

[0048] A flag indicating whether the flip bits are random; if random, generate multiple flip bits randomly; otherwise, retrieve multiple flip bits specified externally.

[0049] After determining the data bits that need to be flipped, flip the data of these flipped bits one by one, and then write the rewritten data back to the original register, thus completing an MBU fault injection.

[0050] The present invention has the following advantages over the prior art:

[0051] (1) This invention can simulate SEU and MBU types of single-event faults. The number of faults injected, fault type, fault ratio, injection address, and flip bit can all be flexibly selected during the injection process. This invention is suitable for verifying the effectiveness of fault-tolerant methods for register files and improving processor reliability.

[0052] (2) This invention modifies the register file module at the RTL level, adding a pair of fault injection read / write interfaces and a read / write bus corresponding to the fault injection read / write ports, and modifying the arbitration logic of the register file read / write ports. Fault injection will not affect the normal operation of processing.

[0053] (3) This invention belongs to the simulation-level single-event fault injection method, which can determine the effectiveness of the register file single-event fault tolerance method in the early stage of design (RTL level) and provide a basis for improving the fault tolerance design as early as possible.

[0054] (4) This invention injects single-event faults into register files by only requiring the addition of a "fault injection control statistics module" and a "fault injection module" in HDL language at the RTL layer, with minor modifications to the register file and the top-level test file. This method is simple and easy to implement in engineering.

[0055] (5) By adding a fault injection control unit at the RTL level and modifying the register file read / write port, this invention can inject different types of single-event faults (SEU and MBU) into different locations (accurate to bits) of the register file in different ways (random or with a certain probability).

[0056] (6) The present invention, combined with the VCS simulation tool, can obtain the effectiveness of the fault tolerance method in the early stage of fault tolerance design, and provide a basis for the improvement of the fault tolerance method.

[0057] (7) This invention adopts the RTL-level simulation stage to perform single-event fault injection and fault result analysis and comparison. It can evaluate the effectiveness of the register file single-event fault tolerance method in the RTL-level design stage and propose targeted directions for improving the fault tolerance method. Attached Figure Description

[0058] Figure 1 This is an embodiment of the register file architecture for reading from M and writing to N in this invention.

[0059] Figure 2 The modified M-read N-write register file architecture for adding fault injection capability to embodiments of the present invention;

[0060] Figure 3 This is a system block diagram based on the overall design concept of this invention.

[0061] Figure 4 This is a schematic diagram illustrating the overall design concept of an embodiment of the present invention.

[0062] Figure 5 This is a flowchart illustrating the fault injection process in an embodiment of the present invention.

[0063] Figure 6 This is an embodiment of the SEU and MBU injection method of the present invention;

[0064] Figure 7 This provides the interface between the fault injection control module, the fault detection and statistics module, and the top-level test module in this embodiment of the invention. Detailed Implementation

[0065] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0066] like Figure 1 and Figure 2 As shown, the main design idea of ​​the HDL-based register file single-event fault injection method provided by this invention is as follows:

[0067] (1) At the RTL level, within the processor HDL code, analyze the register HDL code of the corresponding register file of the processor, analyze the register file architecture, determine the architecture of the read / write ports, read / write buses, and read / write bus arbitration logic, and modify the read / write port, read / write bus, and arbitration logic code of the corresponding register file of the processor. The key to the modification is:

[0068] a. Add one register file read port and one register file write port;

[0069] b. Add one read bus and one write bus;

[0070] c. Modify the register file read / write arbitration logic, merging the gating logic for the added read / write ports and read / write bus with the original gating logic for multiple read / write ports. This ensures that the added read / write ports and bus access to registers do not conflict with the original read / write port accesses; that is, the fault injection interface does not conflict with other read / write interfaces.

[0071] (2) A fault injection control module for single-event fault injection was designed. The fault injection control module uses a read-modify-write approach to inject faults. It reads back the data from the register to which the fault needs to be injected, and then writes the data after flipping the "0"s and "1"s back to the address as needed. When no external fault control parameters are required, the fault injection control module needs to implement a random function to achieve random fault mode (SEU or MBU), random address of the fault injection target register, and random flip bits. The fault injection control module also needs to implement a counting and statistics function to ensure that the total number of injected faults and the proportion of each type of fault are controllable. When external fault control parameters are required, the interface between the fault injection control module and the fault control parameters existing in the top-level test layer includes: fault type selection, number of injected faults, fault ratio, address of the fault injection target register, and flip bits (if a random method is used, there is no need to control the fault ratio, address of the fault target register, and flip bits).

[0072] Therefore, the key to the fault injection control module lies in:

[0073] a. A logical interface with the fault injection read / write port is designed, allowing read and write access to any location in the register file through the fault injection read / write port. The fault injection control module has an interface with the register file fault injection read / write port, corresponding to the added register file fault injection port; the module includes read / modify / write logic, enabling the toggling of specified units and multiple bits of data in the register. The fault injection control module can accept external control information and can perform random testing.

[0074] b. An interface was designed between the fault injection control logic module and the top-level test module. This interface is responsible for receiving external (human) control information. This mainly includes:

[0075] 1) Specify the number of fault injections and the fault ratio;

[0076] 2) Specify the type of injection fault (SEU or MBU);

[0077] 3) Specify the location (address and flip bit) of the single-event fault.

[0078] c. An algorithm flow for fault injection control was designed.

[0079] (3) A fault detection and statistics module was designed.

[0080] The fault detection and statistics module and the test top-level module are designed with an interface. On the one hand, the processor operation results after each fault injection are obtained from the test top-level module. On the other hand, the fault statistical analysis results can be passed to the top-level module as the data basis for further analysis. Combined with the general simulation tool VCS, the impact mechanism of different types of faults on the processor register file can be analyzed, providing a theoretical basis for improving the efficiency of fault tolerance methods.

[0081] The main function of the fault detection and statistics module is to statistically analyze the processor's operating results after different fault injections, analyze the impact of different fault types on the processor register file, obtain the fault rate of different types of faults in the processor, and confirm the fault tolerance effect of different fault tolerance methods on a certain fault type.

[0082] After injecting a fault, the fault detection and statistics module determines the impact of the fault injection on the processor register file based on the processor output. This allows it to assess whether the corresponding fault tolerance method can effectively prevent single-event faults from affecting processor operation. During large-scale injections, statistical analysis can be performed to determine the impact of different fault types and locations on the processor registers. It can also determine the reliability improvement effect of different fault tolerance methods on register files experiencing different fault types.

[0083] (iv) Modify the top-level test file

[0084] The purpose of testing the top-level file is to input necessary peripheral signals and information required for processor program execution to the processor. This invention requires some modifications based on this. On one hand, after fault injection, the top-level file needs to be used to compare and monitor key program execution parameters; on the other hand, the key program execution parameters and the impact of a single fault injection on program execution can be transmitted to the fault injection control and statistics module.

[0085] Based on the above design concept, this invention provides a register file-based single-event fault injection testing system using HDL, wherein the register file is at the RTL level. Figure 3 As shown, the register file is a register stack consisting of L registers, used to store intermediate variables during the execution of the processor program. Each register has a separate read port and write port. The array of multiple registers is accessed in a multi-way concurrent manner through M read ports and N write ports. The M read and N write port configuration can be formed through arbitration logic design, ensuring that the processor can access multiple registers within the same clock cycle.

[0086] like Figure 4As shown, the single-event fault injection test system includes a fault injection read port, a fault injection write port, a read / write arbitration logic module, a fault injection control module, and a fault detection and statistics module. The fault injection read port and fault injection write port are part of the register file interface and have the same function as the original register file read / write ports, capable of accessing any register in the register file, where M and N are greater than or equal to 1. The purpose of this invention is to inject single-event faults into the target register file in a simulated manner. The target register file is modified at the RTL layer by adding two ports: a fault injection read port and a fault injection write port, through modifications to the register array port file and read / write arbitration logic. The injection method does not change the register array of the register file.

[0087] The fault injection control module reads back the data of the register to be injected with faults through the fault injection read port according to the fault injection control parameters. Then, according to the fault type, the read data is flipped to obtain the fault data. The fault data is then written to the register to be injected with faults through the fault injection write port, and the number of fault injections and the proportion of fault types are recorded in real time.

[0088] The read / write arbitration logic module controls external read and write access to the register file. When a read instruction occurs, it determines whether any two read instructions accessing the same register within the same cycle are accessing the same register. If not, data is fetched in parallel and passed to the corresponding read port. If multiple ports access the same register, the register data at that address is fetched and allocated to each read port in parallel. When a write instruction occurs, it determines whether any two write instructions accessing the same register within the same cycle are accessing the same register. If not, data is written to the corresponding register in parallel. If multiple ports access the same register, access is based on a pre-defined priority, with higher-priority ports having priority access within the same cycle, and data from lower-priority ports being discarded. The write port used for fault injection has the lowest access priority among the N+1 write ports of the register.

[0089] The fault detection and statistics module is used to statistically analyze the processor's operating results after different fault injections. It detects whether the program running on the processor malfunctions after a single-particle fault is injected, the type of fault, and the number of times the fault occurs. Based on the type of injected fault and the total number of injected faults, the fault rate is calculated.

[0090] Preferably, the injection control parameters include: total number of fault injections, fault type, fault ratio, fault injection method, address of the fault injection target register, flag indicating whether the toggle bit is random, and the toggle bit; the fault type includes SEU, MBU, and SEU+MBU; when the fault type is SEU or MBU, the fault ratio and fault injection method are invalid; when the fault type is SEU+MBU, the fault injection method includes random selection or proportional injection; when the fault injection method is random selection, the fault ratio is invalid; when the fault injection method is proportional injection, the fault ratio is SEU fault to be injected: MBU fault to be injected.

[0091] like Figure 5 As shown, the processing flow of the fault injection control module is as follows:

[0092] S1. Obtain the total number of fault injections, Sum, and proceed to step S2;

[0093] S2. Determine the type of fault to be injected. When the fault type is SEU, proceed to step S3. When the fault type is MBU, proceed to step S4. When the fault type is SEU+MBU, proceed to step S5.

[0094] S3. Inject SEU fault, inject once, inject SEU fault a total of N times. SEU Add 1, update the number of SEU injection failures N. SEU When N SEU When Sum equals N, the fault injection ends; SEU injects faults N times. SEU Initialize to 0;

[0095] S4. Inject MBU faults, inject once, and inject MBU faults N times. MBU Add 1, update the number of MBU injection failures N. MBU When N MBU When the value equals Sum, the fault injection ends; the number of fault injection attempts (N) in the MBU is calculated. MBU Initialize to 0;

[0096] S5. Determine whether the fault injection method is random selection or proportional injection. If random selection is performed, execute step S5-1; if proportional injection is performed, execute step S5-2.

[0097] S5-1. Randomly select and inject either a SEU fault or an MBU fault. After each fault injection is completed, increment the number of randomly selected faults injected (S) by 1 and update the number of randomly selected faults injected (S). When S = Sum, the fault injection ends; the number of randomly selected faults injected (S) is initialized to 0.

[0098] S5-2. Obtain the fault proportion, and calculate the number X of SEU faults to be injected and the number Y of MBU faults to be injected according to the total number Sum of fault injections; when X'+Y'<Sum, X'<X and Y'<Y, randomly generate an SEU or MBU fault to inject into the register file, after a single SEU injection is completed, increment the number X' of injected SEU faults by 1, and update the number X' of injected SEU faults; after a single MBU injection is completed, increment the number Y' of injected MBU faults by 1, and update the number Y' of injected MBU faults; when X'=X and Y'<Y, only inject MBU faults, and after a single completion, increment the number Y' of injected MBU faults by 1, and update the number Y' of injected MBU faults; when Y'=Y and X'<X, only inject SEU faults, and after a single completion, increment the number X' of injected SEU faults by 1, and update the number X' of injected SEU faults; when X'+Y'=Sum, the fault injection is completed. The number X' of injected SEU faults is initialized to 0, and the number Y' of injected MBU faults is initialized to 0;

[0099] As Figure 6 shown, the methods for injecting SEU or MBU have the same principle and similar steps.

[0100] Preferably, the process of injecting an SEU fault is as follows:

[0101] Read the original data in the register according to the physical address of the register where the fault needs to be injected;

[0102] Determine the flag indicating whether the flipped bit is random; if it is random, randomly generate one flipped bit, otherwise, acquire the externally specified flipped bit;

[0103] Flip the data of the flipped bit, then write the rewritten register data back to the original register, so as to complete one SEU fault injection.

[0104] Preferably, the process of injecting an MBU fault is as follows:

[0105] Read the original data in the register according to the address of the target register where the fault needs to be injected;

[0106] Determine the flag indicating whether the flipped bits are random; if it is random, randomly generate a plurality of flipped bits, otherwise, acquire a plurality of externally specified flipped bits;

[0107] After the data bits that need to be flipped are determined, the data of these flipped bits are flipped respectively, then the rewritten data is written back to the original register, so as to complete one MBU fault injection.

[0108] Preferably, the flipping refers to changing a data bit from 0 to 1 or from 1 to 0.

[0109] Preferably, the types of faults include program function failure faults and silent faults, wherein a silent fault refers to a situation where the program in the processor runs normally, but the running result is incorrect.

[0110] The fault injection control and fault analysis module established at the RTL level in this invention establishes an interface relationship with the top-level test.

[0111] This invention also provides a single-event fault injection test method for register files based on HDL, which provides a simple, efficient and easy-to-implement fault tolerance effectiveness evaluation method for space application processor register file fault tolerance.

[0112] The method includes the following steps:

[0113] S1. Obtain fault injection control parameters, including: total number of fault injections, fault type, fault ratio, and fault injection method. The fault type includes SEU, MBU, and SEU+MBU. When the fault type is SEU or MBU, the fault ratio and fault injection method are invalid. When the fault type is SEU+MBU, the fault injection method includes random selection or proportional injection. When the fault injection method is random selection, the fault ratio is invalid. When the fault injection method is proportional injection, the fault ratio is SEU fault to MBU fault to be injected. Proceed to step S2.

[0114] S2. Determine the type of fault to be injected. When the fault type is SEU, proceed to step S3. When the fault type is MBU, proceed to step S4. When the fault type is SEU+MBU, proceed to step S5.

[0115] S3. Inject SEU fault, inject once, inject SEU fault a total of N times. SEU Add 1, update the number of SEU injection failures N. SEU When N SEU When Sum equals Sum, fault injection ends, proceed to step S6; SEU injects faults N times. SEU Initialize to 0;

[0116] S4. Inject MBU faults, inject once, and inject MBU faults N times. MBU Add 1, update the number of MBU injection failures N. MBU When N MBU When the value equals Sum, the fault injection ends, and the process proceeds to step S6; MBU fault injection count N MBU Initialize to 0;

[0117] S5. Determine whether the fault injection method is random selection or proportional injection. If random selection is performed, execute step S5-1; if proportional injection is performed, execute step S5-2.

[0118] S5-1. Randomly select to inject an SEU fault or an MBU fault. After each fault injection is completed, increment the number S of injected randomly selected faults by 1, and update S. When S=Sum, the fault injection ends, and the process proceeds to step S6. The initial value of the number S of injected randomly selected faults is set to 0;

[0119] S5-2. Acquire the fault proportion, and calculate the number X of SEU faults to be injected and the number Y of MBU faults to be injected according to the total number Sum of fault injections. When X'+Y'<Sum, X'<X and Y'<Y, randomly generate an SEU or MBU fault to inject into the register file. After a single SEU injection is completed, increment the number X' of injected SEU faults by 1, and update X'. After a single MBU injection is completed, increment the number Y' of injected MBU faults by 1, and update Y'. When X'=X and Y'<Y, only MBU faults are injected, and after each single injection is completed, increment the number Y' of injected MBU faults by 1, and update Y'. When Y'=Y and X'<X, only SEU faults are injected, and after each single injection is completed, increment the number X' of injected SEU faults by 1, and update X'. When X'+Y'=Sum, the fault injection ends, and the process proceeds to step S6. The initial value of the number X' of injected SEU faults is set to 0, and the initial value of the number Y' of injected MBU faults is set to 0;

[0120] S6. Detect whether a fault occurs in the program running on the processor after the single-event fault is injected, the type of the occurring fault, and the number of times the fault occurs, and then calculate the fault rate according to the injected fault type and the total number of injected faults.

[0121] Preferably, the fault injection control parameters further include: the address of the fault injection target register, a flag indicating whether the flipped bit is random, and the flipped bit. When the flag indicating whether the flipped bit is random indicates randomness, the flipped bit is invalid; otherwise, the flipped bit is valid.

[0122] Preferably, the process of injecting an SEU fault is as follows:

[0123] Read the original data in the register according to the physical address of the register where the fault needs to be injected;

[0124] Determine the flag indicating whether the flipped bit is random. If it is random, randomly generate a flipped bit; otherwise, acquire the externally specified flipped bit;

[0125] Flip the data of the flipped bit, then write the rewritten register data back to the original register, so as to complete one SEU fault injection.

[0126] Preferably, the process of injecting an MBU fault is as follows:

[0127] As needed, inject the address of the target register for the fault and read the original data from the register.

[0128] A flag indicating whether the flip bits are random; if random, generate multiple flip bits randomly; otherwise, retrieve multiple flip bits specified externally.

[0129] After determining the data bits that need to be flipped, flip the data of these flipped bits one by one, and then write the rewritten data back to the original register, thus completing an MBU fault injection.

[0130] like Figure 7 As shown, the fault detection and statistics module has two main functions: detection and statistics. The detection part is used to determine whether the fault injected into the register file affects the processor operation. There are three types of impact: (1) no impact, that is, after the fault injection, the processor runs normally and the program result is correct; (2) program failure, that is, after the fault injection, the processor fails to run and the program is interrupted; (3) silent fault, that is, the processor runs normally, but the final running result is incorrect. The fault detection and statistics module detects the program running status after each fault injection and statistically analyzes the detection results. The statistical method is divided into two parts: first, for each fault injection, the current detection result is linked with the current injected fault type and recorded; then, the recorded results are classified and sorted to obtain the ratio of the number of failures to the number of fault injections, and to obtain the program failure ratio of different fault types. Finally, the statistical data is transmitted to the underlying module and delivered to the test personnel through the VCS software platform tool.

[0131] In summary, this invention presents a single-event fault injection method for register files based on HDL design. On one hand, this invention injects SEU and MBU into the register file at the RTL level, allowing flexible control over fault type, fault ratio, injection address, and flip bits. On the other hand, this invention can statistically analyze the impact of injected faults on processor performance, and the specific fault impact mechanism can be analyzed through the VCS platform.

[0132] The advantages of this invention include:

[0133] 1) This invention does not require hardware or specialized radiation equipment support. The effectiveness of the fault-tolerant design can be obtained in the simulation stage, and the fault-tolerant design can be improved as early as possible.

[0134] 2) This invention does not modify the application software and will not affect the processor's operating performance;

[0135] 3) For soft errors caused by single-event effects, single-event flip (SEU) and single-event multiple-bit flip (MBU) can be injected into different locations in the register file in a random or fixed-probability manner.

[0136] 4) When combined with VCS software, the impact of injected faults on the processor can be analyzed to determine the effectiveness of the fault tolerance method.

[0137] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A register file single-event fault injection testing system based on HDL, wherein the register file is a register stack consisting of several registers used to store intermediate variables during processor program execution, and the register file is accessed concurrently through M read ports and N write ports, characterized in that... It includes a read port for fault injection, a write port for fault injection, a read / write arbitration logic module, a fault injection control module, and a fault detection and statistics module; The fault injection read port and fault injection write port are part of the register file interface and have the same function as the register file read and write ports. They can access any register in the register file, where M and N are greater than or equal to 1. The fault injection control module reads back the data of the register to be injected with faults through the fault injection read port according to the fault injection control parameters. Then, according to the fault type, the read data is flipped to obtain the fault data. The fault data is then written to the register to be injected with faults through the fault injection write port, and the number of fault injections and the proportion of fault types are recorded in real time. The read / write arbitration logic module controls external read and write access to the register file. When a read instruction occurs, it determines whether any two read instructions accessing the same register within the same cycle are accessing the same register. If not, data is fetched in parallel and passed to the corresponding read port. If multiple ports access the same register, the corresponding register data is fetched and allocated to each read port in parallel. When a write instruction occurs, it determines whether any two write instructions accessing the same register within the same cycle are accessing the same register. If not, data is written to the corresponding register in parallel. If multiple ports access the same register, access is performed according to a pre-defined priority. Higher-priority ports have priority access within the same cycle, and data from lower-priority ports is discarded. The write port used for fault injection has the lowest access priority among the N+1 write ports in the register file. The fault detection and statistics module is used to statistically analyze the processor's operating results after different fault injections. It detects whether the program running on the processor malfunctions after a single-particle fault is injected, the type of fault, and the number of times the fault occurs. Based on the type of injected fault and the total number of injected faults, the fault rate is calculated.

2. The HDL-based register file single-event fault injection testing system according to claim 1, characterized in that... The injection control parameters include: total number of fault injections, fault type, fault ratio, fault injection method, address of the fault injection target register, flag indicating whether the toggle bit is random, and the toggle bit itself. The fault type includes SEU, MBU, and SEU+MBU. When the fault type is SEU or MBU, the fault ratio and fault injection method are invalid. When the fault type is SEU+MBU, the fault injection method includes random selection or proportional injection. When the fault injection method is random selection, the fault ratio is invalid. When the fault injection method is proportional injection, the fault ratio is: number of SEU faults to be injected / number of MBU faults to be injected.

3. The register file single-event fault injection test system based on HDL according to claim 1, characterized in that... The processing flow of the fault injection control module is as follows: S1. Obtain the total number of fault injections, Sum, and proceed to step S2; S2. Determine the type of fault to be injected. When the fault type is SEU, proceed to step S3. When the fault type is MBU, proceed to step S4. When the fault type is SEU+MBU, proceed to step S5. S3. Inject SEU fault, inject once, inject SEU fault a total of N times. SEU Add 1, update the number of SEU injection failures N. SEU When N SEU When =Sum, the fault injection ends; Number of SEU injection failures N SEU Initialize to 0; S4. Inject MBU faults, inject once, and inject MBU faults N times. MBU Add 1, update the number of MBU injection failures N. MBU When N MBU When =Sum, the fault injection ends; N times MBU injection failure MBU Initialize to 0; S5. Determine whether the fault injection mode is random selection or proportional injection; perform step S5-1 for random selection, and perform step S5-2 for proportional injection; S5-1. Randomly select to inject an SEU fault or an MBU fault; after each fault injection is completed, increment the number of injected random selection faults S by 1 to update the number of injected random selection faults S; when S=Sum, the fault injection ends; The number of injected random selection faults S is initialized to 0; S5-2. Acquire the fault ratio, and calculate the number of SEU faults to be injected X and the number of MBU faults to be injected Y according to the total fault injection times Sum; when X'+Y'<Sum, X'<X and Y'<Y, randomly generate an SEU or MBU fault to inject into the register file; after a single SEU injection is completed, increment the number of injected SEU faults X' by 1 to update the number of injected SEU faults X'; after a single MBU injection is completed, increment the number of MBU faults Y' by 1 to update the number of injected MBU faults Y'; when X'=X and Y'<Y, only inject MBU faults, and after each single completion, increment the number of MBU faults Y' by 1 to update the number of injected MBU faults Y'; when Y'=Y and X'<X, only inject SEU faults, and after each single completion, increment the number of injected SEU faults X' by 1 to update the number of injected SEU faults X'; when X'+Y'=Sum, the fault injection is completed; the number of injected SEU faults X' is initialized to 0, and the number of injected MBU faults Y' is initialized to 0.

4. The HDL-based register file single-event fault injection testing system according to claim 1, characterized in that... The process of injecting an SEU fault is as follows: Read the original data in the register according to the physical address of the register where the fault needs to be injected; Determine the flag indicating whether the flipped bit is random; if it is random, randomly generate one flipped bit; otherwise, acquire the externally specified flipped bit; Flip the data of the flipped bit, then write the rewritten register data back to the original register, so as to complete one SEU fault injection.

5. A register file-based single-event fault injection testing system based on HDL according to claim 1, characterized in that... The process of injecting an MBU fault is as follows: Read the original data in the register according to the address of the target register where the fault needs to be injected; Determine the flag indicating whether the flipped bits are random; if they are random, randomly generate a plurality of flipped bits; otherwise, acquire a plurality of externally specified flipped bits; After determining the data bits that need to be flipped, flip the data of these flipped bits respectively, then write the rewritten data back to the original register, so as to complete one MBU fault injection.

6. A register file-based single-event fault injection testing system based on HDL according to any one of claims 4 or 5, characterized in that... Said flipping refers to changing a data bit from 0 to 1 or from 1 to 0.

7. A register file-based single-event fault injection test method for the system according to any one of claims 1 to 6, characterized in that... Comprising the following steps: S1. Obtain fault injection control parameters, where the injection control parameters include: total number of fault injections, fault type, fault ratio, and fault injection mode; the fault types include SEU, MBU, and SEU+MBU; when the fault type is SEU or MBU, the fault ratio is invalid, and the fault injection mode is invalid; when the fault type is SEU+MBU, the fault injection mode includes random selection and proportional injection; when the fault injection mode is random selection, the fault ratio is invalid; when the fault injection mode is proportional injection, the fault ratio is: number of SEU faults to be injected / number of MBU faults to be injected; proceed to step S2; S2. Determine the type of fault to be injected; when the fault type is SEU, proceed to step S3; when the fault type is MBU, proceed to step S4; when the fault type is SEU+MBU, proceed to step S5; S3. Inject SEU fault, inject once, inject SEU fault a total of N times. SEU Add 1, update the number of SEU injection failures N. SEU When N SEU When Sum equals Sum, the fault injection ends, and proceed to step S6; the number of fault injections N for SEU is... SEU Initialize to 0; S4. Inject MBU faults, inject once, and inject MBU faults N times. MBU Add 1, update the number of MBU injection failures N. MBU When N MBU When =Sum, the fault injection ends, proceed to step S6; the number of fault injection attempts N of the MBU is... MBU Initialize to 0; S5. First, determine whether the fault injection mode is random selection or proportional injection; perform step S5-1 for random selection, and perform step S5-2 for proportional injection; S5-1. Randomly select to inject an SEU fault or an MBU fault; after each fault injection is completed, increment the number S of injected randomly selected faults by 1, and update the number S of injected randomly selected faults; when S=Sum, the fault injection ends, and proceed to step S6; the number S of injected randomly selected faults is initialized to 0; S5-2. Obtain the fault ratio, and calculate the number X of SEU faults to be injected and the number Y of MBU faults to be injected according to the total number Sum of fault injections; when X'+Y'<Sum, X'<X and Y'<Y, randomly generate an SEU or MBU fault to inject into the register file; after a single SEU injection is completed, increment the number X' of injected SEU faults by 1, and update the number X' of injected SEU faults; after a single MBU injection is completed, increment the number Y' of injected MBU faults by 1, and update the number Y' of injected MBU faults; when X'=X and Y'<Y, only inject MBU faults, and after each single injection is completed, increment the number Y' of injected MBU faults by 1, and update the number Y' of injected MBU faults; when Y'=Y and X'<X, only inject SEU faults, and after each single injection is completed, increment the number X' of injected SEU faults by 1, and update the number X' of injected SEU faults; when X'+Y'=Sum, the fault injection ends, and proceed to step S6; the number X' of injected SEU faults is initialized to 0, and the number Y' of injected MBU faults is initialized to 0; S6. After the single-event fault is injected, detect whether a fault occurs in the program running on the processor, the type of the occurred fault, and the number of occurred faults, and then calculate the fault rate according to the injected fault type and the total number of injected faults.

8. The HDL-based register file single-event fault injection test method according to claim 7, characterized in that... The fault injection control parameters further include: the address of the target register for fault injection, a flag indicating whether the flipped bit is random, and the flipped bit; when the flag indicating whether the flipped bit is random is random, the flipped bit is invalid; otherwise, the flipped bit is valid.

9. A register file single-event fault injection test method based on HDL according to claim 8, characterized in that... The process of injecting an SEU fault is as follows: Read the original data in the register according to the physical address of the register into which the fault needs to be injected; A flag indicating whether the flip bit is random; if random, generate a random flip bit; otherwise, retrieve the externally specified flip bit. By flipping the data in the flip bit and then writing the rewritten register data back to the original register, a SEU fault injection is completed.

10. A register file single-event fault injection test method based on HDL according to claim 8, characterized in that... The process of injecting an MBU fault is as follows: As needed, inject the address of the target register for the fault and read the original data from the register. A flag indicating whether the flip bits are random; if random, generate multiple flip bits randomly; otherwise, retrieve multiple flip bits specified externally. After determining the data bits that need to be flipped, flip the data of these flipped bits one by one, and then write the rewritten data back to the original register, thus completing an MBU fault injection.

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