A simulation method and apparatus for asynchronous chips
By introducing a simulation device for a data processing unit and a handshake control unit into an asynchronous chip, asynchronous communication is simulated, solving the problem of long verification cycles for asynchronous chip system-level architectures and enabling rapid simulation and performance comparison.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2023-03-27
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies require a long time to verify asynchronous chip system-level architectures, making it difficult for designers to quickly select the best solution, and there is a lack of effective system-level simulators.
A simulation device for an asynchronous chip is provided, including a data processing unit and a handshake control unit. The device simulates the communication between functional modules in the asynchronous chip by controlling the handshake, thereby simulating asynchronous communication.
It enables rapid simulation of asynchronous chips, helping designers verify the functionality of different architectures and compare performance, thereby improving design efficiency.
Smart Images
Figure CN116258103B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design, and more particularly to a simulation method and apparatus for an asynchronous chip. Background Technology
[0002] Compared to synchronous circuits, asynchronous circuits offer advantages such as low power consumption, high speed, and no clock distribution issues. However, there are numerous system-level architecture design schemes for asynchronous chips, and different architectures of asynchronous chips vary significantly in functionality and performance. Verifying the functionality and performance of multiple asynchronous chip system architectures using existing EDA tools requires a lengthy process. To select the optimal solution from among numerous asynchronous chip architectures, designers urgently need a system-level simulator that can quickly provide simulation results for asynchronous chip architectures, helping them verify the functionality of different architectures and compare the performance of various architectural solutions. Summary of the Invention
[0003] To address any of the aforementioned technical problems, embodiments of this application provide a simulation method and apparatus for asynchronous chips.
[0004] To achieve the objectives of the embodiments of this application, this application provides a simulation device for an asynchronous chip. The device includes at least two functional modules, which jointly implement at least some of the functions of the asynchronous chip. Each functional module has at least one of its corresponding superior and subordinate functional modules; wherein:
[0005] Each functional module includes a data processing unit and a handshake control unit; wherein:
[0006] The data processing unit is used to process the received data according to the data processing method corresponding to the functional module in the asynchronous chip;
[0007] The handshake control unit controls local communication with other functional modules in at least one of the following ways:
[0008] When the data processing unit has not processed the data sent by the previous functional module, or after the data processing unit has completed processing the data sent by other previous functional modules and confirmed that the next functional module can perform the data receiving operation, the data sent by the previous functional module is received.
[0009] Before sending local data to the next level functional module, check whether the next level functional module can perform data receiving operations. After confirming that the next level functional module can perform data receiving operations, send the local data to the next level functional module.
[0010] A simulation method for an asynchronous chip, applied to the device described above, wherein at least one functional module of the device performs the following method, including:
[0011] When the local system has not processed the data sent by the previous functional module, or after processing the data sent by other previous functional modules and confirming that the next functional module can perform the data receiving operation, the system performs the receiving operation on the data sent by the previous functional module.
[0012] The system checks whether the next-level functional module can perform data receiving operations. Once it is confirmed that the next-level functional module can perform data receiving operations, the local data is sent to the next-level functional module.
[0013] One of the above technical solutions has the following advantages or beneficial effects:
[0014] By controlling communication with other functional modules, the handshake mechanism of asynchronous communication between functional modules in an asynchronous chip is simulated, thereby achieving the simulation purpose of the asynchronous chip.
[0015] Other features and advantages of the embodiments of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the embodiments of this application. The objects and other advantages of the embodiments of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description
[0016] The accompanying drawings are used to provide a further understanding of the technical solutions of the embodiments of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0017] Figure 1 A schematic diagram of the structure of the simulation device for the asynchronous chip provided in the embodiments of this application;
[0018] Figure 2 A schematic diagram illustrating the application of an asynchronous chip simulation device as an example of the application of this application;
[0019] Figure 3 A schematic diagram illustrating the application of an asynchronous chip simulation device as an example of the application of this application;
[0020] Figure 4 A flowchart illustrating the simulation method for an asynchronous chip provided in this application embodiment;
[0021] Figure 5 A flowchart illustrating the communication method of the functional modules provided in the embodiments of this application. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.
[0023] Figure 1 This is a schematic diagram of the structure of the simulation device for the asynchronous chip provided in the embodiments of this application. Figure 1 As shown, the device includes at least two functional modules, which together implement at least some of the functions of the asynchronous chip.
[0024] For example, at least two functional modules in the device can be configured to jointly implement the core functions of the asynchronous chip, covering most of the functions, so as to complete the rapid simulation of the asynchronous chip; or, at least two functional modules in the device can be configured to jointly implement all the functions of the asynchronous chip, covering all the functions of the asynchronous chip, so as to complete the full simulation of the asynchronous chip.
[0025] This functional module is a system-level functional modeling module, such as the processing core module, network link module, bus module, input buffer module, output buffer module, routing calculation module, and arbitration module.
[0026] Specifically, each functional module has at least one of its corresponding parent and child functional modules.
[0027] Since the above functional modules communicate based on asynchronous communication, in the data processing order of asynchronous communication, the functional module that is executed first only has the corresponding next-level functional module, the functional module that is executed last only has the previous-level functional module, and the functional module that is executed in the middle has both the previous-level functional module and the next-level functional module.
[0028] Furthermore, each functional module can have one or more parent functional modules; similarly, each functional module can have one or more child functional modules.
[0029] Each functional module includes a data processing unit and a handshake control unit; wherein:
[0030] The data processing unit is used to process the received data according to the data processing method corresponding to the functional module in the asynchronous chip; for example, if the functional module is an input buffer module, then the data processing unit in the functional module is used to receive data and buffer the received data.
[0031] The handshake control unit is used to control communication between the local unit and other functional modules.
[0032] Because the functional modules in an asynchronous chip use handshake signals to achieve inter-module interaction, a functional module can only receive data input sent by the previous functional module when the functional module allows it to receive new data. Furthermore, whether or not data reception is allowed between modules is determined by sending request and response signals.
[0033] Based on the working principle of the asynchronous chip described above, this application provides the following solutions, including:
[0034] In one implementation, the receiving operation is performed on the data sent by the previous functional module when the data processing unit has not processed the data sent by the previous functional module, or after the data processing unit has completed processing the data sent by other previous functional modules and confirmed that the next functional module can perform the data receiving operation.
[0035] Specifically, if the data processing unit does not process data sent by the previous-level functional module, it indicates that the data processing unit has not started the data processing flow and is in an idle state. Conversely, if the data processing unit completes the processing of data sent by other previous-level functional modules and confirms that the next-level functional module can perform data receiving operations, it indicates that a round of data processing operations has been completed and it has the ability to start a new round of data processing operations. Both of these situations indicate that the functional module can establish communication with the previous-level functional module to receive data sent by the previous-level functional module.
[0036] In another implementation, before sending local data to the next-level functional module, it is checked whether the next-level functional module can perform the data receiving operation. After determining that the next-level functional module can perform the data receiving operation, the local data is sent to the next-level functional module.
[0037] Specifically, by detecting whether the next-level functional module can perform data receiving operations, it ensures that the local system can successfully establish communication with the next-level functional module, thereby guaranteeing the normal operation of communication between functional modules.
[0038] The device provided in this application embodiment controls the communication with other functional modules based on the handshake control unit, simulating the handshake mechanism of asynchronous communication between functional modules in an asynchronous chip, thereby achieving the simulation purpose of the asynchronous chip.
[0039] In one exemplary embodiment, when the functional module has at least two superior functional modules, during the process from receiving data sent by one superior functional module to completing the processing of the received data, the handshake control unit rejects data sent by other superior functional modules.
[0040] Specifically, during the process from receiving data sent by a higher-level functional module to completing the processing of the received data, the data processing unit is in working state and has no other processing capability to process data sent by other higher-level functional modules. Therefore, by rejecting data sent by other higher-level functional modules, the normal operation of communication between functional modules can be guaranteed.
[0041] In one exemplary embodiment, each functional module is provided with a delay unit;
[0042] The delay unit is connected to the handshake control unit and is used to indicate whether it is allowed to receive data sent by the previous functional module;
[0043] When the handshake control unit processes data sent by a higher-level functional module locally, it sets the delay unit to a busy state to reject data sent by other higher-level functional modules.
[0044] Specifically, when the handshake control unit has not processed the data sent by the previous functional module locally, it sets the delay unit to an idle state to receive the data sent by the previous functional module; or, after completing the processing of the data sent by the previous functional module and confirming that the next functional module can perform the data receiving operation, it sets the delay unit to an idle state to receive the new data sent by the previous functional module.
[0045] Based on the status information of the delay unit, it can be determined whether the functional module is capable of receiving new data, thus realizing a handshake mechanism based on functional modules.
[0046] In one exemplary embodiment, each functional module is provided with at least one of a request unit and a response unit; wherein:
[0047] The response unit is connected to the delay unit and is used to send a response signal to the upper-level functional module according to the status information of the delay unit. The response signal is used to indicate the status information of the delay unit.
[0048] The response signal sent by the response unit can be sent periodically based on a private protocol setting, or it can be sent according to the triggering conditions specified in the general protocol of the asynchronous chip.
[0049] Specifically, if the delay unit is in a busy state, it will not send an acknowledgment signal; if the delay unit is in an idle state, it will send an acknowledgment signal.
[0050] Furthermore, the response unit is also used to send a response signal to the upper-level functional module after receiving a request signal sent by the upper-level functional module.
[0051] Specifically, based on the request-response handshake mechanism, the response unit sends a response signal, effectively controlling the amount of communication data between functional modules and conforming to the communication protocol of asynchronous chips.
[0052] Furthermore, the handshake control unit is also used to set the delay unit to a busy state after receiving a request signal sent by the previous functional module.
[0053] Specifically, upon receiving a request signal from the previous functional module, the delay unit is immediately set to a busy state to avoid conflicts caused by multiple previous functional modules establishing communication with the current functional module.
[0054] Furthermore, the duration for which the delay unit remains in a busy state is determined based on the delay duration required for data processing by the circuit module corresponding to the functional module.
[0055] Specifically, the duration for which the delay unit remains in a busy state can be a preset delay duration, wherein the size of the preset duration can be determined according to the delay duration required for data processing by the circuit module corresponding to the functional module.
[0056] After the delay unit is in a busy state, the time during which the delay unit is in a busy state is timed. The state information of the delay unit is determined by whether the timed operation reaches the preset delay time. If the timed operation reaches the preset delay time, the state information of the delay unit is changed to an idle state; otherwise, the delay unit continues to be in a busy state.
[0057] In one implementation, the request unit is used to send a request signal to the next-level functional module, and the request signal is used to query the status information of the delay unit in the next-level functional module.
[0058] The response signal sent by the requesting unit can be sent periodically based on a private protocol setting, or it can be sent according to the triggering conditions specified in the general protocol of the asynchronous chip.
[0059] Furthermore, the request unit is used to send a request signal to the next-level functional module before sending local data to the next-level functional module.
[0060] Specifically, based on the request-response handshake mechanism, the request unit sends a request signal to effectively control the amount of communication data between functional modules and comply with the communication protocol of the asynchronous chip.
[0061] The following application example illustrates the device provided in this application:
[0062] Figure 2This is a schematic diagram illustrating the application of an asynchronous chip simulation device as an example of this application. For example... Figure 2 As shown, this device simulates an asynchronous chip that implements network routing functionality. The device includes four functional modules: an input buffer module, a route calculation module, an arbitration module, and an output buffer module; wherein:
[0063] The input buffer module includes a data processing unit, a handshake control unit, and a delay unit; wherein:
[0064] When the handshake control unit receives a request signal from the previous functional module, it checks whether the delay unit is idle. If it is idle, it sends a response signal to the previous functional module and sends the delay information of the input buffer module to the delay unit, putting it in a busy state. Otherwise, it does not send a response signal and repeatedly checks whether the delay unit is idle. After the delay unit remains busy, after the delay time of one input buffer module, it sends a request signal to the handshake control unit of the routing calculation module. If it receives a response signal, it sends a data transmission permission signal to the data processing unit of the input buffer module and sets the delay unit to an idle state. Otherwise, it does not send the data transmission permission signal and remains busy. The logical function of the data processing unit of the input buffer module is to receive and buffer data packets sent by the previous functional module, and after receiving the data transmission permission signal, send data packets to the routing calculation module.
[0065] The routing calculation module includes a data processing unit, a handshake control unit, and a delay unit; wherein:
[0066] When the handshake control unit receives a request signal from the input buffer module, it checks whether the delay unit is idle. If it is idle, it sends a response signal to the input buffer module and sends the delay information of the routing calculation module to the delay unit, putting it in a busy state. Otherwise, it does not send a response signal and repeatedly checks whether the delay unit is idle. After the delay unit remains busy, after the delay time of one routing calculation module, it sends a request signal to the handshake control unit of the arbitration module. If it receives a response signal, it sends a data transmission permission signal to the data processing unit of the routing calculation module and sets the delay unit to an idle state. Otherwise, it does not send the data transmission permission signal and remains busy. The data processing unit of the routing calculation module receives data packets from the input buffer module, calculates the port corresponding to the current data packet transmission direction based on the data packet header information and the routing strategy required by the simulation, and sends the data packet to the arbitration module after receiving the data transmission permission signal.
[0067] The arbitration module includes a data processing unit, a handshake control unit, and a delay unit; wherein:
[0068] When the handshake control unit receives a request signal from the routing calculation module, it checks whether the delay unit is idle. If it is idle, it sends a response signal to the routing calculation module and sends the delay information of the routing calculation module to the delay unit, putting it into a busy state. Otherwise, it does not send a response signal and repeatedly checks whether the delay unit is idle. After the delay unit remains busy, after the delay time of the arbitration module, it sends a request signal to the handshake control unit of the output buffer module. If it receives a response signal, it sends a data transmission permission signal to the data processing unit of the arbitration module and sets the delay unit to an idle state. Otherwise, it does not send the data transmission permission signal and remains busy. The logical function of the data processing unit of the arbitration module is to receive data packets from the routing calculation module, allocate each data packet to the designated output port according to the arbitration mechanism required by the simulation, and send the data packet to the output buffer module of that output port after receiving the data transmission permission signal.
[0069] The output buffer module includes a data processing unit, a handshake control unit, and a delay unit; wherein:
[0070] When the handshake control unit receives a request signal from the arbitration module, it checks whether the delay unit is idle. If it is idle, it sends a response signal to the next-level module and sends the delay information of the routing calculation module to the delay unit, putting it in a busy state. Otherwise, it does not send a response signal and repeatedly checks whether the delay unit is idle. After the delay unit remains busy, after the delay time of one output buffer module, it sends a request signal to the next level. If it receives a response signal, it sends a data transmission permission signal to the data processing unit of the output buffer module and sets the delay unit to an idle state. Otherwise, it does not send the data transmission permission signal and remains busy. The logical function of the data processing unit of the output buffer module is to receive and buffer the data packets sent by the arbitration module, and after receiving the data transmission permission signal, send the data packets to the next level.
[0071] Figure 3 This is a schematic diagram illustrating the application of another asynchronous chip simulation device provided as an application example of this application. For example... Figure 3 As shown, this device simulates a multi-core asynchronous chip, which includes multiple processing units and an on-chip network or bus structure supporting communication between the multiple processing units. Correspondingly, the device includes multiple node processing modules and an on-chip communication module. The multiple node processing modules form the topology of the network system according to the connection relationships provided by the on-chip communication module. Wherein:
[0072] Each node processing module is used to read input data, process the data according to the logical functions required by the simulation, and send the processing results. The data processing methods can include neuron membrane potential accumulation, leakage, and pulse emission in spiking neural networks.
[0073] The on-chip communication module includes an asynchronous bus unit, an asynchronous network link unit, and an asynchronous routing unit; wherein there are multiple asynchronous network link modules and routers, including at least one of them.
[0074] The asynchronous network link module connects multiple node processing modules and asynchronous routing units to realize on-chip interconnection, so that multiple node processing modules and multiple asynchronous routing units can be interconnected with each other through network links in the required topology.
[0075] The asynchronous bus module connects multiple node processing modules and is used to control which node processing module occupies the bus at each moment according to the data transmission needs of each node.
[0076] The asynchronous routing unit is used to forward data packets.
[0077] Each node processing module and each unit in the on-chip communication module described above can be further divided into smaller functional units, so that units belonging to the same module or unit can communicate using the processing method of the device described above. For example, the asynchronous routing unit can be implemented using the asynchronous chip processing method described above for implementing network routing functions.
[0078] The device provided in the application example of this application can simulate and verify asynchronous chip architecture, including asynchronous handshake signals, data transmission controlled by the handshake signals, and delay duration, providing system-level simulation for asynchronous chip design and helping designers to select solutions and evaluate performance for large-scale multi-core asynchronous chip designs.
[0079] Figure 4 A flowchart illustrating the simulation method for an asynchronous chip provided in this application embodiment. Figure 4 As shown, the method is applied to the system described above, and the method includes:
[0080] Step 401: After receiving data sent by a higher-level functional module, process the received data to obtain local data, and reject data sent by other higher-level functional modules before completing the processing of the received data.
[0081] Step 402: Process the received data according to the data processing method corresponding to the functional module in the asynchronous chip to obtain local data;
[0082] Step 403: Check whether the next-level functional module can perform the data receiving operation. After confirming that the next-level functional module can perform the data receiving operation, send the local data to the next-level functional module.
[0083] Optionally, the method further includes:
[0084] After receiving data from a higher-level functional module, the functional module rejects data sent by other higher-level functional modules before completing the processing of the received data.
[0085] The method provided in this application simulates the handshake mechanism of asynchronous communication between functional modules in an asynchronous chip by controlling communication with other functional modules, thereby achieving the simulation purpose of the asynchronous chip.
[0086] Figure 5 This is a flowchart illustrating the communication method of the functional modules provided in an embodiment of this application. Figure 5 As shown, this functional module has a higher-level functional module and a lower-level functional module, and the method includes:
[0087] Step 501: Receive the request signal sent by the previous functional module.
[0088] Step 502: Determine whether the delay unit is in an idle state;
[0089] If the delay unit is in an idle state, proceed to step 503; otherwise, proceed to step 504.
[0090] Step 503: Return the response signal, set the delay unit to busy state, and keep it in busy state for the corresponding delay duration of the functional module.
[0091] Step 504: No response signal is returned.
[0092] Step 505: Send a request signal to the next-level functional module;
[0093] Step 506: Determine whether a response signal has been received;
[0094] If a response signal is received, proceed to step 507; otherwise, proceed to step 508.
[0095] Step 507: Set the delay unit to idle state and send data to the next level functional module.
[0096] Step 508: Keep the delay unit in a busy state.
[0097] In the above method, if the functional module has only a parent functional module, then only steps 501 to 504 need to be executed; if the functional module has only a child functional module, then only steps 504 to 508 need to be executed.
[0098] In the above method, the functional module uses the above approach to control communication with other functional modules, simulating the handshake mechanism of asynchronous communication between functional modules in the asynchronous chip, thereby achieving the simulation purpose of the asynchronous chip.
[0099] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
Claims
1. A simulation device for an asynchronous chip, the device comprising at least two functional modules, the at least two functional modules jointly implementing at least some of the functions of the asynchronous chip, each functional module having at least one of its corresponding superior functional module and subordinate functional module; wherein: Each functional module includes a data processing unit and a handshake control unit; wherein: The data processing unit is used to process the received data according to the data processing method corresponding to the functional module in the asynchronous chip; The handshake control unit controls local communication with other functional modules in at least one of the following ways: When the data processing unit has not processed the data sent by the previous functional module, or after the data processing unit has completed processing the data sent by other previous functional modules and confirmed that the next functional module can perform the data receiving operation, the data sent by the previous functional module is received. Before sending local data to the next level functional module, check whether the next level functional module can perform data receiving operations. After confirming that the next level functional module can perform data receiving operations, send the local data to the next level functional module.
2. The apparatus according to claim 1, characterized in that: The handshake control unit is also used to reject data sent by other upper-level functional modules when the functional module has at least two upper-level functional modules, during the process from receiving data sent by one upper-level functional module to completing the processing of the received data.
3. The apparatus according to claim 1, characterized in that: Each functional module is equipped with a delay unit; The delay unit is connected to the handshake control unit and is used to indicate whether to allow the reception of data sent by the previous functional module; When the handshake control unit processes data sent by a higher-level functional module locally, it sets the delay unit to a busy state to reject data sent by other higher-level functional modules. Specifically, when the handshake control unit has not processed the data sent by the previous functional module locally, it sets the delay unit to an idle state to receive the data sent by the previous functional module; or, after completing the processing of the data sent by the previous functional module and confirming that the next functional module can perform the data receiving operation, it sets the delay unit to an idle state to receive the new data sent by the previous functional module.
4. The apparatus according to claim 3, characterized in that: Each handshake control unit in a functional module is equipped with a request unit and a response unit; wherein: The response unit is connected to the delay unit and is used to send a response signal to the upper-level functional module according to the status information of the delay unit. The response signal is used to indicate the status information of the delay unit. The request unit is used to send a request signal to the next-level functional module, and the request signal is used to query the status information of the delay unit in the next-level functional module.
5. The apparatus according to claim 4, characterized in that: The response unit is also used to send a response signal to the upper-level functional module after receiving a request signal from the upper-level functional module.
6. The apparatus according to claim 4, characterized in that: The handshake control unit is also used to set the delay unit to a busy state after receiving a request signal sent by the previous functional module.
7. The apparatus according to claim 6, characterized in that: The duration for which the delay unit remains in a busy state is determined based on the delay duration required for data processing by the circuit module corresponding to the functional module.
8. The apparatus according to claim 4, characterized in that: The request unit is used to send a request signal to the next-level functional module before sending local data to the next-level functional module.
9. A simulation method for an asynchronous chip, applied to the apparatus as described in any one of claims 1 to 7, wherein at least one functional module of the apparatus performs the following method, comprising: When the local system has not processed the data sent by the previous functional module, or after processing the data sent by other previous functional modules and confirming that the next functional module can perform the data receiving operation, the system performs the receiving operation on the data sent by the previous functional module. The received data is processed according to the data processing method corresponding to the functional module in the asynchronous chip to obtain local data; The system checks whether the next-level functional module can perform data receiving operations. Once it is confirmed that the next-level functional module can perform data receiving operations, the local data is sent to the next-level functional module.
10. The method according to claim 9, characterized in that, The method further includes: After receiving data from a higher-level functional module, the functional module rejects data sent by other higher-level functional modules before completing the processing of the received data.