An image processing method, apparatus and electronic device

Abstract

Embodiments of the present application provide an image processing method, device and electronic equipment. In the embodiments, in the process of writing current frame image data into a configuration cache space, if it is found that the number of rows of current frame image data written into the cache space is a specified number of data rows, reading of block data is started, and writing of current frame image data into the cache space is continued at the same time as the reading of the block data, which realizes decoupling of the image caching process and the image reading process, and image reading is not required to wait until a frame of image is completely cached, thereby reducing the delay time of image processing.

Description

Technical Field

[0001] This application relates to the field of image processing technology, and in particular to an image processing method, apparatus and electronic device. Background Technology

[0002] In fields such as video surveillance, due to the characteristics of the data output by image acquisition equipment, each image frame is transmitted and received line by line. The entire frame is buffered before image data processing to restore and enhance image information. However, due to the limitations of processor computing power, the processor cannot process an entire image at once. It needs to read and process the left half of the image first, and then read and process the right half. Thus, because the image frame buffering method and the image reading and processing method are different, it often leads to delays in image processing. Summary of the Invention

[0003] In view of this, embodiments of this application provide an image processing method, apparatus, and electronic device to reduce image processing latency.

[0004] According to a first aspect of the embodiments of this application, an image processing method is provided, the method being applied to an electronic device, the method comprising:

[0005] During the process of writing the current frame image data to the configured cache space, if it is found that the number of current frame image data lines written to the cache space is the specified number of data lines, then the first block of data in each data line is read from the cache space according to the data line writing order of the current frame image data, and the data lines of the current frame image data other than the specified data lines are continued to be written to the cache space.

[0006] After reading the last data line of the current frame image data, the second block of data in each data line is read in the order in which the data lines are written; the second block of data in each data line includes at least the remaining data other than the first block of data.

[0007] According to a second aspect of the embodiments of this application, an image processing apparatus is provided, the apparatus being applied to an electronic device, the apparatus comprising:

[0008] The first reading module is used to read the first block of data from each data line in the cache space according to the data line writing order of the current frame image data during the process of writing the current frame image data to the configured cache space. If it is found that the number of current frame image data lines written to the cache space is a specified number of data lines, the module continues to write the data lines of the current frame image data other than the specified data lines to the cache space.

[0009] The second reading module is used to read the second block of data in each data line according to the data line writing order after reading the last data line of the current frame image data; the second block of data in each data line includes at least the remaining data other than the first block of data.

[0010] According to a third aspect of the embodiments of this application, an electronic device is provided, the electronic device comprising: a processor and a memory;

[0011] The memory is used to store machine-executable instructions;

[0012] The processor is configured to read and execute machine-executable instructions stored in the memory to implement the method as described in the first aspect.

[0013] The technical solutions provided in this application embodiment may include the following beneficial effects:

[0014] In this embodiment, if the number of current frame image data lines written to the configuration cache space is found to be the specified number of data lines during the process of writing current frame image data to the configuration cache space, the block data is read and the current frame image data is continued to be written to the cache space while reading the block data. This decouples the image caching process from the image reading process, and does not require waiting for a frame image to be completely cached before image reading, thus reducing the latency of image processing. Attached Figure Description

[0015] Figure 1 This is an example diagram of an electronic device provided in an embodiment of this application.

[0016] Figure 2 This is an example diagram of the online image receiving unit provided in the embodiments of this application.

[0017] Figure 3 This is an example diagram of the feature parameter configuration of the online image receiving unit provided in the embodiments of this application.

[0018] Figure 4 This is an example diagram of the image block processing unit provided in the embodiments of this application.

[0019] Figure 5 This is an example diagram of the feature parameter configuration of the image block processing unit provided in the embodiments of this application.

[0020] Figure 6 This is a flowchart of the method provided in the embodiments of this application.

[0021] Figure 7 These are example diagrams illustrating image writing and image output provided in the embodiments of this application.

[0022] Figure 8This is another example diagram of image writing and image output provided in the embodiments of this application.

[0023] Figure 9 This is a block diagram of the apparatus provided in the embodiments of this application.

[0024] Figure 10 This is a structural diagram of the electronic device provided in the embodiments of this application. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0026] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0027] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0028] The embodiments described in this specification will now be described in detail.

[0029] like Figure 1 As shown, Figure 1 The embodiments of this application illustrate example diagrams of electronic devices, such as... Figure 1 As shown, the electronic device includes at least: an online image receiving unit, an image frame buffer unit, an image block processing unit, and a general-purpose processor unit.

[0030] The aforementioned online image receiving unit is used to receive image data sent by the image acquisition device and to parse the received image data online in real time. For each frame of image data, it processes the data line by line and provides functions such as line-level programmable interrupt, two-dimensional spatial address management and wrapping address management, and frame-level parameter activation control.

[0031] For example, in this embodiment, the image acquisition device can be a regular camera, an industrial camera, etc., and this application embodiment is not specifically limited.

[0032] Here, row-level programmable interrupt refers to the ability to send an interrupt trigger signal to a general-purpose processor unit after any data row is written to the image buffer unit, so as to notify the general-purpose processor unit to perform the corresponding operation; two-dimensional spatial address management refers to the management of the image data rows and the amount of data in each data row; and wrap-around address management refers to the ability to return to the starting address of the image buffer unit and continue buffering image data after the image data is full.

[0033] The aforementioned image cache unit is used to store image data and provides K-byte (K>=16) addressing access functionality.

[0034] The image block processing unit is used to acquire image frame buffer image data offline, and to perform row-by-row pixel processing on at least two image data obtained from the block in a time-division manner. It provides functions such as programmable row blanking and frame blanking configuration for image processing, frame-level interrupt for block processing, two-dimensional spatial address management, and wrap-around address management.

[0035] Here, the programmable line blanking configuration for image processing refers to the time interval between two data lines obtained from the image buffer unit, that is, the time interval between the end of the previous data line and the beginning of the next data line. The programmable frame blanking configuration for image processing refers to the time interval between two frames of image data obtained from the image buffer unit, that is, the time interval between the end of the previous frame of image data and the beginning of the next frame of image data. The block processing frame-level interrupt refers to the ability to send an interrupt trigger signal to the general-purpose processor unit after processing each block of image data, so as to notify the general-purpose processor unit to perform the corresponding operation.

[0036] The general-purpose processor unit is used to respond to interrupt trigger signals from the online image receiving unit and the image block processing unit, and to perform operations such as corresponding parameter configuration and operation enable control.

[0037] Specifically, in this embodiment, such as Figure 2 As shown, the online image receiving unit includes at least: a transmission protocol parsing module, a configuration interface module, a control and management module, and a cache interface module.

[0038] In this embodiment, the transmission protocol parsing module is used to parse real-time image data online and mark the start position of frames; the configuration interface module is used to provide functions such as row-level programmable interrupts and two-dimensional spatial address parameters; the control management module is used to complete row-level counting and row-level address mapping; and the cache interface module is used to write the received image data frame data row by row into the image cache unit.

[0039] In this embodiment, as Figure 2 As shown, the online image receiving unit can be configured with at least 5 feature parameters and at least 2 interaction signals. These are distributed by software at frame-level intervals through the cfg configuration channel. That is, the feature parameters of each frame of image data can be different or the same. In this application embodiment, the specific values ​​of the feature parameters, the number of feature parameters, and the number of interaction signals for each frame of image are not specifically limited, and can be determined according to the actual situation.

[0040] The five characteristic parameters mentioned above are as follows:

[0041] initial_addr: The starting address of the image buffer unit;

[0042] wrap_addr: The wrap address of the image buffer unit;

[0043] base_addr: The base address of the first line of the image buffer unit where the image data is stored;

[0044] line_stride: The buffer interval for one line of data in the entire image. Here, the buffer interval line_stride is greater than or equal to the data storage size of one line of image, and K-byte alignment is constrained.

[0045] line_thre: Preset value for the number of rows of image data written, represented by the number of image rows, used to trigger an interrupt.

[0046] The two interaction signals are as follows:

[0047] sof: Image frame header start interrupt, which represents the start signal of a new frame of image and reports the interrupt trigger signal to the general-purpose processor unit.

[0048] line_hit: Image line-level interrupt, indicating that the image line count of the current frame image processing has reached the preset value of the number of image data written lines, line_thre, and an interrupt trigger signal is reported to the general-purpose processor unit.

[0049] like Figure 3 As shown, Figure 3 The examples illustrate the roles of the above 5 feature parameters and 2 interaction signals in the image frame buffer, where:

[0050] The area between `initial_addr` and `wrap_addr` represents the configured image buffer unit, with `wrap_addr` > `initial_addr`. Its relationship to the size of the image data is not restricted. When the data line address of a single frame's image buffer reaches `wrap_addr`, the control frame buffer line-level address automatically switches back to `initial_addr`.

[0051] base_addr and line_thre can be dynamically configured per frame. base_addr is constrained between initial_addr and wrap_addr. When the write line height of a single frame image is line_thre, line_hit is triggered.

[0052] The image cache unit includes at least a memory access interface module and a cache entity module, which supports addressing access with address mapping of K bytes (K can be any value, for example, K>=16). The memory access interface module is a standard bus interface module, specifically, it can be an AMBA standard interface, etc., which is not specifically limited in this application embodiment; the cache entity module can generally be SRAM, DRAM, etc., which is not specifically limited in this application embodiment.

[0053] This application embodiment utilizes the control features of the online image receiving unit on interrupt triggering to program row-level interrupt triggering conditions. By using row-level monitoring of image data being written to the image frame buffer unit, the subsequent image block processing control unit is triggered at an appropriate time point, ensuring no read / write conflicts in a single frame buffer.

[0054] like Figure 4 As shown, the image block processing unit includes at least: a cache interface module, a configuration interface module, a control management module, and a computation processing module.

[0055] The buffer interface module is used to read the frame data of the block image line by line from the image buffer unit; the configuration interface module provides functions such as programmable line blanking and frame blanking, block processing frame-level interrupt, and two-dimensional space address parameters; the control and management module is used to complete block processing control, line-level counting and line-level address mapping; and the arithmetic processing module is used to complete the signal processing of the block image.

[0056] In this embodiment, as Figure 4 As shown, the image segmentation processing unit can be configured with at least 7 feature parameters and at least 2 interaction signals. These are sent by the software at frame-level intervals through the cfg configuration channel. That is, the feature parameters of each frame of image data can be different or the same. In this embodiment, the specific values ​​of the feature parameters, the number of feature parameters, and the number of interaction signals for each frame of image are not specifically limited, and can be determined according to the actual situation.

[0057] The seven feature parameters are as follows:

[0058] initial_addr: The starting address of the image buffer unit;

[0059] wrap_addr: The wrap address of the image buffer unit;

[0060] `base_addr`: The address of the first line of the image data stored in the image buffer unit. Each image block has its own first line address, for example... Figure 5 The base_addr0 and base_addr1 shown are shown;

[0061] line_stride: The buffer interval for one line of data in the entire image. Here, the buffer interval line_stride is greater than or equal to the data storage size of one line of image, and K-byte alignment is constrained.

[0062] line_blank: Image line blanking, represented by the number of pixels between data rows;

[0063] line_num: Image height number of rows, represented by the number of rows in the entire frame;

[0064] `line_size`: The line length for image block processing, represented by the number of pixels processed within each line. Each image block has a unique line length. For example... Figure 5 The line_size0 and line_size1 are shown.

[0065] The two interaction signals are as follows:

[0066] sof: Image frame header start interrupt, which represents the start signal of a new whole frame of image and reports the interrupt trigger signal;

[0067] eof_blk: Image block processing completion interrupt, indicating that the current frame's image block processing is complete. Distinguish between the interrupt trigger signals reported for each image block, for example... Figure 5 The examples shown are eof_blk0 and eof_blk1.

[0068] like Figure 5 As shown, the effects of the above 7 feature parameters and 2 interaction signals on the image frame buffer are as follows:

[0069] The area between initial_addr and wrap_addr is the configured image buffer unit, with wrap_addr > initial_addr. It is not limited by the size of the image data. When the data line address of a single frame image buffer reaches wrap_addr, the control frame buffer line address automatically switches back to initial_addr.

[0070] base_addr0 and base_addr1 can be dynamically configured each frame, and both base_addr0 and base_addr1 are constrained between initial_addr and wrap_addr;

[0071] line_num serves as the common image row height for each image block. When the number of rows processed for each image block equals line_num, eof_blk is triggered accordingly.

[0072] This application embodiment utilizes the control features of the image block processing unit in terms of processing speed to programmable row blanking and frame blanking parameters. By adjusting the blanking time period, the processing speed of image reading can be flexibly controlled, thus better avoiding read-write conflicts.

[0073] Furthermore, the embodiments of this application utilize the control features of the image frame buffer unit and the image block processing unit in address management to programmably specify the buffer start address, wrapping address, hardware automatically switching addresses in the buffer space, and programmable frame first line base address, thereby ensuring the timely effectiveness of image processing for each frame.

[0074] Based on the above network topology, such as Figure 6 As shown, an image processing method is provided, which is applied to an electronic device. As an example, the electronic device may be a terminal, a server, etc., but this embodiment is not specifically limited.

[0075] like Figure 6 As shown, the image processing method includes the following steps:

[0076] S610: During the process of writing the current frame image data to the configured cache space, if it is found that the number of current frame image data rows written to the cache space is the specified number of data rows, then the first block of data in each data row is read from the cache space according to the data row writing order of the current frame image data, and the data rows of the current frame image data other than the specified data rows are continued to be written to the cache space.

[0077] For example, in this embodiment, the configured cache space is at least the storage space occupied by a single frame of image data. For instance, the configured cache space can be the storage space occupied by a single frame of image data, or it can be greater than the storage space occupied by a single frame of image data. This embodiment of the application is not specifically limited.

[0078] For example, if the cache space occupied by a single frame of image data is 1920*1080, then the configured cache space should be at least 1920*1080.

[0079] For example, in this embodiment, the specified number of data rows can be 40% of the total number of data rows in the current frame, or 50% of the total number of data rows in the current frame, or 70% of the total number of data rows in the current frame. This embodiment of the application does not specifically limit the number of data rows.

[0080] For example, when the current frame image data line count is 50 and the total includes 100 data lines, the specified number of data lines can be 40, 50, or 70.

[0081] For example, in this embodiment, the data row writing order can be from top to bottom, from left to right, from bottom to top, from left to right, or from top to bottom, from right to left, etc. This application embodiment does not specifically limit the data row writing order.

[0082] In this embodiment, in step S610, provided that the configured cache space is at least the storage space occupied by a single frame of image data, during the process of writing the current frame of image data to the cache space, if it is found that the number of current frame of image data lines written to the cache space is the specified number of data lines, then the first block of data in each data line is read from the cache space according to the data line writing order of the current frame of image data.

[0083] Here, the first block of data can be 40% of the data in the data row, or it can be 50% of the data in the data row, or it can be 60% of the data in the data row. This application embodiment does not specifically limit it.

[0084] S620: After reading the last data line of the current frame image data, read the second block of data in each data line according to the data line writing order.

[0085] For example, in this embodiment, the second block data in each data row includes at least the remaining data other than the first block data. As a preferred embodiment, the second block data and the first block data in each data row have overlapping areas, which ensures that the neighborhood expansion requirements brought about by image block processing are met, ensures that the processing of block image content is not affected, and improves the robustness of image caching and image processing.

[0086] In this embodiment, in step S620, after reading the last data line of the current frame image data, the second block data in each data line is read according to the data line writing order, thereby dividing the current frame image data into two parts and obtaining two block images, namely the left half image and the right half image of the current frame image data.

[0087] In this embodiment, when reading the block data in the data row of the current frame image data, the block data in the data row can be read and stored in a specified storage location. The specified storage location can be a location that is different from the cache space mentioned above. This embodiment of the application does not specifically limit the storage location.

[0088] This completes the work on... Figure 6 Description of the process shown.

[0089] pass Figure 6 As can be seen from the process shown, in this embodiment of the application, if it is found that the number of current frame image data lines written to the configuration cache space is the specified number of data lines during the process of writing the current frame image data to the configuration cache space, the block data is read and the current frame image data is continued to be written to the cache space while reading the block data. This decouples the image caching process from the image reading process, and it is not necessary to wait for a frame image to be completely cached before reading the image, thereby reducing the latency of image processing.

[0090] As an optional implementation of this application, when the cache space is the storage space occupied by a single frame of image data, the data row writing order is from top to bottom and from left to right, and the number of specified data rows is less than the total number of image data rows in the current frame; the first block of data or the second block of data in each data row is greater than or equal to half of the data in each data row, and less than the data in the entire data row.

[0091] Based on the above description, after the total amount of current frame image data is written to the buffer space, the image processing method further includes: while reading the block data, writing the next frame image data from the beginning position of the buffer space.

[0092] For example, in this embodiment, the process of caching images into the cache space is called the front-end, and the process of reading image data from the cache space is called the back-end. In this embodiment, the prerequisite for executing the image processing method is:

[0093] The entire image is input online and processed frame-by-frame.

[0094] The subsequent offline time-division acquisition of left and right sub-images is processed in half-frame row-level.

[0095] There is a frame blanking time between adjacent preceding image frames.

[0096] Post-processing image processing can be configured to perform line blanking and frame blanking.

[0097] The front-end hardware supports programmable row-level fast interrupts.

[0098] The processing speed of the back-end hardware is slightly higher than that of the front-end hardware.

[0099] The following is combined Figure 7 The example diagram shown illustrates the above image processing procedure, such as... Figure 7 As shown, the cache space is the storage space occupied by a single frame of image data. The bold lines represent the data row writing process of the image frame data, and the unbold lines represent the image frame data reading process. During image processing, the current frame image data is written to the row level interrupt of the previous stage to start the reading of the left half of the image in the subsequent stage. The right half of the image in the subsequent stage is switched to the blanking time period of the previous stage. This enables the support of image block processing using only the storage space occupied by a single frame of image data, and meets the overlapping requirements of image neighborhood processing.

[0100] This application's embodiment uses an example where the number of specified data rows is half the total number of data rows in the current frame image. Figure 7 As shown, the specific image processing procedure is as follows:

[0101] (1) When the number of rows of the current frame image data n written to the buffer space is half of the total number of rows of the current frame image data, the hardware triggers a row-level fast interrupt, the software starts, and the subsequent image block processing unit reads and processes the left half of the image according to the data row writing order of the current frame image data n, that is, from top to bottom and from left to right, while continuing to write the other half of the total number of rows of the current frame image data into the buffer space.

[0102] (2) After the current frame image data of the previous stage is completely written into the buffer space, the frame blanking time begins, and the subsequent image block processing unit follows to complete the processing of the left half of the image.

[0103] (3) After the left half of the image is processed, the end interrupt is triggered. The software starts the image block processing of the next stage and reads the right half of the image according to the data row writing order. The next frame of the image data of the current frame of the previous stage, n+1, follows and performs row-level write overwrite.

[0104] (4) After the right half of the image is processed, the software controls the waiting for the next frame of image data from the previous stage to trigger a fast row interrupt.

[0105] As an optional implementation of this application, when the cache space is greater than the storage space occupied by a single frame of image data and less than the storage space occupied by two frames of image data, the data row writing order is from top to bottom and from left to right, the specified number of data rows is the total number of image data rows in the current frame, and the first block of data or the second block of data in each data row is greater than or equal to half of the data in each data row and less than the data in the entire data row.

[0106] As an optional implementation of this application, after the total amount of current frame image data has been written to the cache space, the image processing method further includes:

[0107] Determine a specified position in the buffer space, which is the next buffer position after the current frame image data buffer position in the buffer space. Use the next buffer position as the current buffer position, write the next frame image data to the current buffer position in the buffer space, and when the buffer space is full, jump to the beginning position of the buffer space to continue writing the next frame image data.

[0108] For example, in this embodiment, based on the above description, when reading the current frame image data, the entire current frame image data can be read directly, or the left half of the current frame image data can be read first, and then the right half of the current frame image data can be read. This application embodiment does not specifically limit the method of reading the current frame image data, and can be determined according to the actual situation.

[0109] For example, in this embodiment, the process of caching the image into the cache space is called the front-end, and the process of reading the image data from the cache space is called the back-end. The prerequisite for executing this image processing method is:

[0110] Pre-amplifier hardware write control supports memory address wraparound

[0111] Post-stage hardware read control supports memory address wraparound

[0112] The starting address for writing the front-end image frame supports frame-level configuration.

[0113] The starting address for writing the front-end image frame supports frame-level configuration.

[0114] The processing speeds of the front-end and back-end hardware are relatively balanced between frames.

[0115] The following explanation uses the example of directly reading the entire current frame image data when reading the current frame image data, combined with... Figure 8 The example diagram shown illustrates the above image processing procedure, such as... Figure 8As shown, the configured cache space is larger than the storage space occupied by a single frame of image data but smaller than the storage space occupied by two frames of image data. The bold lines represent the data line writing process of image frame data, and the unbold lines represent the image frame data reading process. During image processing, the cache space is allocated to a size larger than that of a single frame of image data. During frame switching, the starting address of each frame of image data is offset within the entire cache space, reserved for the previous writing buffer, to avoid exceeding the subsequent reading and to balance the difference and fluctuation of the processing speed between the front and rear stages.

[0116] like Figure 8 As shown, the specific image processing procedure is as follows:

[0117] (1) After the current frame image data n of the previous stage is completely written into the buffer space, the hardware triggers the end interrupt and the software starts the processing flow of the subsequent image block processing unit.

[0118] (2) After the frame blanking time of the current frame image data of the previous stage has elapsed, the next frame image data n+1 is written to the next cache position of the current frame image data in the cache space, which does not affect the subsequent stage reading of the current frame image data.

[0119] (3) When the next frame of image data from the previous stage is written to the bottom of the cache space, the previous stage hardware control address wraps back to the beginning of the cache space to continue caching the next frame of image data.

[0120] (4) After the previous stage finishes writing the next frame of image data, the next stage finishes reading the current frame of image data and updates the frame start address.

[0121] As an optional implementation of this application, when the cache space is greater than the storage space occupied by a single frame of image data and less than the storage space occupied by two frames of image data, the data row writing order is from top to bottom and from left to right, the number of specified data rows is less than the total number of image data rows in the current frame, and the first block of data in each data row is greater than or equal to half of each data row and less than the data in the entire data row.

[0122] For example, in this embodiment, the cache space is larger than the storage space occupied by a single frame of image data but smaller than the storage space occupied by two frames of image data. A front-stage write row-level interrupt is used to initiate the reading of the left half of the image in the subsequent stage. The front-stage frame-level blanking time period is used to switch the reading of the right half of the image in the subsequent stage. During the frame-level switching process, the starting address of each frame of image data is offset within the entire cache space, supporting block processing without affecting the requirement for neighbor overlap. This can address the problem of insufficient front-stage frame blanking time and also adjust the reading processing speed of the subsequent stage, balancing the differences and fluctuations in the processing rates of the front and rear stages.

[0123] In this embodiment, the process of caching images into the cache space is called the front-end, and the process of reading image data from the cache space is called the back-end. This embodiment is a combination of the two embodiments described above. Therefore, the prerequisite for executing this process is a combination of the prerequisites of the two embodiments described above.

[0124] This application embodiment uses an example where the number of specified data rows is half the total number of data rows in the current frame image. Specifically:

[0125] (1) When the number of rows of the current frame image data n written to the buffer space is half of the total number of rows of the current frame image data, the hardware triggers a row-level fast interrupt, the software starts, and the subsequent image block processing unit reads and processes the left half of the image according to the data row writing order of the current frame image n data, that is, from top to bottom and from left to right, while continuing to write the other half of the total number of rows of the current frame image data into the buffer space.

[0126] (2) After the current frame image data of the previous stage is completely written into the buffer space, the frame blanking time is entered. The hardware triggers the end interrupt. The next frame image data n+1 is written into the buffer space at the next buffer position of the current frame image data buffer position. This does not affect the subsequent stage reading the current frame image data. At the same time, the subsequent stage image block processing unit follows up to complete the processing of the left half of the image.

[0127] (3) After the left half of the image is processed, the termination interrupt is triggered, and the software starts the image block processing and reads the right half of the image according to the data row writing order.

[0128] (4) After the right half of the image is processed, the software controls the waiting for the next frame of image data from the previous stage to trigger a fast line interrupt.

[0129] (5) When the next frame of image data from the previous stage is written to the bottom of the cache space, the previous stage hardware control address wraps back to the beginning of the cache space to continue caching the next frame of image data.

[0130] (6) After the previous stage finishes writing the next frame of image data, the next stage finishes reading the current frame of image data and updates the frame start address.

[0131] Corresponding to the embodiments of the aforementioned methods, embodiments of the present application also provide embodiments of the apparatus and the terminal to which it is applied.

[0132] like Figure 9 As shown, Figure 9 This is a block diagram illustrating an image processing apparatus according to an embodiment of this application. The image processing apparatus is applied to an electronic device and includes:

[0133] The first reading module is used to read the first block of data from each data line in the cache space according to the data line writing order of the current frame image data when it is found that the number of current frame image data lines written to the cache space is the specified number of data lines during the process of writing the current frame image data to the configured cache space.

[0134] The second reading module is used to read the second block of data in each data line in the order of data line writing after reading the last data line of the current frame image data; the second block of data in each data line includes at least the remaining data other than the first block of data.

[0135] As an optional implementation of this application, the second block of data in each data row overlaps with the first block of data.

[0136] As an optional implementation of this application, the cache space is the storage space occupied by a single frame of image data;

[0137] The data rows are written in the order from top to bottom and from left to right;

[0138] The specified number of data rows is less than the total number of image data rows in the current frame;

[0139] In each data row, the first or second block of data is greater than or equal to half the data in that data row, but less than the data in the entire data row.

[0140] As an optional implementation of this application, after the total amount of current frame image data has been written to the cache space, the method further includes:

[0141] While reading the block data, the next frame of image data is written from the beginning of the buffer space.

[0142] As an optional implementation of this application, the cache space is greater than the storage space occupied by a single frame of image data and less than the storage space occupied by two frames of image data.

[0143] The data rows are written in the order from top to bottom and from left to right;

[0144] The specified number of data rows is less than or equal to the total number of image data rows in the current frame;

[0145] In each data row, the first or second block of data is greater than or equal to half the data in that data row, but less than the data in the entire data row.

[0146] As an optional implementation of this application, the device further includes:

[0147] The specified position determination module is used to determine a specified position in the buffer space while reading block data. The specified position is the next buffer position after the buffer position of the current frame image data in the buffer space.

[0148] The jump module is used to take the next cache position as the current cache position, write the next frame image data into the current cache position in the cache space, and when the cache space is full, jump to the beginning position of the cache space to continue writing the next frame image data.

[0149] This completes the work on... Figure 9 Description of the block diagram shown.

[0150] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0151] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the solution in this specification according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0152] Correspondingly, embodiments of this application also provide Figure 9 The hardware structure diagram of the device shown is as follows: Figure 10 As shown, the electronic device can be a device implementing the above-described method. Figure 10 As shown, the hardware architecture includes a processor and memory.

[0153] The memory is used to store machine-executable instructions;

[0154] The processor is configured to read and execute machine-executable instructions stored in the memory to implement the image processing method embodiment shown above.

[0155] As one embodiment, the memory can be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, etc. For example, the memory can be volatile memory, non-volatile memory, or similar storage media. Specifically, the memory can be RAM (Random Access Memory), flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.

[0156] This concludes the process. Figure 10 Description of the electronic device shown.

[0157] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0158] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0159] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0160] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. An image processing method, characterized in that, The method is applied to an electronic device, and the method includes: During the process of writing the current frame image data to the configured cache space, if it is found that the number of current frame image data lines written to the cache space is the specified number of data lines, then the first block of data in each data line is read from the cache space according to the data line writing order of the current frame image data, and the data lines of the current frame image data other than the specified data lines are continued to be written to the cache space. After reading the first block of data in the last data line of the current frame image data, the second block of data in each data line is read in the order of data line writing; the second block of data in each data line includes at least the remaining data other than the first block of data.

2. The method according to claim 1, characterized in that, In each data row, the second block of data overlaps with the first block of data.

3. The method according to claim 1, characterized in that, The cache space is the storage space occupied by a single frame of image data; The data rows are written in the order from top to bottom and from left to right; The number of specified data rows is less than the total number of data rows in the current frame image; In each data row, the first or second block of data is greater than or equal to half the data in that data row, but less than the data in the entire data row.

4. The method according to claim 3, characterized in that, After the total amount of current frame image data has been written to the cache space, the method further includes: While reading the block data, the next frame of image data is written from the beginning of the cache space.

5. The method according to claim 1, characterized in that, The cache space is greater than the storage space occupied by a single frame of image data and less than the storage space occupied by two frames of image data. The data rows are written in the order from top to bottom and from left to right; The specified number of data rows is less than or equal to the total number of image data rows in the current frame; In each data row, the first or second block of data is greater than or equal to half the data in that data row, but less than the data in the entire data row.

6. The method according to claim 5, characterized in that, After the total amount of current frame image data has been written to the cache space, the method further includes: While reading the block data, a specified position in the cache space is determined. The specified position is the next cache position of the current frame image data in the cache space. The next cache position is used as the current cache position, and the next frame image data is written to the current cache position in the cache space; when the cache space is full, the process jumps to the beginning position of the cache space to continue writing the next frame image data.

7. An image processing apparatus, characterized in that, The device is used in an electronic device, and the device includes: The first reading module is used to read the first block of data from each data line in the cache space according to the data line writing order of the current frame image data when it is found that the number of current frame image data lines written to the cache space is a specified number of data lines during the process of writing current frame image data to the configured cache space. The second reading module is used to read the second block of data in each data line according to the data line writing order after reading the last data line of the current frame image data; the second block of data in each data line includes at least the remaining data other than the first block of data.

8. The apparatus according to claim 7, characterized in that, In each data row, the second block of data overlaps with the first block of data.

9. The apparatus according to claim 7, characterized in that, The cache space is the storage space occupied by a single frame of image data; The data rows are written in the order from top to bottom and from left to right; The number of specified data rows is less than the total number of data rows in the current frame image; In each data row, the first or second block of data is greater than or equal to half the data in that data row, but less than the data in the entire data row.

10. An electronic device, characterized in that, Electronic devices include: processors and memory; The memory is used to store machine-executable instructions; The processor is configured to read and execute machine-executable instructions stored in the memory to implement the method as claimed in any one of claims 1 to 6.

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