Semiconductor package structure and method of manufacturing the same

Abstract

The application discloses a semiconductor packaging structure and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor packaging structure comprises a substrate, a device layer formed on the substrate, a plastic packaging layer formed on the device layer, a metal column packaged in the plastic packaging layer, and a metal wire; one end of the metal wire is connected with one side of the metal column away from the device layer, and the other end of the metal wire is connected with a lead frame; one end of the metal column away from the metal wire is connected with a bonding pad of the device layer; the melting point of the metal column is greater than 350 DEG C; and the hardness of the metal column is greater than 17 HBW. The semiconductor packaging structure and the preparation method thereof cancel a redistribution layer, simplify a process, and can solve the reliability of subsequent high-temperature processes and wire bonding.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] Existing power semiconductor chips have high reliability requirements, so the die must be isolated from the outside world to prevent impurities in the air from corroding the circuits on the chip, causing a decline in electrical performance, and affecting the chip's reliability and lifespan.

[0003] For packaged semiconductor devices, considering the low thermal conductivity of sapphire substrates, poor heat dissipation can lead to poor chip performance in practical applications. Therefore, reducing substrate thickness is currently a common method to improve device heat dissipation. However, thinner substrates result in extremely poor wafer mechanical strength and significantly increased wafer warpage, which is very detrimental to subsequent processes. Furthermore, due to high stress within the substrate and gallium nitride epitaxial layer, thinner substrates make the wafer very fragile and prone to cracking. To address this, epoxy resin molding compounds and solder balls are commonly used as substrate support structures. This allows sapphire substrates to be thinned to very small sizes (below 150μm) without the risk of cracking. However, tin itself has issues such as being soft and having a low melting point, which can complicate subsequent wire bonding and high-temperature processes and reduce reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor packaging structure and its preparation method, which can solve the problems of reliability in subsequent high-temperature processes and wire bonding.

[0005] The embodiments of the present invention are implemented as follows:

[0006] In one aspect, this invention provides a semiconductor packaging structure, comprising a substrate, a device layer formed on the substrate, a molding compound formed on the device layer, a metal pillar encapsulated within the molding compound, and metal wires; one end of the metal wire is metal-connected to the side of the metal pillar opposite to the device layer, and the other end is metal-connected to a lead frame; the end of the metal pillar away from the metal wire is metal-connected to a pad of the device layer; the metal pillar has a melting point greater than 350°C and a hardness greater than 17 HBW. This semiconductor packaging structure and its fabrication method eliminate the redistribution layer, simplify the process, and solve the problems of subsequent high-temperature processes and wire bonding reliability.

[0007] Alternatively, the metal column can be made of copper, aluminum, or nickel.

[0008] Optionally, the diameter of the metal column is between 150 μm and 400 μm.

[0009] Optionally, the semiconductor packaging structure also includes a metal layer deposited on the side of the metal pillar away from the device layer, and the metal wires are metal-connected to the metal pillar through the metal layer.

[0010] Optionally, the metal layer includes a nickel layer and a gold layer formed on the nickel layer, with the nickel layer in contact with the metal pillar.

[0011] Optionally, the thickness of the nickel layer is between 200 nm and 1000 nm, and / or the thickness of the gold layer is between 100 nm and 500 nm.

[0012] Optionally, the thickness of the molding compound is between 50 μm and 250 μm.

[0013] Optionally, the encapsulation layer is made of epoxy resin.

[0014] Optionally, the thickness of the substrate is between 30 μm and 150 μm; and / or, the substrate material is sapphire, silicon, or silicon nitride.

[0015] Alternatively, the metal wire may be made of gold, copper, or aluminum.

[0016] In another aspect, the present invention provides a method for fabricating a semiconductor package structure, the method comprising: forming a device layer on a substrate; electroplating a metal pillar on the device layer, the metal pillar having a melting point greater than 350°C and a hardness greater than 17 HBW; forming a molding compound layer for encapsulating the metal pillar on the device layer; thinning the molding compound layer to expose the upper surface of the metal pillar; thinning the side of the substrate away from the device layer; and wire bonding on the side of the metal pillar away from the device layer to obtain a metal wire connected at one end to the metal pillar and at the other end to a lead frame.

[0017] Optionally, before thinning the side of the substrate away from the device layer, the method further includes forming a metal layer on the exposed metal pillars using a chemical plating process.

[0018] The beneficial effects of this invention include:

[0019] The semiconductor packaging structure provided in this application includes a substrate, a device layer formed on the substrate, a molding compound formed on the device layer, metal pillars encapsulated within the molding compound, and metal wires. One end of the metal wire is metal-connected to the side of the metal pillar away from the device layer, and the other end is metal-connected to a lead frame. The end of the metal pillar away from the metal wire is metal-connected to a pad on the device layer. The metal pillar has a melting point greater than 350°C and a hardness greater than 17 HBW. By forming metal pillars with a melting point greater than 350°C and a hardness greater than 17 HBW within the molding compound, this application improves the reliability of the metal pillars during subsequent wire bonding and high-temperature processes, thereby improving the quality of the semiconductor packaging structure. Furthermore, this application eliminates the redistribution layer formed on the molding compound, thus simplifying the process and improving the reliability of subsequent wire bonding. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in some embodiments of the present invention;

[0022] Figure 2 A flowchart illustrating a method for fabricating a semiconductor packaging structure according to some embodiments of the present invention;

[0023] Figure 3 This is one of the process diagrams for fabricating a semiconductor packaging structure provided in some embodiments of the present invention;

[0024] Figure 4 This is the second diagram illustrating the fabrication process of the semiconductor packaging structure provided in some embodiments of the present invention.

[0025] Figure 5 The third diagram illustrates the fabrication process of the semiconductor packaging structure provided in some embodiments of the present invention;

[0026] Figure 6 Figure 4 illustrates the fabrication process of a semiconductor packaging structure provided in some embodiments of the present invention.

[0027] Figure 7 The fifth diagram illustrates the fabrication process of a semiconductor packaging structure provided in some embodiments of the present invention.

[0028] Icons: 10-Substrate; 20-Device layer; 21-Pad; 30-Encapsulation layer; 40-Metal pillar; 50-Metal layer; 60-Metal wire. Detailed Implementation

[0029] The embodiments described below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the invention and will recognize the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of the invention and the appended claims.

[0030] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," there is no intermediate element. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "above another element" or "extending above another element," it may be directly on or directly extended to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly on another element" or "extending directly to another element," there is no intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0032] Related terms such as “below”, “above”, “upper”, “lower”, “horizontal”, or “vertical” are used herein to describe the relationship of one element, layer, or region to another, as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to cover different orientations of the device other than those depicted in the figures.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, when used herein, the term “comprising” indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that the terms used herein should be interpreted as having the same meaning as they would in the context of this specification and related fields, and not in an idealized or overly formal sense, unless expressly defined herein.

[0035] Please refer to Figure 1 This embodiment provides a semiconductor packaging structure, which includes a substrate 10, a device layer 20 formed on the substrate 10, a molding compound 30 formed on the device layer 20, a metal pillar 40 encapsulated within the molding compound 30, and a metal wire 60. One end of the metal wire 60 is metal-connected to the side of the metal pillar 40 away from the device layer 20, and the other end is metal-connected to a lead frame (not shown). The end of the metal pillar 40 away from the metal wire 60 is metal-connected to a pad 21 of the device layer 20. The melting point of the metal pillar 40 is greater than 350°C, and the hardness of the metal pillar 40 is greater than 17 HBW. This semiconductor packaging structure and its fabrication method eliminate the redistribution layer, simplify the process, and solve the problems of subsequent high-temperature processes and wire bonding reliability.

[0036] The aforementioned device layer 20 is located on the substrate 10, and the side of the device layer 20 facing away from the substrate 10 has pads 21, such as... Figure 1 As shown. This application does not limit the material of the substrate 10, and those skilled in the art can choose a suitable material. For example, the material of the substrate 10 can be sapphire, silicon, or silicon nitride, etc.

[0037] Optionally, the thickness of the substrate 10 is between 30 μm and 150 μm. For example, the thickness of the substrate 10 can be 30 μm, 50 μm, 80 μm, 100 μm, 150 μm, etc. Those skilled in the art can set the specific thickness of the substrate 10 within the above range as needed.

[0038] The aforementioned metal pillar 40 is located on the device layer 20, and the metal pillar 40 is metal-connected to the pad 21 of the device layer 20. In this way, the device layer 20 can conduct electricity through the pad 21 and the metal pillar 40.

[0039] In this embodiment, the melting point of the metal pillar 40 is greater than 350°C. Exemplarily, the melting point of the metal pillar 40 can be 400°C, 660°C, 1064°C, 1084°C, or 1453°C, etc. This application uses a metal pillar 40 with a melting point greater than 350°C, thus preventing the metal pillar 40 from melting during subsequent high-temperature processing of the device, thereby affecting the reliability of the semiconductor packaging structure.

[0040] Furthermore, the metal pillar 40 of this application has a hardness greater than 17 HBW. For example, the hardness of the metal pillar 40 can be 18 HBW, 20 HBW, 25 HBW, or 30 HBW, etc. This application uses a metal pillar 40 with a hardness greater than 17 HBW, which effectively reduces defects such as pitting of the metal pillar 40 during subsequent wire bonding processes in the semiconductor packaging structure, thereby improving the reliability of the device.

[0041] In this embodiment, the material of the metal column 40 can be copper, aluminum, or nickel, etc. Of course, the above-mentioned materials are only examples given in this application and are not intended to limit the metal column 40 of this application. Those skilled in the art can also choose other materials that meet the requirements, as long as the melting point of the metal column 40 is greater than 350°C and the hardness is greater than 17 HBW.

[0042] The aforementioned molding compound 30 is located in the device layer 20, and it encapsulates the metal pillar 40 within it, thus preventing dust, moisture, and other contaminants from affecting the device. In this embodiment, the molding compound 30 may optionally be made of epoxy resin.

[0043] In addition, in this embodiment, the thickness of the molding compound 30 is between 50 μm and 250 μm. For example, the thickness of the molding compound 30 is 50 μm, 70 μm, 80 μm, 100 μm, 150 μm, 200 μm, or 250 μm, etc.

[0044] This application eliminates the redistribution layer formed on the molding layer, and instead makes the metal conductor 60 and the metal post 40 metally connected, simplifying the process.

[0045] The metal wire 60 is connected at one end to the metal post 40 and at the other end to the metal lead frame via a wire bonding process. In this embodiment, the metal wire 60 can be made of gold, copper, or aluminum, etc.

[0046] In addition, in this embodiment, the semiconductor packaging structure further includes a metal layer 50 deposited on the side of the metal pillar 40 facing away from the device layer 20. The metal wire 60 is metallically connected to the metal pillar 40 through the metal layer 50. The metal layer 50 can be used to conduct electricity from the pads 21 of the device layer 20 to the package pins. When the metal layer 50 is formed by the metallization process, unlike conventional PVD or vapor deposition methods, after the metallization is completed, the metal layer 50 is only formed on the metal pillar 40 and not on the molding compound 30. Thus, this application can save steps by at least eliminating the etching process.

[0047] It should be noted that the metal layer 50 can, on the one hand, provide some protection for the metal pillar 40 and prevent it from oxidizing; on the other hand, it can achieve good welding performance and increase the bonding strength of the metal wire 60.

[0048] In summary, the semiconductor packaging structure provided in this application includes a substrate 10, a device layer 20 formed on the substrate 10, a molding compound 30 formed on the device layer 20, metal pillars 40 encapsulated within the molding compound 30, and metal wires 60. One end of the metal wire 60 is metal-connected to the side of the metal pillar 40 away from the device layer 20, and the other end is metal-connected to a lead frame (not shown). The end of the metal pillar 40 away from the metal wire 60 is metal-connected to a pad 21 of the device layer 20. The melting point of the metal pillar 40 is greater than 350°C, and the hardness of the metal pillar 40 is greater than 17 HBW. By forming metal pillars 40 with a melting point greater than 350°C and a hardness greater than 17 HBW within the molding compound 30, this application improves the reliability of the metal pillars 40 during subsequent wire bonding and high-temperature processes, thereby improving the quality of the semiconductor packaging structure. In addition, this application eliminates the redistribution layer formed on the molding compound 30, which simplifies the process and improves the reliability of subsequent wire bonding.

[0049] Optionally, the diameter of the metal column 40 is between 150 μm and 400 μm. For example, the diameter of the metal column 40 can be 150 μm, 200 μm, 300 μm, or 400 μm, etc. Those skilled in the art can select the specific diameter value of the metal column 40 within the above range as needed, and this application does not impose any restrictions.

[0050] Furthermore, in this embodiment, the metal layer 50 includes a nickel layer and a gold layer formed on the nickel layer, with the nickel layer in contact with the metal pillar 40. This allows for direct wire bonding on the gold layer of the metal layer 50 during subsequent wire bonding operations.

[0051] For example, the nickel-gold layer described above is achieved using a nickel immersion gold process, with the nickel layer located on the metal pillar 40 and the gold layer located on top of the nickel layer. Optionally, the thickness of the nickel layer is between 200 nm and 1000 nm. For example, the thickness of the nickel layer can be 200 nm, 500 nm, 700 nm, 1000 nm, etc.

[0052] The thickness of the gold layer is between 100 nm and 500 nm. For example, the thickness of the gold layer can be 100 nm, 300 nm, or 500 nm, etc.

[0053] Please refer to Figure 2 As shown, another aspect of the present invention provides a method for fabricating a semiconductor package structure, the method comprising the following steps:

[0054] S100, Form a device layer 20 on the substrate 10, such as Figure 3 As shown.

[0055] S200, Electroplating metal pillars 40 on device layer 20. The melting point of metal pillars 40 is greater than 350℃, and the hardness of metal pillars 40 is greater than 17HBW. Figure 4 As shown.

[0056] It should be noted that before electroplating the metal pillars 40 on the device layer 20, a seed layer can be sputtered first, and then the metal pillars 40 can be electroplated.

[0057] The metal column 40 can be made of aluminum, copper, or nickel, etc.

[0058] The height of the metal column 40 in step S200 can be between 80 μm and 250 μm, and the diameter of the metal column 40 can be between 150 μm and 400 μm.

[0059] S300, A molding layer 30 for forming encapsulation metal pillars 40 is formed on the device layer 20, such as Figure 5 As shown.

[0060] The molding layer 30 can be made of epoxy resin, and its thickness can be between 100μm and 300μm.

[0061] S400, The molding compound 30 is thinned to expose the upper surface of the metal pillar 40, such as... Figure 6 As shown.

[0062] Specifically, the thickness of the thinned molding layer 30 is between 50 μm and 250 μm, and correspondingly, the height of the metal pillar 40 is between 50 μm and 250 μm. The height of the metal pillar 40 is the same as the thickness of the thinned molding layer 30.

[0063] It should be noted that after step S400 is completed, the washing and spin-drying steps can be performed.

[0064] S500, A metal layer 50 is formed on the exposed metal pillar 40 by a chemical plating process, such as Figure 7 As shown.

[0065] In this embodiment, the metal layer 50 includes a nickel layer formed on the metal pillar 40 by a chemical plating process and a gold layer formed on the nickel layer by a chemical plating process. This application forms the metal layer 50 by a chemical plating process, allowing the metal layer 50 to be formed directly on the metal pillar 40 instead of the molding compound 30, thus eliminating the need for subsequent etching processes. Furthermore, the formed metal layer 50 provides some protection to the metal pillar 40, preventing oxidation, and can increase the bonding strength of the subsequent metal wires 60.

[0066] The thickness of the nickel layer is between 200nm and 1000nm, and the thickness of the gold layer is between 100nm and 500nm.

[0067] S600, the side of the substrate 10 facing away from the device layer 20 is thinned, such as... Figure 7 As shown.

[0068] It should be noted that, in this embodiment, the thickness of the thinned substrate 10 is between 30 μm and 150 μm.

[0069] S700, wire bonding is performed on the side of the metal pillar 40 away from the device layer 20 to obtain a metal wire 60 with one end connected to the metal pillar 40 and the other end connected to the lead frame.

[0070] In this embodiment, the material of the metal wire 60 can be gold, copper, or aluminum, etc.

[0071] It should be noted that when the semiconductor package structure obtained has no metal layer 50, the wire bonding process in step S700 above is to directly bond wires on the metal pillar 40 so that one end of the metal wire 60 is directly connected to the metal pillar 40 and the other end is connected to the lead frame; when the semiconductor package structure obtained has a metal layer 50, the wire bonding process in step S700 above is to directly bond wires on the metal layer 50 so that one end of the metal wire 60 is connected to the metal pillar 40 through the metal layer 50 and the other end is connected to the lead frame.

[0072] In addition, in this embodiment, after step S600 and before step S700, the semiconductor packaging structure fabrication method can further perform dicing and chip mounting processes as needed, and after the wire bonding process in step S700, electroplating, dicing, and other processes can continue to be performed. The specific process steps and their order can be determined by those skilled in the art according to actual needs, and this application does not impose any restrictions.

[0073] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0074] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A semiconductor packaging structure, characterized in that, The package includes a substrate, a device layer formed on the substrate, a molding compound formed on the device layer, a metal pillar encapsulated within the molding compound, and metal wires. One end of the metal wire is metal-connected to the side of the metal pillar away from the device layer, and the other end is metal-connected to a lead frame. The end of the metal pillar away from the metal wire is metal-connected to a pad of the device layer. The metal pillar has a melting point greater than 350°C, a hardness greater than 17 HBW, and is made of aluminum or nickel. The diameter of the metal pillar is between 150 μm and 400 μm. The semiconductor package structure also includes a metal layer plated on the side of the metal pillar away from the device layer. The metal wires are metal-connected to the metal pillar through the metal layer. The metal layer includes a nickel layer and a gold layer formed on the nickel layer. The nickel layer is in contact with the metal pillar. The thickness of the substrate is between 30 μm and 150 μm.

2. The semiconductor packaging structure according to claim 1, characterized in that, The thickness of the nickel layer is between 200 nm and 1000 nm, and / or the thickness of the gold layer is between 100 nm and 500 nm.

3. The semiconductor packaging structure according to claim 1, characterized in that, The thickness of the encapsulation layer is between 50 μm and 250 μm; and / or, the material of the encapsulation layer is epoxy resin.

4. The semiconductor packaging structure according to claim 1, characterized in that, The substrate is made of sapphire, silicon, or silicon nitride.

5. The semiconductor packaging structure according to claim 1, characterized in that, The metal wire is made of gold, copper, or aluminum.

6. A method for fabricating a semiconductor packaging structure, characterized in that, include: Forming a device layer on a substrate; Metal pillars are electroplated on the device layer. The metal pillars have a melting point greater than 350°C, a hardness greater than 17HBW, and are made of aluminum or nickel. The diameter of the metal pillars is between 150μm and 400μm. A molding compound is formed on the device layer to encapsulate the metal pillar; The molding layer is thinned to expose the upper surface of the metal pillar; A metal layer is formed on the exposed metal pillar by a chemical plating process, the metal layer comprising a nickel layer and a gold layer formed on the nickel layer; The side of the substrate facing away from the device layer is thinned, and the thickness of the substrate is between 30 μm and 150 μm; A wire is formed on the side of the metal pillar away from the device layer to obtain a metal wire with one end connected to the metal pillar and the other end connected to the lead frame; wherein the metal wire is metal-connected to the metal pillar through the metal layer, and the nickel layer is in contact with the metal pillar.

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