Semiconductor test structure and method of forming the same

Abstract

A semiconductor test structure and a method of forming the same, wherein the semiconductor test structure comprises: a substrate; an interlayer dielectric layer on the substrate; a structure under test in the interlayer dielectric layer; a ring structure in the interlayer dielectric layer, the ring structure surrounding the structure under test, a top surface of the ring structure being flush with a top surface of the structure under test, a bottom surface of the ring structure being lower than a bottom surface of the structure under test; and an opening in the ring structure, the opening penetrating the ring structure in a direction perpendicular to the top surface of the ring structure. The semiconductor test structure reduces water vapor intrusion around the test components, and improves the authenticity and accuracy of electromigration test results.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor testing structure and its formation method. Background Technology

[0002] In semiconductor package-level reliability testing, electromigration (EM) testing determines the reliability of semiconductor test components by detecting voids or hillocks that occur in the semiconductor test components under the influence of an electric field.

[0003] In electromigration testing, semiconductor test components are diced and packaged before being tested by the testing machine. However, there is a certain exposure time between dicing and testing of the semiconductor test components. During this process, external moisture can easily penetrate the semiconductor test components, leading to a deterioration in their electromigration performance and severely affecting the authenticity and accuracy of the electromigration test.

[0004] Currently, only in some advanced process technologies below 28 nanometers can moisture intrusion be prevented by establishing a fully enclosed protective ring structure around the entire semiconductor test component, and the fabrication cost of such semiconductor test structures is high. Furthermore, for semiconductor test structures in general processes, the fabrication technology still cannot solve the problem of moisture intrusion into the semiconductor test component, thus affecting the authenticity and accuracy of electromigration tests. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor test structure and its formation method, which reduces the intrusion of moisture around the semiconductor test component and improves the authenticity and accuracy of electromigration testing.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor test structure, comprising: a substrate; an interlayer dielectric layer on the substrate; a structure under test (SUT) located within the interlayer dielectric layer; an annular structure located within the interlayer dielectric layer, the annular structure surrounding the SUT, the top surface of the annular structure being flush with the top surface of the SUT, and the bottom surface of the annular structure being lower than the bottom surface of the SUT; and an opening located within the annular structure, the opening penetrating the annular structure in a direction perpendicular to the top surface of the annular structure.

[0007] Optionally, the structure under test includes the line structure under test.

[0008] Optionally, a test ring structure is located between the structure under test and the ring structure, the test ring structure surrounding the structure under test.

[0009] Optionally, the test line structure includes an inner test line structure and an outer test line structure located on the surface of the inner test line structure.

[0010] Optionally, the inner layer test line structure is made of copper; the outer layer test line structure is made of tantalum and tantalum nitride, or a combination of both.

[0011] Optionally, the number of the ring structures is equal to 1 or 2.

[0012] Optionally, when the number of the ring structures is equal to 2, the ring structures are arranged in a concentric ring structure.

[0013] Optionally, the annular structure includes a connecting ring and a virtual ring located on the top surface of the connecting ring, the top surface of the virtual ring being flush with the top surface of the structure under test, and the bottom surface of the virtual ring being flush with the bottom surface of the structure under test.

[0014] Optionally, the material of the ring structure includes copper.

[0015] Optionally, the interlayer dielectric layer includes: a first dielectric structure on the substrate, a second dielectric structure on the first dielectric structure, and a third dielectric structure on the second dielectric structure; the structure under test and the annular structure are located within the second dielectric structure.

[0016] Optionally, the second dielectric structure includes: a first barrier layer located on the first dielectric structure, a first dielectric layer located on the first barrier layer, and a second dielectric layer located on the first dielectric layer, wherein the top surface of the first barrier layer is higher than the bottom surface of the annular structure.

[0017] Optionally, the material of the first dielectric structure includes a low-k material or an ultra-low-k material; the material of the first dielectric layer includes a low-k material or an ultra-low-k material; the material of the second dielectric layer includes a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5.

[0018] Optionally, the material of the first barrier layer includes nitrides.

[0019] Optionally, the semiconductor test structure further includes an electrical interconnect structure located within the first dielectric structure, the electrical interconnect structure being electrically connected to the structure under test.

[0020] Optionally, the third dielectric structure includes: a second barrier layer located on the second dielectric structure and a third dielectric layer located on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.

[0021] Optionally, the material of the second barrier layer includes nitrides.

[0022] Optionally, the material of the third dielectric layer includes a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5.

[0023] Optionally, the semiconductor test structure further includes an electrical interconnect structure located within the third dielectric layer, the electrical interconnect structure being electrically connected to the structure under test.

[0024] Optionally, the substrate includes a substrate, a device layer located on the substrate, and an interconnect layer connecting the device layer.

[0025] Accordingly, the present invention also provides a method for forming a semiconductor test structure, comprising: providing a substrate; forming an interlayer dielectric layer, a structure under test located within the interlayer dielectric layer, and an annular structure located within the interlayer dielectric layer on the substrate, wherein the annular structure surrounds the structure under test, the top surface of the annular structure is flush with the top surface of the structure under test, the bottom surface of the annular structure is lower than the bottom surface of the structure under test, and the annular structure has an opening that penetrates the annular structure in a direction perpendicular to the top surface of the annular structure.

[0026] Optionally, the interlayer dielectric layer includes: a first dielectric structure on the substrate, a second dielectric structure on the first dielectric structure, and a third dielectric structure on the second dielectric structure; the structure under test and the annular structure are located within the second dielectric structure.

[0027] Optionally, the method for forming the interlayer dielectric layer, the structure under test, and the ring structure includes: forming a first dielectric structure on the substrate; forming a second dielectric structure and the structure under test and the ring structure located within the second dielectric structure on the first dielectric structure; and forming a third dielectric structure on the second dielectric structure, the structure under test, and the ring structure.

[0028] Optionally, the second dielectric structure includes: a first barrier layer located on the first dielectric structure, a first dielectric layer located on the first barrier layer, and a second dielectric layer located on the first dielectric layer, wherein the bottom surface of the annular structure is lower than the top surface of the first barrier layer.

[0029] Optionally, the third dielectric structure includes: a second barrier layer located on the second dielectric structure and a third dielectric layer located on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] In the semiconductor test structure, the annular structure surrounds the structure under test (SUT), with its top surface flush with the top surface of the SUT and its bottom surface lower than the bottom surface of the SUT. Therefore, the annular structure surrounds the four sides of the SUT, blocking moisture from entering from the sides of the SUT within the interlayer dielectric layer. This reduces the impact of moisture intrusion on the electromigration performance of the SUT, improving the authenticity and accuracy of the electromigration test results. Furthermore, by selectively adding the annular structure to moisture-sensitive test components, instead of establishing a fully enclosed protective structure around all test components, manufacturing costs are saved, and the versatility of the manufacturing process is improved. Additionally, in the chemical mechanical polishing (CMP) process of the semiconductor test structure fabrication, the annular structure, with its better rigidity and larger surface area, provides better mechanical support to the SUT from all directions, thus improving the polishing effect of the CMP process and effectively reducing the occurrence of cracks in the semiconductor test structure during dicing.

[0032] Furthermore, the number of the ring structures is equal to 1 or 2. By increasing the number of the ring structures, a multi-layered barrier structure can be formed around the structure under test, thereby better reducing the intrusion of external moisture into the structure under test from the side, and further improving the authenticity and accuracy of the electromigration test results.

[0033] In the method for preparing the semiconductor test structure, an annular structure is formed that surrounds the structure under test, with the top surface of the annular structure flush with the top surface of the structure under test and the bottom surface of the annular structure lower than the bottom surface of the structure under test. This blocks moisture from entering from the side of the structure under test, reduces the impact of moisture intrusion on the electromigration performance of the structure under test, and improves the authenticity and accuracy of the electromigration test results. Attached Figure Description

[0034] Figure 1 and Figure 2 A schematic diagram of an embodiment of a semiconductor testing structure;

[0035] Figures 3 to 7 This is a schematic diagram of the semiconductor test structure formation process in one embodiment of the present invention;

[0036] Figure 8 and Figure 9 This is a schematic diagram of the formation process of a semiconductor test structure according to another embodiment of the present invention. Detailed Implementation

[0037] As described in the background section, currently only in some advanced process technologies can moisture intrusion be prevented by establishing a fully enclosed protective ring structure around the overall semiconductor test component, and the fabrication cost of such semiconductor test structures is high. Furthermore, for semiconductor test structures in general processes, the current fabrication technology still cannot solve the problem of moisture intrusion into the semiconductor test component, thus affecting the authenticity and accuracy of electromigration tests.

[0038] Figure 1 and Figure 2 This is a schematic diagram of an embodiment of a semiconductor testing structure. Figure 1 for Figure 2 Top view along direction P, Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the AA' direction.

[0039] Please refer to Figure 1 and Figure 2 The semiconductor test structure includes: a structure under test (SUT) 100, which includes a copper layer 104 and a tantalum layer 105 on the surface of the copper layer 104; a plurality of virtual lines 101 located outside the SUT 100, which are placed parallel to the SUT 100; an upper barrier layer 106 located above the SUT 100, the bottom surface of which is in contact with the top surface of the SUT 100; a lower barrier layer 107 located below the SUT 100, the top surface of which is lower than the bottom surface of the SUT 100; and an interlayer dielectric layer 103 located between the upper barrier layer 106 and the lower barrier layer 107.

[0040] It should be noted that, for ease of understanding, Figure 1 The top view shown does not include the upper blocking layer 106 and the lower blocking layer 107.

[0041] In electromigration testing, the semiconductor test structure undergoes a certain exposure time from cutting to testing. During this process, moisture from the external environment enters the interlayer dielectric layer 103. Since the side and bottom surfaces of the structure under test 100 are in contact with the interlayer dielectric layer 103, the moisture intruding from the side of the interlayer dielectric layer 103 easily diffuses to the side and bottom surfaces of the structure under test 100. The tantalum layer 105 on the surface of the structure under test 100 oxidizes upon contact with the moisture, leading to enhanced interfacial scattering between the copper layer 104 and the tantalum layer 105, thus deteriorating the overall electromigration performance of the structure under test 100. Furthermore, when moisture passes through the tantalum layer 105 and enters the copper layer 104, it oxidizes the copper layer 104, destroying the dense structure of metallic copper and forming a loose copper oxide structure, making electron migration easier. This further deteriorates the overall electromigration performance of the structure under test 100, affecting the authenticity and accuracy of the electromigration test.

[0042] To address the aforementioned problems, this invention provides a semiconductor test structure comprising an annular structure surrounding the structure under test. The annular structure blocks moisture from intruding into the structure under test from its side, thereby significantly reducing the impact of moisture intrusion on the performance of the structure under test and improving the authenticity and accuracy of electromigration test results.

[0043] To address the aforementioned problems, this invention provides a method for forming a semiconductor test structure. This method involves forming a ring-shaped structure surrounding the structure under test, which blocks moisture from intruding into the structure from the side, thereby significantly reducing the impact of moisture intrusion on the performance of the structure under test and improving the authenticity and accuracy of electromigration test results.

[0044] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Figures 3 to 6 This is a schematic diagram of the semiconductor test structure formation process in one embodiment of the present invention.

[0046] Please refer to Figure 3 A substrate 260 is provided; a first dielectric structure 251 is formed on the substrate 260.

[0047] In this embodiment, the substrate 260 is made of a semiconductor material. Specifically, the substrate 260 is made of silicon. In other embodiments, the substrate 260 is made of materials including silicon-germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc.

[0048] In other embodiments, the substrate includes a base, a device layer on the base, and an interconnect layer connecting the device layer.

[0049] In this embodiment, the constituent materials of the first dielectric structure 251 include low-k materials or ultra-low-k materials; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5. The formation process of the first dielectric structure 251 includes chemical vapor deposition or physical vapor deposition.

[0050] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 A cross-sectional view along the BB' direction. Figure 5 for Figure 4In a top view along the X direction, a second medium structure 252 is formed on the first medium structure 251, along with the structure under test 200 and the annular structure 201 located within the second medium structure 252. The annular structure 201 surrounds the structure under test 200, with its top surface flush with the top surface of the structure under test 200 and its bottom surface lower than the bottom surface of the structure under test 200. The annular structure 201 has an opening 204 that penetrates the annular structure 201 in a direction perpendicular to its top surface.

[0051] In this embodiment, the second dielectric structure 252 includes: a first barrier layer 221, a first dielectric layer 231 located on the first barrier layer 221, and a second dielectric layer 232 located on the first dielectric layer 231.

[0052] In this embodiment, the method for forming the semiconductor test structure further includes: forming a test ring structure 205 within the second dielectric structure 252, located between the structure under test 200 and the ring structure 201, wherein the test ring structure 205 surrounds the structure under test 200.

[0053] In this embodiment, the ring structure 201 includes a connecting ring 207 and a virtual ring 206 located on the top surface of the connecting ring 207.

[0054] The method for forming the second dielectric structure 252, the annular structure 201, the structure under test 200, and the test ring structure 205 includes: forming a first barrier layer 221 on the first dielectric structure 251; forming a first dielectric layer 231 on the first barrier layer 221; forming a first annular groove penetrating the first dielectric layer 231 and the first barrier layer 221 within the first dielectric layer 231 and the first barrier layer 221, the first annular groove exposing the top surface of the first dielectric structure 251; forming a connecting ring 207 within the first annular groove; forming a second dielectric layer 232 on the connecting ring 207 and the first dielectric layer 231; and forming a second annular groove penetrating the second dielectric layer 232 within the second dielectric layer 232. The system comprises a third annular groove and a first channel, wherein the second annular groove is located on the connecting ring, the first channel is located at the center of the area surrounded by the second annular groove, and the third annular groove is located between the first channel and the second annular groove; a test structure 200 is formed in the first channel, filling the first channel; a virtual ring 206 is formed in the second annular groove, the bottom surface of the virtual ring 206 is in contact with the top surface of the connecting ring 207, and the annular structure 201 formed by the connecting ring 207 and the virtual ring 206 has an opening 204, the opening 204 penetrating the annular structure 201 in a direction perpendicular to the top surface of the annular structure 201; and a test ring structure 205 is formed in the third annular groove, filling the third annular groove.

[0055] In this embodiment, the first barrier layer 221 is composed of nitrides. The formation process of the first barrier layer 221 includes chemical vapor deposition or physical vapor deposition.

[0056] The first dielectric layer 231 is composed of a low-k material or an ultra-low-k material; the low-k material has a k value less than 3, and the ultra-low-k material has a k value less than 2.5. The formation process of the first dielectric layer 231 includes chemical vapor deposition (CVD) or physical vapor deposition (PVD). The second dielectric layer 232 is composed of a low-k material or an ultra-low-k material; the formation process of the second dielectric layer 232 includes CVD or PVD.

[0057] The steps for forming the first annular trench include: forming a first photoresist pattern layer (not shown) on the surface of the first dielectric layer 231; using the first photoresist pattern layer as a mask, etching the first dielectric layer 231 and the first barrier layer 221 until the top surface of the first dielectric structure 251 is exposed, thereby forming a first annular trench that penetrates the first dielectric layer 231 and the first barrier layer 221.

[0058] In this embodiment, the etching process for the first dielectric layer 231 and the first barrier layer 221 is an anisotropic dry etching process.

[0059] In this embodiment, the forming process of the connecting ring 207 includes chemical vapor deposition or physical vapor deposition. The constituent material of the connecting ring 207 includes copper.

[0060] In this embodiment, the bottom surface of the connecting ring 207 is lower than the top surface of the first barrier layer 221. In other embodiments, the bottom surface of the connecting ring is flush with the top surface of the first barrier layer.

[0061] In this embodiment, the steps for forming the second annular trench, the third annular trench, and the first channel include: forming a second photoresist pattern layer (not shown) on the surface of the second dielectric layer 232; using the second photoresist pattern layer as a mask, etching the second dielectric layer 232 to form a second annular trench, a third annular trench, and a first channel penetrating the second dielectric layer 232, wherein the second annular trench exposes the top surface of the connecting ring 207 and the top surface of the first dielectric layer 231, and the third annular trench and the first channel expose the top surface of the first dielectric layer 231.

[0062] In this embodiment, the etching process for the second dielectric layer 232 is an anisotropic dry etching process.

[0063] In this embodiment, the virtual ring 206 is formed using a process including chemical vapor deposition or physical vapor deposition. The constituent material of the virtual ring 206 includes copper.

[0064] Since the virtual ring 206 and the connecting ring 207 are located on different layers, the virtual ring 206 and the connecting ring 207 may be fabricated using the same or different processes, and the virtual ring 206 and the connecting ring 207 may be made of the same or different materials. Therefore, the ring structure 201 can be applied to the test structure of more semiconductor devices, and the fabrication process of the ring structure 201 can be made more flexible, thereby expanding the applicability of the semiconductor test structure formation method.

[0065] In this embodiment, the structure under test 200 includes a test line structure, specifically, the test line structure is a metal interconnect. The test line structure includes an inner test line structure (not shown) and an outer test line structure (not shown) located on the surface of the inner test line structure.

[0066] The steps for forming the structure under test 200 include: forming an outer layer test line structure covering the sidewalls and bottom surface of the first channel within the first channel; and forming an inner layer test line structure that fills the first channel on the surface of the outer layer test line structure, thereby forming the structure under test 200.

[0067] The inner test line structure is made of copper, and the outer test line structure is made of tantalum. Because tantalum has excellent conductivity and the ability to block other atoms, and because tantalum is highly inert to copper, the outer test line structure made of tantalum is placed over the surface of the inner test line structure made of copper. This outer test line structure acts as a barrier layer, preventing copper diffusion and thus giving the test structure 200 better electrical performance. In other embodiments, the outer test line structure is made of tantalum nitride or a combination of tantalum and tantalum nitride.

[0068] In this embodiment, the length of the structure under test 200 ranges from 300 micrometers to 500 micrometers, and the width of the structure under test 200 ranges from 0.1 micrometers to 5 micrometers.

[0069] In this embodiment, the pattern projected onto the top surface of the substrate 260 by the virtual ring 206 in the annular structure 201 is denoted as the virtual ring projection pattern. The virtual ring projection pattern is a rectangular ring, and the width of the rectangular ring in the virtual ring projection pattern ranges from 0.1 micrometers to 5 micrometers. The pattern projected onto the top surface of the substrate 260 by the structure under test 200 is surrounded by the virtual ring projection pattern.

[0070] In this embodiment, the top surface of the virtual ring 206 is flush with the top surface of the structure under test 200, and the bottom surface of the virtual ring 206 is flush with the bottom surface of the structure under test 200.

[0071] In this embodiment, the pattern projected onto the top surface of the substrate 260 by the connecting ring 207 in the annular structure 201 is denoted as the connecting ring projection pattern. The connecting ring projection pattern is a rectangular ring, and the connecting ring 207 projection pattern is located within the range of the virtual ring 206 projection pattern. The width of the rectangular ring of the connecting ring projection pattern ranges from 0.1 micrometers to 5 micrometers, and the width of the rectangular ring of the connecting ring projection pattern is smaller than the width of the rectangular ring of the virtual ring projection pattern.

[0072] In other embodiments, the virtual ring and the pattern of the connecting ring projected onto the substrate surface include a circular ring, and the pattern of the structure under test projected onto the substrate surface is located at the center of the circular ring.

[0073] In this embodiment, the ring structure 201 formed by the connecting ring 207 and the virtual ring 206 surrounds the structure under test 200. The top surface of the ring structure 201 is flush with the top surface of the structure under test 200, and the bottom surface of the ring structure 201 is lower than the bottom surface of the structure under test 200.

[0074] In this embodiment, the number of the ring structures 201 is equal to 2. Each ring structure 201 is arranged in a concentric ring structure, and each ring structure 201 together surrounds the structure under test 200. The structure under test 200 is located at the center of the concentric ring structure, and the projection of each ring structure 201 on the top surface of the substrate 260 is a rectangular ring.

[0075] In other embodiments, the number of the ring structures is equal to 1.

[0076] In this embodiment, the test ring structure 205 is located between the structure under test 200 and the ring structure 201, and the test ring structure 205 surrounds the structure under test 200. The constituent material of the test ring structure 205 includes copper; the formation process of the test ring structure 205 includes chemical vapor deposition or physical vapor deposition.

[0077] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 A sectional view along the CC' direction. Figure 7 for Figure 6 A top view along the X direction shows a third medium structure 253 formed on the second medium structure 252, the structure under test 200, the annular structure 201, and the test ring structure 205.

[0078] In this embodiment, the third dielectric structure 253 includes: a second barrier layer 222 located on the second dielectric structure 252 and a third dielectric layer 243 located on the second barrier layer 222.

[0079] In this embodiment, the bottom surface of the second barrier layer 222 is flush with the top surface of the annular structure 201. The constituent material of the second barrier layer 222 includes nitrides. The formation process of the second barrier layer 222 includes chemical vapor deposition or physical vapor deposition.

[0080] The third dielectric layer 243 is composed of low-k or ultra-low-k materials; the low-k material has a k value less than 3, and the ultra-low-k material has a k value less than 2.5. The formation process of the third dielectric layer 243 includes chemical vapor deposition or physical vapor deposition.

[0081] In this embodiment, the semiconductor test structure further includes: after forming the third dielectric layer 243, forming an electrical interconnect structure 203 in the third dielectric layer 243, wherein the electrical interconnect structure 203 is electrically connected to the structure under test 200.

[0082] The third dielectric layer 243 includes a third dielectric layer region one (not shown) located in the second barrier layer 222 and a third dielectric layer region two (not shown) located on the third dielectric layer region one.

[0083] The steps for forming the electrical interconnect structure 203 include: after forming the second barrier layer 222, forming a third dielectric layer region 1 on the second barrier layer 222, forming a conductive plug 208 in the third dielectric layer region 1, the conductive plug 208 penetrating the second barrier layer 222, and one end of the conductive plug 208 being connected to the structure under test 200; forming a third dielectric layer region 2 on the third dielectric layer region 1; forming the electrical interconnect structure 203 in the third dielectric layer region 2, the electrical interconnect structure 203 being connected to the other end of the conductive plug 208, and the electrical interconnect structure 203 being electrically connected to the structure under test 200 through the conductive plug 208.

[0084] In this embodiment, the conductive plug 208 is made of copper or tungsten, and the conductive plug 208 is formed by chemical vapor deposition or physical vapor deposition.

[0085] The electrical interconnect structure 203 is made of copper, and the forming process of the electrical interconnect structure 203 includes chemical vapor deposition or physical vapor deposition.

[0086] It should be noted that, for ease of understanding, Figure 7 The top view shown does not include the third medium structure 253.

[0087] Accordingly, embodiments of the present invention also provide a semiconductor testing structure.

[0088] Please continue to refer to this. Figure 6 and Figure 7 The semiconductor test structure includes: a substrate 260; an interlayer dielectric layer 202 on the substrate 260; a structure under test 200 located within the interlayer dielectric layer 202; an annular structure 201 located within the interlayer dielectric layer 202, the annular structure 201 surrounding the structure under test 200, the top surface of the annular structure 201 being flush with the top surface of the structure under test 200, and the bottom surface of the annular structure 201 being lower than the bottom surface of the structure under test 200; and an opening 204 located within the annular structure 201, the opening 204 penetrating the annular structure 201 in a direction perpendicular to the top surface of the annular structure 201.

[0089] In this embodiment, the substrate 260 provides a process platform for the interlayer dielectric layer 202, the ring structure 201, and the structure under test 200. The constituent materials of the substrate 260 include silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc.

[0090] In other embodiments, the substrate includes a base, a device layer on the base, and an interconnect layer connecting the device layer.

[0091] In this embodiment, the structure under test 200 includes a test line structure, specifically, the test line structure is a metal interconnect. In semiconductor reliability testing, the electrical reliability of the structure under test 200 is determined by performing electromigration testing on it.

[0092] The test line structure includes an inner test line structure (not shown) and an outer test line structure (not shown) located on the surface of the inner test line structure. The inner test line structure is made of copper, and the outer test line structure is made of tantalum. Because tantalum has excellent conductivity and the ability to block other atoms, and because tantalum is highly inert to copper, the outer test line structure made of tantalum is placed over the surface of the inner test line structure made of copper. This outer test line structure acts as a barrier layer, preventing copper diffusion and thus giving the test structure 200 better electrical performance.

[0093] In other embodiments, the material constituting the outer test line structure includes tantalum nitride or a combination of tantalum and tantalum nitride.

[0094] In this embodiment, the length of the structure under test 200 ranges from 300 micrometers to 500 micrometers, and the width of the structure under test 200 ranges from 0.1 micrometers to 5 micrometers.

[0095] Please continue to refer to this. Figure 6 and Figure 7 The annular structure 201 surrounds the structure under test 200.

[0096] In this embodiment, the pattern projected onto the top surface of the substrate 260 by the annular structure 201 is a rectangular ring. The pattern projected onto the top surface of the substrate 260 by the structure under test 200 is surrounded by the rectangular ring. Therefore, the annular structure 201 surrounds the structure under test 200, thereby achieving the enclosure of the structure under test 200.

[0097] In other embodiments, the pattern projected onto the substrate surface by the annular structure includes a ring, and the pattern projected onto the substrate surface by the structure under test is located at the center of the ring, thereby causing the annular structure to surround the structure under test.

[0098] Please continue to refer to this. Figure 6The pattern of the annular structure 201 projected onto a plane perpendicular to the top surface of the substrate 260 is denoted as the first pattern, and the pattern of the structure under test 200 projected onto a plane perpendicular to the top surface of the substrate 260 is denoted as the second pattern. The second pattern is completely within the range of the first pattern, so the annular structure 201 achieves the enclosure of the four sides of the structure under test 200.

[0099] Since the annular structure 201 surrounds the four sides of the structure under test 200, it blocks external moisture from entering the structure under test 200 from the sides within the interlayer dielectric layer 202. This improves the stability of the structure under test 200 when exposed to air, reduces the impact of moisture intrusion on its electromigration performance, and enhances the authenticity and accuracy of the electromigration test results. Furthermore, in the chemical mechanical polishing process during semiconductor test structure fabrication, the annular structure 201 provides mechanical support for the structure under test 200. Due to its better rigidity and larger surface area, the annular structure 201 provides better mechanical support from all directions, effectively reducing the likelihood of cracks appearing during the dicing process and improving the polishing effect of the chemical mechanical polishing process.

[0100] In other embodiments, the semiconductor test structure includes several structures under test. By selectively applying the ring structure to moisture-sensitive structures under test, instead of establishing a fully enclosed protective structure around all test components, fabrication costs are saved and the versatility of the fabrication process is improved.

[0101] In this embodiment, the material of the annular structure 201 includes copper.

[0102] Please continue to refer to this. Figure 7 In this embodiment, an opening 204 is provided inside the annular structure 201, which makes the annular structure 201 an open circuit. Therefore, the annular structure 201 has no electrical properties, thus avoiding interference from the annular structure 201 to the test structure 200 during the electromigration test.

[0103] In this embodiment, the number of annular structures 201 is equal to two. Each annular structure 201 is arranged concentrically, surrounding the structure under test 200. The structure under test 200 is located at the center of the concentric surrounding structure. The projection of each annular structure 201 onto the top surface of the substrate 260 is a rectangular ring, and the spacing between the rectangular rings ranges from 0.1 micrometers to 5 micrometers. Because each annular structure 201 surrounds the sides of the structure under test 200 twice, it better reduces the intrusion of moisture into the structure under test 200, further improving the authenticity and accuracy of the electromigration test results of the structure under test 200.

[0104] In this embodiment, the two ring structures 201 are referred to as the first ring structure and the second ring structure, with the second ring structure surrounding the first ring structure. The first ring structure has a first line 231 and a second line 232 disposed opposite to each other, and the second ring structure has a third line 233 and a fourth line 234 disposed opposite to each other. The second line 232 is located between the first line 231 and the fourth line 234, such that the first line 231 and the fourth line 234 are separated by the second line 232, and the first line 231 is located between the third line 233 and the second line 232, with the third line 233 and the second line 232 separated by the first line 231.

[0105] Both the first and second annular structures have openings 204 penetrating the annular structure 201. The opening 204 within the first annular structure is designated as the first opening, and the opening 204 within the second annular structure is designated as the second opening. The first opening is located within the first line 231, and the second opening is located within the fourth line 234. This separation of the first and second openings by the second line 232 prevents external moisture from simultaneously passing through both openings during diffusion. This enhances the blocking ability of the annular structure 201 against external moisture and reduces the likelihood of external moisture intruding into the structure under test 200 from the side through the interlayer medium layer 202.

[0106] In another embodiment, the number of ring structures is equal to 1. The ring structures reduce external moisture intrusion into the structure under test from the side, and at the same time, make the semiconductor test structure simpler, thereby simplifying the fabrication process cost.

[0107] Please continue to refer to this. Figure 6The interlayer dielectric layer 202 includes: a first dielectric structure 251 located on the substrate 260, a second dielectric structure 252 located on the first dielectric structure 251, and a third dielectric structure 253 located on the second dielectric structure 252; the structure under test 200 and the annular structure 201 are located within the second dielectric structure 252.

[0108] In this embodiment, the constituent materials of the first dielectric structure 251 include low-k materials or ultra-low-k materials.

[0109] The second dielectric structure 252 includes: a first barrier layer 221 located on the first dielectric structure 251, a first dielectric layer 231 located on the first barrier layer 221, and a second dielectric layer 232 located on the first dielectric layer 231.

[0110] In this embodiment, the constituent material of the second dielectric layer 242 includes low-k materials or ultra-low-k materials.

[0111] Please continue to refer to this. Figure 6 In this embodiment, the ring structure 201 includes a connecting ring 207 and a virtual ring 206 located on the top surface of the connecting ring 207.

[0112] Specifically, the positions of the annular structure 201 and the structure under test 200 within the second dielectric structure 252 are as follows: the connecting ring 207 is located within the first dielectric layer 231 and the first barrier layer 221, and the bottom surface of the connecting ring 207 is in contact with the top surface of the first dielectric structure 251; the structure under test 200 is located within the second dielectric layer 232; the virtual ring 206 is located within the second dielectric layer 232, and the bottom surface of the virtual ring 206 is in contact with the top surface of the connecting ring 207; the annular structure 201 formed by the virtual ring 206 and the connecting ring 207 surrounds the structure under test 200.

[0113] In this embodiment, the top surface of the virtual ring 206 is flush with the top surface of the structure under test 200, and the bottom surface of the virtual ring 206 is flush with the bottom surface of the structure under test 200.

[0114] In this embodiment, the pattern projected onto the top surface of the substrate 260 by the connecting ring 207 is denoted as the connecting ring projection pattern, which is a rectangular ring. The pattern projected onto the top surface of the substrate 260 by the virtual ring 206 is denoted as the virtual ring projection pattern, which is also a rectangular ring. The connecting ring projection pattern is located within the range of the virtual ring projection pattern. The width of the rectangular ring of the connecting ring projection pattern ranges from 0.1 micrometers to 5 micrometers, and the width of the rectangular ring of the virtual ring projection pattern also ranges from 0.1 micrometers to 5 micrometers. The width of the rectangular ring of the connecting ring projection pattern is smaller than the width of the rectangular ring of the virtual ring projection pattern.

[0115] Please continue to refer to this. Figure 6 and Figure 7 In this embodiment, the semiconductor test structure further includes a test ring structure 205 located within the second dielectric layer 232. The test ring structure 205 is situated between the structure under test 200 and the ring structure 201, and surrounds the structure under test 200. The test ring structure 205 is used to detect metal extrusion on the structure under test 200, thereby monitoring the failure status of the structure under test 200.

[0116] Please continue to refer to this. Figure 6 The third dielectric structure 253 includes: a second barrier layer 222 located on the second dielectric structure 252 and a third dielectric layer 243 located on the second barrier layer 222.

[0117] In this embodiment, the material of the first barrier layer 221 includes nitrides; the material of the second barrier layer 222 includes nitrides. The material of the third dielectric layer 243 includes a low-k material or an ultra-low-k material.

[0118] In this embodiment, the pattern of the structure under test 200 projected onto the top surface of the first barrier layer 221 is located within the area of ​​the top surface of the first barrier layer 221, and the pattern of the structure under test 200 projected onto the bottom surface of the second barrier layer 222 is located within the area of ​​the bottom surface of the second barrier layer 222. The first barrier layer 221 is located below the structure under test 200, thereby reducing external moisture intrusion from the bottom surface of the structure under test 200. The second barrier layer 222 is located on the structure under test 200, thereby blocking external moisture intrusion from the top surface of the structure under test 200. The cooperation of the first barrier layer 221 and the second barrier layer 222 reduces the intrusion of external moisture into the structure under test 200 from a direction perpendicular to the top surface of the substrate 260, improving the authenticity and accuracy of the electromigration test results of the structure under test 200.

[0119] In this embodiment, the virtual ring 206, the connecting ring 207, the first barrier layer 221, and the second barrier layer 222 together constitute an enclosure of the structure under test 200 in various directions, thereby reducing the intrusion of water vapor from various directions into the structure under test 200, reducing the impact of water vapor intrusion on the electromigration performance of the structure under test 200, and improving the authenticity and accuracy of the electromigration test results of the structure under test 200.

[0120] In this embodiment, the top surface of the first barrier layer 221 is higher than the bottom surface of the annular structure 201 formed by the connecting ring 207 and the virtual ring 206, and the bottom surface of the second barrier layer 222 is flush with the top surface of the annular structure 201.

[0121] Please continue to refer to this. Figure 6 and Figure 7 In this embodiment, the semiconductor test structure further includes an electrical interconnect structure 203 located within the third dielectric layer 243, the electrical interconnect structure 203 being electrically connected to the structure under test 200.

[0122] In this embodiment, the third dielectric layer 243 includes a third dielectric layer region 1 (not shown) located on the second barrier layer 222 and a third dielectric layer region 2 (not shown) located on the third dielectric layer region 1.

[0123] Specifically, the electrical interconnect structure 203 is located within the second region of the third dielectric layer. The electrical interconnect structure 203 is located at both ends of the structure under test 200. The electrical interconnect structure 203 is electrically connected to the structure under test 200 via a conductive plug 208. The conductive plug 208 is located within the first region of the third dielectric layer and penetrates the second barrier layer 222. The material of the electrical interconnect structure 203 includes copper, and the material of the conductive plug 208 includes tungsten or copper.

[0124] The structure under test 200 is connected to an electromigration testing device (not shown) via the electrical interconnection structure 203, thereby enabling testing of the structure under test 200. The electromigration testing device includes: a first loading point and a second loading point, used to apply a test voltage to the structure under test 200, causing the current in the structure under test 200 to reach the test conditions; a first sensing point and a second sensing point, used to obtain the sensing voltage of the structure under test 200 under the test conditions. During the electromigration test, by applying a high voltage to the first loading point and the second loading point, a large current density is formed within the structure under test 200, accelerating electromigration within the structure under test 200, causing the structure under test 200 to fail more quickly, thereby measuring the failure time of the structure under test 200 under the test conditions.

[0125] Figure 8 and Figure 9This is a schematic diagram of the formation process of a semiconductor test structure according to another embodiment of the present invention.

[0126] Please refer to Figure 8 and Figure 9 , Figure 8 for Figure 9 A cross-sectional view along the DD' direction. Figure 9 for Figure 8 A top view along the Y direction shows a method for forming the semiconductor test structure, comprising: providing a substrate 360; forming a first dielectric structure 351 on the substrate 360; forming a second dielectric structure 352 on the first dielectric structure 351, and the structure under test 300, the annular structure 301, and the test ring structure 305 located within the second dielectric structure 352, wherein the test ring structure 305 surrounds the structure under test 300 and is located between the structure under test 300 and the annular structure 301. The annular structure 301 surrounds the structure under test 300. The top surface of the annular structure 301 is flush with the top surface of the structure under test 300, and the bottom surface of the annular structure 301 is lower than the bottom surface of the structure under test 300. The annular structure 301 has an opening 304 that penetrates the annular structure 301 in a direction perpendicular to the top surface of the annular structure 301. A third medium structure 353 is formed on the second medium structure 352, the structure under test 300, and the annular structure 301.

[0127] In this embodiment, the method, materials, and structure for forming the substrate 360, the first dielectric structure 351, the second dielectric structure 352, the third dielectric structure 353, the ring structure 301, the structure under test 300, the opening 304 of the ring structure 301, and the test ring structure 305 are respectively related to... Figures 3 to 7 The substrate 260, the first dielectric structure 251, the second dielectric structure 252, the third dielectric structure 253, the ring structure 201, the structure under test 200, the opening 204 of the ring structure 201, and the test ring structure 205 described herein are formed in the same way, using the same materials and structures, and will not be described again here.

[0128] In this embodiment, the second dielectric structure 352 includes: a first barrier layer 321 located on the first dielectric structure 351, a first dielectric layer 331 located on the first barrier layer 321, and a second dielectric layer 332 located on the first dielectric layer 331. The methods, materials, and structures for forming the first barrier layer 321, the first dielectric layer 331, and the second dielectric layer 332 described in this embodiment are respectively... Figures 3 to 7 The first barrier layer 221, the first dielectric layer 231, and the second dielectric layer 232 are formed in the same way, using the same materials and structures, and will not be described again here.

[0129] In this embodiment, the annular structure 301 includes a connecting ring 307 and a virtual ring 306 located on the top surface of the connecting ring 307. The method of forming the connecting ring 307 and the virtual ring 306 described in this embodiment, the materials used, and the structure are respectively... Figures 3 to 7 The connecting ring 207 and the virtual ring 206 are formed in the same way, with the same materials and structure, and will not be described again here.

[0130] In this embodiment, the third dielectric structure 353 includes: a second barrier layer 322 located on the second dielectric structure 352 and a third dielectric layer 343 located on the second barrier layer 322. The formation method, materials, and structure of the second barrier layer 322 and the third dielectric layer 343 described in this embodiment are respectively... Figures 3 to 7 The second barrier layer 222 and the third dielectric layer 243 are formed in the same way, with the same materials and structure, and will not be described again here.

[0131] In this embodiment, the method for forming the semiconductor test structure further includes: forming a test ring structure 305 within the second dielectric structure 352, located between the structure under test 300 and the ring structure 301, wherein the test ring structure 305 surrounds the structure under test 300. The method for forming the test ring structure 305, the materials used, and the structure described in this embodiment are similar to... Figures 3 to 7 The formation method, materials, and structure of the test ring structure 205 are the same, and will not be described again here.

[0132] In this embodiment, the semiconductor test structure further includes: after forming the first dielectric structure 351, forming an electrical interconnect structure 303 within the first dielectric structure 351, wherein the electrical interconnect structure 303 is electrically connected to the subsequently formed structure under test 300.

[0133] The steps for forming the electrical interconnect structure 303 include: after forming the first dielectric structure 351, forming the electrical interconnect structure 303 within the first dielectric structure 351; after forming the first dielectric layer 331 and the first barrier layer 321, forming a conductive plug 308 within the first dielectric layer 331, the conductive plug 308 penetrating the first barrier layer 321, one end of the conductive plug 308 being connected to the electrical interconnect structure 303; the structure under test 300 being formed on the conductive plug 308 and the first dielectric layer 331, the structure under test 300 being connected to the other end of the conductive plug 308, thereby electrically connecting the structure under test 300 to the electrical interconnect structure 303 through the conductive plug 308.

[0134] In this embodiment, the conductive plug 308 is made of copper or tungsten, and the conductive plug 308 is formed by chemical vapor deposition or physical vapor deposition.

[0135] The electrical interconnect structure 303 is made of copper, and the forming process of the electrical interconnect structure 303 includes chemical vapor deposition or physical vapor deposition.

[0136] It should be noted that, for ease of understanding, Figure 9 The top view shown does not include the third medium structure 353.

[0137] Accordingly, embodiments of the present invention also provide a semiconductor testing structure.

[0138] Please continue to refer to this. Figure 8 and Figure 9 The semiconductor test structure includes: a substrate 360; an interlayer dielectric layer 302 located on the substrate 360; a structure under test 300 located within the interlayer dielectric layer 302; an annular structure 301 located within the interlayer dielectric layer 302, the annular structure 301 surrounding the structure under test 300, the top surface of the annular structure 301 being flush with the top surface of the structure under test 300, and the bottom surface of the annular structure 301 being lower than the bottom surface of the structure under test 300; and an opening 304 located within the annular structure 301, the opening 304 penetrating the annular structure 301 in a direction perpendicular to the top surface of the annular structure 301.

[0139] In this embodiment, the materials and structures of the substrate 360, the annular structure 301, the structure under test 300, and the opening 304 of the annular structure 301 are respectively related to... Figure 6 and Figure 7 The substrate 260, the annular structure 201, the structure under test 200, and the opening 204 of the annular structure 201 are made of the same material and have the same structure, and will not be described again here.

[0140] In this embodiment, the interlayer dielectric layer 302 includes: a first dielectric structure 351 located on the substrate 360, a second dielectric structure 352 located on the first dielectric structure 351, and a third dielectric structure 353 located on the second dielectric structure 352; the structure under test 300 and the annular structure 301 are located within the second dielectric structure 352.

[0141] In this embodiment, the second dielectric structure 352 includes: a first barrier layer 321 located on the first dielectric structure 351, a first dielectric layer 331 located on the first barrier layer 321, and a second dielectric layer 332 located on the first dielectric layer 331. The materials and structures of the first dielectric structure 351, the first barrier layer 321, the first dielectric layer 331, and the second dielectric layer 332 in this embodiment are respectively... Figure 6 and Figure 7 The materials and structures of the first dielectric structure 251, the first barrier layer 221, the first dielectric layer 231, and the second dielectric layer 232 are the same, and will not be described again here.

[0142] The annular structure 301 includes a connecting ring 307 and a virtual ring 306 located on the top surface of the connecting ring 307. In this embodiment, the materials and structures of the connecting ring 307 and the virtual ring 306 are respectively... Figure 6 and Figure 7 The connecting ring 207 and the virtual ring 206 described herein are made of the same material and have the same structure, and will not be described again here.

[0143] The third dielectric structure 353 includes: a second barrier layer 322 located on the second dielectric structure 352 and a third dielectric layer 343 located on the second barrier layer 322. In this embodiment, the materials and structures of the second barrier layer 322 and the third dielectric layer 343 are respectively... Figure 6 and Figure 7 The second barrier layer 222 and the third dielectric layer 243 are made of the same material and have the same structure, so they will not be described again here.

[0144] In this embodiment, the semiconductor test structure further includes a test ring structure 305 located within the second dielectric layer 332. The test ring structure 305 is located between the structure under test 300 and the ring structure 301, and the test ring structure 305 surrounds the structure under test 300.

[0145] Please continue to refer to this. Figure 8 In this embodiment, the semiconductor test structure further includes an electrical interconnect structure 303 located within the first dielectric structure 351, the electrical interconnect structure 303 being electrically connected to the structure under test 300.

[0146] The bottom surface of the electrical interconnect structure 303 is in contact with the top surface of the substrate 360. The electrical interconnect structure 303 is located at both ends of the structure under test 300. The electrical interconnect structure 303 and the structure under test 300 are electrically connected through a conductive plug 308. The conductive plug 308 is located in the first dielectric layer 331 and penetrates the first barrier layer 321.

[0147] The electrical interconnect structure 303 is made of copper, and the conductive plug 308 is made of tungsten or copper.

[0148] The structure under test 300 is connected to an electromigration testing device (not shown) via the electrical interconnection structure 303, thereby testing the structure under test 300.

[0149] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor testing structure, characterized in that, include: Substrate; Interlayer dielectric layer located on the substrate; The structure under test located within the interlayer dielectric layer; A ring-shaped structure located within the interlayer dielectric layer surrounds the structure under test. The top surface of the ring-shaped structure is flush with the top surface of the structure under test, and the bottom surface of the ring-shaped structure is lower than the bottom surface of the structure under test. The ring-shaped structure is used to surround the four sides of the structure under test to block moisture from entering from the sides of the structure under test within the interlayer dielectric layer. An opening located within the annular structure, the opening penetrating the annular structure in a direction perpendicular to the top surface of the annular structure; The ring structure includes a connecting ring and a virtual ring located on the top surface of the connecting ring. The top surface of the virtual ring is flush with the top surface of the structure under test, and the bottom surface of the virtual ring is flush with the bottom surface of the structure under test. The bottom surface of the virtual ring is in contact with the top surface of the connecting ring. The interlayer dielectric layer includes: a first dielectric structure on the substrate, a second dielectric structure on the first dielectric structure, and a third dielectric structure on the second dielectric structure; the second dielectric structure includes: a first barrier layer on the first dielectric structure, a first dielectric layer on the barrier layer, and a second dielectric layer on the first dielectric layer; the structure under test and the virtual ring are located within the second dielectric layer, and the connecting ring is located within the first dielectric layer and the first barrier layer; The third medium structure includes: a second barrier layer located on the second medium structure and a third medium layer located on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.

2. The semiconductor test structure as described in claim 1, characterized in that, The structure under test includes the line structure under test.

3. The semiconductor test structure as described in claim 1, characterized in that, Also includes: A test ring structure is located between the structure under test and the ring structure, and the test ring structure surrounds the structure under test.

4. The semiconductor test structure as described in claim 2, characterized in that, The test line structure includes an inner test line structure and an outer test line structure located on the surface of the inner test line structure.

5. The semiconductor test structure as described in claim 4, characterized in that, The inner test line structure is made of copper; the outer test line structure is made of tantalum or a combination of tantalum nitride.

6. The semiconductor test structure as described in claim 1, characterized in that, The number of ring structures is equal to 1 or 2.

7. The semiconductor test structure as described in claim 6, characterized in that, When the number of the ring structures is equal to 2, the ring structures are arranged in a concentric ring structure.

8. The semiconductor test structure as described in claim 1, characterized in that, The material of the ring structure includes copper.

9. The semiconductor test structure as described in claim 1, characterized in that, The material of the first dielectric structure includes a low-k material or an ultra-low-k material; the material of the first dielectric layer includes a low-k material or an ultra-low-k material; the material of the second dielectric layer includes a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.

5.

10. The semiconductor test structure as described in claim 1, characterized in that, The material of the first barrier layer includes nitrides.

11. The semiconductor test structure as described in claim 1, characterized in that, Also includes: An electrical interconnect structure located within the first dielectric structure, wherein the electrical interconnect structure is electrically connected to the structure under test.

12. The semiconductor test structure as described in claim 1, characterized in that, The material of the second barrier layer includes nitrides.

13. The semiconductor test structure as described in claim 1, characterized in that, The material of the third dielectric layer includes low-k material or ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.

5.

14. The semiconductor test structure as described in claim 1, characterized in that, Also includes: An electrical interconnect structure located within the third dielectric layer, the electrical interconnect structure being electrically connected to the structure under test.

15. The semiconductor test structure as described in claim 1, characterized in that, The substrate includes a base, a device layer located on the base, and an interconnect layer connecting the device layer.

16. A method for forming a semiconductor test structure, characterized in that, include: Provide substrate; An interlayer dielectric layer, a structure under test (SUT) located within the interlayer dielectric layer, and an annular structure located within the interlayer dielectric layer are formed on a substrate. The annular structure surrounds the SUT, the top surface of the annular structure is flush with the top surface of the SUT, the bottom surface of the annular structure is lower than the bottom surface of the SUT, and the annular structure has an opening that penetrates the annular structure in a direction perpendicular to the top surface of the annular structure. The annular structure is used to surround the four sides of the structure under test to block water vapor from entering the interlayer medium layer from the sides of the structure under test. The interlayer dielectric layer includes: a first dielectric structure on the substrate, a second dielectric structure on the first dielectric structure, and a third dielectric structure on the second dielectric structure; the structure under test and the annular structure are located within the second dielectric structure. The method for forming the interlayer dielectric layer, the structure under test, and the ring structure includes: forming a first dielectric structure on the substrate; forming a second dielectric structure and the structure under test and the ring structure located within the second dielectric structure on the first dielectric structure; and forming a third dielectric structure on the second dielectric structure, the structure under test, and the ring structure. The ring structure includes a connecting ring and a virtual ring located on the top surface of the connecting ring. The top surface of the virtual ring is flush with the top surface of the structure under test, and the bottom surface of the virtual ring is flush with the bottom surface of the structure under test. The bottom surface of the virtual ring is in contact with the top surface of the connecting ring. The second dielectric structure includes: a first barrier layer located on the first dielectric structure, a first dielectric layer located on the barrier layer, and a second dielectric layer located on the first dielectric layer; the structure under test and the virtual ring are located within the second dielectric layer, and the connecting ring is located within the first dielectric layer and the first barrier layer; The third medium structure includes: a second barrier layer located on the second medium structure and a third medium layer located on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.

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