Overlay mark structures and methods of forming the same

Abstract

A mark structure for overlay measurement and a method for forming the mark structure, wherein the method comprises: providing a substrate, the substrate comprising a plurality of chip regions, each chip region comprising a structure region and at least one dummy structure region adjacent to the structure region, and each dummy structure region comprising at least one mark region; forming at least two layers of device layers on the substrate, each layer of device layers comprising a plurality of mark structures, and each mark structure in each layer of device layers being located on at least one mark region, the number of mark structures being sufficient to meet a high overlay accuracy requirement, increasing the freedom of overlay mark arrangement, and being conducive to improving the overlay measurement accuracy.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an overlay marking structure and a method for forming the same. Background Technology

[0002] Photolithography is a process that transfers a mask pattern onto a wafer through a series of steps, including alignment and exposure. In semiconductor chip manufacturing, multiple photolithography layers are typically required to complete the entire process. Overlay error (OVL) refers to the relative positional deviation between the current layer pattern and the previous layer pattern during photolithography. Achieving overlay accuracy compensation and precise control is crucial for ensuring the performance of semiconductor devices.

[0003] The patterns on a wafer specifically used to measure overlay errors are called overlay marks. These patterns are placed in designated areas during mask design, typically at the edges of the exposure area, usually within the scribeline. To save space, overlay marks were initially larger than approximately 20 μm, then reduced to 15 μm × 15 μm, and further reduced to even smaller 10 μm × 10 μm patterns.

[0004] As advanced manufacturing processes advance and the feature size of semiconductor devices continues to shrink, the overlay accuracy window of photolithography processes is becoming smaller and smaller, and existing overlay marking methods need to be further improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an overlay marking structure and a method for forming the same, so as to improve measurement accuracy.

[0006] To solve the above-mentioned technical problems, the technical solution of the present invention provides an overlay marking structure, comprising: a substrate, the substrate comprising a plurality of chip regions, each chip region comprising a structural region and at least one pseudo-structural region adjacent to the structural region, each pseudo-structural region comprising at least one marking region; at least two overlapping device layers located on the substrate, each device layer having a plurality of marking structures, and each marking structure in each device layer being located on at least one marking region.

[0007] Optionally, at least two overlapping device layers include a first device layer located on the substrate surface, wherein the marking structure within the first device layer includes a plurality of marking fins, the plurality of marking fins being parallel to a second direction and arranged along a first direction.

[0008] Optionally, the distance between adjacent marked fins along the first direction ranges from 30 nm to 500 nm.

[0009] Optionally, each marked fin includes a plurality of first fins, which are parallel to the second direction and arranged along the first direction.

[0010] Optionally, the first device layer may also have a plurality of pseudofins located on the pseudostructure region.

[0011] Optionally, the first device layer may also have a plurality of second fins located on the structural region.

[0012] Optionally, at least two overlapping device layers include a second device layer located on the substrate surface. The marking structure within the second device layer includes a plurality of marking isolation stripes, each of which is parallel to a second direction and arranged along a first direction. The projection of the marking isolation stripes on the substrate surface is located in the middle of the projections of adjacent marking fins on the substrate surface.

[0013] Optionally, along the first direction, the distance between adjacent marker isolation stripes ranges from 60 nm to 1000 nm.

[0014] Optionally, a substrate layer is further provided between the first device layer and the second device layer, the substrate layer including a portion of the marking fin spanning the marking fin portion and located on the sidewall and top surface of the marking fin portion, the plurality of auxiliary gates being parallel to a second direction and arranged along a first direction, and each of the marking isolation stripes cutting off the plurality of auxiliary gates along the second direction.

[0015] Optionally, the second device layer may also have a plurality of pseudo-gates located on the pseudo-structure region.

[0016] Optionally, the marking structure includes some structural features of the current device layer; the marking structure includes one or more of contact holes, sidewalls, and isolation layers.

[0017] Accordingly, the technical solution of the present invention also provides a method for overlay marking, comprising: providing a substrate, the substrate comprising a plurality of chip regions, each chip region comprising a structural region and at least one pseudo-structural region adjacent to the structural region, each pseudo-structural region comprising at least one marking region; forming at least two overlapping device layers on the substrate, each device layer having a plurality of marking structures, and each marking structure in each device layer being located on at least one marking region.

[0018] Optionally, the method for obtaining the marking area includes: setting a marking structure; obtaining a pseudo-structure area in each chip where a pseudo gate needs to be set according to the layout of the devices in each chip in the exposure area; obtaining several initial marking area positions in the pseudo-structure area according to the set marking size; confirming whether the obtained initial marking area positions conform to the design rules of the pseudo gate in the chip, removing some initial marking area positions that do not conform to the design rules, and obtaining several predetermined marking area positions; performing data simulation based on the relationship between the distribution of the marking area and the overlay accuracy, and obtaining the optimal marking area position from the several predetermined marking area positions; inserting the marking structure into the chip design template according to the optimal marking area position obtained by simulation, and obtaining the marking structure design data file.

[0019] Optionally, at least two overlapping device layers include a first device layer located on the substrate surface, wherein the marking structure within the first device layer includes a plurality of marking fins, the plurality of marking fins being parallel to a second direction and arranged along a first direction.

[0020] Optionally, the first device layer may also have a plurality of pseudofins located on the pseudostructure region.

[0021] Optionally, the marking area along the first direction includes a plurality of first areas and a plurality of second areas, the first areas being adjacent to the second areas on both sides, and the plurality of marking fins being located in the second areas; the method for forming the plurality of marking fins includes: forming a plurality of first sacrificial layers on the substrate, the plurality of first sacrificial layers being parallel to the second direction and arranged along the first direction; forming a plurality of first fins on the sidewalls of the plurality of first sacrificial layers; removing unwanted first fins, and forming marking fins with the first fins on the second areas.

[0022] Optionally, at least two overlapping device layers include a second device layer located on the substrate surface. The marking structure within the second device layer includes a plurality of marking isolation stripes, each of which is parallel to a second direction and arranged along a first direction. The projection of the marking isolation stripes on the substrate surface is located in the middle of the projections of adjacent marking fins on the substrate surface.

[0023] Optionally, the formation process of the plurality of marked fins includes a self-aligned multi-pattern process.

[0024] Optionally, a substrate layer is further provided between the first device layer and the second device layer. The substrate layer includes a plurality of auxiliary gates that span the marking fin and are located on the sidewalls and top surface of the marking fin portion, and each of the marking isolation stripes cuts through the plurality of auxiliary gates along the second direction.

[0025] Optionally, the method for forming the substrate layer and the plurality of marked isolation stripes includes: after forming the first device layer, forming a plurality of auxiliary gates across the plurality of first fins on the marked region; after forming the plurality of auxiliary gates, forming a dielectric material layer on the auxiliary gates; forming a plurality of isolation trenches in the dielectric material layer on the first region, the isolation trenches penetrating the plurality of auxiliary gates along the second direction; and forming the marked isolation stripes in the isolation trenches.

[0026] Optionally, the formation process of the auxiliary gate includes a self-aligned multi-pattern process.

[0027] Optionally, the first device layer may also have a plurality of pseudofins located on the pseudostructure region.

[0028] Optionally, the second device layer may also have a plurality of pseudo-gates located on the pseudo-structure region.

[0029] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0030] The overlay marking structure provided by this invention includes a structural region and at least one pseudo-structural region adjacent to the structural region. Each pseudo-structural region includes at least one marking region. The marking structure is placed in the marking region, and both the marking region and the pseudo-gate are placed in the pseudo-structural region, without occupying the position of the structural region where the device is placed. Therefore, it is not affected by the chip pattern distribution and only needs to follow the design rules of the pseudo-gate. Since each chip has a region for forming pseudo-gates, there are a large number of pseudo-gate regions distributed at various exposure positions throughout the exposure area. The total distribution area of ​​the pseudo-gate regions can even reach more than 50% of the entire exposure area. This is beneficial for the existing regions of pseudo-gates that are widely distributed in the exposure area, i.e., forming marking structures in the pseudo-structural regions without occupying the position of the device in the chip, thus improving the chip integration. On the other hand, since the size of the pseudo-gate is much smaller than that of the existing overlay markings, designing the marking structure to be similar to the pseudo-gate structure can form several relatively freely distributed marking structures in an exposure area. The number of marking structures is sufficient to meet the high overlay accuracy requirements, increasing the freedom of overlay marking settings and improving overlay measurement accuracy.

[0031] Furthermore, in the pseudo-structure region, the plurality of pseudo-fins are adjacent to the plurality of marking fins. Since the marking fins include a plurality of first fins, and the first fins and the pseudo-fins have the same feature size, the stress caused by the difference in feature size between the overlay markings and the adjacent device areas is reduced, thus reducing the problem of bending of the marking fins. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the distribution of an overlay marking structure;

[0033] Figure 2 This is a schematic diagram of the chip distribution within the exposure area in another embodiment;

[0034] Figure 3 This is a step in obtaining the marked region in one embodiment of the present invention;

[0035] Figures 4 to 7 This is a schematic diagram of the structure of each step in the method for forming overprinted marks according to an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram showing the positions of several predetermined marked areas obtained in one embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of the distribution of the overlay marking structure in one embodiment of the present invention. Detailed Implementation

[0038] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0039] As described in the background section, existing overlay marking methods need further improvement. A specific overlay marking structure will now be explained and analyzed.

[0040] Figure 1 This is a schematic diagram of the distribution of an overlay marking structure.

[0041] Please refer to Figure 1 The exposure area 10 of the reference layer has 29 overlay marks 101. The exposure area 10 includes 6 chips 102 arranged in an array along the first direction X1 and the second direction Y1. There are cleaving channels 103 between adjacent chips 102. The 29 overlay marks 101 are relatively evenly distributed in the cleaving channels 102.

[0042] The aforementioned overlay mark 101 is used for diffraction-based overlay (DBO) error measurement. The overlay mark 101 includes several dense lines arranged in the horizontal direction and several dense lines arranged in the vertical direction. The total mark length h = w = 10 μm.

[0043] To achieve higher measurement accuracy, in another embodiment, the in-diemetrology (IDM) marking method places the overlay mark near the device location to monitor the overlay error at the device location nearby. In this case, the size of the overlay mark is further reduced to 5μm×5μm.

[0044] In DRAM manufacturing, the individual dies in the exposure area have regular and identical shapes, allowing IDM structures to relatively easily avoid device area placement. However, in multi-project wafer (MPW) fabrication, where multiple integrated circuit designs using the same process are fabricated on the same wafer, the dies in the exposure area have irregular shapes, making the placement of overlay marks more restrictive. Please refer to [reference needed]. Figure 2 .

[0045] Figure 2 This is a schematic diagram of the chip distribution within the exposure area in another embodiment.

[0046] Please refer to Figure 2 The exposure area 20 includes 32 irregularly shaped chips 201.

[0047] In this embodiment, placing the overlay mark within chip 201 requires the customer to reserve space for it. To achieve higher overlay accuracy, a higher-order correction model is needed to obtain correction parameters, thus requiring more overlay marks. With the need for more overlay marks, the irregular shape of chip 201 makes it difficult to retain the intended overlay mark positions, potentially affecting the customer's chip design rules. This results in the overlay mark placement method lacking flexibility.

[0048] To address the aforementioned issues, this invention provides an overlay marking structure in which each chip region includes a structural region and at least one pseudo-structural region adjacent to the structural region. Each pseudo-structural region includes at least one marking region. The marking structure is placed within the marking region, and both the marking region and the pseudo-gate are placed within the pseudo-structural region, without occupying the space of the structural region where the device is placed. Therefore, it is not affected by the chip pattern distribution and only needs to follow the design rules of the pseudo-gate. Since each chip has a region for forming pseudo-gates, there are a large number of pseudo-gate regions distributed at various exposure positions throughout the exposure area. The total distribution area of ​​the pseudo-gate regions can even reach more than 50% of the entire exposure area. By utilizing the existing regions of pseudo-gates that are widely distributed in the exposure area, i.e., forming marking structures in the pseudo-structural regions, the chip integration density is improved without occupying the space of the device in the chip. On the other hand, since the size of the pseudo-gate is much smaller than that of existing overlay marks, designing the marking structure to resemble the pseudo-gate structure allows for the formation of several relatively freely distributed marking structures within an exposure area. The number of marking structures is sufficient to meet the high overlay accuracy requirements, increasing the freedom of overlay mark setting and improving overlay measurement accuracy.

[0049] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0050] Unlike existing technologies that first set up marking areas and then lay out devices within the chip, the technical solution of this invention can first lay out the chip according to the customer's chip design requirements, then obtain the positions of several marking areas according to the design area of ​​the pseudo-gate in the chip layout, and subsequently set overlay marks in each marking area or in each device layer on the marking area.

[0051] Figure 3 This is a step in obtaining the marked area in one embodiment of the present invention.

[0052] Please refer to Figure 3 The method for obtaining the marked region includes the following steps:

[0053] Step S301: Set the marker structure;

[0054] Step S302: Based on the layout of devices within each chip in the exposure area, obtain the pseudo-structure area in each chip where a pseudo gate needs to be set.

[0055] Step S303: According to the set mark size, obtain several initial mark area positions in the pseudo-structure area;

[0056] Step S304: Confirm whether the obtained initial marker region position conforms to the design rules of the pseudo gate in the chip, remove the initial marker region positions that do not conform to the design rules, and obtain several predetermined marker region positions;

[0057] Step S305: Perform data simulation based on the relationship between the distribution of the marking area and the overlay accuracy, and obtain the optimal marking area position from the several predetermined marking area positions;

[0058] Step S306: Based on the optimized marking region position obtained from the simulation, insert the marking structure into the chip design template to obtain the marking structure design data file.

[0059] The following explains each step.

[0060] Execute step S301 to set the marker structure. For the method of forming the marker structure, please refer to... Figures 4 to 7 .

[0061] Figures 4 to 7 This is a schematic diagram of the steps in the method for forming an overlay mark structure according to an embodiment of the present invention.

[0062] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 A top-view structural diagram. Figure 5 yes Figure 4A cross-sectional structural schematic diagram along the EE1 direction is provided, and a substrate 400 is provided. The substrate 400 includes a plurality of chip regions (not shown in the figure). Each chip region includes a structural region (not shown in the figure) and at least one pseudo-structural region adjacent to the structural region. Each pseudo-structural region includes at least one marker region I.

[0063] Each pseudo-structure region includes several marker regions I and an outer region II surrounding and adjacent to each marker region I. In this embodiment, only a structural diagram of one marker region I and one outer region II is shown.

[0064] Subsequently, a marking structure is formed within each device layer on the marking region I; a plurality of pseudo-fins and pseudo-gates located on the pseudo-fins are formed on the peripheral region II.

[0065] Please continue to refer to this. Figure 4 and Figure 5 At least two overlapping device layers are formed on a substrate 400, each device layer having a plurality of marker structures, and each marker structure in each device layer being located on at least one marker region I.

[0066] The marking structure is placed in the marking area, and both the marking area and the dummy gate are placed in the dummy structure area. This does not occupy the space of the structure area where the device is placed, so it is not affected by the chip pattern distribution. It only needs to follow the design rules of the dummy gate. Since each chip has a region for forming dummy gates, there are a large number of dummy gate regions distributed at various exposure positions throughout the exposure area. The total distribution area of ​​the dummy gate regions can even reach more than 50% of the entire exposure area. By utilizing the existing dummy gate regions that are widely distributed in the exposure area, the marking structure is formed in the dummy structure area without occupying the space of the device in the chip, thus improving the chip integration. On the other hand, since the size of the dummy gate is much smaller than that of the existing overlay marks, the marking structure is designed to be similar to the dummy gate structure. Several marking structures can be formed relatively freely distributed within an exposure area. The number of marking structures is sufficient to meet the high overlay accuracy requirements, increasing the freedom of overlay mark setting and helping to improve overlay measurement accuracy.

[0067] Furthermore, each marking structure can be set on two or more adjacent marking areas. Compared to existing technologies, where the number of device layers is large and each layer requires measurement of its overlay error relative to a previous layer after exposure, the limited number of reserved marking areas necessitates that each marking area contain a marking structure for measuring the overlay accuracy between different device layers. The technical solution provided by this invention utilizes the existing pseudo-gate structure's location, allowing for the setting of a large number of marking areas. This enables the setting of a marking structure within the same device layer on two or more adjacent marking areas, thus making the overlay marking setup more flexible.

[0068] The at least two overlapping device layers include a first device layer (not shown in the figure) located on the surface of the substrate 400. The marking structure in the first device layer includes a plurality of marking fins 401, which are parallel to the second direction Y and arranged along the first direction X.

[0069] In this embodiment, the marking area along the first direction X includes a plurality of first areas A and a plurality of second areas B, with the first areas A adjacent to the second areas B on both sides, and the plurality of marking fins 401 located in the second areas B.

[0070] In this embodiment, the method for forming the plurality of marking fins 401 includes: forming a plurality of first sacrificial layers (not shown in the figure) on the substrate 400, the plurality of first sacrificial layers being parallel to the second direction Y and arranged along the first direction X; forming a plurality of first fins (not shown in the figure) on the sidewalls of the plurality of first sacrificial layers; removing the unwanted first fins, and forming marking fins with the first fins on the second region B.

[0071] The formation process of the marker fin 401 includes a self-aligned multi-pattern process. In this embodiment, the formation process of the marker fin is a self-aligned multi-pattern process.

[0072] In this embodiment, the first device layer 400 also has a plurality of pseudo-fins 501 located on the pseudo-structure region. Specifically, the plurality of pseudo-fins 501 are located on the peripheral region II.

[0073] The formation process of the plurality of pseudo-fins 501 includes a self-aligned multi-pattern process. In this embodiment, the formation process of the plurality of pseudo-fins 501 is a self-aligned multi-pattern process.

[0074] In this embodiment, the peripheral region II along the first direction X includes a plurality of third regions C and a plurality of fourth regions D, the third regions C are adjacent to the fourth regions D on both sides, and the plurality of pseudofin portions 501 are located in the fourth regions D.

[0075] In this embodiment, the plurality of pseudofin portions 501 and the marking fin portion 401 are arranged in the same direction and extend in the same direction. However, the plurality of pseudofin portions are arranged around the marking fin portion, so the relative arrangement of the pseudofin portions and the marking fin portion is not limited thereto. In other regions, the arrangement directions of the pseudofin portions and the marking fin portion can be perpendicular to each other.

[0076] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 A top-view structural diagram. Figure 7 yes Figure 6A cross-sectional structural schematic diagram along the EE1 direction shows that at least two overlapping device layers include a second device layer located on the surface of the substrate 400. The marking structure within the second device layer includes a plurality of marking isolation stripes 404. Each of the marking isolation stripes 404 is parallel to the second direction Y and arranged along the first direction X. The projection of the marking isolation stripes 404 on the surface of the substrate 400 is located in the middle of the projection of the adjacent marking fin 401 on the surface of the substrate 400.

[0077] Specifically, after the first device layer is formed, the second device layer is formed.

[0078] Specifically, the first device layer also has a first isolation layer 402. After the marking fin 401 is formed and before the second device layer is formed, the first isolation layer 402 is also formed on the substrate 400.

[0079] In this embodiment, the first isolation layer 402 is located on part of the sidewalls of the plurality of marked fins 401 and the plurality of pseudo fins 501, and the top surface of the first isolation layer 402 is higher than the top surface of the plurality of marked fins 401 and the plurality of pseudo fins 501.

[0080] In this embodiment, a substrate layer is further provided between the first device layer and the second device layer. The substrate layer includes a plurality of auxiliary gates 403, which span the marking fin and are located on the sidewalls and top surface of the marking fin portion. Each of the marking isolation stripes 404 cuts through the plurality of auxiliary gates 403 along the second direction Y.

[0081] The method for forming the substrate layer and the plurality of marked isolation stripes 404 includes: after forming the first device layer, forming a plurality of initial auxiliary gates (not shown in the figure) that span the plurality of first fins on the marked region I; after forming the plurality of initial auxiliary gates, forming a dielectric material layer (not shown in the figure) on the initial auxiliary gates; forming a plurality of isolation trenches (not shown in the figure) in the dielectric material layer on the first region A, the isolation trenches penetrating the plurality of initial auxiliary gates along the second direction Y to form the auxiliary gates; and forming the marked isolation stripes 404 in the isolation trenches.

[0082] In this embodiment, the initial auxiliary gate formation process includes a self-aligned multi-pattern process.

[0083] The second device layer also has a plurality of pseudo gates 503 located on the pseudo structure region.

[0084] Specifically, the plurality of dummy gates 503 are located on the peripheral region II, the dummy gates 503 span the plurality of dummy fins 501, and are located on part of the sidewalls and top surface of the plurality of dummy fins 501; the peripheral region II also has a gate isolation layer 504, the gate isolation layer 504 cutting off the dummy gates 503 along the second direction Y.

[0085] In this embodiment, the plurality of marked isolation stripes 404 and the gate isolation layer 504 are also located in the second isolation layer. After the plurality of auxiliary gates 403 and the pseudo gate 503 are formed, and before the plurality of marked isolation stripes 404 and the gate isolation layer 504 are formed, the method further includes: forming a second isolation layer (not shown in the figure) on the surface of the substrate 400. The second isolation layer is located on the surface of the first isolation layer 402 and on the sidewalls of the plurality of auxiliary gates 403 and the pseudo gate 503.

[0086] This embodiment demonstrates an overlay marking structure within two device layers located on the substrate. Subsequently formed device layers may have marking structures that possess some structural features of the current device layer, i.e., are compatible with the structure of the current device layer, to form the marking structure of that layer; the marking structure may include one or more of contact holes, sidewalls, and isolation layers.

[0087] Accordingly, one embodiment of the present invention also provides an overlay marking structure formed using the above method. Please refer to [the original text]. Figure 6 and Figure 7 The system includes: a substrate 400, which includes a plurality of chip regions (not shown in the figure), each chip region including a structural region (not shown in the figure) and at least one pseudo-structural region adjacent to the structural region, each pseudo-structural region including at least one marker region I; at least two overlapping device layers located on the substrate 400, each device layer having a plurality of marker structures, and each marker structure in each device layer being located on at least one marker region I.

[0088] The at least two overlapping device layers include a first device layer located on the surface of the substrate 400. The marking structure within the first device layer includes a plurality of marking fins 401, which are parallel to the second direction Y and arranged along the first direction X.

[0089] Along the first direction X, the distance m between adjacent marked fins ranges from 30 nm to 500 nm.

[0090] Each marking fin includes a plurality of first fins 401, which are parallel to the second direction Y and arranged along the first direction X.

[0091] The first device layer also has a plurality of pseudo-fins 501 located on the pseudo-structure region.

[0092] On the pseudo-structure area, the plurality of pseudo fins 501 are adjacent to the plurality of marking fins 401. Since the marking fins 401 include a plurality of first fins, the first fins and the pseudo fins 501 have the same feature size, which reduces the stress caused by the difference in feature size between the overprinted markings and the adjacent device area, thus reducing the problem of bending of the marking fins.

[0093] The first device layer also has several second fins (not shown in the figure) located on the structural region. The second fins are used to form the device.

[0094] The at least two overlapping device layers include a second device layer located on the surface of the substrate 400. The marking structure in the second device layer includes a plurality of marking isolation stripes 404, each of which is parallel to the second direction Y and arranged along the first direction X. The projection of the marking isolation stripes 404 on the surface of the substrate 400 is located in the middle of the projection of the adjacent marking fins on the surface of the substrate 400.

[0095] Along the first direction X, the distance n between adjacent marked isolation stripes 404 ranges from 60 nm to 1000 nm.

[0096] A substrate layer 404 is further provided between the first device layer and the second device layer. The substrate layer 404 includes a portion of the marking fin that spans the marking fin portion and is located on the sidewall and top surface of the marking fin portion. The plurality of auxiliary gates 403 are parallel to the second direction Y and arranged along the first direction X. Each of the marking isolation stripes 404 cuts off the plurality of auxiliary gates 403 along the second direction Y.

[0097] The second device layer also has a plurality of pseudo gates 503 located on the pseudo structure region.

[0098] The marking structure includes some structural features of the current device layer; the marking structure includes one or more of contact holes, sidewalls, and isolation layers.

[0099] Please continue to refer to this. Figure 3 Step S302 is executed to obtain the pseudo-structure area in each chip that needs to be set with a pseudo gate, based on the layout of the devices in each chip in the exposure area.

[0100] Specifically, a large number of dummy gates are usually required within the chip to achieve device integrity, but these dummy gates do not have electrical properties. The area is then used to form an overlay marking structure.

[0101] Please continue to refer to this. Figure 3 Then, in step S303, according to the set mark size, several initial mark area positions are obtained in the pseudo-structure area.

[0102] Please refer to Figure 8 A position can be set within all predetermined marker areas according to a certain scanning step size, and the size of this position is the size of a marker structure. In this embodiment, 1242 initial marker area positions (as shown by square image points) were obtained in one exposure area.

[0103] Please continue to refer to this. Figure 3 Step S304 is executed to confirm whether the obtained initial marker region position conforms to the design rules of the pseudo gate in the chip, remove the initial marker region positions that do not conform to the design rules, and obtain several predetermined marker region positions.

[0104] The marker structure needs to be compatible with the pseudo-gate; therefore, after the marker structure is inserted, it needs to comply with the design rules of the pseudo-gate in the chip.

[0105] Please continue to refer to this. Figure 3 Step S305 is executed, and data simulation is performed based on the relationship between the distribution of the marking area and the overlay accuracy to obtain the optimal marking area position from the several predetermined marking area positions.

[0106] Please refer to Figure 9 In this embodiment, 108 optimized marker locations 901 were obtained from 1242 initial marker locations. In other embodiments, the marker locations and number can be obtained according to actual needs.

[0107] It should be noted here that... Figure 9 The marker area 901 in the diagram is only for illustrative purposes; its size is much smaller than the chip area.

[0108] Please continue to refer to this. Figure 3 In step S306, the marker structure is inserted into the chip design template according to the optimal marker region position obtained by simulation, and the marker structure design data file is obtained.

[0109] The design of the marker structure can be obtained through the marker structure design data file, without having to perform steps S301 to S306 every time.

[0110] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A type of overlay marking structure, characterized in that, include: The substrate includes a plurality of chip regions, each chip region including a structural region and at least one pseudo-structural region adjacent to the structural region, each pseudo-structural region including at least one marker region and a peripheral region disposed around and adjacent to the marker region; At least two overlapping device layers are located on a substrate, each device layer has a plurality of marker structures, and each marker structure in each device layer is located on at least one marker region, wherein the plurality of marker structures follow the design rules of a pseudogate. Several pseudo-gates located on the peripheral region.

2. The overlay marking structure as described in claim 1, characterized in that, The at least two overlapping device layers include a first device layer located on the substrate surface, and the marking structure within the first device layer includes a plurality of marking fins, which are parallel to a second direction and arranged along a first direction.

3. The overlay marking structure as described in claim 2, characterized in that, Along the first direction, the distance between adjacent marked fins ranges from 30 nm to 500 nm.

4. The overlay marking structure as described in claim 2, characterized in that, Each marked fin includes a plurality of first fins, which are parallel to the second direction and arranged along the first direction.

5. The overlay marking structure as described in claim 2, characterized in that, The first device layer also has several pseudo-fins located on the pseudo-structure region.

6. The overlay marking structure as described in claim 2, characterized in that, The first device layer also has several second fins located on the structural region.

7. The overlay marking structure as described in claim 2, characterized in that, The device includes at least two overlapping device layers, including a second device layer located on the substrate surface. The marking structure within the second device layer includes a plurality of marking isolation stripes, each of which is parallel to a second direction and arranged along a first direction. The projection of the marking isolation stripes on the substrate surface is located in the middle of the projections of adjacent marking fins on the substrate surface.

8. The overlay marking structure as described in claim 7, characterized in that, Along the first direction, the distance between adjacent marker isolation stripes ranges from 60 nm to 1000 nm.

9. The overlay marking structure as described in claim 7, characterized in that, A substrate layer is further provided between the first device layer and the second device layer. The substrate layer includes a plurality of auxiliary gates that span the marking fin and are located on the sidewalls and top surface of the marking fin portion. The plurality of auxiliary gates are parallel to a second direction and arranged along a first direction, and each of the marking isolation stripes cuts off the plurality of auxiliary gates along the second direction.

10. The overlay marking structure as described in claim 9, characterized in that, The second device layer also has several pseudo-gates located on the pseudo-structure region.

11. The overlay marking structure as described in claim 1, characterized in that, The marking structure includes some structural features of the current device layer; the marking structure includes one or more of contact holes, sidewalls, and isolation layers.

12. A method for forming an overlay marking structure, characterized in that, include: A substrate is provided, the substrate including a plurality of chip regions, each chip region including a structural region and at least one pseudo-structural region adjacent to the structural region, each pseudo-structural region including at least one marker region and a peripheral region disposed around and adjacent to the marker region; At least two overlapping device layers are formed on a substrate, each device layer having a plurality of marker structures, and each marker structure in each device layer is located on at least one marker region, wherein the plurality of marker structures follow the design rules of a pseudogate. Several pseudo-gates are formed on the outer perimeter area.

13. The method for forming the overlay marking structure as described in claim 12, characterized in that, The method for obtaining the marking area includes: setting a marking structure; obtaining the pseudo-structure area in each chip that needs to be set with a pseudo gate according to the layout of the devices in each chip in the exposure area; obtaining several initial marking area positions in the pseudo-structure area according to the set marking size; confirming whether the obtained initial marking area positions comply with the design rules of the pseudo gate in the chip, removing the initial marking area positions that do not comply with the design rules, and obtaining several predetermined marking area positions; performing data simulation based on the relationship between the distribution of the marking area and the overlay accuracy, and obtaining the optimal marking area position from the several predetermined marking area positions; inserting the marking structure into the chip design template according to the optimal marking area position obtained by simulation, and obtaining the marking structure design data file.

14. The method for forming the overlay marking structure as described in claim 12, characterized in that, The at least two overlapping device layers include a first device layer located on the substrate surface, and the marking structure within the first device layer includes a plurality of marking fins, which are parallel to a second direction and arranged along a first direction.

15. The method for forming the overlay marking structure as described in claim 14, characterized in that, The first device layer also has several pseudofins located on the pseudo-structure region.

16. The method for forming the overlay marking structure as described in claim 14, characterized in that, The marking area along the first direction includes a plurality of first areas and a plurality of second areas, the first areas being adjacent to the second areas on both sides, and the plurality of marking fins being located in the second areas; the method of forming the plurality of marking fins includes: forming a plurality of first sacrificial layers on the substrate, the plurality of first sacrificial layers being parallel to the second direction and arranged along the first direction; forming a plurality of first fins on the sidewalls of the plurality of first sacrificial layers; removing unwanted first fins, and forming marking fins with the first fins on the second areas.

17. The method for forming the overlay marking structure as described in claim 16, characterized in that, The device includes at least two overlapping device layers, including a second device layer located on the substrate surface. The marking structure within the second device layer includes a plurality of marking isolation stripes, each of which is parallel to a second direction and arranged along a first direction. The projection of the marking isolation stripes on the substrate surface is located in the middle of the projections of adjacent marking fins on the substrate surface.

18. The method for forming the overlay marking structure as described in claim 16, characterized in that, The formation process of the several marked fins includes a self-aligned multi-pattern process.

19. The method for forming the overlay marking structure as described in claim 17, characterized in that, A substrate layer is further provided between the first device layer and the second device layer. The substrate layer includes a plurality of auxiliary gates that span the marking fin and are located on the sidewalls and top surface of the marking fin portion. Each of the marking isolation stripes cuts through the plurality of auxiliary gates along the second direction.

20. The method for forming the overlay marking structure as described in claim 19, characterized in that, The method for forming the substrate layer and the plurality of marked isolation stripes includes: after forming the first device layer, forming a plurality of auxiliary gates across the plurality of first fins on the marked region; after forming the plurality of auxiliary gates, forming a dielectric material layer on the auxiliary gates; forming a plurality of isolation trenches in the dielectric material layer on the first region, the isolation trenches penetrating the plurality of auxiliary gates along the second direction; and forming the marked isolation stripes in the isolation trenches.

21. The method for forming the overlay marking structure as described in claim 19, characterized in that, The formation process of the auxiliary gate includes a self-aligned multi-pattern process.

22. The method for forming the overlay marking structure as described in claim 17, characterized in that, The first device layer also has several pseudofins located on the pseudo-structure region.

23. The method for forming the overlay marking structure as described in claim 17, characterized in that, The second device layer also has several pseudo-gates located on the pseudo-structure region.

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