A semiconductor structure and its fabrication method

Abstract

This invention discloses a semiconductor structure and its fabrication method. The semiconductor structure includes: a first wafer layer having a first surface and a second surface, a first patterned structure on the first surface of the first wafer layer, and a photoblocking layer above the first patterned structure; a second wafer layer having a first surface and a second surface, a second patterned structure on the first surface of the second wafer layer, and a photoblocking layer above the second patterned structure, the second wafer layer being stacked on the first wafer layer; and a third wafer layer having a first surface and a second surface, a third patterned structure on the first surface of the third wafer layer, and a photoblocking layer above the third patterned structure, the third wafer layer being stacked on the second wafer layer. This method can effectively improve the alignment accuracy during photolithography alignment processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to, but not limited to, a three-dimensional stacked semiconductor structure and a method for preparing the three-dimensional stacked semiconductor structure. Background Technology

[0002] According to Moore's Law, it has become increasingly difficult to improve the performance of integrated circuits by further shrinking the feature size of transistors. Three-dimensional integrated circuits (3D ICs), as an important research and application direction that transcends Moore's Law, will fundamentally change the development trend of integrated circuits. 3D ICs involve stacking two or more functional chips vertically, using technologies such as hybrid bonding, through-silicon vias (TSVs), or microbumps to achieve electrical interconnection, forming a three-dimensional stacked chip.

[0003] One related technology is High Bandwidth Memory (HBM), which can stack and package multiple identical wafers or chips vertically. The resulting three-dimensional stacked chips can achieve high-density interconnection. Direct chip interconnection makes signal transmission paths shorter and faster, and makes it possible to realize chips with complex functions. Moreover, 3D IC packaging greatly reduces the size of the package.

[0004] In related technologies, the manufacturing process of multiple identical wafers or chips requires patterning using photolithography, which necessitates alignment technology. The laser used in the alignment process can penetrate the thickness of multiple stacked wafers or chips. When multiple identical wafers or chips are stacked, the alignment marks on each wafer or chip are located in the same position. This means that during alignment, the pattern and signal of the alignment mark on the current wafer or chip are affected by the alignment mark on the wafer or chip below. This alignment problem is a major factor leading to alignment deviations in three-dimensional stacked chips.

[0005] How to reduce alignment deviations, improve alignment accuracy, and enhance the overall performance of photolithography in the fabrication process of three-dimensional stacked chips is an urgent problem to be solved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a three-dimensional stacked semiconductor structure and a method for preparing the three-dimensional stacked semiconductor structure, so as to solve the technical problem of alignment deviation caused by the mutual influence of alignment marks in the prior art three-dimensional stacked semiconductor structure.

[0007] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a first wafer layer 100 having a first surface and a second surface, a first patterned structure 110 on the first surface of the first wafer layer 100, and a light-blocking layer 400 above the first patterned structure 110; a second wafer layer 200 having a first surface and a second surface, a second patterned structure 210 on the first surface of the second wafer layer 200, and a light-blocking layer 400 above the second patterned structure 210, wherein the second wafer layer 200 is stacked on the first wafer layer 100.

[0008] Furthermore, it also includes: a third wafer layer 300 having a first surface and a second surface, a third patterned structure 310 having a third patterned structure 310 having a light blocking layer 400 above the third patterned structure 310, and the third wafer layer 300 being stacked on the second wafer layer 200.

[0009] Furthermore, the first surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 is the front surface of the wafer layer, and has an active region thereon; the second surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 is the back surface of the wafer layer, and has a bonding structure thereon.

[0010] Furthermore, in the vertical projection direction, the light blocking layer 400 completely blocks the first graphic structure 110, the second graphic structure 210, and the third graphic structure 310.

[0011] Furthermore, the light blocking layer 400 is a separate layer disposed above the first pattern structure 110, the second pattern structure 210, and the third pattern structure 310.

[0012] Furthermore, the light-blocking layer 400 is a functional layer structure in the wafer fabrication process, extending above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310.

[0013] Furthermore, the light-blocking layer 400 is formed using a material layer with low light transmittance and high light absorbance.

[0014] Furthermore, the light-blocking layer 400 is formed using a tungsten metal layer.

[0015] The present invention also provides a method for preparing a semiconductor structure, the method comprising:

[0016] A first wafer layer 100 is provided, having a first surface and a second surface, and a first pattern structure 110 is formed on the first surface of the first wafer layer 100;

[0017] A first dielectric layer is deposited on the first patterned structure 110, and the first dielectric layer is planarized.

[0018] A light-blocking material layer is deposited on the first dielectric layer;

[0019] The light-blocking material layer is patterned to form a light-blocking layer 400, which is located above the first patterned structure 110.

[0020] A second dielectric layer is deposited on the light-blocking layer 400, and the second dielectric layer is planarized.

[0021] Furthermore, the first surface of the first wafer layer 100 is stacked on the carrier wafer layer and flipped, and the second surface of the first wafer layer 100 is thinned.

[0022] Furthermore, a second wafer layer 200 is provided, having a first surface and a second surface, and a second pattern structure 210 is formed on the first surface of the second wafer layer 200.

[0023] A first dielectric layer is deposited on the second pattern structure 210, and the first dielectric layer is planarized.

[0024] A light-blocking material layer is deposited on the first dielectric layer;

[0025] The light-blocking material layer is patterned to form a light-blocking layer 400, which is located above the second patterned structure 210;

[0026] A second dielectric layer is deposited on the light-blocking layer, and the second dielectric layer is planarized.

[0027] The first surface of the second wafer layer 200 is stacked on the second surface of the first wafer layer 100 and flipped, and the second surface of the second wafer layer 200 is thinned.

[0028] Furthermore, a third wafer layer 300 is provided, having a first surface and a second surface, wherein a third pattern structure 310 is formed on the first surface of the third wafer layer 300;

[0029] A first dielectric layer is deposited on the third pattern structure 310, and the first dielectric layer is planarized.

[0030] A light-blocking material layer is deposited on the first dielectric layer;

[0031] The light-blocking material layer is patterned to form a light-blocking layer 400, which is located above the third patterned structure 310.

[0032] A second dielectric layer is deposited on the light-blocking layer 400, and the second dielectric layer is planarized.

[0033] The first surface of the third wafer layer 300 is stacked on the second surface of the second wafer layer 200 and flipped, and the second surface of the third wafer layer 300 is thinned.

[0034] Furthermore, the first surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 is the front surface of the wafer layer, and has an active region thereon; the second surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 is the back surface of the wafer layer, and has a bonding structure thereon.

[0035] Furthermore, in the vertical projection direction, the light blocking layer 400 completely blocks the first graphic structure 110, the second graphic structure 210, and the third graphic structure 310.

[0036] Furthermore, the light blocking layer 400 is a separate layer disposed above the first pattern structure 110, the second pattern structure 210, and the third pattern structure 310.

[0037] Furthermore, the light-blocking layer 400 is a functional layer structure in the wafer fabrication process, extending above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310.

[0038] Furthermore, the light-blocking layer 400 is formed using a material layer with low light transmittance and high light absorbance.

[0039] Furthermore, the light-blocking layer 400 is formed using a tungsten metal layer.

[0040] In summary, the semiconductor structure and its fabrication method of the present invention have the following advantages:

[0041] 1. The semiconductor structure provided by the present invention enables multiple stacked identical wafers or chips to use the same photomask when manufacturing the alignment mark layer, eliminating the need to continuously change the photomask of the alignment mark layer to prepare wafers or chips with different alignment mark positions, as is done in the prior art. This greatly reduces the complexity and production cost in the wafer manufacturing process.

[0042] 2. The semiconductor structure provided by this invention can be made into multiple identical wafer layers, which can be interchanged with each other, reducing waste caused by special wafer pairing process;

[0043] 3. The semiconductor structure provided by the present invention can use the same photomask during the fabrication of multiple wafer layers, avoiding the situation of fabricating multiple different photomasks in the prior art, and greatly reducing the manufacturing cost of photomasks;

[0044] 4. The light blocking layer in the semiconductor structure provided by the present invention can effectively avoid the interference of the alignment mark structure on the lower wafer to the alignment mark structure on the upper wafer during the photolithography alignment process, greatly reducing alignment deviation and improving alignment accuracy. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the alignment mark containing a "striped" pattern in the present invention.

[0046] Figure 2 This is a schematic diagram of normal alignment stripes on a single wafer or chip in the photolithography alignment process of the present invention.

[0047] Figure 3 This is a schematic diagram of the structure of multiple identical wafers stacked in three dimensions in this invention.

[0048] Figure 4 This is a schematic diagram of alignment stripes that cause fluctuations and interference during the photolithography alignment process of multiple wafers or chips in this invention.

[0049] Figure 5 This is a schematic diagram of the structure in this invention, in which multiple sets of identical alignment marks are respectively set at different positions on the alignment mark layer of each wafer or chip.

[0050] Figure 6 This is a schematic diagram of the structure of a three-dimensional stacked chip according to a specific embodiment of the present invention.

[0051] Figure 7 This is a schematic diagram of the process flow of a single wafer layer in a three-dimensional stacked structure according to a specific embodiment of the present invention. Implementation

[0052] To facilitate understanding of this disclosure, exemplary embodiments thereof will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0053] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of actual embodiments, nor well-known functions and structures, may be described herein.

[0054] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0055] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0057] As described in the background art, in the manufacturing process of multiple identical wafers or chips, photolithography is required to pattern them. Through processes such as exposure, development, baking, and etching, the pattern on the photomask is transferred to the wafer or chip. To ensure that the pattern on the photomask is accurately transferred to the corresponding position on the wafer or chip, photolithographic alignment technology is necessary. In photolithographic alignment technology, alignment marks are fabricated as two sets of gratings with similar periods, formed respectively on the wafer or chip and the photomask. The grating structure in the alignment marks typically uses a pattern containing "stripes," as shown in the attached figure. Figure 1As shown, it presents a structural schematic diagram of alignment marks containing a "striped" pattern.

[0058] In some embodiments, a TTL (Through The Lens) alignment system is used to align alignment marks on a wafer or chip with alignment marks on a photomask. The TTL alignment system consists of an alignment laser, an alignment optical path, alignment marks, and an alignment signal processing module. The laser beam emitted by the laser is split and image-transformed, forming two sets of interference fringes with different periods. These two sets of interference fringes further interfere and superimpose on the image plane of the alignment system to form alignment fringes. After being magnified by a magnifying lens group, the alignment fringes are imaged by a CCD camera. (See attached image.) Figure 2 As shown, it illustrates a schematic diagram of normal alignment stripes on a single wafer or chip during the photolithography alignment process.

[0059] In 3D stacked chip fabrication, multiple identical wafers or chips are stacked and packaged vertically. To reduce the complexity and production cost of wafer manufacturing, alignment marks are typically placed at the same positions on each identical wafer or chip. (See attached image) Figure 3 As shown, this diagram illustrates the structure of multiple identical wafers stacked in three dimensions. During the photolithography alignment process, the laser used can penetrate the thickness of multiple stacked wafers or chips. This causes the alignment marks on the upper wafer 1 to be affected by the alignment marks on the lower wafers 2 and 3. Specifically, the diffracted light reflected from the alignment marks on the lower wafers 2 and 3 affects the diffracted light reflected from the alignment marks on the upper wafer 1, further affecting the phase information of the interference fringes, resulting in fluctuations and interference in the final alignment fringes. (See attached diagram) Figure 4 As shown, this diagram illustrates the alignment stripes that cause fluctuations and interference during the photolithography alignment process of multiple wafers or chips. Furthermore, in actual 3D stacked chip fabrication processes, the bonding of multiple identical wafers or chips in the vertical direction cannot achieve perfect alignment, resulting in a 1 / 10 to 1 / 7 offset in feature size. This further leads to deviations in the vertical direction of the alignment marks on multiple identical wafers or chips. Such deviations cause phase fluctuations between the reflected and diffracted light, thus exacerbating the noise generated by the final alignment stripes and significantly affecting the alignment accuracy.

[0060] To avoid the aforementioned problems, some existing technologies employ a solution where, during the fabrication of a single wafer or chip, multiple identical alignment marks are deliberately placed at different locations on the alignment mark layer of each wafer or chip in the layer where alignment marks need to be formed, such as the AA layer (Active Area). (See attached figure.) Figure 5As shown in the diagram. During photolithography alignment, the aforementioned process effectively avoids the influence of alignment marks on the lower wafer or chip on the patterns and signals of alignment marks on the upper wafer or chip, significantly reducing alignment deviation and improving alignment accuracy. However, since corresponding alignment marks need to be set at different positions on the alignment mark layer of each wafer or chip, multiple photolithography masks with alignment mark layers are ultimately required. Fabricating multiple different photolithography masks significantly increases production costs. Furthermore, in the aforementioned process, it is necessary to continuously replace the photolithography masks of the alignment mark layers to prepare wafers or chips with different alignment mark positions. These multiple wafers or chips cannot be interchanged and require special pairing for multi-layer stacking, making the fabrication process more complex and correspondingly increasing scheduling difficulties and production costs.

[0061] In existing 3D stacked chip fabrication processes, the photolithography alignment process still needs improvement. This will be analyzed and explained in conjunction with specific embodiments.

[0062] Appendix Figure 6 This is a schematic diagram of the structure of a three-dimensional stacked chip according to a specific embodiment of the present invention.

[0063] Please refer to the attached document. Figure 6 A semiconductor structure is provided, the semiconductor structure comprising: a first wafer layer 100 having a first surface and a second surface, a first patterned structure 110 having a first patterned structure 110 having a light-blocking layer 400 above the first patterned structure 110; a second wafer layer 200 having a first surface and a second surface, a second patterned structure 210 having a first surface having a second patterned structure 210 having a light-blocking layer 400 above the second patterned structure 210, the second wafer layer 200 being stacked on the first wafer layer 100.

[0064] Furthermore, it includes: a third wafer layer 300 having a first surface and a second surface, a third patterned structure 310 having a third patterned structure 310 having a light blocking layer 400 above the third patterned structure 310, and the third wafer layer 300 being stacked on the second wafer layer 200.

[0065] Furthermore, the first surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 can be the front surface of the wafer layer, having an active area thereon. The second surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 can be the back surface of the wafer layer, having a bonding structure thereon.

[0066] Furthermore, the first pattern structure 110, the second pattern structure 210, and the third pattern structure 310 are alignment pattern structures, i.e., alignment mark structures, used to align the pattern on the wafer with the pattern on the photolithography mask during the photolithography alignment process. The alignment marks typically employ a grating structure containing a "striped" pattern. The first pattern structure 110, the second pattern structure 210, and the third pattern structure 310 are all pre-set on the first surfaces of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300, respectively, as alignment marks in the subsequent three-dimensional stacked chip fabrication process.

[0067] Furthermore, the light-blocking layers 400 are all disposed above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310. In the vertical projection direction, the light-blocking layers 400 completely block the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310. Furthermore, in the fabrication process, the light-blocking layer 400 can be a single layer disposed above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310; it can also be a functional layer structure in the wafer fabrication process, extending above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310. The functional layer structure can be one of the following: a gate electrode layer, a source / drain electrode layer, a word line layer, a bit line layer, or an electrode plate of a capacitor structure, but is not limited to these; it can also be other functional layers in the wafer fabrication process.

[0068] Furthermore, in the fabrication process, the light-blocking layer 400 is formed using a material layer with low transmittance and high absorbance. In this invention, a metal material layer is preferentially used to form the light-blocking layer, and a tungsten metal layer is more preferred. However, this is not limited to this embodiment, and other material layers with low transmittance and high absorbance can also be used to form the light-blocking layer.

[0069] In the fabrication process of a three-dimensional stacked chip, the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 need to be thinned from the second surface and then subjected to photolithographic alignment. Further bonding structures are then formed on the second surface. Alignment lasers are incident from the second surface direction onto the alignment photolithography mask and the first pattern structure 110, the second pattern structure 210, and the third pattern structure 310. That is, the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 need to be thinned from the back side and then subjected to photolithographic alignment. Alignment lasers are incident from the back side direction onto the alignment photolithography mask and the alignment mark structure. At this time, the light-blocking layer 400 can prevent the alignment laser from penetrating to the lower wafer. The alignment mark structure on the lower wafer will not reflect diffracted light that affects the diffracted light reflected by the alignment mark structure on the upper wafer. Therefore, it will not affect the phase information of the interference fringes, nor will it cause fluctuations or interference in the alignment fringes. The alignment fringes in the photolithographic alignment process are normal alignment fringes, as shown in the attached diagram. Figure 2 This ensures that the reading of the alignment mark structure on the wafer of the current layer is not affected.

[0070] Furthermore, a first dielectric layer is disposed on the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310; a light-blocking layer 400 is disposed on the first dielectric layer; and a second dielectric layer is disposed on the light-blocking layer 400. The first dielectric layer and the second dielectric layer are one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0071] Furthermore, the three-dimensional stacked chip in this invention is not limited to the stacking of three-layer wafers, but can also stack wafers with more layers to further improve the chip integration.

[0072] In summary, the semiconductor structure of the present invention has the following advantages:

[0073] 1. The semiconductor structure provided by the present invention enables multiple stacked identical wafers or chips to use the same photomask when manufacturing the alignment mark layer, eliminating the need to continuously change the photomask of the alignment mark layer to prepare wafers or chips with different alignment mark positions, as is done in the prior art. This greatly reduces the complexity and production cost in the wafer manufacturing process.

[0074] 2. The semiconductor structure provided by this invention can be made into multiple identical wafer layers, which can be interchanged with each other, reducing waste caused by special wafer pairing process;

[0075] 3. The semiconductor structure provided by the present invention can use the same photomask during the fabrication of multiple wafer layers, avoiding the situation of fabricating multiple different photomasks in the prior art, and greatly reducing the manufacturing cost of photomasks;

[0076] 4. The light blocking layer in the semiconductor structure provided by the present invention can effectively avoid the interference of the alignment mark structure on the lower wafer to the alignment mark structure on the upper wafer during the photolithography alignment process, greatly reducing alignment deviation and improving alignment accuracy.

[0077] Appendix Figure 7 This is a schematic diagram of the process flow of a single wafer layer in a three-dimensional stacked structure according to a specific embodiment of the present invention.

[0078] Please refer to the attached document. Figure 7 The present invention also provides a method for fabricating a semiconductor structure, the method comprising: providing a first wafer layer 100 having a first surface and a second surface, forming a first pattern structure 110 on the first surface of the first wafer layer 100, the method of forming the first pattern structure 110 on the first surface of the first wafer layer 100 employing an etching process; the etching process may employ dry etching or wet etching.

[0079] Furthermore, a first dielectric layer 120 is deposited on the first patterned structure 110. The first dielectric layer 120 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The deposition process of the first dielectric layer 120 can be thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD). The first dielectric layer 120 is planarized by chemical mechanical polishing (CMP).

[0080] Furthermore, a light-blocking material layer 130 is deposited on the first dielectric layer 120, wherein the light-blocking material layer 130 is selected from a material layer with low light transmittance and high light absorption.

[0081] Furthermore, the aforementioned photoblocking material layer 130 is patterned: a layer of photoresist is coated onto the photoblocking material layer using methods such as spin coating and spray coating; then, the pattern on the photomask is transferred onto the photoresist through exposure and development; the photoblocking material layer is etched using the patterned photoresist as a mask, retaining the photoblocking material layer 130 covered by the photoresist, and finally the photoresist is removed to form a photoblocking layer 400, which is located above the first patterned structure 110.

[0082] Furthermore, a second dielectric layer 140 is deposited on the light-blocking layer. The second dielectric layer 140 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The deposition process of the second dielectric layer 140 can be thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD). The second dielectric layer 140 is planarized by chemical mechanical polishing (CMP).

[0083] Furthermore, the first surface of the first wafer layer 100 is stacked on the carrier wafer layer and flipped, and the second surface of the first wafer layer 100 is thinned to an appropriate thickness.

[0084] Furthermore, a second wafer layer 200 is provided, having a first surface and a second surface. A second pattern structure 210 is formed on the first surface of the second wafer layer 200. The method for forming the second pattern structure 210 on the first surface of the second wafer layer 200 employs an etching process. The etching process may employ dry etching or wet etching.

[0085] Furthermore, a first dielectric layer is deposited on the second patterned structure 210. The first dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The deposition process of the first dielectric layer can be thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD), etc., and chemical mechanical planarization (CMP) is used to planarize the first dielectric layer.

[0086] Furthermore, a light-blocking material layer is deposited on the first dielectric layer, wherein the light-blocking material layer is selected from materials with low light transmittance and high light absorption.

[0087] Furthermore, the aforementioned photoblocking material layer is patterned: a layer of photoresist is coated onto the photoblocking material layer using methods such as spin coating and spray coating; then, the pattern on the photomask is transferred onto the photoresist through exposure and development; the photoblocking material layer is etched using the patterned photoresist as a mask, retaining the photoblocking material layer covered by the photoresist, and finally the photoresist is removed to form a photoblocking layer, which is located above the second pattern structure 210.

[0088] Furthermore, a second dielectric layer is deposited on the light-blocking layer. The second dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The deposition process of the second dielectric layer can be thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD). The second dielectric layer is planarized using chemical mechanical polishing (CMP).

[0089] Furthermore, the first surface of the second wafer layer 200 is stacked on the second surface of the first wafer layer 100 and flipped, and the second surface of the second wafer layer 200 is thinned to an appropriate thickness. Then, an alignment laser is irradiated from the second surface of the second wafer 200, at which time the light blocking layer can prevent the alignment laser from penetrating to the lower wafer.

[0090] Furthermore, a third wafer layer 300 is provided, having a first surface and a second surface. A third pattern structure 310 is formed on the first surface of the third wafer layer 300. The method for forming the third pattern structure 310 on the first surface of the third wafer layer 300 employs an etching process. The etching process may employ dry etching or wet etching.

[0091] Furthermore, a first dielectric layer is deposited on the third patterned structure 310. The first dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The deposition process of the first dielectric layer can be thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD), etc., and chemical mechanical planarization (CMP) is used to planarize the first dielectric layer.

[0092] Furthermore, a light-blocking material layer is deposited on the first dielectric layer, wherein the light-blocking material layer is selected from materials with low light transmittance and high light absorption.

[0093] Furthermore, the aforementioned photoblocking material layer is patterned: a layer of photoresist is coated onto the photoblocking material layer using methods such as spin coating and spray coating; then, the pattern on the photomask is transferred onto the photoresist through exposure and development; the photoblocking material layer is etched using the patterned photoresist as a mask, retaining the photoblocking material layer covered by the photoresist, and finally the photoresist is removed to form a photoblocking layer, which is located above the third pattern structure 310.

[0094] Furthermore, a second dielectric layer is deposited on the light-blocking layer. The second dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The deposition process of the second dielectric layer can be thermal oxidation, chemical vapor deposition (CVD), and atomic layer deposition (ALD). The second dielectric layer is planarized using chemical mechanical polishing (CMP).

[0095] Furthermore, the first surface of the third wafer layer 300 is stacked on the second surface of the second wafer layer 200 and flipped. The second surface of the third wafer layer 300 is then thinned to an appropriate thickness. A alignment laser is then irradiated from the second surface of the third wafer 300, at which point a light-blocking layer prevents the alignment laser from penetrating to the lower wafer layer.

[0096] Furthermore, the first surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 can be the front surface of the wafer layer, having an active area thereon. The second surface of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 can be the back surface of the wafer layer, having a bonding structure thereon.

[0097] Furthermore, the first pattern structure 110, the second pattern structure 210, and the third pattern structure 310 are alignment pattern structures, i.e., alignment mark structures, used to align the pattern on the wafer with the pattern on the photolithography mask during the photolithography alignment process. The alignment marks typically employ a grating structure containing a "striped" pattern. The first pattern structure 110, the second pattern structure 210, and the third pattern structure 310 are all pre-set on the first surfaces of the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300, respectively, as alignment marks in the subsequent three-dimensional stacked chip fabrication process.

[0098] Furthermore, the light-blocking layers 400 are all disposed above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310. In the vertical projection direction, the light-blocking layers 400 completely block the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310. Furthermore, in the fabrication process, the light-blocking layer 400 can be a single layer disposed above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310; it can also be a functional layer structure in the wafer fabrication process, extending above the first patterned structure 110, the second patterned structure 210, and the third patterned structure 310. The functional layer structure can be one of the following: a gate electrode layer, a source / drain electrode layer, a word line layer, a bit line layer, or an electrode plate of a capacitor structure, but is not limited to these; it can also be other functional layers in the wafer fabrication process.

[0099] Furthermore, in the fabrication process, the light-blocking layer 400 is formed using a material layer with low transmittance and high absorbance. In this invention, a metal material layer is preferentially used to form the light-blocking layer, and a tungsten metal layer is more preferred. However, this is not limited to this embodiment, and other material layers with low transmittance and high absorbance can also be used to form the light-blocking layer.

[0100] In the fabrication process of a three-dimensional stacked chip, the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 need to be thinned from the second surface and then subjected to photolithographic alignment. Further bonding structures are then formed on the second surface. Alignment lasers are incident from the second surface direction onto the alignment photolithography mask and the first pattern structure 110, the second pattern structure 210, and the third pattern structure 310. That is, the first wafer layer 100, the second wafer layer 200, and the third wafer layer 300 need to be thinned from the back side and then subjected to photolithographic alignment. Alignment lasers are incident from the back side direction onto the alignment photolithography mask and the alignment mark structure. At this time, the light-blocking layer 400 can prevent the alignment laser from penetrating to the lower wafer. The alignment mark structure on the lower wafer will not reflect diffracted light that affects the diffracted light reflected by the alignment mark structure on the upper wafer. Therefore, it will not affect the phase information of the interference fringes, nor will it cause fluctuations or interference in the alignment fringes. The alignment fringes in the photolithographic alignment process are normal alignment fringes, as shown in the attached diagram. Figure 2 This ensures that the reading of the alignment mark structure on the wafer of the current layer is not affected.

[0101] In summary, the method for preparing the semiconductor structure of the present invention has the following advantages:

[0102] 1. The semiconductor structure provided by the present invention enables multiple stacked identical wafers or chips to use the same photomask when manufacturing the alignment mark layer, eliminating the need to continuously change the photomask of the alignment mark layer to prepare wafers or chips with different alignment mark positions, as is done in the prior art. This greatly reduces the complexity and production cost in the wafer manufacturing process.

[0103] 2. The semiconductor structure provided by this invention can be made into multiple identical wafer layers, which can be interchanged with each other, reducing waste caused by special wafer pairing process;

[0104] 3. The semiconductor structure provided by the present invention can use the same photomask during the fabrication of multiple wafer layers, avoiding the situation of fabricating multiple different photomasks in the prior art, and greatly reducing the manufacturing cost of photomasks;

[0105] 4. The light blocking layer in the semiconductor structure provided by the present invention can effectively avoid the interference of the alignment mark structure on the lower wafer to the alignment mark structure on the upper wafer during the photolithography alignment process, greatly reducing alignment deviation and improving alignment accuracy.

[0106] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0107] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0108] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A first wafer layer (100) is provided, having a first surface and a second surface, and a first patterned structure (110) is formed on the first surface of the first wafer layer (100) by an etching process. A first dielectric layer is deposited on the first pattern structure (110), and the first dielectric layer is planarized; A light-blocking material layer is deposited on the first dielectric layer; The light-blocking material layer is patterned to form a light-blocking layer (400), which is located above the first patterned structure (110); A second dielectric layer is deposited on the light-blocking layer (400), and the second dielectric layer is planarized. The first surface of the first wafer layer (100) is stacked on the carrier wafer layer and flipped, and the second surface of the first wafer layer (100) is thinned. A second wafer layer (200) is provided, having a first surface and a second surface, and a second patterned structure (210) is formed on the first surface of the second wafer layer (200) by an etching process; A first dielectric layer is deposited on the second pattern structure (210), and the first dielectric layer is planarized; A light-blocking material layer is deposited on the first dielectric layer; The light-blocking material layer is patterned to form a light-blocking layer (400), which is located above the second patterned structure (210); A second dielectric layer is deposited on the light-blocking layer, and the second dielectric layer is planarized. The first surface of the second wafer layer (200) is stacked on the second surface of the first wafer layer (100) and flipped, and the second surface of the second wafer layer (200) is thinned. The first graphic structure (110) and the second graphic structure (210) are aligned graphic structures, which are grating structures containing a "striped" pattern; The first surface of the second wafer layer (200) is stacked on the second surface of the first wafer layer (100); The first pattern structure (110) and the second pattern structure (210) use the same photomask; The first surface of the first wafer layer (100) and the second wafer layer (200) is the front side of the wafer layer, and has an active region thereon; the second surface of the first wafer layer (100) and the second wafer layer (200) is the back side of the wafer layer, and has a bonding structure thereon. In the vertical projection direction, the light blocking layer (400) completely blocks the first graphic structure (110) and the second graphic structure (210).

2. The preparation method according to claim 1, characterized in that, A third wafer layer (300) is provided, having a first surface and a second surface, wherein a third pattern structure (310) is formed on the first surface of the third wafer layer (300). A first dielectric layer is deposited on the third pattern structure (310), and the first dielectric layer is planarized. A light-blocking material layer is deposited on the first dielectric layer; The light-blocking material layer is patterned to form a light-blocking layer (400), which is located above the third patterned structure (310); A second dielectric layer is deposited on the light-blocking layer (400), and the second dielectric layer is planarized. The first surface of the third wafer layer (300) is stacked on the second surface of the second wafer layer (200) and flipped, and the second surface of the third wafer layer (300) is thinned. The third graphic structure (310) is an aligned graphic structure, which is a grating structure containing a "striped" pattern; The first surface of the third wafer layer (300) is stacked on the second surface of the second wafer layer (200).

3. The preparation method according to claim 2, characterized in that, The first surface of the third wafer layer (300) is the front side of the wafer layer, and it has an active region thereon; the second surface of the third wafer layer (300) is the back side of the wafer layer, and it has a bonding structure thereon.

4. The preparation method according to claim 3, characterized in that, In the vertical projection direction, the light blocking layer (400) completely blocks the third graphic structure (310).

5. The preparation method according to claim 4, characterized in that, The light-blocking layer (400) is a separate layer disposed above the first graphic structure (110), the second graphic structure (210), and the third graphic structure (310).

6. The preparation method according to claim 4, characterized in that, The light-blocking layer (400) is a functional layer structure in the wafer fabrication process, extending above the first patterned structure (110), the second patterned structure (210), and the third patterned structure (310).

7. The preparation method according to claim 5 or 6, characterized in that, The light-blocking layer (400) is formed using a tungsten metal layer.

8. A semiconductor structure formed by the method for preparing a semiconductor structure as described in any one of claims 1 to 7, characterized in that, The semiconductor structure includes: A first wafer layer (100) has a first surface and a second surface. A first pattern structure (110) is formed on the first surface of the first wafer layer (100). A first dielectric layer is deposited on the first pattern structure (110), and a light blocking layer (400) is located on the first dielectric layer. A second wafer layer (200) has a first surface and a second surface. A second pattern structure (210) is formed on the first surface of the second wafer layer (200). A first dielectric layer is deposited on the second pattern structure (210), and a light blocking layer (400) is located on the first dielectric layer. The first surface of the second wafer layer (200) is stacked on the second surface of the first wafer layer (100). The first pattern structure (110) and the second pattern structure (210) are aligned pattern structures, which are grating structures containing a "striped" pattern.

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