ESD protection device
By introducing a second P-type well into the ESD protection device to form a depletion region with the drift region, the current density is controlled, which solves the problem of insufficient electrostatic protection capability of existing ESD devices, realizes effective electrostatic protection under high voltage and negative voltage environments, and reduces the design difficulty.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI MICROELECTRONICS CORP
- Filing Date
- 2023-04-26
- Publication Date
- 2026-07-31
AI Technical Summary
Existing ESD protection devices are insufficient in electrostatic protection and have limited application areas, especially in complex environments such as high voltage and negative voltage, and are difficult to design.
Design an ESD protection device including a P-type substrate, an N-type ion implantation region, first and second P-type wells, a drain region, a gate, and a local field oxide layer. By adding a second P-type well and a drift region to form a depletion region, the current density distribution can be controlled to achieve devices with different breakdown voltages and ESD capabilities, suitable for various operating conditions.
It reduces the design difficulty of ESD devices, expands their application range, improves electrostatic protection capabilities, and adapts to various complex working conditions, especially high-voltage and negative-voltage environments.
Smart Images
Figure CN116259625B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronics manufacturing technology, and in particular to an ESD protection device. Background Technology
[0002] Commonly used ESD (Electrostatic Discharge Protection Devices) design schemes mainly include GGNMOS (Gate Ground NMOS), GCNMOS (Gate Coupled NMOS), STNMOS (Substratet Rigging NMOS), and GGNLDMOS. However, each design scheme still has limitations in its application areas, as detailed below:
[0003] GGNMOS: Its principle is to use the switching on of the body parasitic transistor as a path for discharging ESD static current. The gate, source, and body terminals of the NMOS device are connected together and parallel to the cathode, while the drain is connected to the anode. However, it utilizes the body parasitic transistor as a path for discharging ESD static current. But the huge parasitic capacitance limits its application in fields such as SerDes (serial-to-parallel converters) and AD-DA (digital-to-analog converters), making device simulation difficult.
[0004] GCNMOS: Utilizes the channel of an NMOS device as a discharge path. There are two ways to turn on an NMOS transistor using a GCNMOS: one is by using the electrostatic frequency as the trigger condition, and the other is by using the electrostatic voltage as the trigger condition. However, it requires a large area and cannot be used in complex applications such as high voltage or negative voltage, and its layout and wiring also have corresponding requirements.
[0005] STNMOS: It utilizes the channel of an NMOS device as a discharge path. The difference between STNMOS and GCNMOS lies in its body-triggered ESD protection. However, it cannot be used in complex applications such as high voltage or negative voltage, and its design is complex.
[0006] GGNLDMOS: Similar to GGNMOS, its source, gate and body are grounded. However, LDMOS has a higher risk of thermal failure and requires redistribution of the electric field. The layout size and device structure need to be changed to prevent the electric field from being too concentrated, which makes the design difficult.
[0007] GGNMOS, GCNMOS, and STNMOS, which are based on NMOS structures, are difficult to withstand high breakdown voltages. GGNMOS devices based on LDMOS structures are mainly used in industrial and automotive-grade products, where the working environment is more complex and variable, and the requirements for ESD and surge protection are relatively high. There is an urgent need for a new type of ESD protection device that is easy to design and use in various fields and has good electrostatic protection capabilities. Summary of the Invention
[0008] The purpose of this invention is to provide an ESD protection device to solve the problems of low electrostatic protection capability and limited application fields of existing ESD devices.
[0009] To solve the above-mentioned technical problems, the present invention provides an ESD protection device, comprising:
[0010] P-type substrate;
[0011] An N-type ion implantation region is formed in the P-type substrate. The N-type ion implantation region includes an N-type well, an N-type buried layer, and a drift region. The N-type well is formed in the P-type substrate, and the N-type buried layer and the drift region are distributed sequentially from left to right on its top.
[0012] A first P-type well is formed in the N-type buried layer, and a P-type well lead-out region and a source region are formed in the first P-type well.
[0013] A drain region is formed in the drift region and is connected to a first potential input terminal, which serves as an electrostatic input terminal. A local field oxide layer is also provided in the P-type substrate located between the first P-type well and the drain region.
[0014] A gate is formed on the surface of the P-type substrate, and covers at least a portion of the first P-type well and extends to the surface of the local field oxide layer. The source region, the gate, and the exit terminal of the P-type substrate are all connected to a ground terminal.
[0015] At least one second P-type well is formed in the N-type ion implantation region and is at least partially located in the drift region, with a portion of the drift region between the second P-type well and the local field oxide layer.
[0016] Preferably, a second P-type well is provided, and there is a gap between it and the first P-type well.
[0017] Preferably, the first P-type well is in contact with the boundary of the adjacent second P-type well, or the first P-type well and the adjacent second P-type well at least partially overlap.
[0018] Preferably, at least two second P-type traps are provided and are spaced apart along the length of the channel between the source region and the drain region.
[0019] Preferably, the N-type buried layer is formed by growing an N-type epitaxial layer on the P-type substrate using an epitaxial process.
[0020] Preferably, the local field oxide layer is flush with the surface of the P-type substrate to form a shallow trench isolation structure.
[0021] Preferably, at least one polysilicon field plate is formed on the local field oxide layer for connecting to the second potential input terminal to regulate the current in the drift region.
[0022] Preferably, the second P-type well is in contact with the boundary of the N-type well, or the second P-type well is at least partially located within the N-type well.
[0023] Preferably, N-type ions are implanted into the P-type substrate to form the N-type well, wherein the implantation depth of the N-type ions ranges from 0.8 to 2.7 μm.
[0024] Preferably, P-type ions are implanted into the P-type substrate to form the second P-type well, wherein the implantation depth of the P-type ions ranges from 2.3 to 4.7 μm.
[0025] In the ESD protection device provided by the present invention, the gate, P-type substrate and source region are grounded, and a second P-type well is added at the drift region and N-type well. The second P-type well and the drift region form a depletion region, which further regulates the current density distribution. The ESD surge current enters the parasitic transistor inside the device through the drain region and is released instantaneously.
[0026] Furthermore, this invention enables the creation of devices with varying breakdown voltages and ESD capabilities by controlling the size of the second P-type well, allowing them to operate under diverse conditions. This facilitates the design of ESD devices for various application scenarios, significantly reducing the design complexity. For example, designing only one second P-type well reduces the breakdown voltage and correspondingly improves the ESD capability as the well length decreases. Additionally, at least two second P-type wells can be used to improve the distribution of lateral and longitudinal currents within the device, maximizing the breakdown voltage and enhancing ESD capability. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of GGNMOS;
[0028] Figures 2a-2c This is a voltage triggering circuit diagram for GCNMOS;
[0029] Figures 3a-3b This is a frequency triggering circuit diagram for GCNMOS;
[0030] Figure 4 This is a circuit diagram of STNMOS;
[0031] Figure 5 This is a schematic diagram of GGNLDMOS;
[0032] Figure 6 This is a schematic diagram of the structure of an ESD protection device provided by the present invention, which has a second P-type well connected to a first P-type well.
[0033] Figure 7 This is a schematic diagram of the structure of an ESD protection device provided by the present invention, which has a second P-type well that is not connected to the first P-type well.
[0034] Figure 8 This is a schematic diagram of the structure of the ESD protection device with three spaced-out second P-type wells provided by the present invention.
[0035] Figure 9 This is a schematic diagram of the lateral current path according to Embodiment 1 of the present invention;
[0036] Figure 10 This is a schematic diagram of the longitudinal current path of Embodiment 1 provided by the present invention;
[0037] Figure 11 This is a schematic diagram of the current path in Embodiment 2 provided by the present invention;
[0038] Figure 12 This is a schematic diagram of the current path in Embodiment 3 provided by the present invention.
[0039] In the picture,
[0040] 1. P-type substrate; 2. N-type well; 3. Second P-type well; 4. N-type buried layer; 5. Drain region; 6. Local field oxide layer; 7. P-type well extraction region; 8. Source region; 9. First P-type well; 10. Drift region; 11. Gate; 12. Polysilicon field plate; 13. N-type ion implantation region. Detailed Implementation
[0041] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0042] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0044] The ESD protection device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0045] The inventors discovered some defects in common ESD devices:
[0046] GGNMOS: Its principle is to utilize the switching on of the body parasitic transistor to provide a discharge path for ESD static current. For example... Figure 1 As shown, in an NMOS device, the gate, source, and body terminals are all connected to the cathode, while the drain is connected to the anode. ESD current causes the reverse-biased junction between the drain and the P-sub (P-type substrate) to break down. At this point, avalanche breakdown carriers dominate, and the current (Isub) flows to the p-sub. The resistance of the p-sub generates a bias voltage under the influence of the avalanche carriers. The NPN parasitic transistor formed between the drain, P-sub, and source is fully turned on. This voltage, called the Trigger Voltage, indicates that the device begins to exhibit snap-back characteristics, and the conduction mechanism changes. Once the offset carriers provide all the current, the voltage decreases; this voltage is called the Holding Voltage. Afterward, the device's circuit characteristics resemble a resistor until secondary breakdown occurs, leading to device damage. However, it utilizes the body parasitic transistor as a discharge path for ESD static current. However, its huge parasitic capacitance limits its application in fields such as SerDes (serial-to-parallel converters) and AD-DA (digital-to-analog converters), making device simulation difficult.
[0047] GCNMOS: The channel of the NMOS device is utilized as a discharge path. There are two ways to turn on the NMOS transistor in GCNMOS: one is to use the electrostatic frequency as the triggering condition, and the other is to use the static voltage as the triggering condition. As Figures 2a-2c shown in the voltage triggering circuit (in the figure, VSS is the digital ground; VDD is the digital power supply; Z-diode is the Zener diode), after an ESD current is generated on VDD, this part of the current will accumulate at the anode of the diode string or the cathode of the Zener diode until the voltage is high enough to turn on the device. As Figure 2c , by utilizing this characteristic, the turn-on voltage Von of the Zener diode or the diode string is adjusted such that VDD < Von < Vbreakdown (breakdown voltage), and the voltage to turn on the diode should be greater than the normal operating voltage and less than the breakdown voltage of the internal device. Figures 3a-3b Shown in the frequency triggering circuit, through the frequency characteristic of the RC circuit, the high-frequency ESD current is distinguished from the waveform of normal power-on. When the voltage is higher than the NMOS threshold voltage, the channel is turned on, and a static current discharge path from VDD to GND (ground terminal) appears. However, it requires a large area and cannot be applied to complex scenarios such as high voltage and negative voltage, and there are corresponding requirements for layout and wiring.
[0048] STNMOS: It utilizes the channel of the NMOS device as a discharge path. The difference from GCNMOS lies in achieving ESD protection through body triggering. As Figure 4 in which there are ProtectionNMOS (protected NMOS transistor), Substrate-triggeringNMOS (substrate-triggered NMOS transistor), VSS (digital ground), and PAD (interface circuit). Part of the current is injected into the substrate of the ProtectionNMOS (protected NMOS transistor) to assist in turning on the parasitic NPN transistor in the ProtectionNMOS. Body triggering is to inject the holding current Ih into the base of the parasitic transistor, so that the transistor can be turned on without forming an avalanche breakdown between the Drain (drain) and the substrate (substrate), and it can also reduce the Trigger voltage and utilize the transistor to form a discharge path. It utilizes the channel of the NMOS device as a discharge path. The difference from GCNMOS is that it achieves ESD protection through body triggering. However, it cannot be applied to complex scenarios such as high voltage and negative voltage, and the design is complex.
[0049] GGNLDMOS: It is similar to GGNMOS, and its source, gate, and body terminals are grounded. As Figure 5As shown in the figure, HVNW is the high-voltage N-well, LVPW is the low-voltage P-well, N-epi is the N-type epitaxial layer, and NBL is the N-type buried layer. The drain is connected to I / OPAD (chip pin processing module). However, LDMOS has a high risk of thermal failure and requires redistribution of the electric field. The layout size and device structure need to be changed to prevent the electric field from being too concentrated, which makes the design difficult.
[0050] These devices based on NMOS (N-Metal-Oxide-Semiconductor) structures are difficult to withstand high breakdown voltages, thus limiting their application areas. While GGNLDMOS based on LDMOS (Lateral Double Diffused MOSFET) structures has relatively higher breakdown voltages and can be used in industrial and automotive-grade products, this also places higher demands on the ESD and surge protection of GGNLDMOS, making the design more difficult.
[0051] Based on this, the core idea of this invention is to add a second P-type well to nLDMOS, forming a depletion region with the drift region, and ground the gate to form a GGNMOS device. The surge current is instantaneously released through the parasitic transistor inside the device. By adjusting the length of the second P-type well, the range of the depletion region can be changed, thus altering the current shunt. This facilitates the design and formation of devices with different breakdown voltages and ESD capabilities to suit various operating conditions.
[0052] For details, please refer to Figures 6-12 This is a schematic diagram of an embodiment of the present invention. Figure 6As shown, an ESD protection device includes: a P-type substrate 1; an N-type ion implantation region 13 formed in the P-type substrate 1, the N-type ion implantation region 13 including an N-type well 2, an N-type buried layer 4, and a drift region 10, the N-type well 2 being formed in the P-type substrate 1, and the N-type buried layer 4 and the drift region 10 being sequentially distributed from left to right on its top; a first P-type well 9 formed in the N-type buried layer 4, the first P-type well 9 having a P-type well lead-out region 7 and a source region 8; and a drain region 5 formed in the drift region 10, the drain region 5 being connected to a first potential input terminal, the first potential input terminal serving as a static... The electrical input terminal includes a local field oxide layer 6 in the P-type substrate 1 located between the first P-type well 9 and the drain region 5; a gate 11 formed on the surface of the P-type substrate 1, covering at least a portion of the first P-type well 9 and extending to the surface of the local field oxide layer 6; the source region 8, the gate 11, and the output terminal of the P-type substrate 1 are all connected to a ground terminal; at least one second P-type well 3 is formed in the N-type ion implantation region 13 and is at least partially located in the drift region 10, with a portion of the drift region 10 between the second P-type well 3 and the local field oxide layer 6.
[0053] like Figure 6 From left to right, a P-type well lead-out region 7, a source region 8, a local field oxide layer 6, and a drain region 5 are sequentially arranged on the surface of the P-type substrate 1. The direction from left to right is from the source region 8 to the drain region 5. The P-type well lead-out region 7 and the source region 8 are arranged sequentially on the surface of the P-type substrate 1. The gate 11 is grounded to form a GGNMOS device. Further, the source region 8 and the P-type substrate 1 are grounded. The polysilicon field plate 12 is connected to an independent potential to control the electric field of the drift region 10. This high resistance reduces the channel electric field and increases the operating voltage. A second P-type well 3 (also known as a P-type deep well DPW) is added to form a depletion region with the drift region 10, further regulating the current density distribution. This allows ESD surge current to be instantly released through the drain region 5 into the parasitic BJT (Bipolar Junction Transistor) inside the device. Furthermore, by adjusting the length of the second P-type well 3, devices with different breakdown voltages and ESD capabilities can be formed, facilitating the design of devices that operate under various conditions. Among them, the N-type well 2, the drift region 10, the source region 8 and the drain region 5 are all formed by N-type ions implanted into the P-type substrate 1, the second P-type well 3, the first P-type well 9 and the P-type well lead-out region 7 are all formed by P-type ions implanted into the P-type substrate 1, the P-type substrate 1 is connected from the P-type well lead-out region 7 and is grounded after being connected together with the source region 8.
[0054] Understandably, N-type epitaxial layers have better conductivity. The N-type buried layer 4 is formed by growing an N-type epitaxial layer on the P-type substrate 1 using an epitaxial process.
[0055] In one embodiment, the local field oxide layer 6 is flush with the surface of the P-type substrate 1 to form a shallow trench isolation structure. By using the STI shallow trench isolation structure, the device size can be reduced, enabling the ESD device of this application to be designed and formed based on LDMOS at 55nm and below nodes.
[0056] Specifically, at least one polysilicon field plate 12 is formed on the local field oxide layer 6, used to connect to a different potential input terminal to regulate the current in the drift region 10. That is, the polysilicon field plate 12 is connected to an independent positive potential, controlling the electric field distribution below the shallow trench isolation structure, affecting the current density. The polysilicon field plate 12 acts as a high resistor to reduce the channel electric field and increase the operating voltage. Grounding the gate 11 terminal has no modulation effect; applying a separate potential to the polysilicon field plate 12 can regulate the current in the HVNDF region (drift region 10). The second P-type well 3 is connected to the boundary of the N-type well 2, or the second P-type well 3 is at least partially located within the N-type well 2.
[0057] In one embodiment, N-type ions are implanted into the P-type substrate 1 to form the N-type well 2, wherein the implantation depth of the N-type ions ranges from 0.8 to 2.7 μm. P-type ions are implanted into the P-type substrate 1 to form the second P-type well 3, wherein the implantation depth of the P-type ions ranges from 2.3 to 4.7 μm.
[0058] More specifically, the second P-type trap 3 (DPW) uses P-type elements for implantation, commonly boron (B), and employs a high-energy IMP (ion implantation) machine to a depth of approximately 1–2.5 μm; the N-type trap 2 (also known as the N-type deep trap DNW) uses N-type elements, commonly phosphorus (P), and employs a high-energy IMP machine to an ion implantation depth of approximately 2.5–4.5 μm.
[0059] The distribution of the second P-type well 3 (DPW) affects the depletion region distribution from the drift region 10 to the first P-type well 9, thus affecting the performance of the NPN transistor. Furthermore, the second P-type well 3 also affects the distribution of lateral and longitudinal currents. Therefore, based on the above-mentioned technical solution, with the source and gate grounded at all three terminals, the polysilicon field plate 12 connected to an independent potential, and the drain region 5 connected to the I / O input circuit, embodiments of ESD protection devices with different second P-type wells 3 are given:
[0060] Example 1
[0061] like Figure 6As shown, the first P-type well 9 is connected to the boundary of the adjacent second P-type well 3, or the first P-type well 9 and the adjacent second P-type well 3 at least partially overlap. Only one second P-type well 3 is designed here, and it is connected to the first P-type well 9, forming a parasitic transistor between the source region 8, the first P-type well 9, and the N-type buried layer 4. The path of the lateral current is as follows... Figure 9 As shown, the path of the longitudinal current is as follows Figure 10 As shown, the I / O input current mainly passes through the lateral current path. The high voltage region of drift region 10 (HVNDF) can withstand high withstand voltage and has a high breakdown voltage, but its ESD capability (It2 secondary breakdown current) is relatively low. Figure 10 The polycrystalline silicon field plate 12 in the middle is connected to an independent potential.
[0062] The length of the second P-type well 3 (DPW) is equal to the length of the shallow trench isolation structure (STIwidth) plus the length of the gate (gate 11) overlapping HVNDF (drift region 10) and N-epi (N-type buried layer 4). That is, the length of the second P-type well 3 is the length of the local field oxide layer 6 plus the length of the gate 11 overlapping the drift region 10 and the N-type buried layer 4. This length is the length along the channel length direction. The left boundary of the second P-type well 3 must coincide with the boundary of the first P-type well 9 (P-body). The actual length range of the second P-type well 3 is affected by other dimensions of the device and is approximately 3μm to 8μm.
[0063] Example 2
[0064] like Figure 7 As shown, a second P-type well 3 is provided, and there is a gap between it and the first P-type well 9. Figure 10 The polycrystalline silicon field plate 12 in the middle is connected to an independent potential. For example... Figure 11 As shown in the circuit diagram, the length of the second P-type well 3 is reduced compared to that in Embodiment 1, resulting in increased lateral and longitudinal currents and a significant improvement in ESD capability (It2). However, since the first P-type well 9 and the second P-type well 3 are not connected, the current will converge in the lateral path, leading to a relatively low breakdown voltage. In this embodiment, the length of the integral second P-type well 3 (DPW) is reduced compared to Embodiment 1, with its left side just below the HVNDF (drift region 10) boundary, and the length range is approximately 2.7 μm to 7.5 μm.
[0065] Example 3
[0066] Based on Embodiment 1, a device with superior ESD protection capability is provided: at least two second P-type wells 3 are provided, and they are spaced apart along the length of the channel between the source region 8 and the drain region 5. For example... Figure 8The schematic diagram shows that three second P-type traps 3 can be arranged at intervals in the drift region 10. The leftmost second P-type trap 3 is connected to the first P-type trap 9, and the rightmost second P-type trap 3 is divided into multiple blocks, as shown in the diagram. Figure 12 The current path is designed to increase the longitudinal current, thereby enhancing the ESD capability (It2) while minimizing the reduction in breakdown voltage. The ESD protection device here has both lateral and longitudinal current paths, and the segmented design of multiple second P-type wells 3 ensures a balance between current magnitude and breakdown voltage.
[0067] In Embodiment 3, the second P-type well 3 can be in two or three segments. The leftmost segment must be connected to the boundary of the first P-type well 9 to ensure a certain high breakdown voltage. The minimum process range of each segment is about 0.5 μm long, and there is a gap of about 0.5 μm between the two segments.
[0068] In summary, the ESD protection device provided in this invention, based on the existing nLDMOS device design, adds a second P-type well. By adjusting the length of the second P-type well and changing the range of the depletion region, different breakdown voltages and ESD capabilities can be achieved, and the current shunt can be altered. This facilitates the design of devices with different ESD capabilities to adapt to various operating conditions. When forming an integral second P-type well, connecting the second P-type well to the first P-type well results in a device with a higher breakdown voltage but lower ESD capability; shortening the second P-type well and separating it from the first P-type well results in a device with a lower breakdown voltage but better ESD capability. Alternatively, the second P-type well can be designed in segments, i.e., at least two second P-type wells can be designed. When the leftmost second P-type well is connected to the first P-type well, the breakdown voltage can be maximized, thus improving the ESD capability.
[0069] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. An ESD protection device, characterized by, include: P-type substrate; An N-type ion implantation region is formed in the P-type substrate. The N-type ion implantation region includes an N-type well, an N-type buried layer, and a drift region. The N-type well is formed in the P-type substrate, and the N-type buried layer and the drift region are distributed sequentially from left to right on its top. A first P-type well is formed in the N-type buried layer, and a P-type well lead-out region and a source region are formed in the first P-type well. A drain region is formed in the drift region and is connected to a first potential input terminal, which serves as an electrostatic input terminal. A local field oxide layer is also provided in the P-type substrate located between the first P-type well and the drain region. A gate is formed on the surface of the P-type substrate, and covers at least a portion of the first P-type well and extends to the surface of the local field oxide layer. The source region, the gate, and the exit terminal of the P-type substrate are all connected to a ground terminal. At least one second P-type well is formed in the N-type ion implantation region and is at least partially located in the drift region. The drift region is partially between the second P-type well and the local field oxide layer. The boundary between the second P-type well and the N-type well is adjacent. Alternatively, the second P-type well is at least partially located in the N-type well. In this case, the second P-type well and the drift region form a depletion region.
2. The ESD protection device of claim 1, wherein, A second P-type well is provided, and there is a gap between it and the first P-type well.
3. The ESD protection device of claim 1, wherein, The first P-type well is in contact with the boundary of the adjacent second P-type well, or the first P-type well and the adjacent second P-type well at least partially overlap.
4. The ESD protection device as described in claim 3, characterized in that, At least two second P-type traps are provided and are spaced apart along the length of the channel between the source region and the drain region.
5. The ESD protection device of claim 1, wherein, The N-type buried layer is formed by growing an N-type epitaxial layer on the P-type substrate using an epitaxial process.
6. The ESD protection device of claim 1, wherein, The local field oxide layer is flush with the surface of the P-type substrate to form a shallow trench isolation structure.
7. The ESD protection device of claim 1, wherein, At least one polysilicon field plate is formed on the local field oxide layer for connecting to the second potential input terminal to regulate the current in the drift region.
8. The ESD protection device of claim 1, wherein, N-type ions are implanted into the P-type substrate to form the N-type well, wherein the implantation depth of the N-type ions ranges from 0.8 to 2.7 µm.
9. The ESD protection device of claim 1, wherein, P-type ions are implanted into the P-type substrate to form the second P-type well, wherein the implantation depth of the P-type ions ranges from 2.3 to 4.7 µm.