Tft substrate and method for manufacturing tft substrate

Abstract

The present application relates to a TFT substrate and a manufacturing method of a TFT substrate. The present application provides a TFT substrate and a manufacturing method of a TFT substrate capable of suppressing characteristic variation of a thin film transistor using an oxide semiconductor. The TFT substrate includes a substrate, a plurality of transistors provided over the substrate and including an oxide semiconductor layer, a plurality of scan lines electrically connected to gate electrodes of the plurality of transistors and extending in a first direction, a plurality of signal lines electrically connected to the oxide semiconductor layers of the plurality of transistors and extending in a second direction intersecting the first direction, an insulating film covering the plurality of signal lines and the oxide semiconductor layer, and a connection wiring provided over the insulating film, at least one of the signal lines being separated in the second direction with a slit, the connection wiring electrically connecting one signal line and another signal line adjacent to each other in the second direction with the slit.

Description

Technical Field

[0001] This invention relates to TFT (Thin Film Transistor) substrates and methods for manufacturing TFT substrates. Background Technology

[0002] In display devices, detection devices, and the like, TFT substrates with multiple thin-film transistors (TFTs) disposed on a substrate are used. As semiconductor materials used for thin-film transistors, oxide semiconductors are known, for example (see Patent Documents 1 and 2).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-123861

[0006] Patent Document 2: Japanese Patent Application Publication No. 2007-96055 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] The requirement is to suppress characteristic deviations of thin-film transistors in TFT substrates that utilize oxide semiconductors.

[0009] The purpose of this invention is to provide a TFT substrate and a method for manufacturing the TFT substrate that can suppress characteristic deviations of thin-film transistors using oxide semiconductors.

[0010] Methods for solving problems

[0011] One aspect of the TFT substrate of the present invention includes: a substrate; a plurality of transistors disposed on the substrate and including an oxide semiconductor layer; a plurality of scan lines electrically connected to the gates of the plurality of transistors and extending in a first direction; a plurality of signal lines electrically connected to the oxide semiconductor layer of the plurality of transistors and extending in a second direction intersecting the first direction; an insulating film covering the plurality of signal lines and the oxide semiconductor layer; and a connection wiring disposed on the insulating film, wherein at least one of the signal lines is separated in the second direction by a slit, and the connection wiring electrically connects one adjacent signal line in the second direction by another signal line separated by the slit.

[0012] A method for manufacturing a TFT substrate according to one aspect of the present invention includes: a step of sequentially stacking a plurality of scan lines, an oxide semiconductor layer, and a plurality of signal lines on a substrate, forming a slit in at least one of the aforementioned signal lines to separate the signal lines in the extending direction of the aforementioned signal lines; a step of forming an insulating film covering the aforementioned oxide semiconductor layer and the plurality of signal lines, and forming a contact hole in a region of the aforementioned insulating film that overlaps with one signal line and another signal line adjacent to each other across the aforementioned slit; and a step of forming a connection wiring on the aforementioned insulating film, electrically connecting the aforementioned one signal line and the aforementioned other signal line through the aforementioned contact hole. Attached Figure Description

[0013] [ Figure 1 ] Figure 1 This is an explanatory diagram illustrating an example of a display device having the TFT substrate according to the first embodiment.

[0014] [ Figure 2 ] Figure 2 A block diagram illustrating a system example of a display device.

[0015] [ Figure 3 ] Figure 3 A circuit diagram illustrating an example of the pixel configuration of a display device.

[0016] [ Figure 4 ] Figure 4 This is a cross-sectional view showing an example of a display section.

[0017] [ Figure 5 ] Figure 5 A top view is provided to schematically illustrate the relationship between the TFT substrate, transistors, scan lines, and signal lines according to the first embodiment.

[0018] [ Figure 6 ] Figure 6 To show in magnified form Figure 5 The top view of area A shown.

[0019] [ Figure 7 ] Figure 7 for Figure 6 Sectional view of VII-VII'.

[0020] [ Figure 8 ] Figure 8 for Figure 6 Sectional view of VIII-VIII'.

[0021] [ Figure 9 ] Figure 9 A cross-sectional view is shown schematically of the manufacturing method of the TFT substrate according to the first embodiment.

[0022] [ Figure 10 ] Figure 10 This is an explanatory diagram illustrating the manufacturing method of the TFT substrate according to the first embodiment.

[0023] [ Figure 11 ] Figure 11 A diagram illustrating the characteristic deviation of the transistors in the TFT substrate according to the first embodiment is shown schematically.

[0024] [ Figure 12 ] Figure 12 This is an explanatory diagram used to illustrate the manufacturing method of the TFT substrate involved in the comparative example.

[0025] [ Figure 13 ] Figure 13 A diagram illustrating the characteristic deviation of the transistors on the TFT substrate involved in the comparative example is shown schematically.

[0026] [ Figure 14 ] Figure 14 A top view illustrating the relationship between the TFT substrate, transistors, scan lines, and signal lines in a variation of the first embodiment.

[0027] [ Figure 15 ] Figure 15 for Figure 14 XV-XV' sectional view.

[0028] [ Figure 16 ] Figure 16 This is a top view showing an example of a detection apparatus having the TFT substrate according to the second embodiment.

[0029] [ Figure 17 ] Figure 17 A circuit diagram is shown for the detection element of the TFT substrate according to the second embodiment.

[0030] [ Figure 18 ] Figure 18 A cross-sectional view of the TFT substrate according to the second embodiment is shown schematically.

[0031] Explanation of reference numerals in the attached figures

[0032] 1. 1A display device

[0033] 2 Display Unit

[0034] 3 driver ICs

[0035] 6 backlights

[0036] 11gr, 11gl surrounding area

[0037] 21 display areas

[0038] 22A First Vertical Driver

[0039] 22B Second Vertical Drive

[0040] 24. GLS scan lines

[0041] 24G, 124G gate electrodes

[0042] 25, 25c, 25d, SLS signal lines

[0043] 25a and 125a source electrodes

[0044] 25b and 125b drain electrodes

[0045] 25S slit

[0046] 25B, 25Ba, 125B connection wiring

[0047] 71, 171 substrate

[0048] 72-pixel electrode

[0049] 74a, 74b, 174a, 174b insulating films

[0050] 80, 80A mother substrate

[0051] 81 and 81A single chips form a predetermined area

[0052] 90, 190 semiconductor layers

[0053] 100 detection device

[0054] 130 LED

[0055] 135 detection element

[0056] Pix, SPX pixels

[0057] SUB1, SUB1A, SUB1B TFT substrate

[0058] SUB2 Opposite Baseboard

[0059] Tr and TrS thin-film transistors Detailed Implementation

[0060] The embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the contents described in the following embodiments. Furthermore, the constituent elements described below include constituent elements readily conceived by those skilled in the art and actually identical constituent elements. Moreover, the constituent elements described below can be appropriately combined. It should be noted that the disclosed content is merely an example, and appropriate modifications that retain the spirit of the present invention and are readily conceived by those skilled in the art are naturally included within the scope of the present invention. Additionally, regarding the accompanying drawings, for the purpose of clarity, there are instances where the width, thickness, shape, etc., of various parts are schematically shown compared to the actual embodiment; this is merely an example and does not constitute a limitation on the interpretation of the present invention. Furthermore, in the present invention and the various drawings, the same reference numerals are used for elements identical to those described above in existing drawings, and detailed descriptions are sometimes appropriately omitted.

[0061] In this specification and claims, when describing the state of other structures being disposed on a certain structure, the phrase "on" is used, unless otherwise specified, to include both the case of other structures being disposed directly above a certain structure in connection with it, and the case of other structures being disposed above a certain structure with another structure in between.

[0062] (First Embodiment)

[0063] Figure 1 This is an explanatory diagram illustrating an example of a display device having the TFT substrate according to the first embodiment. (See diagram below.) Figure 1 As shown, the display device 1 includes a display unit 2 and a backlight 6. The display device 1 can be a transmissive type, a semi-transmissive type, or a reflective type display device without a backlight 6.

[0064] When viewed from above, the display unit 2 includes: a display area 21 for displaying images; and peripheral areas 11gl and 11gr located around the display area 21 as non-display areas that cannot display images.

[0065] The backlight 6 is located on the lower side of the display unit 2 (the side opposite to the surface displaying the image). The backlight 6 may be, for example, a side-lit type backlight having a light guide plate positioned corresponding to the display area 21 and multiple light sources arranged at one or both ends of the light guide plate. As a light source, a light-emitting diode (LED) emitting a predetermined color can be used, for example. Alternatively, the backlight 6 may be a direct-lit type backlight having a light source (e.g., an LED) positioned directly below the display area 21. It should be noted that, in the case of the display device 1 of this embodiment, the backlight 6 located on the lower side of the display unit 2 is described as the light source, but a front light source located on the upper side of the display unit 2 may also be used.

[0066] Figure 2 This is a block diagram representing a system example of a display device. For example... Figure 2 As shown, the display area 21 has pixels SPX (units constituting one pixel on the display) including a liquid crystal layer arranged in a matrix (row-column) structure of m rows × n columns. It should be noted that in this embodiment, a row refers to a pixel row having n pixels SPX arranged in one direction. Furthermore, a column refers to a pixel column having m pixels SPX arranged in a direction orthogonal to the direction in which the rows are arranged. The values ​​of m and n are determined based on the display resolution in the vertical direction and the display resolution in the horizontal direction.

[0067] Transferred by a flexible printed circuit board (FPC, not shown) Figure 2 The external signal of the driver IC3 shown or the driving power of the driver IC3. The first vertical driver 22A and the second vertical driver 22B (vertical drive circuit) are configured to sandwich the display area 21.

[0068] Driver IC3 has the functions of an interface (I / F) and a timing signal generator. Driver IC3 generates a common potential (opposite electrode potential) Vcom for each pixel electrode 72 of each pixel SPX, which is provided to the display area 21. It should be noted that driver IC3 can also be an integrated circuit integrated with horizontal driver 23.

[0069] In display area 21, for an m-row, n-column arrangement of pixels SPX, each row has scan lines 24 and each column has signal lines 25. The first vertical driver 22A and the second vertical driver 22B sequentially output gate drive signals to the multiple scan lines 24, selecting pixels SPX row by row. The horizontal driver 23 writes display data to each pixel SPX in the selected row via the signal lines 25.

[0070] Figure 3 This is a circuit diagram showing an example of the pixel configuration of a display device. In display area 21, oriented pixels are formed. Figure 3 The diagram shows the wiring for each pixel SPX, including the signal line 25 supplying pixel signals as display data to the transistor (TFT) Tr, and the scan line 24 driving each transistor Tr. Each pixel SPX has a transistor Tr and a liquid crystal capacitor LC. In this example, the transistor Tr is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT. One of the source and drain electrodes of the transistor Tr is connected to the signal line 25, the gate is connected to the scan line 24, and the other of the source and drain electrodes is connected to one end of the liquid crystal capacitor LC. One end of the liquid crystal capacitor LC is connected to the transistor Tr, and the other end is connected to the common potential Vcom of the common electrode com.

[0071] The common potential Vcom of the common electrode com is connected to a drive electrode driver (not shown), which supplies voltage to the pixel SPX. Furthermore, the pixel SPX is interconnected with other pixels SPX belonging to the same column of the display area 21 via the common potential Vcom of the common electrode com.

[0072] Scan line 24 and signal line 25 are arranged with and color filter 66 (see Figure 4 The area where the black matrix 76a overlaps with each other on the same layer. In addition, the area where no black matrix 76a is configured becomes the opening 76b.

[0073] Color filter 66 (see Figure 4 For example, a color gamut colored with red (R), green (G), and blue (B) is arranged periodically. The color gamut of color filter 66, including red (R), green (G), and blue (B), is similar to... Figure 3 The openings 76b shown are arranged accordingly. A pixel Pix contains three pixels SPX, with the color gamuts of R, G, and B grouped together for each pixel SPX. Furthermore, pixels SPX corresponding to the three color gamuts are grouped together to form a pixel Pix. Therefore, pixels SPX are also called sub-pixels. It should be noted that the color filter 66 can also contain a color gamut of four or more colors. In this case, a pixel Pix can also contain four or more pixels SPX.

[0074] Figure 4 This is a cross-sectional view showing an example of a display section. For example... Figure 4As shown, the display unit 2 includes: a TFT substrate SUB1; an opposing substrate SUB2 disposed in a direction perpendicular to the surface of the TFT substrate SUB1; and a liquid crystal layer 54 interposed between the TFT substrate SUB1 and the opposing substrate SUB2. It should be noted that a backlight source 6 is disposed on the surface of the TFT substrate SUB1 opposite to the liquid crystal layer 54. It should also be noted that in this specification, the direction from the TFT substrate SUB1 toward the opposing substrate SUB2 is defined as "up" or "above side".

[0075] Multiple liquid crystals are dispersed in the liquid crystal layer 54. The liquid crystals in the liquid crystal layer 54 modulate the light passing through it according to the state of the electric field, and are driven by liquid crystals in transverse electric field modes such as FFS (fringe field switching) or IPS (in plane switching).

[0076] The TFT substrate SUB1 includes: a light-transmitting substrate, such as glass, i.e., substrate 71; a first alignment film 62 stacked on the side of the liquid crystal layer 54 on substrate 71; and a first polarizing plate 63 stacked on substrate 71 on the opposite side to the liquid crystal layer 54. The first alignment film 62 is an alignment film that aligns the liquid crystal molecules within the liquid crystal layer 54 in a predetermined direction and is directly in contact with the liquid crystal layer 54. The first alignment film 62 is formed, for example, from a polymer material such as polyimide, and is formed, for example, by rubbing a coated polyimide material. The first polarizing plate 63 has the function of converting light incident from the backlight source 6 side into linearly polarized light.

[0077] The opposing substrate SUB2 includes: a light-transmitting insulating substrate, such as glass, i.e., a substrate 64; a color filter 66 formed on the side of the liquid crystal layer 54 of the substrate 64; a second alignment film 67 formed on the side of the liquid crystal layer 54 of the color filter 66; a phase retardation plate 68 formed on the substrate 64 on the side opposite to the side of the liquid crystal layer 54; and a second polarizing plate 69 formed on the phase retardation plate 68 on the side opposite to the side of the substrate 64.

[0078] It should be noted that the display device 1 may also be provided with a cover component formed of a glass substrate or a resin substrate, a touch panel, or other detection devices, as needed.

[0079] Next, the detailed structure of the TFT substrate SUB1 will be explained. Figure 5 This is a top view schematically illustrating the relationship between the TFT substrate, transistors, scan lines, and signal lines according to the first embodiment. Figure 5As shown, multiple scan lines 24 extend along a first direction Dx and are arranged side-by-side along a second direction Dy that intersects the first direction Dx. Multiple signal lines 25 extend along the second direction Dy and are arranged side-by-side along the first direction Dx. Multiple transistors Tr are disposed near the intersection of the scan lines 24 and the signal lines 25.

[0080] It should be noted that in the following description, the first direction Dx is a direction within a plane parallel to the substrate 71. The second direction Dy is a direction within a plane parallel to the substrate 71, and is orthogonal to the first direction Dx. It should also be noted that the second direction Dy may not be orthogonal to the first direction Dx and may intersect it. The third direction Dz is a direction orthogonal to both the first direction Dx and the second direction Dy, and is the normal direction of the principal surface of the substrate 71. Furthermore, "top view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 71.

[0081] At least one of the multiple signal lines 25 has a slit 25S, which separates the signal line in the second direction Dy. In other words, the length of the signal line 25 connected to a transistor Tr in the second direction Dy is shorter than the length of the display area 21 in the second direction Dy. Furthermore, the TFT substrate SUB1 also has a connection wiring 25B. The connection wiring 25B electrically connects one adjacent signal line 25 to another signal line 25 separated by the slit 25S in the second direction Dy. The adjacent signal line 25 separated by the slit 25S and the other signal line 25 are formed on the same layer.

[0082] It should be noted that the location, quantity, and spacing P1 of the slits 25S and connecting wiring 25B can be appropriately changed. For example, in Figure 5 In the example shown, a slit 25S and a connecting wire 25B are provided in one signal line 25 located at the center of the first direction Dx among the multiple signal lines 25. However, this is not a limitation; slits 25S and connecting wires 25B may be provided in all signal lines 25. Furthermore, it is sufficient that a slit 25S and a connecting wire 25B are provided at at least one location in a single signal line 25. Alternatively, slits 25S and connecting wires 25B may be provided in each of the multiple pixels SPX in a single signal line 25.

[0083] Figure 6 It is shown in magnification Figure 5 The top view of area A shown. Figure 6 A magnified view shows two adjacent pixels SPX in the first direction Dx. (Example) Figure 6As shown, the transistor Tr includes: a semiconductor layer 90; a source electrode 25a; a drain electrode 25b; and a gate electrode 24G. Regarding the semiconductor layer 90, an oxide semiconductor is used as the semiconductor material, such as zinc oxide (ZnO) or InGaO3 (ZnO) composed of indium oxide, gallium oxide, and zinc oxide. m (m is a natural number) is used as an oxide semiconductor layer.

[0084] The semiconductor layer 90 extends along the scan line 24 in the first direction Dx. One end of the semiconductor layer 90 in the first direction Dx is connected to the source electrode 25a, and the other end is connected to the drain electrode 25b. The source electrode 25a is connected to the signal line 25 and branches off from the signal line 25, extending in the first direction Dx. In other words, a portion of the signal line 25 functions as the source electrode 25a of the transistor Tr. Thus, the signal line 25 is electrically connected to the semiconductor layer 90 of the transistor Tr, which is formed of an oxide semiconductor layer. The drain electrode 25b is formed in the same layer as the source electrode 25a and is electrically connected to the pixel electrode 72 via a via SH1. In this embodiment, the scan line 24 is a wiring of a metal such as molybdenum (Mo) or aluminum (Al), and the signal line 25 is a wiring of a metal such as aluminum.

[0085] The gate electrode 24G is connected to the scan line 24 and branches off from the scan line 24, extending in the second direction Dy. The gate electrode 24G intersects a portion of the semiconductor layer 90, functioning as the gate of the transistor Tr. The point where the gate electrode 24G intersects a portion of the semiconductor layer 90 is designated as point 1. The thin-film transistor Tr is a single-gate transistor with a channel region serving as an n-channel. Because the gate electrode 24G is located below the semiconductor layer 90, this structure of the thin-film transistor Tr is called a bottom-gate structure or an anti-interlaced structure.

[0086] One signal line 25 is separated by a slit 25S, and one signal line 25c and another signal line 25d are arranged adjacent to each other in the second direction Dy. A connecting wire 25B extends along the signal line 25. One end of the connecting wire 25B in the second direction Dy is electrically connected to one signal line 25c via a contact hole CH1, and the other end is electrically connected to another signal line 25d via a contact hole CH2. The connecting wire 25B uses a metallic material with good conductivity, such as a multilayer film of molybdenum (Mo) and aluminum (Al), i.e., MAM (Mo / Al / Mo) film, a multilayer film of titanium (Ti) and aluminum (Al), i.e., TAT (Ti / Al / Ti) film, or a single layer film of Mo. The signal lines 25c, 25d, and the connecting wire 25B have contact portions forming contact holes CH1 and CH2. These contact portions are formed to be larger than the width (length in the first direction Dx) of each wire other than the contact portions. As a result, poor connection between the signal line 25 and the connecting wire 25B can be suppressed.

[0087] At locations other than the contact portion, the connecting wiring 25B has the same width as the signal line 25 (length in the first direction Dx). Therefore, by using a signal line 25 with and without the slit 25S and connecting wiring 25B, deviations in capacitance and resistance can be suppressed.

[0088] It should be noted that regarding the stack-up structure of signal line 25, connection wiring 25B, and transistor Tr, in Figure 8 The narrative will be presented in the text.

[0089] Figure 7 yes Figure 6 Sectional view of VII-VII'. Figure 7 This is a schematic cross-sectional view showing the connection portion between the drain electrode 25b and the pixel electrode 72. (See diagram below.) Figure 7 As shown, a common electrode com, an insulating film 74a, a drain electrode 25b, an insulating film 74b, and a pixel electrode 72 are sequentially stacked on a substrate 71. The pixel electrode 72 and the common electrode com are insulated by insulating layers 74 (insulating films 74a and 74b) and are positioned opposite each other in a direction perpendicular to the surface of the substrate 71. The pixel electrode 72 and the common electrode com are formed, for example, of a light-transmitting conductive material (light-transmitting conductive oxide) such as ITO (Indium Tin Oxide). In this embodiment, the insulating films 74a and 74b are SiN. x (Silicon nitride) or SiO x An inorganic insulating film of silicon oxide. It should be noted that the materials used to form the layers of insulating films 74a and 74b are not limited to this. Furthermore, insulating films 74a and 74b can be made of the same insulating material or different insulating materials. Moreover, insulating films 74a and 74b are not limited to single-layer films; for example, they can also be made of SiN. x (Silicon nitride) or SiO x It is formed by a stack of (silicon oxide) films.

[0090] Pixel electrodes 72 are provided in each pixel SPX, and an opening SL is formed in each pixel electrode 72. Thus, in the electric field formed between the common electrode com and the pixel electrode 72, the liquid crystal is driven by the electric field (edge ​​electric field) leaking from the opening SL of the pixel electrode 72.

[0091] Figure 8 for Figure 6 Sectional view VIII-VIII'. (See also...) Figure 8As shown, a gate electrode 24G, an insulating film 74a, a semiconductor layer 90, a source electrode 25a, a drain electrode 25b, and an insulating film 74b are sequentially stacked on a transparent insulating substrate, i.e., substrate 71. More specifically, the insulating film 74a covers the gate electrode 24G and is disposed on the substrate 71. The semiconductor layer 90 is disposed on the gate electrode 24G through the insulating film 74a. The portion of the semiconductor layer 90 that overlaps with the gate electrode 24G forms a channel region.

[0092] The source electrode 25a and drain electrode 25b are configured to sandwich the channel region of the semiconductor layer 90, and are respectively disposed on the semiconductor layer 90 in a manner connected to the semiconductor layer 90. A signal line 25, continuously formed with the source electrode 25a, is disposed on the insulating film 74a. As described above, one signal line 25 is separated into one signal line 25c and another signal line 25d by the slit 25S.

[0093] An insulating film 74b is provided to cover the source electrode 25a, the drain electrode 25b, the signal line 25, and the semiconductor layer 90. A contact hole CH1 is formed in the insulating film 74b in a region overlapping with one signal line 25c. A contact hole CH2 is formed in the insulating film 74b in a region overlapping with another signal line 25d. Furthermore, a contact hole is formed in the second direction Dy (see [reference]) across a slit 25S. Figure 6 Between adjacent signal lines 25c and 25d, no other conductor layers such as wiring are provided; instead, an insulating film 74b is continuously provided. In other words, in the region overlapping with the slit 25S, the insulating film 74b is connected to and stacked on top of the insulating film 74a.

[0094] The connecting wire 25B is disposed on the insulating film 74b, with one end connected to a signal line 25c via a contact hole CH1, and the other end connected to another signal line 25d via a contact hole CH2.

[0095] Next, the manufacturing method of the TFT substrate SUB1 in this embodiment will be described. Figure 9 This is a cross-sectional view schematically illustrating a method for manufacturing a TFT substrate according to the first embodiment.

[0096] like Figure 9 As shown, a gate electrode 24G, an insulating film 74a, a semiconductor layer 90, and signal lines 25 (source electrode 25a and drain electrode 25b) are sequentially stacked on the substrate 71 (step ST1). More specifically, a low-resistance metal film forming the scan lines 24 is deposited on the substrate 71 by sputtering, and the shape of the gate electrode 24G is patterned by etching, together with the scan lines 24.

[0097] Next, an insulating film 74a is formed on the gate electrode 24G. The insulating film 74a is, for example, formed by plasma CVD using a SiN… x Formed to the specified thickness.

[0098] Next, a semiconductor layer 90 is formed on the insulating film 74a. The semiconductor layer 90 may be, for example, ZnO or InGaO3 (ZnO). m Oxide semiconductor materials are deposited into films using CVD or sputtering methods and then patterned into specified shapes.

[0099] Next, a low-resistance metal film for forming the signal line 25 is formed on the insulating film 74a by sputtering in a manner that covers the semiconductor layer 90. Together with the signal line 25, the shapes of the source electrode 25a and the drain electrode 25b are patterned by etching. In the same process, slits 25S of the signal line 25 are formed to separate one signal line 25c from another signal line 25d.

[0100] Next, an insulating film 74b is formed on the signal line 25, the source electrode 25a, and the drain electrode 25b (step ST2). The insulating film 74b is, for example, formed by plasma CVD using a SiN electrode. x Formed to a specified thickness. A portion of the area in the insulating film 74b that overlaps with each of the signal lines 25c and 25d is removed by etching to form contact holes CH1 and CH2.

[0101] Next, a low-resistance metal film for forming the connection wiring 25B is deposited on the insulating film 74b by sputtering, and the shape of the connection wiring 25B is patterned by etching (step ST3). Thus, the connection wiring 25B is formed to be electrically connected to one signal line 25c via contact hole CH1 and to another signal line 25d via contact hole CH2. This manufactures the TFT substrate SUB1.

[0102] Next, refer to Figures 10 to 12 The effect of the configuration formed by separating at least one signal line 25 into multiple segments through the slit 25S in the TFT substrate SUB1 of this embodiment will be explained. Figure 10 This is an explanatory diagram illustrating the manufacturing method of the TFT substrate according to the first embodiment. Figure 11 A diagram illustrating the characteristic deviation of the transistors in the TFT substrate according to the first embodiment is shown schematically. Figure 12 This is an explanatory diagram used to illustrate the manufacturing method of the TFT substrate involved in the comparative example. Figure 13 A diagram illustrating the characteristic deviation of the transistors on the TFT substrate involved in the comparative example is shown schematically.

[0103] like Figure 10 As shown, in the manufacturing process of the TFT substrate SUB1 according to the first embodiment, a mother substrate 80 is used to perform... Figure 9 The process described herein. A plurality of pre-defined regions 81 are arranged on the mother substrate 80. These pre-defined regions 81 are regions corresponding to the TFT substrate SUB1, respectively. Figure 9 Following the film deposition process shown, multiple TFT substrates SUB1 are formed from one mother substrate 80 by dividing the substrate into predetermined regions 81 for each individual wafer. It should be noted that... Figure 10 The diagram is shown schematically for ease of observation. Figure 10 In this case, four monoliths are arranged on the mother substrate 80 to form a predetermined region 81, but it is not limited to this. More than five monoliths can also be arranged on one mother substrate 80 to form a predetermined region 81.

[0104] exist Figure 9 In each of the processes shown, process deviations occur in the central portion 80C, the middle portion 80M, and the peripheral portion 80E of the mother substrate 80. As an example, the process deviations are caused by the plasma distribution of the CVD apparatus. For example, sometimes the plasma density is high at the central portion 80C of the mother substrate 80, and decreases towards the peripheral side in the order of the middle portion 80M and the peripheral portion 80E.

[0105] Figure 10 The image shows a magnified view of a single-wafer formed predetermined region 81 (TFT substrate SUB1) of the mother substrate 80. Deviations in the aforementioned process can also occur within this single-wafer formed predetermined region 81. As an example, in... Figure 10 In the monolithically formed predetermined region 81 shown in the enlarged view, the plasma density increases in the direction of extension of the signal line 25 in the order of region L1 (left side region) on one end, region M1 in the middle, and region R1 (right side region) on the other end.

[0106] like Figure 12 As shown, the comparative example TFT substrate SUB10 has a configuration in which signal lines 25 are continuously formed from one end of the display area 21 to the other without forming slits 25S. Similarly, in the comparative example mother substrate 80A, process deviations occur in the central portion 80AC, the middle portion 80AM, and the peripheral portion 80AE. Furthermore, in forming a predetermined area 81A (TFT substrate SUB10) on a single wafer, the plasma density also increases in the direction of signal line 25 in the order of region L2 (left side), region M2 in the middle, and region R2 (right side).

[0107] In this embodiment, as described above, at least one signal line 25 is separated into multiple segments through the slit 25S. Therefore, compared to the configuration shown in the comparative example, where the slit 25S is not formed and the signal line 25 is continuously formed from one end of the display area 21 to the other, the length of the signal line 25 connected to the semiconductor layer 90 of one transistor Tr is shortened.

[0108] Therefore, in the formation Figure 9 Even if process deviations occur in the various steps of the semiconductor layer 90 formed from oxide semiconductor, the signal line 25, and the insulating film 74b, it is possible to suppress the shift in oxidation degree on the semiconductor layer 90 of the transistor Tr caused by the signal line 25. For example, in a plurality of semiconductor layers 90 arranged along one signal line 25, the deviation in oxidation degree of the semiconductor layer 90 can be suppressed in the region L1 (left side region) on one end and the region R1 (right side region) on the other end.

[0109] More specifically, variations in the process can lead to uneven charge distribution on the signal line 25. In this case, in the comparative example, the longer the signal line 25 connected to the semiconductor layer 90 formed of oxide semiconductor, the more significant the deviation in the degree of oxidation of the semiconductor layer 90. On the other hand, in this embodiment, since the signal line 25 is separated through the slit 25S, the length of the signal line 25 connected to the semiconductor layer 90 formed of oxide semiconductor can be shortened. Therefore, compared to the signal line 25 in the comparative example, the charge distribution within the signal line 25 connected to the semiconductor layer 90 is smaller. As a result, in this embodiment, the unevenness in the degree of oxidation of the semiconductor layer 90 caused by the signal line 25 can be suppressed.

[0110] Figure 11 It shows Figure 10 The VI characteristics of transistors Tr in the TFT substrate SUB1 of this embodiment, specifically in the region L1 (left side), the region M1 in the middle, and the region R1 (right side). Figure 13 It shows Figure 12 The VI characteristics of transistors Tr in the TFT substrate SUB10 of the comparative example shown are as follows: L2 (left side region), M2 (middle region), and R2 (right side region). Figure 11 , Figure 13 In the graph, the horizontal axis represents gate voltage, and the vertical axis represents leakage current. It should be noted that... Figure 11 , Figure 13 The diagrams shown are merely schematic representations of the VI characteristics of transistor Tr.

[0111] like Figure 11As shown, in this embodiment, the oxidation degree deviation of the semiconductor layer 90 can be suppressed in the region L1 (left side region), the middle region M1, and the other side region R1 (right side region), thereby reducing the deviation σ1 of the threshold voltage Vth of the transistor Tr.

[0112] In contrast, such as Figure 13 As shown, in the comparative example, the deviation in the degree of oxidation of the semiconductor layer 90 caused by the signal line 25 increases in the region L2 (left side), the middle region M2, and the other side region R2 (right side), thereby increasing the deviation σ2 of the threshold voltage Vth of the transistor Tr. In this embodiment, the deviation σ1 is less than 1.0V, for example, about 0.1V, while in the comparative example, the deviation σ2 is more than 1.0V, for example, about 10V.

[0113] As described above, in this embodiment, at least one signal line 25 of the TFT substrate SUB1 is separated into multiple lines through the slit 25S. Therefore, depending on the formation... Figure 9 The deviations in the oxidation degree of the semiconductor layer 90 (formed from oxide semiconductor), signal line 25, and insulating film 74b caused by the signal line 25, due to process variations in each layer, are suppressed. As a result, it is shown that characteristic deviations in the transistor Tr using the oxide semiconductor layer 90 can be suppressed. It should be noted that the number, arrangement pattern, and spacing P1 of the slits 25S and connecting lines 25B can be appropriately changed according to the aforementioned process variations (e.g., plasma distribution in a CVD apparatus), the time constant of the signal line 25, etc.

[0114] (Modified Example)

[0115] Figure 14 This is a top view illustrating the relationship between the TFT substrate, transistors, scan lines, and signal lines in a variation of the first embodiment. Figure 14 As shown, in the TFT substrate SUB1A (display device 1A) of the modified example, multiple connecting lines 25B and 25Ba are arranged according to multiple pixels SPX along the extension direction (second direction Dy) of the signal line 25.

[0116] More specifically, multiple connecting wires 25B and 25Ba overlap with one signal line 25 and are arranged in the second direction Dy. The connecting wire 25B is located in the area that overlaps with the slit 25S of the signal line 25. The connecting wire 25Ba is located in the area of ​​the signal line 25 where there is no slit 25S.

[0117] Figure 15 yes Figure 14 The XV-XV' sectional view. (See example...) Figure 15As shown, in the portion of signal line 25 where the slit 25S is provided, similarly to the first embodiment described above, the connecting wire 25B is provided on the insulating film 74b, one end of which is electrically connected to a signal line 25c via a contact hole CH1, and the other end of which is electrically connected to another signal line 25d via a contact hole CH2.

[0118] In the portion of signal line 25 without the slit 25S, a connecting wire 25Ba is disposed on the insulating film 74b. One end of the connecting wire 25Ba is electrically connected to a signal line 25c via a contact hole CH1, and the other end is electrically connected to the same signal line 25c via a contact hole CH2. That is, the connecting wire 25Ba is connected in parallel with a signal line 25c. As a result, the TFT substrate SUB1A of the modified example can suppress the resistance value of the signal line 25.

[0119] For example, the connection wiring 25B (slit 25S) can be configured to be located in one of the 15 pixel SPX arranged in the second direction Dy, and the connection wiring 25Ba can be located in the other 14 pixel SPX arranged in the second direction Dy. However, it is not limited to this, and the number and configuration pattern of the connection wirings 25B and 25Ba can be appropriately changed according to the deviations of the above-mentioned process (e.g., plasma distribution of the CVD device), the time constant of the signal line 25, etc.

[0120] It should be noted that in the first embodiment and its variations, examples of using TFT substrates SUB1 and SUB1A in a display device 1 using liquid crystal elements as display elements were described, but the invention is not limited thereto. TFT substrates SUB1 and SUB1A can also be used in, for example, organic light emitting diode (OLED) displays, inorganic light emitting diode (EL) displays (micro LED, mini LED), or electrophoretic display panels (EPDs) using electrophoretic elements as display elements. Furthermore, TFT substrates SUB1 and SUB1A can also be used in other electronic devices different from the display device 1.

[0121] (Second Implementation)

[0122] Figure 16 This is a top view showing an example of a detection apparatus having the TFT substrate according to the second embodiment. It should be noted that in the following description, the same reference numerals are used for components identical to those described in the above embodiments, and repeated descriptions are omitted.

[0123] In the second embodiment, the configuration in which the TFT substrate SUB1B is used in the detection device 100 will be described. The detection device 100 is a light sensor having a PIN-type light-emitting diode 130 as a sensor element. The detection device 100 is configured as a fingerprint sensor capable of detecting information such as fingerprints based on light from a subject such as a finger. Alternatively, the detection device 100 may also be configured as a biosensor that detects, for example, the vascular pattern of a finger or palm, pulse wave, pulse, blood oxygen concentration, etc.

[0124] like Figure 16 As shown, the detection device 100 includes: a TFT substrate SUB1B (substrate 171); a sensor unit 110; a scan line drive circuit 115; a signal line selection circuit 116; a detection circuit 148; a control circuit 102; and a power supply circuit 103.

[0125] The control substrate 501 is electrically connected to the TFT substrate SUB1B (substrate 171) via the wiring substrate 510. The wiring substrate 510 is, for example, a flexible printed circuit board or a rigid substrate. A detection circuit 148 is provided on the wiring substrate 510. The control substrate 501 is provided with a control circuit 102 and a power supply circuit 103. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 110, the scan line drive circuit 115, and the signal line selection circuit 116 to control the detection operation of the sensor unit 110. The power supply circuit 103 transmits power supply potential SVS and reference potential VR1 (see...) to the sensor unit 110. Figure 17 The voltage signal is supplied to the sensor section 110, the scan line drive circuit 115 and the signal line selection circuit 116.

[0126] The TFT substrate SUB1B has a detection area AA and a peripheral area GA. The detection area AA is the area where the multiple light-emitting diodes 130 of the sensor unit 110 are provided. The peripheral area GA is the area between the outer periphery of the detection area AA and the outer edge of the substrate 171, and is the area where the multiple light-emitting diodes 130 are not provided.

[0127] The scan line drive circuit 115 and the signal line selection circuit 116 are disposed in the peripheral region GA. Specifically, the scan line drive circuit 115 is disposed in the peripheral region GA extending along the second direction Dy. The signal line selection circuit 116 is disposed in the peripheral region GA extending along the first direction Dx, and is disposed between the sensor unit 110 and the detection circuit 148.

[0128] The sensor unit 110 comprises multiple detection elements 135, each of which is a light sensor having a light-emitting diode (LED) 130 as a sensor element. The LED 130 is a photoelectric conversion element that outputs an electrical signal corresponding to the light it is illuminated. More specifically, the LED 130 is a PIN (Positive Intrinsic Negative) LED. Alternatively, the LED 130 may also be an OPD (Organic Photodiode) using an organic semiconductor. The multiple detection elements 135 (LEDs 130) are arranged in a matrix in the detection area AA.

[0129] The light-emitting diodes 130 of the multiple detection elements 135 are detected according to the gate drive signal supplied from the scan line drive circuit 115. The multiple light-emitting diodes 130 output an electrical signal corresponding to the light they are illuminated as a detection signal Vdet to the signal line selection circuit 116. The detection device 100 detects information related to the object being detected based on the detection signal Vdet from the multiple light-emitting diodes 130.

[0130] Figure 17 This is a circuit diagram showing the detection element of the TFT substrate according to the second embodiment. Figure 17 As shown, the detection element 135 includes a light-emitting diode 130, a capacitor element Ca, and a transistor TrS. The transistor TrS is disposed corresponding to the light-emitting diode 130. The transistor TrS is constructed of a thin-film transistor, in this example, a MOSFET of the n-channel type. The gate of the transistor TrS is connected to the scan line GLS. The source of the transistor TrS is connected to the output signal line SLS. The drain of the transistor TrS is connected to the anode of the light-emitting diode 130 and the capacitor element Ca.

[0131] A power supply potential SVS is supplied from the power supply circuit 103 to the cathode of the light-emitting diode 130. Furthermore, a reference potential VR1, which serves as the initial potential of the capacitor element Ca, is supplied from the power supply circuit 103 to the capacitor element Ca.

[0132] If the detection element 135 is illuminated by light, a current corresponding to the amount of light flows through the light-emitting diode 130, thereby accumulating charge in the capacitor element Ca. When the transistor TRS is turned on, a current corresponding to the charge accumulated in the capacitor element Ca flows through the output signal line SLS. The output signal line SLS is connected to the detection circuit 148 via the signal line selection circuit 116. Thus, the detection device 100 can detect a signal corresponding to the amount of light illuminating the light-emitting diode 130 for each detection element 135.

[0133] It should be noted that, Figure 17The diagram shows one detection element 1353, while the scan line GLS and output signal line SLS are connected to multiple detection elements 135. Specifically, the scan line GLS is in the first direction Dx (see...). Figure 16 The output signal line SLS extends along the first direction Dx and is connected to a plurality of detection elements 135 arranged along the second direction Dy.

[0134] Furthermore, although the illustration is omitted, in the TFT substrate SUB1B of this embodiment, similarly to the first embodiment, at least one output signal line SLS is separated in the second direction Dy by a slit. Moreover, the output signal lines SLS separated in the second direction Dy are electrically connected by connection wiring 125B formed on different layers.

[0135] Figure 18 This is a schematic cross-sectional view of the TFT substrate according to the second embodiment. Figure 8 As shown, the transistor TRS is constructed by sequentially stacking a gate electrode 124G, an insulating film 174a, a semiconductor layer 190, a source electrode 125a, a drain electrode 125b, and an insulating film 174b on a transparent insulating substrate, i.e., substrate 171. The semiconductor layer 190 uses oxide semiconductor as the semiconductor material. The stacked structure of the transistor TRS is similar to... Figure 8 The transistor Tr described herein is the same, and repeated descriptions are omitted.

[0136] The light-emitting diode 130 is disposed on the insulating film 174b. More specifically, the lower electrode 132, the light-emitting diode 130, and the upper electrode 131 are sequentially stacked on the insulating film 174b.

[0137] The lower electrode 132 is disposed on the insulating film 174b and extends from the region overlapping with the light-emitting diode 130 toward the transistor TRS side. The lower electrode 132 is electrically connected to the drain electrode 125b via the contact hole CH12. The lower electrode 132 is the anode of the light-emitting diode 130 and is used to read the detection signal Vdet. The lower electrode 132 is disposed on the same layer as the connection wiring 125B and can be made of the same material as the connection wiring 125B, such as a metal material like MAM (Mo / Al / Mo) film, TAT (Ti / Al / Ti) film, or Mo monolayer film. Alternatively, the lower electrode 132 can also be a laminated film of multiple layers of the above-mentioned metal materials. The lower electrode 132 can also be a conductive material with light transmittance, such as ITO.

[0138] The light-emitting diode 130 includes an i-type semiconductor layer, an n-type semiconductor layer, and a p-type semiconductor layer as semiconductor layers. The i-type semiconductor layer, n-type semiconductor layer, and p-type semiconductor layer are formed, for example, from amorphous silicon (a-Si). Although not shown in the figure, the p-type semiconductor layer, i-type semiconductor layer, and n-type semiconductor layer are stacked in the order of p-type semiconductor layer, i-type semiconductor layer, and n-type semiconductor layer in a direction perpendicular to the surface of the substrate 171.

[0139] An n-type semiconductor layer is formed by doping a-Si with impurities to create an n+ region. A p-type semiconductor layer is formed by doping a-Si with impurities to create a p+ region. An i-type semiconductor layer, for example, is an undoped intrinsic semiconductor and has lower conductivity than both n-type and p-type semiconductor layers.

[0140] The upper electrode 131 is the cathode of the light-emitting diode 130 and is used to supply the power supply potential SVS to the photoelectric conversion layer. The upper electrode 131 is, for example, a light-transmitting conductive layer such as ITO, and multiple electrodes are provided for each light-emitting diode 130.

[0141] Insulating films 175 and 176 are provided to cover the insulating film 174b and the lower electrode 132 extending from the light-emitting diode 130. Insulating film 175 is, for example, an inorganic insulating film, and insulating film 176 is, for example, an organic insulating film. Insulating films 175 and 176 cover the periphery of the upper electrode 131 and have openings at positions overlapping with the upper electrode 131. Power supply wiring 133 connects to the upper electrode 131 in areas overlapping with the openings of insulating films 175 and 176. An insulating layer 177 is provided on top of the insulating film 176, covering the upper electrode 131 and the power supply wiring 133. An insulating layer 178, serving as a planarization layer, is provided on top of the insulating layer 177.

[0142] The detection device 100 having a TFT substrate SUB1B is configured as described above. It should be noted that the configuration of the detection device 100 is only one example and can be modified appropriately. For example, the lower electrode 132 of the light-emitting diode 130 can be disposed on a different layer than the connecting wiring 125B.

[0143] The preferred embodiments of the present invention have been described above, but the present invention is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various modifications can be made without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention are of course also within the technical scope of the present invention. Without departing from the spirit of the above embodiments and variations, at least one of various omissions, substitutions, and modifications of the constituent elements can be made.

Claims

1. A TFT substrate, which has the following characteristics: substrate; A plurality of transistors disposed on the substrate and comprising an oxide semiconductor layer; Multiple scan lines electrically connected to the gates of the multiple transistors and extending in the first direction; Multiple signal lines electrically connected to the oxide semiconductor layer of the plurality of transistors and extending in a second direction intersecting the first direction; An insulating film covering the multiple signal lines and the oxide semiconductor layer; and The connecting wiring is disposed on the insulating film. In this configuration, at least one of the signal lines is separated in the second direction by a slit, and no slit is formed on the other signal line adjacent to the at least one of the signal lines. The connection wiring electrically connects one signal line to another signal line that are adjacent in the second direction, separated by the slit.

2. The TFT substrate as described in claim 1, wherein it has multiple connection wirings. Multiple connecting wires are arranged in the second direction, overlapping with one signal line, and are respectively arranged to overlap with the area of ​​the slit of at least one signal line and the area of ​​the signal line where the slit is not provided.

3. The TFT substrate as described in claim 1 or 2, wherein, The connection wiring has the same width as the signal line.

4. The TFT substrate as described in claim 1 or 2, wherein, The insulating film is provided continuously between one signal line and the other signal line adjacent to each other in the second direction, separated by the slit, without a conductor layer.

5. A method for manufacturing a TFT substrate, comprising: A process of sequentially stacking multiple scan lines, an oxide semiconductor layer, and multiple signal lines on a substrate, forming a slit in at least one of the signal lines while separating the signal line in the extension direction of the signal line, and not forming a slit in the other signal line adjacent to the at least one of the signal lines; The process of forming an insulating film covering the oxide semiconductor layer and multiple signal lines, and forming a contact hole in the area of ​​the insulating film that overlaps with one signal line and another signal line adjacent to each other through the slit; and The process of forming connection wiring on the insulating film and electrically connecting one signal line to the other signal line through the contact hole.

6. The method for manufacturing a TFT substrate as described in claim 5, wherein, In the process of forming the connection wiring on the insulating film, Multiple connecting wires overlap with one signal line and are arranged in the extension direction of the signal line, and are respectively arranged to overlap with the area of ​​the slit of at least one signal line and the area of ​​the signal line without the slit.

7. The method for manufacturing a TFT substrate as described in claim 5 or 6, wherein, The connection wiring is formed in a manner that has the same width as the signal line.

8. The method for manufacturing a TFT substrate as described in claim 5 or 6, wherein, The insulating film is continuously disposed between one signal line and the other signal line that are adjacent to each other across the slit, without a conductor layer.

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