Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the problem of serious random disturbance of threshold voltage, and the preparation method comprises the following steps: providing a substrate, the substrate comprising a well region, the well region comprising first-type impurity atoms; forming a barrier layer in the well region, the barrier layer dividing the well region into a first region and a second region, the first region being located above the barrier layer, and the second region being located below the barrier layer, and the barrier layer being used for inhibiting the diffusion of the first-type impurity atoms in the second region into the first region; forming an oxide layer on the surface of the first region through a thermal oxidation process, wherein, during the thermal oxidation process, the first-type impurity atoms in the first region are leached into the oxide layer; removing the oxide layer; and forming an epitaxial layer on the remaining first region. The application can overcome the problem that the random disturbance of threshold voltage is serious with the decrease of the size of a transistor, thereby improving the stability of the threshold voltage and further improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor that can be widely used in analog and digital circuits.

[0003] In related technologies, in order to improve the performance of MOS transistors, the substrate is usually doped with ions through a doping process. For example, N-type doping is performed in a P-type semiconductor to form an NMOS transistor, and P-type doping is performed in an N-type semiconductor to form a PMOS transistor. The threshold voltage is one of the important device parameters of MOS transistors, and the random fluctuation and deviation of the number of doping ions in the substrate seriously affects the magnitude and standard deviation of the threshold voltage. Therefore, the magnitude of the threshold voltage is usually adjusted by ion doping.

[0004] However, as transistor size continues to shrink, the threshold voltage is subjected to increasingly severe random perturbations, which in turn affect the electrical performance of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, this application provides a semiconductor structure and its fabrication method, which can overcome the problem of severe random disturbances caused by the reduction of threshold voltage as transistor size decreases, thereby improving the electrical performance of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] The first aspect of this application provides a method for fabricating a semiconductor structure, including:

[0008] A substrate is provided, the substrate including a well region, the well region including first-type impurity atoms;

[0009] A barrier layer is formed within the well region, which divides the well region into a first region and a second region. The first region is located above the barrier layer, and the second region is located below the barrier layer. The barrier layer is used to suppress the diffusion of the first type of impurity atoms in the second region into the first region.

[0010] An oxide layer is formed on the surface of the first region by a thermal oxidation process, wherein, during the thermal oxidation process, the first type of impurity atoms in the first region diffuse into the oxide layer;

[0011] Remove the oxide layer;

[0012] An epitaxial layer is formed on the remaining first region.

[0013] In some alternative embodiments, the step of forming a barrier layer within the well region includes:

[0014] Inert impurity atoms are injected into the well region, and a thermal annealing process is performed to form the barrier layer.

[0015] In some alternative embodiments, the implantation depth of the inert impurity atoms is 9 nm-10 nm.

[0016] In some alternative embodiments, the first type of impurity atom includes boron atoms, and the inert impurity atom includes at least one of germanium atoms, carbon atoms, and argon atoms.

[0017] In some alternative implementations, the step of forming an epitaxial layer on the remaining first region includes:

[0018] An undoped epitaxial layer is selectively grown on the top surface of the remaining first region, wherein the epitaxial layer comprises an epitaxial silicon layer or an epitaxial germanium-silicon layer.

[0019] In some alternative embodiments, prior to forming the oxide layer, the following steps are also included:

[0020] A shallow trench isolation structure is formed on the substrate, and the top surface of the first region is flush with the top surface of the shallow trench isolation structure.

[0021] After the oxide layer is removed, the top surface of the remaining first region is lower than the top surface of the shallow trench isolation structure.

[0022] In some alternative implementations, the remaining thickness of the first region is 2nm-5nm in a direction perpendicular to the main surface of the substrate.

[0023] In some alternative embodiments, the thickness of the epitaxial layer is 10 nm-12 nm in a direction perpendicular to the main surface of the substrate.

[0024] In some alternative implementations, after forming the epitaxial layer on the remaining first region, the method further includes:

[0025] A transistor is formed on the epitaxial layer.

[0026] A second aspect of this application provides a semiconductor structure, including:

[0027] A substrate includes a well region and a barrier layer disposed within the well region. The well region includes first-type impurity atoms. The barrier layer divides the well region into a first region and a second region. The first region is located above the barrier layer, and the second region is located below the barrier layer. The barrier layer is configured to suppress the diffusion of first-type impurity atoms in the second region into the first region.

[0028] An epitaxial layer is disposed on the first region, wherein the average concentration of the first type of impurity atoms in the epitaxial layer is less than the average concentration of the first type of impurity atoms in the first region, and the average concentration of the first type of impurity atoms in the first region is less than the average concentration of the first type of impurity atoms in the second region.

[0029] In some alternative embodiments, the semiconductor junction further includes a shallow trench isolation structure, the top surface of which is higher than the interface between the epitaxial layer and the first region.

[0030] In some alternative implementations, the first region and the second region comprise the same bulk semiconductor material.

[0031] In some alternative implementations, the thickness of the first region is 2nm-5nm in a direction perpendicular to the main surface of the substrate.

[0032] In some alternative embodiments, the thickness of the epitaxial layer is 10 nm-12 nm in a direction perpendicular to the main surface of the substrate.

[0033] In some alternative embodiments, the semiconductor structure further includes a transistor disposed on the epitaxial layer, wherein the channel region of the transistor is located at least in the epitaxial layer.

[0034] In the semiconductor structure and its fabrication method provided in this application embodiment, a barrier layer is formed in the well region, dividing the well region into a first region and a second region. The first region is located above the barrier layer, and the second region is located below the barrier layer. The barrier layer is used to suppress the diffusion of first-type impurity atoms from the second region into the first region. An oxide layer is formed on the surface of the first region through a thermal oxidation process. During the thermal oxidation process, first-type impurity atoms in the first region diffuse into the oxide layer. After the oxide layer is removed, the concentration of first-type impurity atoms in the first region can be further reduced. In addition, an epitaxial layer is formed on the remaining first region, so that the average concentration of first-type impurity atoms in the epitaxial layer is less than the average concentration of first-type impurity atoms in the first region, and the average concentration of first-type impurity atoms in the first region is less than the average concentration of first-type impurity atoms in the second region, thereby improving or avoiding random perturbation effects and improving the electrical performance of the semiconductor structure.

[0035] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0038] Figure 2 A schematic cross-sectional view of the semiconductor structure after the barrier layer is formed, provided in an embodiment of this application.

[0039] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the oxide layer is formed, provided in an embodiment of this application.

[0040] Figure 4 A schematic cross-sectional structure of a semiconductor structure after removing the oxide layer, provided in an embodiment of this application;

[0041] Figure 5 A schematic diagram of another cross-sectional structure of the semiconductor structure after removing the oxide layer, provided in an embodiment of this application;

[0042] Figure 6 A schematic cross-sectional view of the semiconductor structure after the epitaxial layer is formed in an embodiment of this application;

[0043] Figure 7 A schematic diagram of the boron concentration distribution perpendicular to the silicon surface in a semiconductor structure obtained from numerical simulation in an embodiment of this application;

[0044] Figure 8 A schematic diagram of the normalized standard deviation of the threshold voltage distribution caused by random perturbation obtained from numerical simulation in the semiconductor structure provided in the embodiments of this application;

[0045] Figure 9This is a schematic diagram of the gate voltage-drain current curve of an NMOS transistor in the saturation region operating state obtained by numerical simulation in the semiconductor structure provided in the embodiments of this application.

[0046] Figure label:

[0047] 100 - Semiconductor structure; 110 - Substrate; 111 - Well region; 1111 - First region; 1112 - Second region; 112 - Shallow trench isolation structure; 120 - Barrier layer; 130 - Oxide layer; 140 - Epitaxial layer. Detailed Implementation

[0048] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in analog and digital circuits. In related technologies, to improve the performance of MOSFETs, the substrate is typically doped with ions. For example, N-type doping in a P-type semiconductor forms an NMOS transistor, and P-type doping in an N-type semiconductor forms a PMOS transistor. The threshold voltage is one of the important device parameters of a MOSFET, and the random fluctuations and deviations in the number of dopant ions in the substrate significantly affect the magnitude and standard deviation of the threshold voltage. Therefore, the magnitude of the threshold voltage is usually adjusted through ion doping. However, as transistor sizes continue to shrink, the threshold voltage suffers increasingly severe random perturbations, thus affecting the electrical performance of the semiconductor structure.

[0049] To address the aforementioned problems, this application provides a semiconductor structure and its fabrication method. A barrier layer is formed within the well region, dividing the well region into a first region and a second region. The first region is located above the barrier layer, and the second region is located below it. The barrier layer suppresses the diffusion of first-type impurity atoms from the second region into the first region. An oxide layer is formed on the surface of the first region using a thermal oxidation process. During this process, first-type impurity atoms from the first region diffuse into the oxide layer. After removing the oxide layer, the concentration of first-type impurity atoms in the first region is further reduced. Furthermore, an epitaxial layer is formed on the remaining first region, resulting in an average concentration of first-type impurity atoms in the epitaxial layer that is lower than the average concentration in the first region. The average concentration of first-type impurity atoms in the first region is also lower than the average concentration in the second region, thereby improving or avoiding random perturbation effects and ultimately enhancing the electrical performance of the semiconductor structure.

[0050] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment; Figure 2 A schematic cross-sectional view of the semiconductor structure after the barrier layer is formed, provided in an embodiment of this application.

[0052] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the oxide layer is formed, provided in an embodiment of this application. Figure 4 A schematic cross-sectional structure of a semiconductor structure after removing the oxide layer, provided in an embodiment of this application; Figure 5 A schematic diagram of another cross-sectional structure of the semiconductor structure after removing the oxide layer, provided in an embodiment of this application; Figure 6 A schematic cross-sectional view of the semiconductor structure after the epitaxial layer is formed in an embodiment of this application; Figure 7 A schematic diagram of the boron concentration distribution perpendicular to the silicon surface in a semiconductor structure obtained from numerical simulation in an embodiment of this application; Figure 8 A schematic diagram of the normalized standard deviation of the threshold voltage distribution caused by random perturbation obtained from numerical simulation in the semiconductor structure provided in the embodiments of this application; Figure 9 This is a schematic diagram of the gate voltage-drain current curve of an NMOS transistor in the saturation region operating state obtained by numerical simulation in the semiconductor structure provided in the embodiments of this application.

[0053] Please refer to Figure 1 As shown in the figure, this application provides a method for fabricating a semiconductor structure, the steps of which include:

[0054] Step S101: Provide a substrate, the substrate including a well region, the well region including first type impurity atoms.

[0055] Please combine Figure 2As shown, substrate 110 can provide a structural basis for subsequent structures and processes. The material of substrate 110 can be one or more of silicon, germanium, silicon germanium, silicon-on-insulator, and germanium-on-insulator. For example, at least a portion of substrate 110 is a silicon substrate, and the silicon material can be single-crystal silicon. Substrate 110 can be prepared by chemical vapor deposition (CVD). In the embodiments of this application, a silicon substrate is used as an example for illustration.

[0056] In some alternative embodiments, a well region 111 is formed on the substrate 110 by a doping process. The well region 111 can be classified as an N-type well region 111 or a P-type well region 111 depending on the type of doped atoms.

[0057] In addition, the well region 111 may include multiple device regions. After the well region 111 is formed, a shallow channel isolation structure 112 may be formed in each device region. The device regions can be separated by the shallow channel isolation structure 112 to form at least one active region. In subsequent processes, device units are formed in the active regions. For example, the device units may include transistors.

[0058] For example, the material of the shallow trench isolation structure 112 may include, but is not limited to, insulating materials such as silicon dioxide (SiO2).

[0059] Transistors can also be classified into NMOS transistors and PMOS transistors depending on the type of doped ions. The following explanation will take NMOS transistors as an example.

[0060] In this embodiment of the application, after the well region 111 is doped by doping processes such as ion implantation, the well region 111 includes a first type of impurity atoms. For example, the first type of impurity atoms include, but are not limited to, boron (B) atoms.

[0061] It should be noted that for NMOS transistors, boron atoms are typically doped into the well region 111 to adjust the threshold voltage of the transistor subsequently formed in the well region 111. Of course, boron atoms are also doped when the well region 111 is ion-doped.

[0062] Step S102: A barrier layer is formed in the well region, which divides the well region into a first region and a second region. The first region is located above the barrier layer and the second region is located below the barrier layer. The barrier layer is used to suppress the diffusion of type 1 impurity atoms in the second region into the first region.

[0063] It should be noted that type I impurity atoms diffuse towards the surface of well region 111, resulting in their accumulation primarily near the surface of well region 111. This means the concentration of type I impurity atoms on the surface of well region 111 is higher than the concentration at the bottom of substrate 110. Since the concentration of type I impurity atoms on the surface of well region 111 directly affects the threshold voltage of the transistor, for example, an increased concentration of boron atoms near the top surface of the well region in the substrate leads to stronger random impurity perturbations, resulting in larger threshold voltage perturbations in the transistor and affecting the electrical performance of the semiconductor structure.

[0064] Therefore, in order to ensure the stability of the threshold voltage of the transistor and reduce random disturbances in the threshold voltage, in this embodiment, a barrier layer 120 is formed in the well region 111, such as... Figure 2 As shown, the well region 111 is divided into a first region 1111 and a second region 1112 by a barrier layer 120. The first region 1111 is located above the barrier layer 120, and the second region 1112 is located below the barrier layer 120. In this way, the barrier layer 120 can suppress the diffusion of first type impurity atoms in the second region 1112 into the first region 1111, thereby avoiding the random perturbation of the threshold voltage of the transistor caused by the increase of the concentration of first type impurity atoms in the first region 1111.

[0065] In some alternative embodiments, the step of forming the barrier layer 120 in the well region 111 includes: implanting inert impurity atoms into the well region 111 and performing a thermal annealing process to form the barrier layer 120.

[0066] For example, before forming the barrier layer 120 in the well region 111, a first mask layer can be formed on the substrate 110 and patterned so that the first mask layer exposes the upper surface of the well region 111. Then, inert impurity atoms are injected into the exposed upper surface of the well region 111 with a certain energy and dose. In this way, the concentration of inert impurity atoms near the upper surface of the well region 111 is relatively high. After that, a thermal annealing process is performed so that the inert atoms in the well region 111 combine with the first type of impurity atoms in the well region 111 to form the barrier layer 120, thereby suppressing the diffusion of the first type of impurity atoms near the bottom of the substrate 110 to the top of the well region 111.

[0067] For example, the first type of impurity atom includes boron atoms, and the inert impurity atom includes at least one of germanium atoms, carbon atoms, and argon atoms. For example, the inert impurity atom is germanium atom, that is, germanium atoms are implanted into the well region 111 by ion implantation and subjected to a rapid thermal annealing process, wherein the rapid thermal annealing temperature can be between 800°C and 1000°C, so that the boron atoms and germanium atoms near the surface in the well region 111 form germanium-boron atom pairs, that is, the germanium-boron atom pairs form a barrier layer 120, thereby suppressing the diffusion of boron atoms from the second region 1112 into the first region 1111.

[0068] In some optional embodiments, the implantation depth of inert impurity atoms is 9 nm to 10 nm. It is understood that after implantation, the inert impurity atoms are mainly concentrated at a depth of 9 nm to 10 nm vertically downward from the upper surface of the well region 111. Thus, after a rapid thermal annealing process, boron atoms and inert impurity atoms (e.g., germanium atoms) combine in the region at a depth of 9 nm to 10 nm to form a boron-germanium pair, thereby forming a barrier layer 120. That is, the barrier layer 120 is located at a depth of 9 nm to 10 nm from the upper surface of the well region 111, so that the well region 111 is divided into a first region 1111 and a second region 1112 by the barrier layer 120, with the first region 1111 located above the barrier layer 120 and the second region 1112 located below the barrier layer 120. Thus, the dimension of the first region 1111 along the depth direction of the well region 111 is 9 nm to 10 nm.

[0069] It should be noted that after the barrier layer 120 divides the trap region 111 into the first region 1111 and the second region 1112, the top surface of the first region 1111 is flush with the top surface of the shallow channel isolation structure 112.

[0070] Step S103: An oxide layer is formed on the surface of the first region by a thermal oxidation process, wherein, during the thermal oxidation process, first type impurity atoms in the first region diffuse into the oxide layer.

[0071] Please combine Figure 3 As shown, after the barrier layer 120 is formed in the trap region 111, an oxide layer 130 can be formed on the surface of the first region 1111 by a thermal oxidation process. In this way, during the thermal oxidation process, first type impurity atoms (e.g., boron atoms) in the first region 1111 diffuse into the oxide layer 130, thereby reducing the concentration of first type impurity atoms in the first region 1111.

[0072] For example, in the thermal oxidation process, the thermal oxidation temperature can be, for example, 950°C, and the thermal oxidation time can be, for example, 8 seconds. The specific thermal oxidation conditions can be adapted to actual needs and are not specifically limited here.

[0073] The oxide layer 130 can be a thin oxide layer 130 formed on the top surface of the first region 1111.

[0074] Step S104: Remove the oxide layer.

[0075] Please combine Figure 4 and Figure 5 As shown, for example, an oxide layer 130 is formed on the top surface of the first region 1111 by a thermal oxidation process. First type impurity atoms (e.g., boron atoms) in the first region 1111 diffuse into the oxide layer 130 during the thermal oxidation process to reduce the concentration of first type impurity atoms in the first region 1111. Then, the oxide layer 130 is removed to expose the first region 1111 in the trap region 111.

[0076] In some alternative embodiments, the oxide layer 130 is removed to expose the top surface of the first region 1111, and the top surface of the first region 1111 is flush with the top surface of the shallow trench isolation structure 112, such as... Figure 4 As shown in the image.

[0077] In some alternative embodiments, while removing the oxide layer 130, a portion of the first region 1111 is also removed, such that the top surface of the remaining first region 1111 is lower than the top surface of the shallow trench isolation structure 112, as shown below. Figure 5 As shown in the figure, this is to ensure complete removal of the oxide layer 130, which has a high concentration of first-type impurity atoms.

[0078] For example, in the direction perpendicular to the main surface of the substrate 110 (e.g., the upper surface of the substrate 110), the thickness of the remaining first region 1111 is 2nm to 5nm, for example, the thickness of the remaining first region 1111 is 2nm, 3nm, 4nm, or 5nm, etc.

[0079] Step S105: Form an epitaxial layer on the remaining first region.

[0080] Please combine Figure 6 As shown, for example, after removing the oxide layer 130, an epitaxial layer 140 is selectively epitaxially grown on the top surface of the exposed first region 1111. For example, the epitaxial layer 140 is an epitaxial silicon layer, and the thickness of the epitaxial layer 140 is 10 nm to 12 nm in the direction perpendicular to the main surface of the substrate 110.

[0081] Understandably, during the epitaxial growth process and subsequent thermal processes, type I impurity atoms (such as boron atoms) diffuse from the second region 1112 into the epitaxial layer 140. However, due to the suppression of the barrier layer 120 in the first region 1111 and the second region 1112, the concentration of type I impurity atoms that can diffuse into the epitaxial layer 140 is very low. Since the epitaxial layer 140 is formed by epitaxial growth on the top surface where the type I impurity atoms are already very small, the concentration of type I impurity atoms in the epitaxial layer 140 is also very low, thus ensuring a low doping concentration in the epitaxial layer 140.

[0082] In some alternative embodiments, transistors can be formed on the epitaxial layer 140, wherein the channel region of the transistor is located at least in the epitaxial layer 140, thereby ensuring a low channel doping concentration in the transistor and thus suppressing random perturbations in the threshold voltage of the transistor.

[0083] In this embodiment, the boron atom concentration distribution in the semiconductor structure (represented by A) with no barrier layer 120, oxide layer 130, and epitaxial layer 140 in the well region 111, the semiconductor structure (represented by B) with only an epitaxial layer 140 on the top surface of the well region 111, and the semiconductor structure (represented by C) provided in this embodiment (i.e., the semiconductor structure provided in this embodiment with a barrier layer 120 and oxide layer 130 in the well region 111, with the oxide layer 130 removed and an epitaxial layer 140 on the top surface of the well region 111) are simulated. The simulation results are as follows. Figure 7 As shown, from Figure 7The simulation results show that the boron concentration near the surface of the well region 111, from high to low, is as follows: no epitaxial layer 140 on the top surface of the well region 111 (i.e., A), only an epitaxial layer 140 on the top surface of the well region 111 (i.e., B), and the structure provided in this embodiment, which has an epitaxial layer 140 on the top surface of the well region 111 and a barrier layer 120 and an oxide layer 130 in the well region 111 and removes the oxide layer 130 (i.e., C). That is, the boron atom concentration near the surface of the well region in the above three structures, from high to low, is A, B, and C. Then, for the above three structures, NMOS transistors with a gate length of 64.5 nm are constructed on the well region 111 of the three structures respectively, and the standard deviation of the transistor threshold voltage distribution caused by the boron doping concentration is simulated. Among them, for the structure with only an epitaxial layer 140 on the top surface of the well region 111, the standard deviation of the boron doping concentration is simulated. The simulation results of the surface-mount epitaxial layer 140 (i.e., B) and the structure provided in this application embodiment, which has an epitaxial layer 140 on the top surface of the well region 111 and a barrier layer 120 and an oxide layer 130 in the well region 111 and then removes the oxide layer 130 (i.e., C), are normalized. It should be noted that normalizing the standard deviation values ​​of the threshold voltages of A, B, and C means taking the actual standard deviation value of the threshold voltage obtained from the simulation of A as 1, and dividing the actual standard deviation values ​​of the threshold voltages of B and C by the actual standard deviation value of the threshold voltage of A, respectively. The resulting values ​​are the normalized values ​​of the standard deviation values ​​of the threshold voltages of A, B, and C. The normalized values ​​of the standard deviation values ​​of the threshold voltages are then compared. The normalized values ​​of the standard deviation values ​​of the threshold voltages are as follows: Figure 8 As shown, by Figure 8 It can be seen that the standard deviation of the threshold voltage distribution caused by random disturbances in the threshold voltage is the smallest in the solution provided in this application embodiment; in addition, by Figure 9 The schematic diagrams of the drain current versus gate voltage curves in the saturation region of the transistor in the three structures show that after the epitaxial layer 140 is grown on the top surface of the well region 111, the performance of the transistor (such as the on-state current and the off-state current) does not change significantly.

[0084] Therefore, in this embodiment, by forming a barrier layer 120 within the well region 111, the barrier layer 120 divides the well region 111 into a first region 1111 and a second region 1112. The first region 1111 is located above the barrier layer 120, and the second region 1112 is located below the barrier layer 120. This barrier layer 120 is used to suppress the diffusion of first-type impurity atoms from the second region 1112 into the first region 1111. An oxide layer 130 is formed on the surface of the first region 1111 through a thermal oxidation process. Thus, during the thermal oxidation process, first-type impurity atoms in the first region 1111 diffuse into the oxide layer 1112. After dialysis in region 30, the oxide layer 130 is removed, which further reduces the concentration of the first type of impurity atoms in the first region 1111. In addition, an epitaxial layer 140 is formed on the remaining first region 1111, so that the average concentration of the first type of impurity atoms in the epitaxial layer 140 is less than the average concentration of the first type of impurity atoms in the first region 1111, and the average concentration of the first type of impurity atoms in the first region 1111 is less than the average concentration of the first type of impurity atoms in the second region 1112, thereby improving or avoiding random perturbation effects and improving the electrical performance of the semiconductor structure 100.

[0085] In some alternative embodiments, in order to reduce the doping concentration of the first type of impurity atoms in the first region of the well region, for example, to reduce the doping concentration of boron atoms in the first region, in the embodiments of this application, when doping the well region with boron atoms, the energy of ion implantation can be increased to implant boron atoms into a deeper location along the direction perpendicular to the main surface of the substrate, thereby reducing the doping concentration of boron atoms on the top surface of the substrate, thereby reducing the doping concentration of boron atoms in the channel region of the transistor, thereby reducing the random perturbation effect of the threshold voltage of the transistor and improving the electrical performance of the semiconductor structure.

[0086] Please refer to Figure 5 As shown, this application embodiment also provides a semiconductor structure 100, including: a substrate 110, the substrate 110 including a well region 111 and a barrier layer 120 disposed in the well region 111, the well region 111 including first type impurity atoms, the barrier layer 120 dividing the well region 111 into a first region 1111 and a second region 1112, the first region 1111 being located above the barrier layer 120, the second region 1112 being located below the barrier layer 120, and the barrier layer 120 being configured to suppress the diffusion of first type impurity atoms in the second region 1112 into the first region 1111.

[0087] In the above scheme, by setting a barrier layer 120 in the well region 111, the well region 111 is divided into a first region 1111 and a second region 1112 by the barrier layer 120. The first region 1111 is located above the barrier layer 120, and the second region 1112 is located below the barrier layer 120. This allows the barrier layer 120 to suppress the diffusion of first-type impurity atoms in the second region 1112 into the first region 1111, thereby preventing the concentration of first-type impurity atoms in the first region 1111 from continuously increasing.

[0088] The substrate 110 may include, but is not limited to, a silicon substrate. In this embodiment, a silicon substrate is used as an example for illustration. The substrate 110 can serve as a supporting foundation for devices subsequently formed on the substrate 110.

[0089] In addition, the well region 111 can be divided into N-type well region 111 or P-type well region 111 depending on the type of doped atoms. The well region 111 can include multiple device regions. A shallow channel isolation structure 112 can be formed in the device region to separate the device region and form at least one active region. In subsequent processes, transistors, capacitors and other devices are formed in the active region.

[0090] It is understandable that the doping atom types include type I impurity atoms, such as boron atoms.

[0091] In some alternative embodiments, the barrier layer 120 can be an atom pair formed by combining a first type of impurity atom and an inert impurity atom. For example, the first type of impurity atom is a boron atom and the inert impurity atom is a germanium atom. In this way, the barrier layer 120 is a boron-germanium atom pair formed by boron atoms and germanium atoms, thereby suppressing the diffusion of boron atoms in the second region 1112 into the first region 1111 through the boron-germanium atom pair.

[0092] It should be noted that the first region 1111 and the second region 1112 after the well region 111 is divided by the barrier layer 120 are made of the same block semiconductor material, such as a silicon substrate doped with the same type of doped atoms.

[0093] In some optional embodiments, the semiconductor structure 100 further includes an epitaxial layer 140 disposed on the first region 1111, wherein the average concentration of first type impurity atoms in the epitaxial layer 140 is less than the average concentration of first type impurity atoms in the first region 1111, and the average concentration of first type impurity atoms in the first region 1111 is less than the average concentration of first type impurity atoms in the second region 1112.

[0094] It is understood that the epitaxial layer 140 is an epitaxial silicon layer formed on the top surface of the first region 1111 by selective epitaxial growth. Since the epitaxial silicon layer is undoped, the average concentration of first-type impurity atoms in the epitaxial silicon layer is less than the average concentration of first-type impurity atoms in the first region 1111. Due to the suppression of the barrier layer 120, first-type impurity atoms in the second region 1112 cannot diffuse into the first region 1111. Thus, the average concentration of first-type impurity atoms in the first region 1111 is less than the average concentration of first-type impurity atoms in the second region 1112. The transistor is fabricated on the first region 1111, and the channel region of the transistor is located at least within the first region 1111. Thus, the doping concentration of the channel region of the transistor is relatively small, thereby improving or avoiding the random perturbation effect of the channel region doping concentration on the threshold voltage of the transistor, thereby improving the electrical performance of the semiconductor structure 100.

[0095] In some alternative embodiments, the interface between the epitaxial layer 140 and the first region 1111 is below the top surface of the shallow trench isolation structure 112.

[0096] In some alternative embodiments, after the barrier layer 120 is formed in the well region 111 and before the epitaxial layer 140 is formed on the first region 1111, an oxide layer 130 can be formed on the surface of the first region 1111 by a thermal oxidation process. In this way, during the thermal oxidation process, first type impurity atoms (e.g., boron atoms) in the first region 1111 diffuse into the oxide layer 130, thereby reducing the concentration of first type impurity atoms in the first region 1111.

[0097] After the thermal oxidation process is completed, the oxide layer 130 is removed to expose the first region 1111, so that the concentration of the first type of impurity atoms in the first region 1111 is less than the concentration of the first type of impurity atoms in the second region 1112. Then, an epitaxial layer 140 is grown on the first region 1111 by selective epitaxial growth.

[0098] In some alternative embodiments, after the epitaxial layer 140 is formed on the first region 1111, the interface between the first region 1111 and the epitaxial layer 140 (i.e., the retained top surface of the first region 1111) is flush with the top surface of the shallow trench isolation structure 112, such as... Figure 4 As shown in the image.

[0099] In some alternative embodiments, to ensure complete removal of the oxide layer 130, a portion of the first region 1111 may also be removed, such that the top surface of the remaining first region 1111 (i.e., the interface between the epitaxial layer 140 and the first region 1111) is lower than the top surface of the shallow trench isolation structure 112, such as... Figure 5As shown, an epitaxial layer 140 is then formed on the top surface of the retained first region 1111 by selective epitaxial growth.

[0100] In some alternative embodiments, the thickness of the first region 1111 is 2nm-5nm in the direction perpendicular to the main surface of the substrate 110, and the distance between the barrier layer 120 and the top surface of the shallow trench isolation structure 112 is 9nm-10nm.

[0101] In some optional embodiments, the thickness of the epitaxial layer 140 is 10nm-12nm in the direction perpendicular to the main surface of the substrate 110. For example, the thickness of the epitaxial layer 140 may be 10nm, 11nm or 12nm, etc.

[0102] In some alternative embodiments, a transistor is disposed on the epitaxial layer 140, the transistor including a source, a drain and a gate, the gate being located between the source and the drain, and a channel region being disposed below the gate.

[0103] In this configuration, a source region is provided at the position corresponding to the source of the transistor in the well region, and a drain region is provided at the position corresponding to the drain of the transistor in the well region. That is, the source region is electrically connected to the source of the transistor, and the drain region is electrically connected to the drain region of the transistor.

[0104] In addition, a gate oxide layer is provided between the gate and the channel region of the transistor. The gate oxide layer can be made of insulating materials such as silicon dioxide.

[0105] In the semiconductor structure and its fabrication method provided in this application embodiment, a barrier layer is formed in the well region, dividing the well region into a first region and a second region. The first region is located above the barrier layer, and the second region is located below the barrier layer. The barrier layer is used to suppress the diffusion of first-type impurity atoms from the second region into the first region. An oxide layer is formed on the surface of the first region through a thermal oxidation process. During the thermal oxidation process, first-type impurity atoms in the first region diffuse into the oxide layer. After the oxide layer is removed, the concentration of first-type impurity atoms in the first region can be further reduced. In addition, an epitaxial layer is formed on the remaining first region, so that the average concentration of first-type impurity atoms in the epitaxial layer is less than the average concentration of first-type impurity atoms in the first region, and the average concentration of first-type impurity atoms in the first region is less than the average concentration of first-type impurity atoms in the second region, thereby improving or avoiding random perturbation effects and improving the electrical performance of the semiconductor structure.

[0106] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0107] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a well region, the well region including first-type impurity atoms; Inert impurity atoms are injected into the well region to form a barrier layer within the well region. The barrier layer divides the well region into a first region and a second region. The first region is located above the barrier layer, and the second region is located below the barrier layer. The barrier layer is used to suppress the diffusion of the first type of impurity atoms in the second region into the first region. The first region and the second region are made of the same bulk semiconductor material. An oxide layer is formed on the surface of the first region by a thermal oxidation process, wherein, during the thermal oxidation process, the first type of impurity atoms in the first region diffuse into the oxide layer; Remove the oxide layer; An epitaxial layer is formed on the remaining first region.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a barrier layer within the well region includes: Inert impurity atoms are injected into the well region, and a thermal annealing process is performed to form the barrier layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The first type of impurity atom includes boron atoms, and the inert impurity atom includes at least one of germanium atoms, carbon atoms, and argon atoms.

4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The step of forming an epitaxial layer on the remaining first region includes: An undoped epitaxial layer is selectively grown on the top surface of the remaining first region, wherein the epitaxial layer comprises an epitaxial silicon layer or an epitaxial germanium-silicon layer.

5. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, Before the formation of the oxide layer, the following are also included: A shallow trench isolation structure is formed on the substrate, and the top surface of the first region is flush with the top surface of the shallow trench isolation structure. After the oxide layer is removed, the top surface of the remaining first region is lower than the top surface of the shallow trench isolation structure.

6. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, After forming the epitaxial layer on the remaining first region, the process further includes: A transistor is formed on the epitaxial layer.

7. A semiconductor structure, characterized in that, include: A substrate includes a well region and a barrier layer disposed within the well region. The well region includes first-type impurity atoms. The barrier layer divides the well region into a first region and a second region. The first region is located above the barrier layer, and the second region is located below the barrier layer. The barrier layer is configured to suppress the diffusion of first-type impurity atoms in the second region into the first region. The first region and the second region comprise the same bulk semiconductor material. An epitaxial layer is disposed on the first region, wherein the average concentration of the first type of impurity atoms in the epitaxial layer is less than the average concentration of the first type of impurity atoms in the first region, and the average concentration of the first type of impurity atoms in the first region is less than the average concentration of the first type of impurity atoms in the second region.

8. The semiconductor structure according to claim 7, characterized in that, The semiconductor junction further includes a shallow trench isolation structure, the top surface of which is higher than the interface between the epitaxial layer and the first region.

9. The semiconductor structure according to any one of claims 7-8, characterized in that, Also includes: A transistor is disposed on the epitaxial layer, wherein the channel region of the transistor is located at least in the epitaxial layer.

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