Asymmetric half-bridge flyback switching power supply and its control circuit

Abstract

An asymmetric half-bridge flyback switching power supply and its control circuit are provided. The control circuit is configured to: after the upper switching transistor changes from an on state to an off state and before changing from an off state to an on state, generate a first turn-on control signal for controlling the lower switching transistor to change from an off state to an on state for the first time, based on an upper transistor control signal for controlling the on and off of the upper switching transistor; generate a first turn-off control signal for controlling the lower switching transistor to change from an on state to an off state for the first time, based on a demagnetization characterization signal characterizing the demagnetization of the transformer; generate a second turn-on control signal for controlling the lower switching transistor to change from an off state to an on state again, based on the demagnetization characterization signal and an output feedback signal characterizing the output voltage of the asymmetric half-bridge flyback switching power supply; and generate a second turn-off control signal for controlling the lower switching transistor to change from an on state to an off state again, based on the demagnetization characterization signal.

Description

Technical Field

[0001] This invention relates to the field of circuits, and more specifically to an asymmetric half-bridge flyback switching power supply and its control circuit. Background Technology

[0002] A switching power supply, also known as a switching converter or switching power supply, is a type of power supply. The function of a switching power supply is to convert a voltage level from one voltage level to the voltage or current required by the user through different architectures (e.g., flyback, buck, or boost architectures). Summary of the Invention

[0003] According to an embodiment of the present invention, a control circuit for an asymmetric half-bridge flyback switching power supply includes an upper switching transistor, a lower switching transistor, and a transformer. The control circuit is configured to, after the upper switching transistor changes from an on state to an off state and before changing from an off state to an on state: generate a first turn-on control signal for controlling the lower switching transistor to change from an off state to an on state for the first time, based on an upper transistor control signal for controlling the on and off states of the upper switching transistor; generate a first turn-off control signal for controlling the lower switching transistor to change from an on state to an off state for the first time, based on a demagnetization characterization signal characterizing the demagnetization of the transformer; generate a second turn-on control signal for controlling the lower switching transistor to change from an off state to an on state again, based on the demagnetization characterization signal and an output feedback signal characterizing the output voltage of the asymmetric half-bridge flyback switching power supply; and generate a second turn-off control signal for controlling the lower switching transistor to change from an on state to an off state again, based on the demagnetization characterization signal.

[0004] The asymmetric half-bridge flyback switching power supply according to an embodiment of the present invention includes the control circuit described above for the asymmetric half-bridge flyback switching power supply. Attached Figure Description

[0005] The invention can be better understood from the following description of specific embodiments of the invention in conjunction with the accompanying drawings, wherein:

[0006] Figure 1 A schematic diagram of the topology of a traditional asymmetric half-bridge flyback switching power supply is shown.

[0007] Figure 2 It shows Figure 1 The diagram shows the waveforms of multiple signals when the switching power supply is operating in critical conduction mode.

[0008] Figure 3 It shows Figure 1 The diagram shows the waveforms of multiple signals when the switching power supply is operating in discontinuous conduction mode.

[0009] Figure 4 A circuit diagram of a control circuit for an asymmetric half-bridge flyback switching power supply according to an embodiment of the present invention is shown.

[0010] Figure 5 It shows Figure 4 The circuit schematic shown is an example circuit implementation of the ZVS enable module.

[0011] Figure 6 This shows the situation when the enable signal Tzvs_ENA is turned on again. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply.

[0012] Figure 7 This shows the case where the enable signal Tzvs_ENA is in a disabled state when it is turned on again. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply.

[0013] Figure 8 It shows Figure 4 The circuit schematic shown is an example circuit implementation of the ZVS computing module.

[0014] Figure 9 This shows the case where the voltage V3 in the ZVS calculation module is higher than the reference voltage Vref. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply.

[0015] Figure 10 This shows the case where the voltage V3 in the ZVS calculation module is lower than the reference voltage Vref. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply.

[0016] Figure 11 This shows the case where the voltage V3 in the ZVS calculation module is equal to the reference voltage Vref. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply.

[0017] Figure 12 It shows Figure 4 The circuit schematic is shown as another example of the ZVS computing module implementation. Detailed Implementation

[0018] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of the invention. Well-known structures and techniques are not shown in the drawings and the following description in order to avoid unnecessarily obscuring the invention.

[0019] Figure 1 A schematic diagram of a traditional asymmetric half-bridge flyback switching power supply topology is shown. Figure 1 In the switching power supply 100 shown, zero-voltage switching (ZVS) of the upper switch Q1 and the lower switch Q2 can be achieved through the resonance of the resonant capacitor Cr and the primary inductance Lp and primary leakage inductance Lr of the transformer T. Typically, Figure 1 The switching power supply 100 shown operates in critical conduction mode (CRM) under heavy system load and in discontinuous conduction mode (DCM) under light system load. It can operate in a cyclic manner of n (n≥1) critical conduction modes plus 1 discontinuous conduction mode or continuously operate in discontinuous conduction mode.

[0020] Figure 2 It shows Figure 1 The diagram shows the waveforms of multiple signals when the switching power supply is operating in critical conduction mode. Here, Q1 gate represents the upper transistor control signal used to control the on / off state of the upper switching transistor Q1, Q2 gate represents the lower transistor control signal used to control the on / off state of the lower switching transistor Q2, and I... Lr Represents the primary resonant current I of transformer T. Do HB represents the secondary current of transformer T, and HB voltage represents the voltage at the midpoint between the upper switch Q1 and the lower switch Q2.

[0021] like Figure 1 and Figure 2 As shown, Figure 1 The operation of the switching power supply 100 in critical conduction mode is as follows: At time t0, the upper switching transistor Q1 changes from the off state to the on state, and the input voltage Vin charges the primary magnetizing inductance Lm (Lm=Lp+Lr) of the transformer T through the resonant capacitor Cr. The primary resonant current I of the transformer T... LrThe upward trend continues; at time t1, the upper switch Q1 changes from the on state to the off state, and the circuit for charging the primary excitation inductor Lm of transformer T by the input voltage Vin is broken. Since the current in the inductor cannot change abruptly, the primary resonant current I of transformer T... Lr Discharging the parasitic capacitance of the lower switch Q2 and charging the parasitic capacitance of the upper switch Q1 causes the HB voltage to drop to 0V, and the body diode of the lower switch Q2 changes from the off state to the on state. At time t2, the lower switch Q2 changes from the off state to the on state, thus achieving zero-voltage conduction. After that, the resonant capacitor Cr and the primary leakage inductance Lr of the transformer T resonate, and the primary resonant current I of the transformer T... Lr After dropping to 0A, the negative current increases, and at the same time, transformer T demagnetizes, and the primary excitation current I of transformer T... Lm The primary resonant current I of transformer T decreases linearly; at time t3, the primary resonant current I of transformer T decreases linearly. Lr Resonance to the primary excitation current I Lm With the same magnitude, the demagnetization of transformer T ends, and the secondary current I of transformer T... Do Returning to 0A, the resonant capacitor Cr then discharges through the lower switch Q2 to the primary magnetizing inductance Lm of transformer T, and the primary resonant current I of transformer T... Lr The negative value increases; at time t4, the lower switch Q2 changes from the on state to the off state, and the circuit for the resonant capacitor Cr to discharge to the primary excitation inductor Lm of the transformer T is broken. Since the current in the inductor cannot change abruptly, the primary resonant current I of the transformer T... Lr The parasitic capacitance of the upper switch Q1 is discharged and the parasitic capacitance of the lower switch Q2 is charged, the HB voltage rises to the input voltage Vin, and the body diode of the upper switch Q1 changes from the off state to the on state; at time t5, the upper switch Q1 changes from the off state to the on state, thus achieving zero voltage conduction.

[0022] Figure 3 It shows Figure 1 The diagram shows the waveforms of multiple signals when the switching power supply operates in discontinuous conduction mode. Here, Q1 gate represents the upper transistor control signal used to control the on / off state of the upper switching transistor Q1, Q2 gate represents the lower transistor control signal used to control the on / off state of the lower switching transistor Q2, and I... Lr Represents the primary resonant current I of transformer T. Do HB represents the secondary current of transformer T, and HB voltage represents the voltage at the midpoint between the upper switch Q1 and the lower switch Q2.

[0023] like Figure 1 and Figure 3 As shown, Figure 1The operation of the switching power supply 100 in discontinuous conduction mode is as follows: At time t0, the upper switching transistor Q1 changes from the off state to the on state, and the input voltage Vin charges the primary magnetizing inductance Lm (Lm=Lp+Lr) of the transformer T through the resonant capacitor Cr. The primary resonant current I of the transformer T... Lr The upward trend continues; at time t1, the upper switch Q1 changes from the on state to the off state, and the circuit for charging the primary excitation inductor Lm of transformer T by the input voltage Vin is broken. Since the current in the inductor cannot change abruptly, the primary resonant current I of transformer T... Lr Discharging the parasitic capacitance of the lower switch Q2 and charging the parasitic capacitance of the upper switch Q1 causes the HB voltage to drop to 0V, and the body diode of the lower switch Q2 changes from the off state to the on state. At time t2, the lower switch Q2 changes from the off state to the on state, thus achieving zero-voltage conduction. After that, the resonant capacitor Cr and the primary leakage inductance Lr of the transformer T resonate, and the primary resonant current I of the transformer T... Lr After dropping to 0A, the negative current increases, and at the same time, the primary excitation current I of transformer T... Lm At time t3, the lower switch Q2 changes from the on state to the off state, breaking the resonant circuit of the resonant capacitor Cr and the primary leakage inductance Lr of the transformer T. Then, the parasitic capacitances of the upper switch Q1 and the lower switch Q2 resonate with the primary magnetizing inductance Lm of the transformer T. If the resonant amplitude of the HB voltage is not large enough, and the resonant peak value cannot reach the input voltage Vin, then at time t4, the lower switch Q2 needs to change from the off state to the on state again. The resonant capacitor Cr discharges through the lower switch Q2 to the primary magnetizing inductance Lm of the transformer T, and the primary resonant current I of the transformer T... Lr The negative value increases; at time t5, the lower switch Q2 changes from the on state to the off state, and the circuit for the resonant capacitor Cr to discharge to the primary excitation inductance Lm of the transformer T is broken. The primary excitation inductance Lm of the transformer T and the parasitic capacitances of the upper switch Q1 and the lower switch Q2 resonate. Since the current in the inductor cannot change abruptly, the primary resonant current I of the transformer T increases. Lr Discharging the parasitic capacitance of the upper switching transistor Q1 and charging the parasitic capacitance of the lower switching transistor Q2, if the primary resonant current I of the transformer T... Lr If the voltage is large enough, the HB voltage will rise to the input voltage Vin, and the body diode of the upper switch Q1 will change from the off state to the on state; at time t6, the upper switch Q1 will change from the off state to the on state, thus achieving zero-voltage conduction.

[0024] exist Figure 1 When the switching power supply 100 shown operates in discontinuous conduction mode, whether the lower switching transistor Q2 can achieve zero-voltage conduction at time t2 depends on the primary resonant current I of the transformer T. LrThe forward peak current Ip when the upper switch Q1 changes from the on state to the off state is sufficient to make the HB voltage resonate to 0V even under light system load. Therefore, the lower switch Q2 can definitely achieve zero-voltage turn-on. Whether the upper switch Q1 can achieve zero-voltage turn-on at time t6 depends on the primary resonant current I of the transformer T when the lower switch Q2 changes from the on state to the off state again at time t5. Lr The negative current amplitude In_zvs depends on the duration of the lower switch Q2's off state (Tdcm) and its subsequent on-state (Tzvs). A shorter Tzvs results in a smaller negative current amplitude In_zvs, and a smaller resonant energy of the primary magnetizing inductance Lm of transformer T and the parasitic capacitances of the upper and lower power transistors Q1 and Q2 during the t5-t6 period. Too small a resonant energy prevents the upper switch Q1 from achieving zero-voltage turn-on. Conversely, a longer Tzvs results in a larger negative current amplitude In_zvs, and a larger resonant energy of the primary magnetizing inductance Lm of transformer T and the parasitic capacitances of the upper and lower switch transistors Q1 and Q2 during the t5-t6 period. While a larger resonant energy makes it easier for the upper switch Q1 to achieve zero-voltage turn-on, there is energy loss during resonance, and a larger resonant energy results in greater energy loss. On the other hand, the larger the negative current amplitude In_zvs, the larger the positive peak current Ip needs to be to maintain a constant output. This leads to a larger loss when the upper switching transistor Q1 changes from the on state to the off state. Therefore, an excessively long Tzvs time will actually reduce efficiency. Therefore, Tzvs needs to be controlled so that the upper switching transistor Q1 can just achieve zero-voltage turn-on.

[0025] In view of the above, a control circuit for an asymmetric half-bridge flyback switching power supply according to an embodiment of the present invention is proposed. This circuit can control the duration Tzvs of the lower switch Q2 being in the conducting state again when the asymmetric half-bridge flyback switching power supply is operating in discontinuous conduction mode, and control the primary resonant current I of the transformer T when the lower switch Q2 changes from the conducting state to the off state. Lr The negative current amplitude In_zvs ensures that the upper switch Q1 can still achieve zero-voltage conduction under light system load conditions, without wasting resonant energy, thus guaranteeing optimal efficiency under light load.

[0026] Figure 4 A circuit diagram of a control circuit for an asymmetric half-bridge flyback switching power supply according to an embodiment of the present invention is shown. Figure 4As shown, the control circuit for an asymmetric half-bridge flyback switching power supply 400 according to an embodiment of the present invention includes a circuit section 402 for controlling the on and off of the upper switching transistor Q1 and a circuit section 404 for controlling the on and off of the lower switching transistor Q2. The circuit section 402 is configured to generate an upper switching transistor control signal gate_up based on an output feedback signal FB characterizing the output voltage Vo of the asymmetric half-bridge flyback switching power supply 400, a current characterization signal Vcs characterizing the resonant current on the primary side of the transformer T, and a lower switching transistor control signal gate_down for controlling the on and off of the lower switching transistor Q2. The circuit section 404 is configured to generate a lower switching transistor control signal gate_down based on the output feedback signal FB, a demagnetization characterization signal INV characterizing the demagnetization of the transformer T, and the upper switching transistor control signal gate_up.

[0027] like Figure 4 As shown, in some embodiments, circuit section 402 is further configured to generate the upper MOSFET control signal gate_up through the following processes: generating an upper MOSFET turn-off control signal CV_off based on the output feedback signal FB and the current characterization signal Vcs (e.g., by comparing the voltage divider signal of the output feedback signal FB and the current characterization signal Vcs); generating an upper MOSFET turn-on control signal up_on based on the lower MOSFET control signal gate_down; and generating the upper MOSFET control signal gate_up based on the upper MOSFET turn-off control signal CV_off and the upper MOSFET turn-on control signal up_on.

[0028] like Figure 4 As shown, in some embodiments, circuit section 404 is further configured to generate a lower switch control signal gate_down through the following processes after the upper switch Q1 changes from the on state to the off state and before changing from the off state to the on state: based on the upper switch control signal gate_up, generate a first turn-on control signal down_on for controlling the lower switch Q2 to change from the off state to the on state for the first time; based on the demagnetization characterization signal INV, generate a first turn-off control signal down_off for controlling the lower switch Q2 to change from the on state to the off state for the first time; based on the demagnetization characterization signal INV and the output feedback signal FB, generate a second turn-on control signal ZVS_on (not shown in the figure) for controlling the lower switch Q2 to change from the off state to the on state again; and based on the demagnetization characterization signal INV, generate a second turn-off control signal ZVS_off for controlling the lower switch Q2 to change from the on state to the off state again. Here, the gate_down control signal is generated based on the first turn-on control signal down_on, the first turn-off control signal down_off, the turn-on control signal ZVS_on, and the turn-off control signal ZVS_off.

[0029] like Figure 4 As shown, in some embodiments, circuit section 404 is further configured to generate a re-conduction control signal ZVS_on through the following processes: generating a re-conduction enable signal Tzvs_ENA based on the demagnetization detection signal INV to control whether the lower switch Q2 is allowed to change from the off state to the on state again; generating a mode / frequency control signal DCM_on based on the output feedback signal FB to control at least one of the operating mode and operating frequency of the asymmetric half-bridge flyback switching power supply 400; and generating the re-conduction control signal ZVS_on based on the re-conduction enable signal Tzvs_ENA and the mode / frequency control signal DCM_on.

[0030] like Figure 4 As shown, in some embodiments, after a first predetermined time period starting from the moment when the upper switch Q1 is controlled by the upper control signal gate_up to change from the on state to the off state, the lower switch Q2 is first turned on by the first turn-on control signal down_on. After a second predetermined time period starting from the moment when the lower switch Q2 is controlled by the lower control signal gate_down to change from the on state to the off state, the upper switch Q1 is turned on by the upper turn-on control signal up_on.

[0031] Specifically, in Figure 4 In the asymmetric half-bridge flyback switching power supply 400 shown: the output voltage Vo is divided by resistors and then processed by TL431 and optocoupler to generate voltage FB (i.e., output feedback signal FB); after the upper switch Q1 changes from the off state to the on state, the input voltage Vin charges the primary magnetizing inductance Lm of transformer T through resonant capacitor Cr, and the primary resonant current I of transformer T... Lr As the current rises, the voltage Vcs across the current sensing resistor Rcs (i.e., the current characterization signal Vcs) increases. When the voltage Vcs across the current sensing resistor Rcs is higher than the voltage at the midpoint between the upper switch Q1 and the lower switch Q2 (i.e., the voltage HB after voltage division), the upper switch turn-off control signal CV_off changes from low to high, and the upper switch Q1 changes from the on state to the off state. After the upper switch Q1 changes from the on state to the off state, the primary resonant current I of the transformer T... LrThe parasitic capacitance of the lower switch Q2 is discharged while the parasitic capacitance of the upper switch Q1 is charged. The HB voltage drops to 0V, and the body diode of the lower switch Q2 changes from off to on. The dead-time module starts timing at the moment the upper switch Q1 changes from on to off, and after fixing the dead time, controls the lower switch Q2 to change from off to on, achieving zero-voltage turn-on of the lower switch Q2. The voltage INV on the auxiliary winding side of transformer T (i.e., the demagnetization characterization signal INV) is sent to the first turn-off control signal down_off generated by the demagnetization detection module. After controlling the lower switch Q2 to change from on to off, the primary excitation inductance Lm of transformer T resonates with the parasitic capacitances of the upper and lower switches Q1 and Q2. The voltage INV is then sent to the ZVS enable module to generate a re-turn-on enable. The signal Tzvs_ENA controls whether the lower switch Q2 is allowed to change from the off state to the on state again; the voltage FB, after being divided, is sent to the mode / frequency control signal DCM_on generated by the mode / frequency module to limit the operating state and frequency of the asymmetric half-bridge flyback switching power supply 400 (for example, the mode / frequency control signal DCM_on can reduce the system operating frequency when the system load decreases); when the mode / frequency control signal DCM_on flips, if the re-enable signal Tzvs_ENA is enabled, the lower switch Q2 changes from the off state to the on state again; the voltage INV is sent to the re-turn-off control signal ZVS_off generated by the ZVS calculation module to control the lower switch Q2 to change from the on state to the off state again, and the primary resonant current I of the transformer... Lr The parasitic capacitance of the upper switch Q1 is discharged while the parasitic capacitance of the lower switch Q2 is charged. The HB voltage rises to the input voltage Vin, and the body diode of the upper switch Q1 changes from the off state to the on state. At this moment, the dead-time module starts timing at the moment the lower switch Q2 changes from the on state to the off state, and after a fixed dead-time, controls the upper switch Q1 to change from the off state to the on state, achieving zero-voltage turn-on of the upper switch Q1. When the mode / frequency control signal DCM_on toggles, if the enable signal Tzvs_ENA is deactivated again, the lower switch Q2 will not change from the off state to the on state. The dead-time module generates a fixed dead-time delay and controls the upper switch Q1 to change from the off state to the on state when the HB voltage resonates to its highest value, achieving zero-voltage turn-on of the upper switch Q1. It should be noted that zero-voltage turn-on does not necessarily mean that the voltage difference before and after the switch is turned on is 0V; any relatively low voltage value constitutes zero-voltage turn-on.

[0032] After the initial turn-off control signal `down_off` generated by the demagnetization detection module causes switch Q2 to change from the on state to the off state, the primary magnetizing inductance Lm of transformer T and the sum of the parasitic capacitances of the upper switch Q1 and the lower switch Q2 resonate (Coss). The resonant circuit includes the resonant capacitance Cr of transformer T, and the resonant capacitance Cr is much larger than the sum of the parasitic capacitances of the upper switch Q1 and the lower switch Q2 (Coss). The voltage across the resonant capacitance Cr is N˙Vo. If there is no negative current in the resonant circuit at the initial moment, the resonant center value of the HB voltage is N˙Vo, and the resonant amplitude is also N˙Vo. Therefore, the highest resonant voltage can reach 2N˙Vo. If Vin < 2N˙Vo, then it is not necessary to control the lower switch Q2 to change from the off state to the on state again to basically achieve zero-voltage turn-on of the upper switch Q1.

[0033] Figure 5 It shows Figure 4 The circuit schematic shown is an example implementation of the ZVS enable module. Figure 5 As shown, in some embodiments, the ZVS enable module is configured to: generate a first sampling signal V1 by sampling the demagnetization characterization signal INV during the period when the upper switch Q1 is in the on state and the lower switch Q2 is in the off state; generate a second sampling signal V2 by sampling the demagnetization characterization signal INV during the period when the upper switch Q1 is in the off state and the lower switch Q2 is in the on state; and generate a re-enable signal Tzvs_ENA by comparing the first sampling signal V1 and the second sampling signal V2.

[0034] like Figure 4 and Figure 5 As shown, voltage INV is sampled by the sampling unit to generate voltages V1 and V2. Voltage V1 = m1·(Vin-N·Vo) is a voltage proportional to the magnetizing voltage (Vin-N·Vo) sampled during the period when the upper switch Q1 is in the on state and the lower switch Q2 is in the off state. Voltage V2 = m2·N·Vo is a voltage proportional to the demagnetizing voltage (N·Vo) sampled during the period when the upper switch Q1 is in the off state and the lower switch Q2 is in the on state. After simple calculation and transformation by the calculation and comparison unit, voltages V1 and V2 are compared or directly compared to generate a re-enable signal Tzvs_ENA used to control whether the lower switch Q2 is allowed to change from the off state to the on state again.

[0035] Figure 6 This shows the situation when the enable signal Tzvs_ENA is turned on again. Figure 4The diagram shows the waveforms of multiple signals in the switching power supply. Here, Q1 gate represents the upper transistor control signal used to control the on / off state of the upper switching transistor Q1, Q2 gate represents the lower transistor control signal used to control the on / off state of the lower switching transistor Q2, and I... Lr The primary resonant current of transformer T is represented by DCM_on, the mode / frequency control signal is represented by ZVS_off, the turn-off control signal is represented by INV, and the demagnetization characterization signal is represented by INV.

[0036] like Figure 4 and Figure 6 As shown, when the enable signal Tzvs_ENA is turned on again, Figure 4 The working process of the switching power supply 400 shown is as follows: At time t0, the upper switching transistor Q1 changes from the off state to the on state, and the primary resonant current I of the transformer T... Lr As the current rises, the voltage Vcs across the current sensing resistor Rcs increases. When the voltage Vcs across the current sensing resistor Rcs rises to a level higher than the voltage divider of FB, at time t1, the upper switch Q1 changes from the on state to the off state. Since the current in the inductor cannot change abruptly, the primary resonant current I of the transformer T... Lr The parasitic capacitance of the lower switch Q2 is discharged while the parasitic capacitance of the upper switch Q1 is charged, causing the HB voltage to drop to 0V. The body diode of the lower switch Q2 changes from the off state to the on state. At time t2, the first turn-on control signal down_on flips, and the lower switch Q2 changes from the off state to the on state, thus achieving zero-voltage turn-on. Afterward, the resonant capacitor Cr and the primary leakage inductance Lr of the transformer T resonate, and at the same time, the transformer T demagnetizes, and the primary excitation current I of the transformer T... Lm At time t3, the initial turn-off control signal dem_off flips, and the lower switch Q2 changes from the on state to the off state. Afterwards, the parasitic capacitances of the upper switch Q1 and the lower switch Q2 resonate with the primary magnetizing inductance Lm of the transformer T, with a resonant period of td. At time t4, the mode / frequency control signal DCM_on flips, while the re-enable signal Tzvs_ENA is enabled. The lower switch Q2 changes from the off state to the on state again. The resonant capacitor Cr discharges through the lower switch Q2 to the primary magnetizing inductance Lm of the transformer T, and the primary resonant current I of the transformer T increases. Lr The negative value increases; at time t5, the control signal ZVS_off flips again, and the lower switch Q2 changes from the on state to the off state again. The circuit for the resonant capacitor Cr to discharge to the primary excitation inductance Lm of the transformer T is broken. The primary excitation inductance Lm of the transformer T and the parasitic capacitances of the upper switch Q1 and the lower switch Q2 resonate. Since the current in the inductor cannot change abruptly, the primary resonant current I of the transformer T... LrThe parasitic capacitance of the upper switch Q1 is discharged and the parasitic capacitance of the lower switch Q2 is charged, the HB voltage rises to the input voltage Vin, and the body diode of the upper switch Q1 changes from the off state to the on state; at time t6, the upper switch Q1 turns on control signal up_on, and the upper switch Q1 changes from the off state to the on state again, thus achieving zero voltage turn-on.

[0037] Figure 7 This shows the case where the enable signal Tzvs_ENA is in a disabled state when it is turned on again. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply. Here, Q1 gate represents the upper transistor control signal used to control the on / off state of the upper switching transistor Q1, Q2 gate represents the lower transistor control signal used to control the on / off state of the lower switching transistor Q2, and I... Lr The primary resonant current of transformer T is represented by DCM_on, the mode / frequency control signal is represented by ZVS_off, the turn-off control signal is represented by INV, and the demagnetization characterization signal is represented by INV.

[0038] like Figure 4 and Figure 7 As shown, when the enable signal Tzvs_ENA is turned on again and is in a disabled state, Figure 4 The working process of the switching power supply 400 shown is as follows: At time t0, the upper switching transistor Q1 changes from the off state to the on state, and the primary resonant current I of the transformer T... Lr As the current rises, the voltage Vcs across the current sensing resistor Rcs increases. When the voltage Vcs across the current sensing resistor Rcs rises to a level higher than the voltage divider of FB, at time t1, the upper switch Q1 changes from the on state to the off state. Since the current in the inductor cannot change abruptly, the primary resonant current I of the transformer T... Lr The parasitic capacitance of the lower switch Q2 is discharged while the parasitic capacitance of the upper switch Q1 is charged, causing the HB voltage to drop to 0V. The body diode of the lower switch Q2 changes from the off state to the on state. At time t2, the first turn-on control signal down_on flips, and the lower switch Q2 changes from the off state to the on state, thus achieving zero-voltage turn-on. Afterward, the resonant capacitor Cr and the primary leakage inductance Lr of the transformer T resonate, and at the same time, the transformer T demagnetizes, and the primary excitation current I of the transformer T... LmAt time t3, the first turn-off control signal dem_off flips, and the lower switch Q2 changes from the on state to the off state. After that, the parasitic capacitances of the upper switch Q1 and the lower switch Q2 and the primary magnetizing inductance Lm of the transformer T resonate, with a resonant period of td. At time t4, the mode / frequency control signal DCM_on flips, while the turn-on enable signal Tzvs_ENA is in the disabled state, and the lower switch Q2 no longer changes from the off state to the on state. At time t5, the upper switch turn-on control signal up_on flips, and the upper switch Q1 changes from the off state to the on state again, thus achieving low-voltage turn-on.

[0039] Figure 8 It shows Figure 4 The circuit schematic shown is an example circuit implementation of the ZVS computing module. Figure 8 As shown, in some embodiments, the ZVS calculation module is configured to: generate a third sampling signal V3 by sampling the demagnetization characterization signal INV, wherein the third sampling signal V3 can reflect the voltage (i.e., HB voltage) at the midpoint between the upper switch Q1 and the lower switch Q2 before the upper switch Q1 changes from the off state to the on state, or the voltage (i.e., HB voltage) change at the midpoint between the upper switch Q1 and the lower switch Q2 before and after the upper switch Q1 changes from the off state to the on state; generate a compensation control signal ZVS_comp by integrating the difference between the third sampling signal V3 and the reference signal Vref; and generate a re-turn-off control signal ZVS_off by comparing the compensation control signal ZVS_comp with a predetermined ramp signal.

[0040] like Figure 4 and Figure 8 As shown, the voltage INV is sampled by the sampling unit to generate voltage V3 (i.e., the third sampling signal V3). Voltage V3 is proportional to the difference in HB voltage before and after the upper switch Q1 changes from the off state to the on state, or only proportional to the HB voltage before the upper switch Q1 changes from the off state to the on state. The reference voltage Vref can be a fixed voltage or generated by the sampling unit by sampling voltage INV during the period when the upper switch Q1 is in the on state. Voltage V3 and reference voltage Vref are fed together into the integrator to generate compensation voltage ZVS_comp (i.e., compensation control signal ZVS_comp). The compensation voltage ZVS_comp is compared with the predetermined ramp voltage generated by the ramp generator to determine the turn-off time of the lower switch Q2 (i.e., the duration of the on state). This method can accurately control the difference in HB voltage before and after the upper switch Q1 changes from the off state to the on state, and control the on-state voltage of the upper switch Q1 at the target value. The optimal efficiency of the switching transistor Q1 is not 0V, so the target value is usually a voltage higher than 0V.

[0041] Figure 9 This shows the case where the voltage V3 in the ZVS calculation module is higher than the reference voltage Vref. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply. Here, Q1 gate represents the upper transistor control signal used to control the on / off state of the upper switching transistor Q1, Q2 gate represents the lower transistor control signal used to control the on / off state of the lower switching transistor Q2, and I... Lr ZVS_comp represents the primary resonant current of transformer T, INV represents the voltage INV, and HB represents the voltage at the midpoint between the upper switch Q1 and the lower switch Q2.

[0042] like Figure 4 and Figure 9 As shown, when the voltage V3 is higher than the reference voltage Vref, the HB voltage difference Vs before and after the upper switch Q1 changes from the off state to the on state is higher than the target value. The compensation voltage ZVS_comp rises, and the duration Tzvs of the lower switch Q2 being in the on state again becomes longer. Therefore, the HB voltage difference before and after the upper switch Q1 changes from the off state to the on state will decrease until it reaches the target value.

[0043] Figure 10 This shows the case where the voltage V3 in the ZVS calculation module is lower than the reference voltage Vref. Figure 4 The diagram shows the waveforms of multiple signals in the switching power supply. Here, Q1 gate represents the upper transistor control signal used to control the on / off state of the upper switching transistor Q1, Q2 gate represents the lower transistor control signal used to control the on / off state of the lower switching transistor Q2, and I... Lr ZVS_comp represents the primary resonant current of transformer T, INV represents the voltage INV, and HB represents the voltage at the midpoint between the upper switch Q1 and the lower switch Q2.

[0044] like Figure 4 and Figure 10 As shown, when the voltage V3 is lower than the reference voltage Vref, the HB voltage difference Vs before and after the upper switch Q1 changes from the off state to the on state is lower than the target value. The compensation voltage ZVS_comp decreases, and the duration Tzvs of the lower switch Q2 being in the on state again becomes shorter. Therefore, the HB voltage difference before and after the upper switch Q1 changes from the off state to the on state will increase until it reaches the target value.

[0045] Figure 11 This shows the case where the voltage V3 in the ZVS calculation module is equal to the reference voltage Vref. Figure 4The diagram shows the waveforms of multiple signals in the switching power supply. Here, Q1 gate represents the upper transistor control signal used to control the on / off state of the upper switching transistor Q1, Q2 gate represents the lower transistor control signal used to control the on / off state of the lower switching transistor Q2, and I... Lr ZVS_comp represents the primary resonant current of transformer T, INV represents the voltage INV, and HB represents the voltage at the midpoint between the upper switch Q1 and the lower switch Q2.

[0046] like Figure 4 and Figure 11 As shown, when the voltage V3 equals the reference voltage Vref, the HB voltage difference Vs before and after the upper switch Q1 changes from the off state to the on state is equal to the target value. The compensation voltage ZVS_comp remains unchanged, and the duration Tzvs of the lower switch Q2 being in the on state again also remains unchanged. Therefore, the HB voltage difference before and after the upper switch Q1 changes from the off state to the on state will stabilize at the target value.

[0047] For the resonance between the sum of the parasitic capacitances Coss of the upper and lower switches Q1 and Q2 and the primary magnetizing inductance Lm of the transformer T after the lower switch Q2 changes from the on state to the off state and before the upper switch Q1 changes from the off state to the on state, the negative current required for the HB voltage to resonate to the input voltage Vin can be calculated.

[0048] According to the law of conservation of energy:

[0049] Therefore, the negative current required for the upper switch Q1 to achieve zero-voltage turn-on is:

[0050]

[0051] The duration for which the lower switch Q2 remains in the conducting state again is:

[0052]

[0053] The following was obtained through linear fitting:

[0054]

[0055] in, td is the resonant period of the parasitic capacitances of the upper switch Q1 and the lower switch Q2 and the primary magnetizing inductance Lm of the transformer T.

[0056] Figure 12 It shows Figure 4 The circuit schematic is shown as another example implementation of the ZVS computing module. Figure 12As shown, in some embodiments, the ZVS calculation module is configured to: generate a fourth sampling signal V4 by sampling the demagnetization characterization signal INV during the period when the upper switch Q1 is in the on state and the lower switch Q2 is in the off state; generate a fifth sampling signal V5 by sampling the demagnetization characterization signal INV during the period when the upper switch Q1 is in the off state and the lower switch Q2 is in the on state; generate a duration-related signal Vm related to the duration Tzvs of the lower switch Q2 being in the on state again by controlling the charging of a predetermined capacitor C1 based on the fifth sampling signal V5 and the re-on control signal ZVS_on; and generate a re-off control signal ZVS_off based on the fourth sampling signal V4 and the duration-related signal Vm.

[0057] like Figure 12 As shown, in some embodiments, the ZVS calculation module is further configured to generate a duration-related signal Vm by: generating a charging current I1 proportional to the fifth sampling signal V5 using a voltage-controlled current source; and controlling the charging current I1 to charge a predetermined capacitor C1 using a re-on control signal ZVS_on. For example, the re-on control signal ZVS_on controls switch S1 to also be in the on state while the lower switch Q2 is in the on state again, thereby controlling the charging current I1 to charge the predetermined capacitor C1 while the lower switch Q2 is in the on state again, until the voltage Vm is higher than the voltage V4 and the re-off control signal ZVS_off changes from low to high. At this time, the re-off control signal ZVS_off controls switch S2 to change from the off state to the on state, causing the predetermined capacitor C1 to discharge in preparation for the next charging.

[0058] like Figure 4 and Figure 12 As shown, the voltage INV is sampled by the sampling unit to generate voltages V4 and V5. V4 = m3·(Vin-N·Vo) is the voltage sampled during the period when the upper switch Q1 is in the on state and the lower switch is in the off state, which is proportional to the magnetizing voltage (Vin-N·Vo). V5 = m4·N·Vo is the voltage sampled during the period when the upper switch Q1 is in the off state and the lower switch Q2 is in the on state, which is proportional to the demagnetizing voltage (N·Vo).

[0059] It should be noted that the sampling unit in the ZVS calculation module can be shared with the sampling unit in the ZVS enable module. In this case, m3 = m1, m4 = m2, V4 = V1, V5 = V2. Voltage V5 is converted into current I1 (I1 = k·V3) through a voltage-controlled current source. During the period when the lower switch Q2 is in the conducting state again, current I1 charges capacitor C1 to generate voltage Vm. Voltages Vm and V4 are compared to determine the turn-off time of the lower switch Q2 (i.e., the duration of the lower switch Q2 being in the conducting state again). Here, the duration of the lower switch Q2 being in the conducting state again... C1, m1, m2, and k are all internal parameters; we only need to let... This will allow the upper switching transistor Q1 to conduct at zero voltage. The equation can be satisfied by external settings, or the zero-voltage turn-on of the upper switch Q1 can be achieved by automatically adjusting the resonant period td through the demagnetization characterization signal INV, thus optimizing the system's light-load efficiency.

[0060] This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment can be modified without departing from the basic spirit of the invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning and scope of the claims and their equivalents are thus included within the scope of the invention.

Claims

1. A control circuit for an asymmetric half-bridge flyback switching power supply, the asymmetric half-bridge flyback switching power supply including an upper switching transistor, a lower switching transistor, and a transformer, the control circuit being configured to: after the upper switching transistor changes from an on state to an off state and before changing from an off state to an on state: Based on the upper switch control signal used to control the on and off states of the upper switch, a first turn-on control signal is generated to control the lower switch to change from the off state to the on state for the first time, wherein... After a first predetermined time period following the moment when the upper switch control signal controls the upper switch to change from the on state to the off state, the first turn-on control signal controls the lower switch to change from the off state to the on state. Based on the demagnetization characterization signal characterizing the demagnetization of the transformer, a first turn-off control signal is generated to control the lower switch to change from the on state to the off state for the first time. Based on the demagnetization characterization signal and the output feedback signal characterizing the output voltage of the asymmetric half-bridge flyback switching power supply, a re-conduction control signal is generated to control the lower switch to change from the off state to the on state again. This includes: generating a re-conduction enable signal based on the demagnetization detection signal to control whether the lower switch is allowed to change from the off state to the on state again; generating a mode / frequency control signal based on the output feedback signal to control at least one of the operating mode and operating frequency of the asymmetric half-bridge flyback switching power supply; and generating the re-conduction control signal based on the re-conduction enable signal and the mode / frequency control signal. as well as Based on the demagnetization characterization signal, a re-shutdown control signal is generated to control the lower switch to change from the on state to the off state again.

2. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 1, wherein, The process of generating the re-enabling signal includes: A first sampling signal is generated by sampling the demagnetization characterization signal during the period when the upper switch is in the on state and the lower switch is in the off state. A second sampling signal is generated by sampling the demagnetization characterization signal while the upper switch is in the off state and the lower switch is in the on state; and The re-enabling signal is generated by comparing and calculating the first sampled signal and the second sampled signal.

3. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 1, wherein, The process of generating the re-shutdown control signal includes: A third sampling signal is generated by sampling the demagnetization characterization signal, wherein the third sampling signal can reflect the voltage at the midpoint between the upper switch and the lower switch before the upper switch changes from the off state to the on state, or the voltage change amplitude at the midpoint between the upper switch and the lower switch before and after the upper switch changes from the off state to the on state. A compensation control signal is generated by integrating the difference between the third sampled signal and the reference signal; and The re-shutdown control signal is generated by comparing the compensation control signal and the predetermined ramp signal.

4. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 3, wherein, The reference signal is a fixed voltage or is generated by sampling the demagnetization characterization signal while the upper switch is in the on state.

5. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 1, wherein, The process of generating the re-shutdown control signal includes: A fourth sampling signal is generated by sampling the demagnetization characterization signal during the period when the upper switch is in the on state and the lower switch is in the off state. A fifth sampling signal is generated by sampling the demagnetization characterization signal during the period when the upper switch is in the off state and the lower switch is in the on state; By controlling the charging of a predetermined capacitor based on the fifth sampling signal and the re-turn-on control signal, a duration-related signal is generated that relates to the duration for which the lower switch is in the on-state again; and The re-shutdown control signal is generated based on the fourth sampling signal and the duration-related signal.

6. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 5, wherein, The process of generating the duration-related signal includes: A charging current proportional to the fifth sampled signal is generated using a voltage-controlled current source; and The predetermined capacitor is charged using a charging current proportional to the fifth sampling signal, controlled by the re-conduction control signal.

7. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 6, wherein, During the period when the re-conduction control signal controls the lower switch to be in the conduction state again, a charging current proportional to the fifth sampling signal charges the predetermined capacitor.

8. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 1 is further configured as follows: The upper switch control signal is generated based on the output feedback signal, the current characterization signal characterizing the resonant current on the primary side of the transformer, and the lower switch control signal used to control the on and off of the lower switch.

9. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 8, wherein, The lower control signal is generated based on the initial turn-on control signal, the initial turn-off control signal, the re-turn-on control signal, and the re-turn-off control signal, and the process for generating the upper control signal includes: Based on the output feedback signal and the current characterization signal, a power switch turn-off control signal is generated. Based on the lower tube control signal, an upper tube conduction control signal is generated; and The upper tube control signal is generated based on the upper tube turn-off control signal and the upper tube turn-on control signal.

10. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 9, wherein, The upper tube turn-off control signal is generated by comparing the voltage divider signal of the output feedback signal with the current characterization signal.

11. The control circuit for an asymmetric half-bridge flyback switching power supply according to claim 9, wherein, After a second predetermined time period following the moment when the lower switch control signal controls the lower switch to change from the on state to the off state, the upper switch control signal controls the upper switch to change from the off state to the on state.

12. An asymmetric half-bridge flyback switching power supply, comprising the control circuit for the asymmetric half-bridge flyback switching power supply as described in any one of claims 1 to 11.

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