Clock dithering system

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a clock dithering system. The clock dithering system comprises an input clock end, a first digital phase-locked loop, an integral differential modulator, a second digital phase-locked loop, a voltage-controlled oscillator and an output clock end which are connected in sequence, the first digital phase-locked loop is connected with the output clock end through a multi-mode divider, and the second digital phase-locked loop is connected with the output clock end; the application further comprises a digital signal processor, an input end of which is connected with an output end of the first digital phase-locked loop, and the digital signal processor is used for normalizing signals output by the first digital phase-locked loop; a first accumulator is connected between the second digital phase-locked loop and the voltage-controlled oscillator, and an input end of the first accumulator is further connected with an output end of the digital signal processor, and the first accumulator is used for accumulating signals output by the digital signal processor and signals output by the second digital phase-locked loop and then transmitting the accumulated signals to the voltage-controlled oscillator. The application adjusts the frequency of the second digital phase-locked loop through a two-point injection mode, eliminates an extra pole and makes the system stable.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a clock clearing system. Background Technology

[0002] Communication chips often require clock jitter removal. Typically, the input clock frequency drifts significantly or has poor phase noise, while the desired output clock is one that has been filtered in the frequency domain, resulting in minimal jitter in the time domain.

[0003] like Figure 1 As shown, CLK IN It's a clock that needs to be dejittered; its frequency drift is random, and its phase noise jitter is significant. And CLK... OUT It is the output clock of the debouncing system, with stable frequency and low phase noise. Figure 1 This is a general system block diagram, which uses PLL1 (digital phase-locked loop) to control CLK. IN CLK after frequency reduction via MMD (Multi-Mode Divider) OUT Phase comparison is performed. The phase error may be presented in the digital or analog domain. The phase error passes through a filter (LF) and then controls a signal or module in the PLL2 (digital phase-locked loop). The filter is optional and may not be used in some applications. This negative feedback method ensures that the average value of the two input phase errors of the PLL1 is a fixed constant, such as zero, when the entire loop reaches equilibrium. This achieves CLK (Concurrent Phase-Locked Loop). IN and CLK OUT Frequency and phase locking. The PLL2's reference clock can be a high-precision crystal oscillator, thus ensuring CLK... OUT The output has low phase noise, thus enabling the entire system to achieve debouncing.

[0004] like Figure 2 As shown, is Figure 1This represents another, more typical implementation of the anti-shake system. In this implementation, the output of PLL1 directly controls the SDM (Sigma-Delta Modulator) input of PLL2, which is the frequency control word of PLL2. From the perspective of PLL2, this is equivalent to modulating the frequency of PLL2 through the input of the SDM; this is a single-point low-pass modulation. The output frequency of PLL2 ultimately responds to the input of the SDM: the frequency control word. This introduces an additional settling time. From the perspective of PLL1, this frequency update method is equivalent to adding a pole. Considering that the bandwidth of PLL2 might be on the order of several hundred kHz, this forces the maximum bandwidth of PLL1 to be compressed to below 10 kHz. In other words, the bandwidth of PLL2 should ideally be about 10 times or more than the bandwidth of PLL1 to ensure sufficient phase margin, thus limiting the bandwidth of PLL1. Summary of the Invention

[0005] This invention addresses the technical problem that existing clock clearing systems introduce additional settling time and limit the bandwidth of PLL1 by directly controlling the SDM input of PLL2 through the output of PLL1. The purpose is to provide a clock clearing system.

[0006] A clock debouncing system includes an input clock terminal, a first digital phase-locked loop (PLL), an integral differential modulator (ICM), a second digital PLL, a voltage-controlled oscillator (VCO), and an output clock terminal connected in sequence. The first PLL is connected to the output clock terminal via a multi-mode divider, and the second PLL is connected to the output clock terminal.

[0007] The clock clearing system also includes:

[0008] A digital signal processor, with its input connected to the output of the first digital phase-locked loop, normalizes the signal output by the first digital phase-locked loop.

[0009] A first accumulator is connected between the second digital phase-locked loop and the voltage-controlled oscillator. Its input terminal is also connected to the output terminal of the digital signal processor. The accumulator adds the signal output by the digital signal processor and the signal output by the second digital phase-locked loop and then transmits the sum to the voltage-controlled oscillator.

[0010] As a preferred embodiment, the first digital phase-locked loop includes:

[0011] A frequency-locked counter, with its input terminals connected to the input clock terminal and the output terminal of the multi-mode divider, respectively.

[0012] A phase lock-in, with its input terminals connected to the input clock terminal and the output terminal of the multi-mode divider, respectively;

[0013] A second accumulator, the input terminals of which are respectively connected to the output terminal of the frequency-locked counter and the output terminal of the phase-locked unit;

[0014] A first digital filter has its input connected to the output of the second accumulator, and its output serves as the output of the first digital phase-locked loop.

[0015] As a preferred embodiment, the phase locker includes:

[0016] A snapshot circuit, with its input terminal connected to the output terminal of the multi-mode divider;

[0017] A first-time digital converter has its input terminals connected to the input clock terminal and the output terminal of the snapshot circuit, respectively, and its output terminal serves as the output terminal of the phase lock-in.

[0018] As a preferred embodiment, the multi-mode divider includes:

[0019] A first divider, with its input connected to the output clock terminal and its output connected to the input terminal of the frequency-locked counter;

[0020] A second divider has its input connected to the first divider and its output connected to the input of the phase lock.

[0021] As a preferred embodiment, the second digital phase-locked loop includes:

[0022] A reference clock terminal;

[0023] A numerically controlled oscillator gain terminal;

[0024] A third divider, with its input terminals connected to the output clock terminal and the output terminal of the integral differential modulator, respectively;

[0025] A second time-to-digital converter, the input terminals of which are respectively connected to the reference clock terminal and the output terminal of the third divider;

[0026] A second digital filter, the input of which is connected to the output of the second time-to-digital converter;

[0027] A first multiplier has its input terminals connected to the output terminal of the second digital filter and the gain terminal of the numerically controlled oscillator, respectively, and its output terminal serves as the output terminal of the second digital phase-locked loop.

[0028] As a preferred embodiment, the reference clock terminal is connected to a crystal oscillator.

[0029] As a preferred option, the third divider uses another multi-mode divider.

[0030] As a preferred option, the second digital filter is a PI filter.

[0031] As a preferred embodiment, the second digital filter is a digital filter composed of a cascaded PI filter and an IIR filter.

[0032] As a preferred embodiment, the second digital filter has α coefficients, β coefficients, and a third accumulator. The signal filtered by the β coefficients is processed by an integrator or accumulator and then transmitted to the input of the third accumulator. The signal filtered by the α coefficients is transmitted to the input of the third accumulator. The output of the third accumulator serves as the output of the second digital filter.

[0033] As a preferred embodiment, the digital signal processor includes a second multiplier, which normalizes the signal output from the first digital phase-locked loop.

[0034] The positive and progressive effects of this invention are as follows: This invention employs a clock debouncing system, which has the following advantages:

[0035] 1. The output of the first digital phase-locked loop directly controls the SDM of the second digital phase-locked loop. The frequency of the second digital phase-locked loop is modulated by the SDM, which is a single-point low-pass modulation. The output of the digital signal processor is a high-pass modulation. The frequency of the second digital phase-locked loop is adjusted by a two-point injection method. The high-pass + low-pass = full-pass method does not introduce additional poles.

[0036] 2. The output of the digital signal processor requires a high-pass injection point. Therefore, the coefficients of the second multiplier need to be matched with the gain corresponding to the low-pass injection point of the first digital phase-locked loop. By connecting the digital signal processor to the output of the first digital phase-locked loop, a better all-pass effect can be achieved.

[0037] 3. Through the circuit improvement of the present invention, the extra poles are eliminated, the system can always be stable, and the phase margin can be fully guaranteed by controlling the system gain. Attached Figure Description

[0038] Figure 1 This is a general system block diagram for clock clearing in the prior art;

[0039] Figure 2 for Figure 1 A typical implementation system block diagram;

[0040] Figure 3 for Figure 2 Root locus diagram of the system;

[0041] Figure 4 for Figure 2 Bode plot of the system;

[0042] Figure 5 for Figure 2 Frequency response diagram of the second digital phase-locked loop (PLL2) in the system;

[0043] Figure 6 This is a system block diagram of the present invention;

[0044] Figure 7 for Figure 6 A specific implementation circuit diagram;

[0045] Figure 8 for Figure 6 Root locus diagram of the system;

[0046] Figure 9 for Figure 6 Bode plot of the system;

[0047] Figure 10 for Figure 6 Frequency response diagram of the second digital phase-locked loop (PLL2) in the system. Detailed Implementation

[0048] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0049] Reference Figure 2 and Figure 6 The present invention provides a clock debouncing system, including an input clock terminal CLK connected in sequence. IN The system consists of: a first digital phase-locked loop (PLL1), an integral-differential modulator (SDM), a second digital phase-locked loop (PLL2), a voltage-controlled oscillator (VCO), and an output clock terminal (CLK). OUT .

[0050] Input clock terminal CLK IN The input is the clock signal that needs to be debounced, the input clock terminal CLK. IN The input terminal of the first digital phase-locked loop (PLL1) is connected to the output clock signal, which is down-clocked by the multi-mode divider (MMD). This output clock signal is generated by the output clock terminal CLK. OUT Provided. The first digital phase-locked loop (PLL1) performs a phase comparison between the input clock signal and the down-clocked output clock signal. The resulting phase error controls the frequency control word of the second digital PLL2 via an integral differential modulator (SDM). The second digital PLL2 is connected to the output clock terminal CLK. OUT The second digital phase-locked loop (PLL2) will output the clock signal CLK. OUT The provided output clock signal is subjected to phase difference and other operations with the external reference clock signal to ensure the output clock terminal CLK. OUT The output has the characteristic of low phase noise.

[0051] The clock debouncing system designed above has the problems of introducing additional settling time and bandwidth limitation of the first digital phase-locked loop (PLL1).

[0052] Reference Figure 3 , is the root locus diagram of the clock clearing system designed above, where the extra pole at (-8*10^6, 0) causes a change in the root locus.

[0053] Reference Figure 4 The diagram shows the Bode plot of the clock debouncing system designed above, where the phase margin is less than 90 degrees. Figure 4 The phase margin is approximately 50 degrees. This phase margin changes as the location of the additional pole changes.

[0054] Reference Figure 5 This is the frequency response diagram of the second digital phase-locked loop (PLL2) in the clock clearing system designed above. The second digital PLL2 has a certain settling time.

[0055] To address the two shortcomings mentioned above, refer to... Figure 6 Distinguished from Figure 2 The present invention introduces a two-point modulation approach to update the frequency of the second digital phase-locked loop (PLL2): adding a digital signal processor (DSP) and a first accumulator (A1).

[0056] The input of a digital signal processor (DSP) is connected to the output of a first digital phase-locked loop (PLL1). The DSP normalizes the signal output from the PLL1. The output of the DSP is then connected to a first accumulator (A1). The first accumulator (A1) is positioned between a second digital phase-locked loop (PLL2) and a voltage-controlled oscillator (VCO). Specifically, the output of the PLL2 is not directly transmitted to the VCO, but rather accumulated by the first accumulator (A1) before being transmitted. The first accumulator (A1) accumulates the signals output by the DSP and the PLL2 before transmitting them to the VCO.

[0057] Since the output of the first digital phase-locked loop (PLL1) provides a low-pass frequency, the digital signal processor (DSP) uses the gain corresponding to this low-pass frequency for matching, making the DSP output a high-pass frequency as the high-pass injection point. Combined with the first accumulator A1, this achieves a high-pass + low-pass = all-pass mode, solving the problem... Figure 2 The problems existing in the system shown.

[0058] Reference Figure 8 This is the root trajectory diagram of the clock clearing system of the present invention, and... Figure 3In contrast, with other modules remaining the same, this invention, by adding a digital signal processor (DSP) and a first accumulator (A1), does not introduce additional poles.

[0059] Reference Figure 9 This is the root trajectory diagram of the clock clearing system of the present invention, and... Figure 4 In contrast, with other modules remaining the same, this invention, by adding a digital signal processor (DSP) and a first accumulator (A1), eliminates extra poles, ensuring system stability and sufficient phase margin.

[0060] Reference Figure 10 This is the frequency response diagram of the second digital phase-locked loop (PLL2) in the clock clearing system of the present invention, and... Figure 5 In contrast, with other modules remaining the same, this invention, by adding a digital signal processor (DSP) and a first accumulator (A1), adjusts the frequency of the second digital phase-locked loop (PLL2) through a two-point injection method, resulting in a high-pass + low-pass = all-pass mode, which does not introduce additional poles, and the frequency response of the second digital PLL2 has no settling time.

[0061] In some embodiments, the first digital phase-locked loop (PLL1) can be a digital phase-locked loop module of the prior art, but preferably adopts the circuit structure of the present invention:

[0062] Reference Figure 7 The first digital phase-locked loop (PLL1) includes a frequency-locked counter (CNT), a phase lock, a second accumulator (A2), and a first digital filter (DLF1).

[0063] The input terminals of the frequency-locked counter CNT are connected to the input clock terminal CLK. IN The output of the multimode divider (MMD) is frequency-locked via a frequency-locked counter (CNT).

[0064] The input terminals of the phase-locked loop are connected to the input clock terminal CLK respectively. IN The output of the multimode divider (MMD) is phase-locked via a phase-locked circuit. Frequency phase locking is achieved using a frequency-locked counter (CNT) and a phase-locked circuit.

[0065] The input of the second accumulator A2 is connected to the output of the frequency lock counter CNT and the output of the phase lock, respectively.

[0066] The input of the first digital filter DLF1 is connected to the output of the second accumulator A2, and the output of the first digital filter DLF1 serves as the output of the first digital phase-locked loop PLL1.

[0067] In some embodiments, refer to Figure 7The phase-locked circuit includes a snapshot circuit (Snapshot) and a first-time digital-to-digital converter (TDC1), which achieve phase locking. The input of the snapshot circuit (Snapshot) is connected to the output of the multi-mode divider (MMD), and the input of the first-time digital-to-digital converter (TDC1) is connected to the input clock terminal (CLK). IN The output of the snapshot circuit Snapshot and the output of the first time digital converter TDC1 serve as the output of the phase lockout.

[0068] In some embodiments, the down-frequency signal provided by the multimode divider (MMD) to the frequency-locked counter (CNT) and the phase-locked circuit can be the same, but preferably different.

[0069] Therefore, the multimode divider (MMD) of the present invention includes a first divider DIV1 and a second divider DIV2. The input terminal of the first divider DIV1 is connected to the output clock terminal CLK. OUT The output of the first divider DIV1 is connected to the input of the frequency-locked counter CNT. The input of the second divider DIV2 is connected to the first divider DIV1, and the output of the second divider DIV2 is connected to the input of the phase-locked circuit. The use of the first divider DIV1 and the second divider DIV2 increases the configurability of the frequency and the flexibility of the analog module design.

[0070] In some embodiments, the second digital phase-locked loop (PLL2) can be a digital phase-locked loop module of the prior art, but preferably adopts the circuit structure of the present invention:

[0071] Reference Figure 7 The second digital phase-locked loop (PLL2) includes a reference clock terminal and a digitally controlled oscillator gain terminal K. DCO The system consists of a third divider DIV3, a second time-to-digital converter TDC2, a second digital filter DLF2, and a first multiplier M1.

[0072] The reference clock input provides a reference clock signal, preferably connected to a crystal oscillator (XO) to provide the reference clock signal. Other high-performance reference sources can also be used instead.

[0073] CNC oscillator gain terminal K DCO A gain signal is provided, which is provided by the communication chip through gain calculation. This gain signal is existing technology and will not be described in detail here.

[0074] The inputs of the third divider DIV3 are connected to the output clock terminal CLK. OUT The output of the integral differential modulator SDM is controlled by the SDM to operate the third divider DIV3 on the output clock terminal CLK. OUTThe provided output clock signal is down-clocked. The third divider, DIV3, is preferably a multi-mode divider.

[0075] The inputs of the second time-to-digital converter TDC2 are connected to the reference clock terminal and the output of the third divider DIV3, respectively. The second time-to-digital converter TDC2 quantizes the phase difference between the reference clock signal and the down-clocked output clock signal.

[0076] The input of the second digital filter DLF2 is connected to the output of the second time-to-digital converter TDC2 to filter the signal provided by the second time-to-digital converter TDC2.

[0077] The input terminals of the first multiplier M1 are connected to the output terminal of the second digital filter DLF2 and the gain terminal K of the digitally controlled oscillator, respectively. DCO The output of the first multiplier M1 serves as the output of the second digital phase-locked loop (PLL2). The filtered signal is multiplied by the gain terminal K of the digitally controlled oscillator. DCO The provided gain signal is normalized to control the frequency of the numerically controlled oscillator.

[0078] In some embodiments, the second digital filter DLF2 employs a PI filter, i.e., a proportional path and an integral path. However, the second digital filter DLF2 is not limited to a PI filter; for example, the second digital filter DLF2 can be a digital filter composed of a cascaded PI filter and an IIR filter.

[0079] In some embodiments, refer to Figure 7 The second digital filter DLF2 has α coefficients, β coefficients, and a third accumulator A3. The signal filtered by the β coefficients is processed by an integrator or accumulator and then transmitted to the input of the third accumulator. The signal filtered by the α coefficients is transmitted to the input of the third accumulator A3. The output of the third accumulator A3 serves as the output of the second digital filter DLF2.

[0080] Specifically, the preferred formula for the integrator or accumulator is:

[0081]

[0082] In some embodiments, the digital signal processor (DSP) includes a second multiplier to normalize the signal output from the first digital phase-locked loop (PLL1).

[0083] In some embodiments, the coefficients of the second multiplier are selected to match the gain corresponding to the low-pass injection point (i.e., the output of the first digital phase-locked loop PLL1).

[0084] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A clock debouncing system, comprising an input clock terminal, a first digital phase-locked loop, an integral differential modulator, a second digital phase-locked loop, a voltage-controlled oscillator, and an output clock terminal connected in sequence, wherein the first digital phase-locked loop is connected to the output clock terminal through a multi-mode divider, and the second digital phase-locked loop is connected to the output clock terminal; Its features are, Also includes: A digital signal processor, with its input connected to the output of the first digital phase-locked loop, normalizes the signal output by the first digital phase-locked loop. A first accumulator is connected between the second digital phase-locked loop and the voltage-controlled oscillator, and its input terminal is also connected to the output terminal of the digital signal processor. It accumulates the signal output by the digital signal processor and the signal output by the second digital phase-locked loop and then transmits it to the voltage-controlled oscillator. The first digital phase-locked loop includes: A frequency-locked counter, with its input terminals connected to the input clock terminal and the output terminal of the multi-mode divider, respectively. A phase lock-in, with its input terminals connected to the input clock terminal and the output terminal of the multi-mode divider, respectively; A second accumulator, the input terminals of which are respectively connected to the output terminal of the frequency-locked counter and the output terminal of the phase-locked unit; A first digital filter, the input of which is connected to the output of the second accumulator, and the output of which serves as the output of the first digital phase-locked loop; The phase locker includes: A snapshot circuit, with its input terminal connected to the output terminal of the multi-mode divider; A first-time digital converter has its input terminals connected to the input clock terminal and the output terminal of the snapshot circuit, respectively, and its output terminal serves as the output terminal of the phase lock-in.

2. The clock clearing system as described in claim 1, characterized in that, The multi-mode divider includes: A first divider, with its input connected to the output clock terminal and its output connected to the input terminal of the frequency-locked counter; A second divider has its input connected to the first divider and its output connected to the input of the phase lock.

3. The clock clearing system as described in claim 1, characterized in that, The second digital phase-locked loop includes: A reference clock terminal; A numerically controlled oscillator gain terminal; A third divider, with its input terminals connected to the output clock terminal and the output terminal of the integral differential modulator, respectively; A second time-to-digital converter, the input terminals of which are respectively connected to the reference clock terminal and the output terminal of the third divider; A second digital filter, the input of which is connected to the output of the second time-to-digital converter; A first multiplier has its input terminals connected to the output terminal of the second digital filter and the gain terminal of the numerically controlled oscillator, respectively, and its output terminal serves as the output terminal of the second digital phase-locked loop.

4. The clock clearing system as described in claim 3, characterized in that, The reference clock terminal is connected to a crystal oscillator.

5. The clock clearing system as described in claim 3, characterized in that, The third divider uses another multi-mode divider.

6. The clock clearing system as described in claim 3, characterized in that, The second digital filter is a PI filter or a digital filter composed of a PI filter and an IIR filter cascaded together.

7. The clock clearing system as described in claim 6, characterized in that, The second digital filter has α coefficients, β coefficients, and a third accumulator. The signal filtered by the β coefficients is processed by an integrator or accumulator and then transmitted to the input of the third accumulator. The signal filtered by the α coefficients is transmitted to the input of the third accumulator. The output of the third accumulator serves as the output of the second digital filter.

8. The clock clearing system according to any one of claims 1 to 7, characterized in that, The digital signal processor includes a second multiplier, which normalizes the signal output from the first digital phase-locked loop.

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